]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/op_helper.c
7 #ifdef USE_INT_TO_FLOAT_HELPERS
10 FT0
= (float) *((int32_t *)&FT1
);
15 DT0
= (double) *((int32_t *)&FT1
);
36 if (isnan(FT0
) || isnan(FT1
)) {
37 T0
= FSR_FCC1
| FSR_FCC0
;
38 env
->fsr
&= ~(FSR_FCC1
| FSR_FCC0
);
40 if (env
->fsr
& FSR_NVM
) {
41 raise_exception(TT_FP_EXCP
);
45 } else if (FT0
< FT1
) {
47 } else if (FT0
> FT1
) {
57 if (isnan(DT0
) || isnan(DT1
)) {
58 T0
= FSR_FCC1
| FSR_FCC0
;
59 env
->fsr
&= ~(FSR_FCC1
| FSR_FCC0
);
61 if (env
->fsr
& FSR_NVM
) {
62 raise_exception(TT_FP_EXCP
);
66 } else if (DT0
< DT1
) {
68 } else if (DT0
> DT1
) {
76 void helper_ld_asi(int asi
, int size
, int sign
)
81 case 3: /* MMU probe */
85 mmulev
= (T0
>> 8) & 15;
89 ret
= mmu_probe(T0
, mmulev
);
93 printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0
, mmulev
, ret
);
97 case 4: /* read MMU regs */
99 int reg
= (T0
>> 8) & 0xf;
101 ret
= env
->mmuregs
[reg
];
102 if (reg
== 3 || reg
== 4) /* Fault status, addr cleared on read*/
106 case 0x20 ... 0x2f: /* MMU passthrough */
107 cpu_physical_memory_read(T0
, (void *) &ret
, size
);
111 bswap16s((uint16_t *)&ret
);
120 void helper_st_asi(int asi
, int size
, int sign
)
123 case 3: /* MMU flush */
127 mmulev
= (T0
>> 8) & 15;
129 case 0: // flush page
130 tlb_flush_page(cpu_single_env
, T0
& 0xfffff000);
132 case 1: // flush segment (256k)
133 case 2: // flush region (16M)
134 case 3: // flush context (4G)
135 case 4: // flush entire
136 tlb_flush(cpu_single_env
, 1);
144 case 4: /* write MMU regs */
146 int reg
= (T0
>> 8) & 0xf, oldreg
;
148 oldreg
= env
->mmuregs
[reg
];
150 env
->mmuregs
[reg
] &= ~(MMU_E
| MMU_NF
);
151 env
->mmuregs
[reg
] |= T1
& (MMU_E
| MMU_NF
);
153 env
->mmuregs
[reg
] = T1
;
154 if (oldreg
!= env
->mmuregs
[reg
]) {
156 // XXX: Only if MMU mapping change, we may need to flush?
157 tlb_flush(cpu_single_env
, 1);
165 case 0x17: /* Block copy, sta access */
168 // address (T0) = dst
170 int src
= T1
, dst
= T0
;
175 cpu_physical_memory_read(src
, (void *) &temp
, 32);
176 cpu_physical_memory_write(dst
, (void *) &temp
, 32);
179 case 0x1f: /* Block fill, stda access */
182 // address (T0) = dst
187 val
= (((uint64_t)T1
) << 32) | T2
;
190 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
191 cpu_physical_memory_write(dst
, (void *) &val
, 8);
195 case 0x20 ... 0x2f: /* MMU passthrough */
201 bswap16s((uint16_t *)&temp
);
203 cpu_physical_memory_write(T0
, (void *) &temp
, size
);
215 cwp
= (env
->cwp
+ 1) & (NWINDOWS
- 1);
216 if (env
->wim
& (1 << cwp
)) {
217 raise_exception(TT_WIN_UNF
);
220 env
->psrs
= env
->psrps
;
223 void helper_ldfsr(void)
225 switch (env
->fsr
& FSR_RD_MASK
) {
227 fesetround(FE_TONEAREST
);
230 fesetround(FE_TOWARDZERO
);
233 fesetround(FE_UPWARD
);
236 fesetround(FE_DOWNWARD
);
241 void cpu_get_fp64(uint64_t *pmant
, uint16_t *pexp
, double f
)
245 *pmant
= ldexp(frexp(f
, &exptemp
), 53);
249 double cpu_put_fp64(uint64_t mant
, uint16_t exp
)
251 return ldexp((double) mant
, exp
- 53);
256 env
->exception_index
= EXCP_DEBUG
;