]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
11 //#define DEBUG_PSTATE
14 #define DPRINTF_MMU(fmt, ...) \
15 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
17 #define DPRINTF_MMU(fmt, ...) do {} while (0)
21 #define DPRINTF_MXCC(fmt, ...) \
22 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
24 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
28 #define DPRINTF_ASI(fmt, ...) \
29 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
33 #define DPRINTF_PSTATE(fmt, ...) \
34 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
43 #define AM_CHECK(env1) (1)
47 #define DT0 (env->dt0)
48 #define DT1 (env->dt1)
49 #define QT0 (env->qt0)
50 #define QT1 (env->qt1)
52 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
53 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
54 int is_asi
, int size
);
57 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
58 // Calculates TSB pointer value for fault page size 8k or 64k
59 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
60 uint64_t tag_access_register
,
63 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
64 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
65 int tsb_size
= tsb_register
& 0xf;
67 // discard lower 13 bits which hold tag access context
68 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
71 uint64_t tsb_base_mask
= ~0x1fffULL
;
72 uint64_t va
= tag_access_va
;
74 // move va bits to correct position
75 if (page_size
== 8*1024) {
77 } else if (page_size
== 64*1024) {
82 tsb_base_mask
<<= tsb_size
;
85 // calculate tsb_base mask and adjust va if split is in use
87 if (page_size
== 8*1024) {
88 va
&= ~(1ULL << (13 + tsb_size
));
89 } else if (page_size
== 64*1024) {
90 va
|= (1ULL << (13 + tsb_size
));
95 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
98 // Calculates tag target register value by reordering bits
99 // in tag access register
100 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
102 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
105 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
106 uint64_t tlb_tag
, uint64_t tlb_tte
,
109 target_ulong mask
, size
, va
, offset
;
111 // flush page range if translation is valid
112 if (TTE_IS_VALID(tlb
->tte
)) {
114 mask
= 0xffffffffffffe000ULL
;
115 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
118 va
= tlb
->tag
& mask
;
120 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
121 tlb_flush_page(env1
, va
+ offset
);
129 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
130 const char* strmmu
, CPUState
*env1
)
136 int is_demap_context
= (demap_addr
>> 6) & 1;
139 switch ((demap_addr
>> 4) & 3) {
141 context
= env1
->dmmu
.mmu_primary_context
;
144 context
= env1
->dmmu
.mmu_secondary_context
;
154 for (i
= 0; i
< 64; i
++) {
155 if (TTE_IS_VALID(tlb
[i
].tte
)) {
157 if (is_demap_context
) {
158 // will remove non-global entries matching context value
159 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
160 !tlb_compare_context(&tlb
[i
], context
)) {
165 // will remove any entry matching VA
166 mask
= 0xffffffffffffe000ULL
;
167 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
169 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
173 // entry should be global or matching context value
174 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
175 !tlb_compare_context(&tlb
[i
], context
)) {
180 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
182 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
189 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
190 uint64_t tlb_tag
, uint64_t tlb_tte
,
191 const char* strmmu
, CPUState
*env1
)
193 unsigned int i
, replace_used
;
195 // Try replacing invalid entry
196 for (i
= 0; i
< 64; i
++) {
197 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
198 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
200 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
207 // All entries are valid, try replacing unlocked entry
209 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
211 // Used entries are not replaced on first pass
213 for (i
= 0; i
< 64; i
++) {
214 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
216 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
218 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
219 strmmu
, (replace_used
?"used":"unused"), i
);
226 // Now reset used bit and search for unused entries again
228 for (i
= 0; i
< 64; i
++) {
229 TTE_SET_UNUSED(tlb
[i
].tte
);
234 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
241 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
243 #ifdef TARGET_SPARC64
245 addr
&= 0xffffffffULL
;
250 static void raise_exception(int tt
)
252 env
->exception_index
= tt
;
256 void HELPER(raise_exception
)(int tt
)
261 void helper_check_align(target_ulong addr
, uint32_t align
)
264 #ifdef DEBUG_UNALIGNED
265 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
266 "\n", addr
, env
->pc
);
268 raise_exception(TT_UNALIGNED
);
272 #define F_HELPER(name, p) void helper_f##name##p(void)
274 #define F_BINOP(name) \
275 float32 helper_f ## name ## s (float32 src1, float32 src2) \
277 return float32_ ## name (src1, src2, &env->fp_status); \
281 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
285 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
294 void helper_fsmuld(float32 src1
, float32 src2
)
296 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
297 float32_to_float64(src2
, &env
->fp_status
),
301 void helper_fdmulq(void)
303 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
304 float64_to_float128(DT1
, &env
->fp_status
),
308 float32
helper_fnegs(float32 src
)
310 return float32_chs(src
);
313 #ifdef TARGET_SPARC64
316 DT0
= float64_chs(DT1
);
321 QT0
= float128_chs(QT1
);
325 /* Integer to float conversion. */
326 float32
helper_fitos(int32_t src
)
328 return int32_to_float32(src
, &env
->fp_status
);
331 void helper_fitod(int32_t src
)
333 DT0
= int32_to_float64(src
, &env
->fp_status
);
336 void helper_fitoq(int32_t src
)
338 QT0
= int32_to_float128(src
, &env
->fp_status
);
341 #ifdef TARGET_SPARC64
342 float32
helper_fxtos(void)
344 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
349 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
354 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
359 /* floating point conversion */
360 float32
helper_fdtos(void)
362 return float64_to_float32(DT1
, &env
->fp_status
);
365 void helper_fstod(float32 src
)
367 DT0
= float32_to_float64(src
, &env
->fp_status
);
370 float32
helper_fqtos(void)
372 return float128_to_float32(QT1
, &env
->fp_status
);
375 void helper_fstoq(float32 src
)
377 QT0
= float32_to_float128(src
, &env
->fp_status
);
380 void helper_fqtod(void)
382 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
385 void helper_fdtoq(void)
387 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
390 /* Float to integer conversion. */
391 int32_t helper_fstoi(float32 src
)
393 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
396 int32_t helper_fdtoi(void)
398 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
401 int32_t helper_fqtoi(void)
403 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
406 #ifdef TARGET_SPARC64
407 void helper_fstox(float32 src
)
409 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
412 void helper_fdtox(void)
414 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
417 void helper_fqtox(void)
419 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
422 void helper_faligndata(void)
426 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
427 /* on many architectures a shift of 64 does nothing */
428 if ((env
->gsr
& 7) != 0) {
429 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
431 *((uint64_t *)&DT0
) = tmp
;
434 #ifdef HOST_WORDS_BIGENDIAN
435 #define VIS_B64(n) b[7 - (n)]
436 #define VIS_W64(n) w[3 - (n)]
437 #define VIS_SW64(n) sw[3 - (n)]
438 #define VIS_L64(n) l[1 - (n)]
439 #define VIS_B32(n) b[3 - (n)]
440 #define VIS_W32(n) w[1 - (n)]
442 #define VIS_B64(n) b[n]
443 #define VIS_W64(n) w[n]
444 #define VIS_SW64(n) sw[n]
445 #define VIS_L64(n) l[n]
446 #define VIS_B32(n) b[n]
447 #define VIS_W32(n) w[n]
465 void helper_fpmerge(void)
472 // Reverse calculation order to handle overlap
473 d
.VIS_B64(7) = s
.VIS_B64(3);
474 d
.VIS_B64(6) = d
.VIS_B64(3);
475 d
.VIS_B64(5) = s
.VIS_B64(2);
476 d
.VIS_B64(4) = d
.VIS_B64(2);
477 d
.VIS_B64(3) = s
.VIS_B64(1);
478 d
.VIS_B64(2) = d
.VIS_B64(1);
479 d
.VIS_B64(1) = s
.VIS_B64(0);
480 //d.VIS_B64(0) = d.VIS_B64(0);
485 void helper_fmul8x16(void)
494 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
495 if ((tmp & 0xff) > 0x7f) \
497 d.VIS_W64(r) = tmp >> 8;
508 void helper_fmul8x16al(void)
517 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
518 if ((tmp & 0xff) > 0x7f) \
520 d.VIS_W64(r) = tmp >> 8;
531 void helper_fmul8x16au(void)
540 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
541 if ((tmp & 0xff) > 0x7f) \
543 d.VIS_W64(r) = tmp >> 8;
554 void helper_fmul8sux16(void)
563 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
564 if ((tmp & 0xff) > 0x7f) \
566 d.VIS_W64(r) = tmp >> 8;
577 void helper_fmul8ulx16(void)
586 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
587 if ((tmp & 0xff) > 0x7f) \
589 d.VIS_W64(r) = tmp >> 8;
600 void helper_fmuld8sux16(void)
609 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
610 if ((tmp & 0xff) > 0x7f) \
614 // Reverse calculation order to handle overlap
622 void helper_fmuld8ulx16(void)
631 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
632 if ((tmp & 0xff) > 0x7f) \
636 // Reverse calculation order to handle overlap
644 void helper_fexpand(void)
649 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
651 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
652 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
653 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
654 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
659 #define VIS_HELPER(name, F) \
660 void name##16(void) \
667 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
668 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
669 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
670 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
675 uint32_t name##16s(uint32_t src1, uint32_t src2) \
682 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
683 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
688 void name##32(void) \
695 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
696 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
701 uint32_t name##32s(uint32_t src1, uint32_t src2) \
713 #define FADD(a, b) ((a) + (b))
714 #define FSUB(a, b) ((a) - (b))
715 VIS_HELPER(helper_fpadd
, FADD
)
716 VIS_HELPER(helper_fpsub
, FSUB
)
718 #define VIS_CMPHELPER(name, F) \
719 void name##16(void) \
726 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
727 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
728 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
729 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
734 void name##32(void) \
741 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
742 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
747 #define FCMPGT(a, b) ((a) > (b))
748 #define FCMPEQ(a, b) ((a) == (b))
749 #define FCMPLE(a, b) ((a) <= (b))
750 #define FCMPNE(a, b) ((a) != (b))
752 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
753 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
754 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
755 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
758 void helper_check_ieee_exceptions(void)
762 status
= get_float_exception_flags(&env
->fp_status
);
764 /* Copy IEEE 754 flags into FSR */
765 if (status
& float_flag_invalid
)
767 if (status
& float_flag_overflow
)
769 if (status
& float_flag_underflow
)
771 if (status
& float_flag_divbyzero
)
773 if (status
& float_flag_inexact
)
776 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
777 /* Unmasked exception, generate a trap */
778 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
779 raise_exception(TT_FP_EXCP
);
781 /* Accumulate exceptions */
782 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
787 void helper_clear_float_exceptions(void)
789 set_float_exception_flags(0, &env
->fp_status
);
792 float32
helper_fabss(float32 src
)
794 return float32_abs(src
);
797 #ifdef TARGET_SPARC64
798 void helper_fabsd(void)
800 DT0
= float64_abs(DT1
);
803 void helper_fabsq(void)
805 QT0
= float128_abs(QT1
);
809 float32
helper_fsqrts(float32 src
)
811 return float32_sqrt(src
, &env
->fp_status
);
814 void helper_fsqrtd(void)
816 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
819 void helper_fsqrtq(void)
821 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
824 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
825 void glue(helper_, name) (void) \
827 target_ulong new_fsr; \
829 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
830 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
831 case float_relation_unordered: \
832 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
833 if ((env->fsr & FSR_NVM) || TRAP) { \
834 env->fsr |= new_fsr; \
835 env->fsr |= FSR_NVC; \
836 env->fsr |= FSR_FTT_IEEE_EXCP; \
837 raise_exception(TT_FP_EXCP); \
839 env->fsr |= FSR_NVA; \
842 case float_relation_less: \
843 new_fsr = FSR_FCC0 << FS; \
845 case float_relation_greater: \
846 new_fsr = FSR_FCC1 << FS; \
852 env->fsr |= new_fsr; \
854 #define GEN_FCMPS(name, size, FS, TRAP) \
855 void glue(helper_, name)(float32 src1, float32 src2) \
857 target_ulong new_fsr; \
859 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
860 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
861 case float_relation_unordered: \
862 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
863 if ((env->fsr & FSR_NVM) || TRAP) { \
864 env->fsr |= new_fsr; \
865 env->fsr |= FSR_NVC; \
866 env->fsr |= FSR_FTT_IEEE_EXCP; \
867 raise_exception(TT_FP_EXCP); \
869 env->fsr |= FSR_NVA; \
872 case float_relation_less: \
873 new_fsr = FSR_FCC0 << FS; \
875 case float_relation_greater: \
876 new_fsr = FSR_FCC1 << FS; \
882 env->fsr |= new_fsr; \
885 GEN_FCMPS(fcmps
, float32
, 0, 0);
886 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
888 GEN_FCMPS(fcmpes
, float32
, 0, 1);
889 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
891 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
892 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
894 static uint32_t compute_all_flags(void)
896 return env
->psr
& PSR_ICC
;
899 static uint32_t compute_C_flags(void)
901 return env
->psr
& PSR_CARRY
;
904 static inline uint32_t get_NZ_icc(int32_t dst
)
910 } else if (dst
< 0) {
916 #ifdef TARGET_SPARC64
917 static uint32_t compute_all_flags_xcc(void)
919 return env
->xcc
& PSR_ICC
;
922 static uint32_t compute_C_flags_xcc(void)
924 return env
->xcc
& PSR_CARRY
;
927 static inline uint32_t get_NZ_xcc(target_long dst
)
933 } else if (dst
< 0) {
940 static inline uint32_t get_V_div_icc(target_ulong src2
)
950 static uint32_t compute_all_div(void)
954 ret
= get_NZ_icc(CC_DST
);
955 ret
|= get_V_div_icc(CC_SRC2
);
959 static uint32_t compute_C_div(void)
964 static inline uint32_t get_C_add_icc(uint32_t dst
, uint32_t src1
)
974 static inline uint32_t get_C_addx_icc(uint32_t dst
, uint32_t src1
,
979 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1U << 31)) {
985 static inline uint32_t get_V_add_icc(uint32_t dst
, uint32_t src1
,
990 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1U << 31)) {
996 #ifdef TARGET_SPARC64
997 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
1007 static inline uint32_t get_C_addx_xcc(target_ulong dst
, target_ulong src1
,
1012 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1ULL << 63)) {
1018 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
1023 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63)) {
1029 static uint32_t compute_all_add_xcc(void)
1033 ret
= get_NZ_xcc(CC_DST
);
1034 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1035 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1039 static uint32_t compute_C_add_xcc(void)
1041 return get_C_add_xcc(CC_DST
, CC_SRC
);
1045 static uint32_t compute_all_add(void)
1049 ret
= get_NZ_icc(CC_DST
);
1050 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1051 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1055 static uint32_t compute_C_add(void)
1057 return get_C_add_icc(CC_DST
, CC_SRC
);
1060 #ifdef TARGET_SPARC64
1061 static uint32_t compute_all_addx_xcc(void)
1065 ret
= get_NZ_xcc(CC_DST
);
1066 ret
|= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1067 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1071 static uint32_t compute_C_addx_xcc(void)
1075 ret
= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1080 static uint32_t compute_all_addx(void)
1084 ret
= get_NZ_icc(CC_DST
);
1085 ret
|= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1086 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1090 static uint32_t compute_C_addx(void)
1094 ret
= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1098 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1102 if ((src1
| src2
) & 0x3) {
1108 static uint32_t compute_all_tadd(void)
1112 ret
= get_NZ_icc(CC_DST
);
1113 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1114 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1115 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1119 static uint32_t compute_all_taddtv(void)
1123 ret
= get_NZ_icc(CC_DST
);
1124 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1128 static inline uint32_t get_C_sub_icc(uint32_t src1
, uint32_t src2
)
1138 static inline uint32_t get_C_subx_icc(uint32_t dst
, uint32_t src1
,
1143 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1U << 31)) {
1149 static inline uint32_t get_V_sub_icc(uint32_t dst
, uint32_t src1
,
1154 if (((src1
^ src2
) & (src1
^ dst
)) & (1U << 31)) {
1161 #ifdef TARGET_SPARC64
1162 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1172 static inline uint32_t get_C_subx_xcc(target_ulong dst
, target_ulong src1
,
1177 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1ULL << 63)) {
1183 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1188 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63)) {
1194 static uint32_t compute_all_sub_xcc(void)
1198 ret
= get_NZ_xcc(CC_DST
);
1199 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1200 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1204 static uint32_t compute_C_sub_xcc(void)
1206 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1210 static uint32_t compute_all_sub(void)
1214 ret
= get_NZ_icc(CC_DST
);
1215 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1216 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1220 static uint32_t compute_C_sub(void)
1222 return get_C_sub_icc(CC_SRC
, CC_SRC2
);
1225 #ifdef TARGET_SPARC64
1226 static uint32_t compute_all_subx_xcc(void)
1230 ret
= get_NZ_xcc(CC_DST
);
1231 ret
|= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1232 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1236 static uint32_t compute_C_subx_xcc(void)
1240 ret
= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1245 static uint32_t compute_all_subx(void)
1249 ret
= get_NZ_icc(CC_DST
);
1250 ret
|= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1251 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1255 static uint32_t compute_C_subx(void)
1259 ret
= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1263 static uint32_t compute_all_tsub(void)
1267 ret
= get_NZ_icc(CC_DST
);
1268 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1269 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1270 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1274 static uint32_t compute_all_tsubtv(void)
1278 ret
= get_NZ_icc(CC_DST
);
1279 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1283 static uint32_t compute_all_logic(void)
1285 return get_NZ_icc(CC_DST
);
1288 static uint32_t compute_C_logic(void)
1293 #ifdef TARGET_SPARC64
1294 static uint32_t compute_all_logic_xcc(void)
1296 return get_NZ_xcc(CC_DST
);
1300 typedef struct CCTable
{
1301 uint32_t (*compute_all
)(void); /* return all the flags */
1302 uint32_t (*compute_c
)(void); /* return the C flag */
1305 static const CCTable icc_table
[CC_OP_NB
] = {
1306 /* CC_OP_DYNAMIC should never happen */
1307 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1308 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1309 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1310 [CC_OP_ADDX
] = { compute_all_addx
, compute_C_addx
},
1311 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_add
},
1312 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_add
},
1313 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1314 [CC_OP_SUBX
] = { compute_all_subx
, compute_C_subx
},
1315 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_sub
},
1316 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_sub
},
1317 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1320 #ifdef TARGET_SPARC64
1321 static const CCTable xcc_table
[CC_OP_NB
] = {
1322 /* CC_OP_DYNAMIC should never happen */
1323 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1324 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1325 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1326 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1327 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1328 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1329 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1330 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1331 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1332 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1333 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1337 void helper_compute_psr(void)
1341 new_psr
= icc_table
[CC_OP
].compute_all();
1343 #ifdef TARGET_SPARC64
1344 new_psr
= xcc_table
[CC_OP
].compute_all();
1347 CC_OP
= CC_OP_FLAGS
;
1350 target_ulong
helper_compute_C_icc(void)
1354 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1358 static inline void memcpy32(target_ulong
*dst
, const target_ulong
*src
)
1370 static void set_cwp(int new_cwp
)
1372 /* put the modified wrap registers at their proper location */
1373 if (env
->cwp
== env
->nwindows
- 1) {
1374 memcpy32(env
->regbase
, env
->regbase
+ env
->nwindows
* 16);
1378 /* put the wrap registers at their temporary location */
1379 if (new_cwp
== env
->nwindows
- 1) {
1380 memcpy32(env
->regbase
+ env
->nwindows
* 16, env
->regbase
);
1382 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
1385 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
1387 CPUState
*saved_env
;
1395 static target_ulong
get_psr(void)
1397 helper_compute_psr();
1399 #if !defined (TARGET_SPARC64)
1400 return env
->version
| (env
->psr
& PSR_ICC
) |
1401 (env
->psref
? PSR_EF
: 0) |
1402 (env
->psrpil
<< 8) |
1403 (env
->psrs
? PSR_S
: 0) |
1404 (env
->psrps
? PSR_PS
: 0) |
1405 (env
->psret
? PSR_ET
: 0) | env
->cwp
;
1407 return env
->version
| (env
->psr
& PSR_ICC
) |
1408 (env
->psref
? PSR_EF
: 0) |
1409 (env
->psrpil
<< 8) |
1410 (env
->psrs
? PSR_S
: 0) |
1411 (env
->psrps
? PSR_PS
: 0) | env
->cwp
;
1415 target_ulong
cpu_get_psr(CPUState
*env1
)
1417 CPUState
*saved_env
;
1427 static void put_psr(target_ulong val
)
1429 env
->psr
= val
& PSR_ICC
;
1430 env
->psref
= (val
& PSR_EF
)? 1 : 0;
1431 env
->psrpil
= (val
& PSR_PIL
) >> 8;
1432 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1433 cpu_check_irqs(env
);
1435 env
->psrs
= (val
& PSR_S
)? 1 : 0;
1436 env
->psrps
= (val
& PSR_PS
)? 1 : 0;
1437 #if !defined (TARGET_SPARC64)
1438 env
->psret
= (val
& PSR_ET
)? 1 : 0;
1440 set_cwp(val
& PSR_CWP
);
1441 env
->cc_op
= CC_OP_FLAGS
;
1444 void cpu_put_psr(CPUState
*env1
, target_ulong val
)
1446 CPUState
*saved_env
;
1454 static int cwp_inc(int cwp
)
1456 if (unlikely(cwp
>= env
->nwindows
)) {
1457 cwp
-= env
->nwindows
;
1462 int cpu_cwp_inc(CPUState
*env1
, int cwp
)
1464 CPUState
*saved_env
;
1474 static int cwp_dec(int cwp
)
1476 if (unlikely(cwp
< 0)) {
1477 cwp
+= env
->nwindows
;
1482 int cpu_cwp_dec(CPUState
*env1
, int cwp
)
1484 CPUState
*saved_env
;
1494 #ifdef TARGET_SPARC64
1495 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1496 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1497 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1499 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1500 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1501 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1503 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1504 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1505 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1507 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1508 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1509 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1511 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1512 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1513 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1515 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1516 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1517 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1521 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1523 static void dump_mxcc(CPUState
*env
)
1525 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1527 env
->mxccdata
[0], env
->mxccdata
[1],
1528 env
->mxccdata
[2], env
->mxccdata
[3]);
1529 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1531 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1533 env
->mxccregs
[0], env
->mxccregs
[1],
1534 env
->mxccregs
[2], env
->mxccregs
[3],
1535 env
->mxccregs
[4], env
->mxccregs
[5],
1536 env
->mxccregs
[6], env
->mxccregs
[7]);
1540 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1541 && defined(DEBUG_ASI)
1542 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1548 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1549 addr
, asi
, r1
& 0xff);
1552 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1553 addr
, asi
, r1
& 0xffff);
1556 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1557 addr
, asi
, r1
& 0xffffffff);
1560 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1567 #ifndef TARGET_SPARC64
1568 #ifndef CONFIG_USER_ONLY
1569 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1572 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1573 uint32_t last_addr
= addr
;
1576 helper_check_align(addr
, size
- 1);
1578 case 2: /* SuperSparc MXCC registers */
1580 case 0x01c00a00: /* MXCC control register */
1582 ret
= env
->mxccregs
[3];
1584 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1587 case 0x01c00a04: /* MXCC control register */
1589 ret
= env
->mxccregs
[3];
1591 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1594 case 0x01c00c00: /* Module reset register */
1596 ret
= env
->mxccregs
[5];
1597 // should we do something here?
1599 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1602 case 0x01c00f00: /* MBus port address register */
1604 ret
= env
->mxccregs
[7];
1606 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1610 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1614 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1615 "addr = %08x -> ret = %" PRIx64
","
1616 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1621 case 3: /* MMU probe */
1625 mmulev
= (addr
>> 8) & 15;
1629 ret
= mmu_probe(env
, addr
, mmulev
);
1630 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1634 case 4: /* read MMU regs */
1636 int reg
= (addr
>> 8) & 0x1f;
1638 ret
= env
->mmuregs
[reg
];
1639 if (reg
== 3) /* Fault status cleared on read */
1640 env
->mmuregs
[3] = 0;
1641 else if (reg
== 0x13) /* Fault status read */
1642 ret
= env
->mmuregs
[3];
1643 else if (reg
== 0x14) /* Fault address read */
1644 ret
= env
->mmuregs
[4];
1645 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1648 case 5: // Turbosparc ITLB Diagnostic
1649 case 6: // Turbosparc DTLB Diagnostic
1650 case 7: // Turbosparc IOTLB Diagnostic
1652 case 9: /* Supervisor code access */
1655 ret
= ldub_code(addr
);
1658 ret
= lduw_code(addr
);
1662 ret
= ldl_code(addr
);
1665 ret
= ldq_code(addr
);
1669 case 0xa: /* User data access */
1672 ret
= ldub_user(addr
);
1675 ret
= lduw_user(addr
);
1679 ret
= ldl_user(addr
);
1682 ret
= ldq_user(addr
);
1686 case 0xb: /* Supervisor data access */
1689 ret
= ldub_kernel(addr
);
1692 ret
= lduw_kernel(addr
);
1696 ret
= ldl_kernel(addr
);
1699 ret
= ldq_kernel(addr
);
1703 case 0xc: /* I-cache tag */
1704 case 0xd: /* I-cache data */
1705 case 0xe: /* D-cache tag */
1706 case 0xf: /* D-cache data */
1708 case 0x20: /* MMU passthrough */
1711 ret
= ldub_phys(addr
);
1714 ret
= lduw_phys(addr
);
1718 ret
= ldl_phys(addr
);
1721 ret
= ldq_phys(addr
);
1725 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1728 ret
= ldub_phys((target_phys_addr_t
)addr
1729 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1732 ret
= lduw_phys((target_phys_addr_t
)addr
1733 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1737 ret
= ldl_phys((target_phys_addr_t
)addr
1738 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1741 ret
= ldq_phys((target_phys_addr_t
)addr
1742 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1746 case 0x30: // Turbosparc secondary cache diagnostic
1747 case 0x31: // Turbosparc RAM snoop
1748 case 0x32: // Turbosparc page table descriptor diagnostic
1749 case 0x39: /* data cache diagnostic register */
1752 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1754 int reg
= (addr
>> 8) & 3;
1757 case 0: /* Breakpoint Value (Addr) */
1758 ret
= env
->mmubpregs
[reg
];
1760 case 1: /* Breakpoint Mask */
1761 ret
= env
->mmubpregs
[reg
];
1763 case 2: /* Breakpoint Control */
1764 ret
= env
->mmubpregs
[reg
];
1766 case 3: /* Breakpoint Status */
1767 ret
= env
->mmubpregs
[reg
];
1768 env
->mmubpregs
[reg
] = 0ULL;
1771 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1775 case 8: /* User code access, XXX */
1777 do_unassigned_access(addr
, 0, 0, asi
, size
);
1787 ret
= (int16_t) ret
;
1790 ret
= (int32_t) ret
;
1797 dump_asi("read ", last_addr
, asi
, size
, ret
);
1802 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1804 helper_check_align(addr
, size
- 1);
1806 case 2: /* SuperSparc MXCC registers */
1808 case 0x01c00000: /* MXCC stream data register 0 */
1810 env
->mxccdata
[0] = val
;
1812 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1815 case 0x01c00008: /* MXCC stream data register 1 */
1817 env
->mxccdata
[1] = val
;
1819 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1822 case 0x01c00010: /* MXCC stream data register 2 */
1824 env
->mxccdata
[2] = val
;
1826 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1829 case 0x01c00018: /* MXCC stream data register 3 */
1831 env
->mxccdata
[3] = val
;
1833 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1836 case 0x01c00100: /* MXCC stream source */
1838 env
->mxccregs
[0] = val
;
1840 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1842 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1844 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1846 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1848 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1851 case 0x01c00200: /* MXCC stream destination */
1853 env
->mxccregs
[1] = val
;
1855 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1857 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1859 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1861 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1863 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1866 case 0x01c00a00: /* MXCC control register */
1868 env
->mxccregs
[3] = val
;
1870 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1873 case 0x01c00a04: /* MXCC control register */
1875 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
1878 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1881 case 0x01c00e00: /* MXCC error register */
1882 // writing a 1 bit clears the error
1884 env
->mxccregs
[6] &= ~val
;
1886 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1889 case 0x01c00f00: /* MBus port address register */
1891 env
->mxccregs
[7] = val
;
1893 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1897 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1901 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
1902 asi
, size
, addr
, val
);
1907 case 3: /* MMU flush */
1911 mmulev
= (addr
>> 8) & 15;
1912 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1914 case 0: // flush page
1915 tlb_flush_page(env
, addr
& 0xfffff000);
1917 case 1: // flush segment (256k)
1918 case 2: // flush region (16M)
1919 case 3: // flush context (4G)
1920 case 4: // flush entire
1931 case 4: /* write MMU regs */
1933 int reg
= (addr
>> 8) & 0x1f;
1936 oldreg
= env
->mmuregs
[reg
];
1938 case 0: // Control Register
1939 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1941 // Mappings generated during no-fault mode or MMU
1942 // disabled mode are invalid in normal mode
1943 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
1944 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
1947 case 1: // Context Table Pointer Register
1948 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
1950 case 2: // Context Register
1951 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
1952 if (oldreg
!= env
->mmuregs
[reg
]) {
1953 /* we flush when the MMU context changes because
1954 QEMU has no MMU context support */
1958 case 3: // Synchronous Fault Status Register with Clear
1959 case 4: // Synchronous Fault Address Register
1961 case 0x10: // TLB Replacement Control Register
1962 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
1964 case 0x13: // Synchronous Fault Status Register with Read and Clear
1965 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
1967 case 0x14: // Synchronous Fault Address Register
1968 env
->mmuregs
[4] = val
;
1971 env
->mmuregs
[reg
] = val
;
1974 if (oldreg
!= env
->mmuregs
[reg
]) {
1975 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1976 reg
, oldreg
, env
->mmuregs
[reg
]);
1983 case 5: // Turbosparc ITLB Diagnostic
1984 case 6: // Turbosparc DTLB Diagnostic
1985 case 7: // Turbosparc IOTLB Diagnostic
1987 case 0xa: /* User data access */
1990 stb_user(addr
, val
);
1993 stw_user(addr
, val
);
1997 stl_user(addr
, val
);
2000 stq_user(addr
, val
);
2004 case 0xb: /* Supervisor data access */
2007 stb_kernel(addr
, val
);
2010 stw_kernel(addr
, val
);
2014 stl_kernel(addr
, val
);
2017 stq_kernel(addr
, val
);
2021 case 0xc: /* I-cache tag */
2022 case 0xd: /* I-cache data */
2023 case 0xe: /* D-cache tag */
2024 case 0xf: /* D-cache data */
2025 case 0x10: /* I/D-cache flush page */
2026 case 0x11: /* I/D-cache flush segment */
2027 case 0x12: /* I/D-cache flush region */
2028 case 0x13: /* I/D-cache flush context */
2029 case 0x14: /* I/D-cache flush user */
2031 case 0x17: /* Block copy, sta access */
2037 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
2039 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
2040 temp
= ldl_kernel(src
);
2041 stl_kernel(dst
, temp
);
2045 case 0x1f: /* Block fill, stda access */
2048 // fill 32 bytes with val
2050 uint32_t dst
= addr
& 7;
2052 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
2053 stq_kernel(dst
, val
);
2056 case 0x20: /* MMU passthrough */
2060 stb_phys(addr
, val
);
2063 stw_phys(addr
, val
);
2067 stl_phys(addr
, val
);
2070 stq_phys(addr
, val
);
2075 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2079 stb_phys((target_phys_addr_t
)addr
2080 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2083 stw_phys((target_phys_addr_t
)addr
2084 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2088 stl_phys((target_phys_addr_t
)addr
2089 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2092 stq_phys((target_phys_addr_t
)addr
2093 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2098 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2099 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2100 // Turbosparc snoop RAM
2101 case 0x32: // store buffer control or Turbosparc page table
2102 // descriptor diagnostic
2103 case 0x36: /* I-cache flash clear */
2104 case 0x37: /* D-cache flash clear */
2105 case 0x4c: /* breakpoint action */
2107 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2109 int reg
= (addr
>> 8) & 3;
2112 case 0: /* Breakpoint Value (Addr) */
2113 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2115 case 1: /* Breakpoint Mask */
2116 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2118 case 2: /* Breakpoint Control */
2119 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
2121 case 3: /* Breakpoint Status */
2122 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
2125 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
2129 case 8: /* User code access, XXX */
2130 case 9: /* Supervisor code access, XXX */
2132 do_unassigned_access(addr
, 1, 0, asi
, size
);
2136 dump_asi("write", addr
, asi
, size
, val
);
2140 #endif /* CONFIG_USER_ONLY */
2141 #else /* TARGET_SPARC64 */
2143 #ifdef CONFIG_USER_ONLY
2144 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2147 #if defined(DEBUG_ASI)
2148 target_ulong last_addr
= addr
;
2152 raise_exception(TT_PRIV_ACT
);
2154 helper_check_align(addr
, size
- 1);
2155 addr
= address_mask(env
, addr
);
2158 case 0x82: // Primary no-fault
2159 case 0x8a: // Primary no-fault LE
2160 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2162 dump_asi("read ", last_addr
, asi
, size
, ret
);
2167 case 0x80: // Primary
2168 case 0x88: // Primary LE
2172 ret
= ldub_raw(addr
);
2175 ret
= lduw_raw(addr
);
2178 ret
= ldl_raw(addr
);
2182 ret
= ldq_raw(addr
);
2187 case 0x83: // Secondary no-fault
2188 case 0x8b: // Secondary no-fault LE
2189 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2191 dump_asi("read ", last_addr
, asi
, size
, ret
);
2196 case 0x81: // Secondary
2197 case 0x89: // Secondary LE
2204 /* Convert from little endian */
2206 case 0x88: // Primary LE
2207 case 0x89: // Secondary LE
2208 case 0x8a: // Primary no-fault LE
2209 case 0x8b: // Secondary no-fault LE
2227 /* Convert to signed number */
2234 ret
= (int16_t) ret
;
2237 ret
= (int32_t) ret
;
2244 dump_asi("read ", last_addr
, asi
, size
, ret
);
2249 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2252 dump_asi("write", addr
, asi
, size
, val
);
2255 raise_exception(TT_PRIV_ACT
);
2257 helper_check_align(addr
, size
- 1);
2258 addr
= address_mask(env
, addr
);
2260 /* Convert to little endian */
2262 case 0x88: // Primary LE
2263 case 0x89: // Secondary LE
2282 case 0x80: // Primary
2283 case 0x88: // Primary LE
2302 case 0x81: // Secondary
2303 case 0x89: // Secondary LE
2307 case 0x82: // Primary no-fault, RO
2308 case 0x83: // Secondary no-fault, RO
2309 case 0x8a: // Primary no-fault LE, RO
2310 case 0x8b: // Secondary no-fault LE, RO
2312 do_unassigned_access(addr
, 1, 0, 1, size
);
2317 #else /* CONFIG_USER_ONLY */
2319 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2322 #if defined(DEBUG_ASI)
2323 target_ulong last_addr
= addr
;
2328 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2329 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2330 && asi
>= 0x30 && asi
< 0x80
2331 && !(env
->hpstate
& HS_PRIV
)))
2332 raise_exception(TT_PRIV_ACT
);
2334 helper_check_align(addr
, size
- 1);
2336 case 0x82: // Primary no-fault
2337 case 0x8a: // Primary no-fault LE
2338 case 0x83: // Secondary no-fault
2339 case 0x8b: // Secondary no-fault LE
2341 /* secondary space access has lowest asi bit equal to 1 */
2342 int access_mmu_idx
= ( asi
& 1 ) ? MMU_KERNEL_IDX
2343 : MMU_KERNEL_SECONDARY_IDX
;
2345 if (cpu_get_phys_page_nofault(env
, addr
, access_mmu_idx
) == -1ULL) {
2347 dump_asi("read ", last_addr
, asi
, size
, ret
);
2353 case 0x10: // As if user primary
2354 case 0x11: // As if user secondary
2355 case 0x18: // As if user primary LE
2356 case 0x19: // As if user secondary LE
2357 case 0x80: // Primary
2358 case 0x81: // Secondary
2359 case 0x88: // Primary LE
2360 case 0x89: // Secondary LE
2361 case 0xe2: // UA2007 Primary block init
2362 case 0xe3: // UA2007 Secondary block init
2363 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2364 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2365 && env
->hpstate
& HS_PRIV
) {
2368 ret
= ldub_hypv(addr
);
2371 ret
= lduw_hypv(addr
);
2374 ret
= ldl_hypv(addr
);
2378 ret
= ldq_hypv(addr
);
2382 /* secondary space access has lowest asi bit equal to 1 */
2386 ret
= ldub_kernel_secondary(addr
);
2389 ret
= lduw_kernel_secondary(addr
);
2392 ret
= ldl_kernel_secondary(addr
);
2396 ret
= ldq_kernel_secondary(addr
);
2402 ret
= ldub_kernel(addr
);
2405 ret
= lduw_kernel(addr
);
2408 ret
= ldl_kernel(addr
);
2412 ret
= ldq_kernel(addr
);
2418 /* secondary space access has lowest asi bit equal to 1 */
2422 ret
= ldub_user_secondary(addr
);
2425 ret
= lduw_user_secondary(addr
);
2428 ret
= ldl_user_secondary(addr
);
2432 ret
= ldq_user_secondary(addr
);
2438 ret
= ldub_user(addr
);
2441 ret
= lduw_user(addr
);
2444 ret
= ldl_user(addr
);
2448 ret
= ldq_user(addr
);
2454 case 0x14: // Bypass
2455 case 0x15: // Bypass, non-cacheable
2456 case 0x1c: // Bypass LE
2457 case 0x1d: // Bypass, non-cacheable LE
2461 ret
= ldub_phys(addr
);
2464 ret
= lduw_phys(addr
);
2467 ret
= ldl_phys(addr
);
2471 ret
= ldq_phys(addr
);
2476 case 0x24: // Nucleus quad LDD 128 bit atomic
2477 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2478 // Only ldda allowed
2479 raise_exception(TT_ILL_INSN
);
2481 case 0x04: // Nucleus
2482 case 0x0c: // Nucleus Little Endian (LE)
2486 ret
= ldub_nucleus(addr
);
2489 ret
= lduw_nucleus(addr
);
2492 ret
= ldl_nucleus(addr
);
2496 ret
= ldq_nucleus(addr
);
2501 case 0x4a: // UPA config
2507 case 0x50: // I-MMU regs
2509 int reg
= (addr
>> 3) & 0xf;
2512 // I-TSB Tag Target register
2513 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2515 ret
= env
->immuregs
[reg
];
2520 case 0x51: // I-MMU 8k TSB pointer
2522 // env->immuregs[5] holds I-MMU TSB register value
2523 // env->immuregs[6] holds I-MMU Tag Access register value
2524 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2528 case 0x52: // I-MMU 64k TSB pointer
2530 // env->immuregs[5] holds I-MMU TSB register value
2531 // env->immuregs[6] holds I-MMU Tag Access register value
2532 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2536 case 0x55: // I-MMU data access
2538 int reg
= (addr
>> 3) & 0x3f;
2540 ret
= env
->itlb
[reg
].tte
;
2543 case 0x56: // I-MMU tag read
2545 int reg
= (addr
>> 3) & 0x3f;
2547 ret
= env
->itlb
[reg
].tag
;
2550 case 0x58: // D-MMU regs
2552 int reg
= (addr
>> 3) & 0xf;
2555 // D-TSB Tag Target register
2556 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2558 ret
= env
->dmmuregs
[reg
];
2562 case 0x59: // D-MMU 8k TSB pointer
2564 // env->dmmuregs[5] holds D-MMU TSB register value
2565 // env->dmmuregs[6] holds D-MMU Tag Access register value
2566 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2570 case 0x5a: // D-MMU 64k TSB pointer
2572 // env->dmmuregs[5] holds D-MMU TSB register value
2573 // env->dmmuregs[6] holds D-MMU Tag Access register value
2574 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2578 case 0x5d: // D-MMU data access
2580 int reg
= (addr
>> 3) & 0x3f;
2582 ret
= env
->dtlb
[reg
].tte
;
2585 case 0x5e: // D-MMU tag read
2587 int reg
= (addr
>> 3) & 0x3f;
2589 ret
= env
->dtlb
[reg
].tag
;
2592 case 0x46: // D-cache data
2593 case 0x47: // D-cache tag access
2594 case 0x4b: // E-cache error enable
2595 case 0x4c: // E-cache asynchronous fault status
2596 case 0x4d: // E-cache asynchronous fault address
2597 case 0x4e: // E-cache tag data
2598 case 0x66: // I-cache instruction access
2599 case 0x67: // I-cache tag access
2600 case 0x6e: // I-cache predecode
2601 case 0x6f: // I-cache LRU etc.
2602 case 0x76: // E-cache tag
2603 case 0x7e: // E-cache tag
2605 case 0x5b: // D-MMU data pointer
2606 case 0x48: // Interrupt dispatch, RO
2607 case 0x49: // Interrupt data receive
2608 case 0x7f: // Incoming interrupt vector, RO
2611 case 0x54: // I-MMU data in, WO
2612 case 0x57: // I-MMU demap, WO
2613 case 0x5c: // D-MMU data in, WO
2614 case 0x5f: // D-MMU demap, WO
2615 case 0x77: // Interrupt vector, WO
2617 do_unassigned_access(addr
, 0, 0, 1, size
);
2622 /* Convert from little endian */
2624 case 0x0c: // Nucleus Little Endian (LE)
2625 case 0x18: // As if user primary LE
2626 case 0x19: // As if user secondary LE
2627 case 0x1c: // Bypass LE
2628 case 0x1d: // Bypass, non-cacheable LE
2629 case 0x88: // Primary LE
2630 case 0x89: // Secondary LE
2631 case 0x8a: // Primary no-fault LE
2632 case 0x8b: // Secondary no-fault LE
2650 /* Convert to signed number */
2657 ret
= (int16_t) ret
;
2660 ret
= (int32_t) ret
;
2667 dump_asi("read ", last_addr
, asi
, size
, ret
);
2672 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2675 dump_asi("write", addr
, asi
, size
, val
);
2680 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2681 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2682 && asi
>= 0x30 && asi
< 0x80
2683 && !(env
->hpstate
& HS_PRIV
)))
2684 raise_exception(TT_PRIV_ACT
);
2686 helper_check_align(addr
, size
- 1);
2687 /* Convert to little endian */
2689 case 0x0c: // Nucleus Little Endian (LE)
2690 case 0x18: // As if user primary LE
2691 case 0x19: // As if user secondary LE
2692 case 0x1c: // Bypass LE
2693 case 0x1d: // Bypass, non-cacheable LE
2694 case 0x88: // Primary LE
2695 case 0x89: // Secondary LE
2714 case 0x10: // As if user primary
2715 case 0x11: // As if user secondary
2716 case 0x18: // As if user primary LE
2717 case 0x19: // As if user secondary LE
2718 case 0x80: // Primary
2719 case 0x81: // Secondary
2720 case 0x88: // Primary LE
2721 case 0x89: // Secondary LE
2722 case 0xe2: // UA2007 Primary block init
2723 case 0xe3: // UA2007 Secondary block init
2724 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2725 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2726 && env
->hpstate
& HS_PRIV
) {
2729 stb_hypv(addr
, val
);
2732 stw_hypv(addr
, val
);
2735 stl_hypv(addr
, val
);
2739 stq_hypv(addr
, val
);
2743 /* secondary space access has lowest asi bit equal to 1 */
2747 stb_kernel_secondary(addr
, val
);
2750 stw_kernel_secondary(addr
, val
);
2753 stl_kernel_secondary(addr
, val
);
2757 stq_kernel_secondary(addr
, val
);
2763 stb_kernel(addr
, val
);
2766 stw_kernel(addr
, val
);
2769 stl_kernel(addr
, val
);
2773 stq_kernel(addr
, val
);
2779 /* secondary space access has lowest asi bit equal to 1 */
2783 stb_user_secondary(addr
, val
);
2786 stw_user_secondary(addr
, val
);
2789 stl_user_secondary(addr
, val
);
2793 stq_user_secondary(addr
, val
);
2799 stb_user(addr
, val
);
2802 stw_user(addr
, val
);
2805 stl_user(addr
, val
);
2809 stq_user(addr
, val
);
2815 case 0x14: // Bypass
2816 case 0x15: // Bypass, non-cacheable
2817 case 0x1c: // Bypass LE
2818 case 0x1d: // Bypass, non-cacheable LE
2822 stb_phys(addr
, val
);
2825 stw_phys(addr
, val
);
2828 stl_phys(addr
, val
);
2832 stq_phys(addr
, val
);
2837 case 0x24: // Nucleus quad LDD 128 bit atomic
2838 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2839 // Only ldda allowed
2840 raise_exception(TT_ILL_INSN
);
2842 case 0x04: // Nucleus
2843 case 0x0c: // Nucleus Little Endian (LE)
2847 stb_nucleus(addr
, val
);
2850 stw_nucleus(addr
, val
);
2853 stl_nucleus(addr
, val
);
2857 stq_nucleus(addr
, val
);
2863 case 0x4a: // UPA config
2871 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
2872 // Mappings generated during D/I MMU disabled mode are
2873 // invalid in normal mode
2874 if (oldreg
!= env
->lsu
) {
2875 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
2884 case 0x50: // I-MMU regs
2886 int reg
= (addr
>> 3) & 0xf;
2889 oldreg
= env
->immuregs
[reg
];
2893 case 1: // Not in I-MMU
2898 val
= 0; // Clear SFSR
2899 env
->immu
.sfsr
= val
;
2903 case 5: // TSB access
2904 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
2905 PRIx64
"\n", env
->immu
.tsb
, val
);
2906 env
->immu
.tsb
= val
;
2908 case 6: // Tag access
2909 env
->immu
.tag_access
= val
;
2918 if (oldreg
!= env
->immuregs
[reg
]) {
2919 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2920 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
2927 case 0x54: // I-MMU data in
2928 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
2930 case 0x55: // I-MMU data access
2934 unsigned int i
= (addr
>> 3) & 0x3f;
2936 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
2939 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
2944 case 0x57: // I-MMU demap
2945 demap_tlb(env
->itlb
, addr
, "immu", env
);
2947 case 0x58: // D-MMU regs
2949 int reg
= (addr
>> 3) & 0xf;
2952 oldreg
= env
->dmmuregs
[reg
];
2958 if ((val
& 1) == 0) {
2959 val
= 0; // Clear SFSR, Fault address
2962 env
->dmmu
.sfsr
= val
;
2964 case 1: // Primary context
2965 env
->dmmu
.mmu_primary_context
= val
;
2967 case 2: // Secondary context
2968 env
->dmmu
.mmu_secondary_context
= val
;
2970 case 5: // TSB access
2971 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
2972 PRIx64
"\n", env
->dmmu
.tsb
, val
);
2973 env
->dmmu
.tsb
= val
;
2975 case 6: // Tag access
2976 env
->dmmu
.tag_access
= val
;
2978 case 7: // Virtual Watchpoint
2979 case 8: // Physical Watchpoint
2981 env
->dmmuregs
[reg
] = val
;
2985 if (oldreg
!= env
->dmmuregs
[reg
]) {
2986 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2987 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2994 case 0x5c: // D-MMU data in
2995 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
2997 case 0x5d: // D-MMU data access
2999 unsigned int i
= (addr
>> 3) & 0x3f;
3001 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
3004 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
3009 case 0x5f: // D-MMU demap
3010 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
3012 case 0x49: // Interrupt data receive
3015 case 0x46: // D-cache data
3016 case 0x47: // D-cache tag access
3017 case 0x4b: // E-cache error enable
3018 case 0x4c: // E-cache asynchronous fault status
3019 case 0x4d: // E-cache asynchronous fault address
3020 case 0x4e: // E-cache tag data
3021 case 0x66: // I-cache instruction access
3022 case 0x67: // I-cache tag access
3023 case 0x6e: // I-cache predecode
3024 case 0x6f: // I-cache LRU etc.
3025 case 0x76: // E-cache tag
3026 case 0x7e: // E-cache tag
3028 case 0x51: // I-MMU 8k TSB pointer, RO
3029 case 0x52: // I-MMU 64k TSB pointer, RO
3030 case 0x56: // I-MMU tag read, RO
3031 case 0x59: // D-MMU 8k TSB pointer, RO
3032 case 0x5a: // D-MMU 64k TSB pointer, RO
3033 case 0x5b: // D-MMU data pointer, RO
3034 case 0x5e: // D-MMU tag read, RO
3035 case 0x48: // Interrupt dispatch, RO
3036 case 0x7f: // Incoming interrupt vector, RO
3037 case 0x82: // Primary no-fault, RO
3038 case 0x83: // Secondary no-fault, RO
3039 case 0x8a: // Primary no-fault LE, RO
3040 case 0x8b: // Secondary no-fault LE, RO
3042 do_unassigned_access(addr
, 1, 0, 1, size
);
3046 #endif /* CONFIG_USER_ONLY */
3048 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
3050 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
3051 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
3052 && asi
>= 0x30 && asi
< 0x80
3053 && !(env
->hpstate
& HS_PRIV
)))
3054 raise_exception(TT_PRIV_ACT
);
3057 case 0x24: // Nucleus quad LDD 128 bit atomic
3058 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3059 helper_check_align(addr
, 0xf);
3061 env
->gregs
[1] = ldq_kernel(addr
+ 8);
3063 bswap64s(&env
->gregs
[1]);
3064 } else if (rd
< 8) {
3065 env
->gregs
[rd
] = ldq_kernel(addr
);
3066 env
->gregs
[rd
+ 1] = ldq_kernel(addr
+ 8);
3068 bswap64s(&env
->gregs
[rd
]);
3069 bswap64s(&env
->gregs
[rd
+ 1]);
3072 env
->regwptr
[rd
] = ldq_kernel(addr
);
3073 env
->regwptr
[rd
+ 1] = ldq_kernel(addr
+ 8);
3075 bswap64s(&env
->regwptr
[rd
]);
3076 bswap64s(&env
->regwptr
[rd
+ 1]);
3081 helper_check_align(addr
, 0x3);
3083 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3085 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3086 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3088 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3089 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3095 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3100 helper_check_align(addr
, 3);
3102 case 0xf0: // Block load primary
3103 case 0xf1: // Block load secondary
3104 case 0xf8: // Block load primary LE
3105 case 0xf9: // Block load secondary LE
3107 raise_exception(TT_ILL_INSN
);
3110 helper_check_align(addr
, 0x3f);
3111 for (i
= 0; i
< 16; i
++) {
3112 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
3122 val
= helper_ld_asi(addr
, asi
, size
, 0);
3126 *((uint32_t *)&env
->fpr
[rd
]) = val
;
3129 *((int64_t *)&DT0
) = val
;
3137 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3140 target_ulong val
= 0;
3142 helper_check_align(addr
, 3);
3144 case 0xe0: // UA2007 Block commit store primary (cache flush)
3145 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3146 case 0xf0: // Block store primary
3147 case 0xf1: // Block store secondary
3148 case 0xf8: // Block store primary LE
3149 case 0xf9: // Block store secondary LE
3151 raise_exception(TT_ILL_INSN
);
3154 helper_check_align(addr
, 0x3f);
3155 for (i
= 0; i
< 16; i
++) {
3156 val
= *(uint32_t *)&env
->fpr
[rd
++];
3157 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
3169 val
= *((uint32_t *)&env
->fpr
[rd
]);
3172 val
= *((int64_t *)&DT0
);
3178 helper_st_asi(addr
, val
, asi
, size
);
3181 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
3182 target_ulong val2
, uint32_t asi
)
3186 val2
&= 0xffffffffUL
;
3187 ret
= helper_ld_asi(addr
, asi
, 4, 0);
3188 ret
&= 0xffffffffUL
;
3190 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
3194 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
3195 target_ulong val2
, uint32_t asi
)
3199 ret
= helper_ld_asi(addr
, asi
, 8, 0);
3201 helper_st_asi(addr
, val1
, asi
, 8);
3204 #endif /* TARGET_SPARC64 */
3206 #ifndef TARGET_SPARC64
3207 void helper_rett(void)
3211 if (env
->psret
== 1)
3212 raise_exception(TT_ILL_INSN
);
3215 cwp
= cwp_inc(env
->cwp
+ 1) ;
3216 if (env
->wim
& (1 << cwp
)) {
3217 raise_exception(TT_WIN_UNF
);
3220 env
->psrs
= env
->psrps
;
3224 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
3229 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3233 raise_exception(TT_DIV_ZERO
);
3237 if (x0
> 0xffffffff) {
3246 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
3251 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3255 raise_exception(TT_DIV_ZERO
);
3259 if ((int32_t) x0
!= x0
) {
3261 return x0
< 0? 0x80000000: 0x7fffffff;
3268 void helper_stdf(target_ulong addr
, int mem_idx
)
3270 helper_check_align(addr
, 7);
3271 #if !defined(CONFIG_USER_ONLY)
3274 stfq_user(addr
, DT0
);
3277 stfq_kernel(addr
, DT0
);
3279 #ifdef TARGET_SPARC64
3281 stfq_hypv(addr
, DT0
);
3288 stfq_raw(address_mask(env
, addr
), DT0
);
3292 void helper_lddf(target_ulong addr
, int mem_idx
)
3294 helper_check_align(addr
, 7);
3295 #if !defined(CONFIG_USER_ONLY)
3298 DT0
= ldfq_user(addr
);
3301 DT0
= ldfq_kernel(addr
);
3303 #ifdef TARGET_SPARC64
3305 DT0
= ldfq_hypv(addr
);
3312 DT0
= ldfq_raw(address_mask(env
, addr
));
3316 void helper_ldqf(target_ulong addr
, int mem_idx
)
3318 // XXX add 128 bit load
3321 helper_check_align(addr
, 7);
3322 #if !defined(CONFIG_USER_ONLY)
3325 u
.ll
.upper
= ldq_user(addr
);
3326 u
.ll
.lower
= ldq_user(addr
+ 8);
3330 u
.ll
.upper
= ldq_kernel(addr
);
3331 u
.ll
.lower
= ldq_kernel(addr
+ 8);
3334 #ifdef TARGET_SPARC64
3336 u
.ll
.upper
= ldq_hypv(addr
);
3337 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3345 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
3346 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
3351 void helper_stqf(target_ulong addr
, int mem_idx
)
3353 // XXX add 128 bit store
3356 helper_check_align(addr
, 7);
3357 #if !defined(CONFIG_USER_ONLY)
3361 stq_user(addr
, u
.ll
.upper
);
3362 stq_user(addr
+ 8, u
.ll
.lower
);
3366 stq_kernel(addr
, u
.ll
.upper
);
3367 stq_kernel(addr
+ 8, u
.ll
.lower
);
3369 #ifdef TARGET_SPARC64
3372 stq_hypv(addr
, u
.ll
.upper
);
3373 stq_hypv(addr
+ 8, u
.ll
.lower
);
3381 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
3382 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
3386 static inline void set_fsr(void)
3390 switch (env
->fsr
& FSR_RD_MASK
) {
3391 case FSR_RD_NEAREST
:
3392 rnd_mode
= float_round_nearest_even
;
3396 rnd_mode
= float_round_to_zero
;
3399 rnd_mode
= float_round_up
;
3402 rnd_mode
= float_round_down
;
3405 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3408 void helper_ldfsr(uint32_t new_fsr
)
3410 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3414 #ifdef TARGET_SPARC64
3415 void helper_ldxfsr(uint64_t new_fsr
)
3417 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3422 void helper_debug(void)
3424 env
->exception_index
= EXCP_DEBUG
;
3428 #ifndef TARGET_SPARC64
3429 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3431 void helper_save(void)
3435 cwp
= cwp_dec(env
->cwp
- 1);
3436 if (env
->wim
& (1 << cwp
)) {
3437 raise_exception(TT_WIN_OVF
);
3442 void helper_restore(void)
3446 cwp
= cwp_inc(env
->cwp
+ 1);
3447 if (env
->wim
& (1 << cwp
)) {
3448 raise_exception(TT_WIN_UNF
);
3453 void helper_wrpsr(target_ulong new_psr
)
3455 if ((new_psr
& PSR_CWP
) >= env
->nwindows
) {
3456 raise_exception(TT_ILL_INSN
);
3458 cpu_put_psr(env
, new_psr
);
3462 target_ulong
helper_rdpsr(void)
3468 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3470 void helper_save(void)
3474 cwp
= cwp_dec(env
->cwp
- 1);
3475 if (env
->cansave
== 0) {
3476 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3477 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3478 ((env
->wstate
& 0x7) << 2)));
3480 if (env
->cleanwin
- env
->canrestore
== 0) {
3481 // XXX Clean windows without trap
3482 raise_exception(TT_CLRWIN
);
3491 void helper_restore(void)
3495 cwp
= cwp_inc(env
->cwp
+ 1);
3496 if (env
->canrestore
== 0) {
3497 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3498 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3499 ((env
->wstate
& 0x7) << 2)));
3507 void helper_flushw(void)
3509 if (env
->cansave
!= env
->nwindows
- 2) {
3510 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3511 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3512 ((env
->wstate
& 0x7) << 2)));
3516 void helper_saved(void)
3519 if (env
->otherwin
== 0)
3525 void helper_restored(void)
3528 if (env
->cleanwin
< env
->nwindows
- 1)
3530 if (env
->otherwin
== 0)
3536 static target_ulong
get_ccr(void)
3542 return ((env
->xcc
>> 20) << 4) | ((psr
& PSR_ICC
) >> 20);
3545 target_ulong
cpu_get_ccr(CPUState
*env1
)
3547 CPUState
*saved_env
;
3557 static void put_ccr(target_ulong val
)
3559 target_ulong tmp
= val
;
3561 env
->xcc
= (tmp
>> 4) << 20;
3562 env
->psr
= (tmp
& 0xf) << 20;
3563 CC_OP
= CC_OP_FLAGS
;
3566 void cpu_put_ccr(CPUState
*env1
, target_ulong val
)
3568 CPUState
*saved_env
;
3576 static target_ulong
get_cwp64(void)
3578 return env
->nwindows
- 1 - env
->cwp
;
3581 target_ulong
cpu_get_cwp64(CPUState
*env1
)
3583 CPUState
*saved_env
;
3593 static void put_cwp64(int cwp
)
3595 if (unlikely(cwp
>= env
->nwindows
|| cwp
< 0)) {
3596 cwp
%= env
->nwindows
;
3598 set_cwp(env
->nwindows
- 1 - cwp
);
3601 void cpu_put_cwp64(CPUState
*env1
, int cwp
)
3603 CPUState
*saved_env
;
3611 target_ulong
helper_rdccr(void)
3616 void helper_wrccr(target_ulong new_ccr
)
3621 // CWP handling is reversed in V9, but we still use the V8 register
3623 target_ulong
helper_rdcwp(void)
3628 void helper_wrcwp(target_ulong new_cwp
)
3633 // This function uses non-native bit order
3634 #define GET_FIELD(X, FROM, TO) \
3635 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3637 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3638 #define GET_FIELD_SP(X, FROM, TO) \
3639 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3641 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3643 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3644 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3645 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3646 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3647 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3648 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3649 (((pixel_addr
>> 55) & 1) << 4) |
3650 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3651 GET_FIELD_SP(pixel_addr
, 11, 12);
3654 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3658 tmp
= addr
+ offset
;
3660 env
->gsr
|= tmp
& 7ULL;
3664 target_ulong
helper_popc(target_ulong val
)
3666 return ctpop64(val
);
3669 static inline uint64_t *get_gregset(uint32_t pstate
)
3673 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3675 (pstate
& PS_IG
) ? " IG" : "",
3676 (pstate
& PS_MG
) ? " MG" : "",
3677 (pstate
& PS_AG
) ? " AG" : "");
3678 /* pass through to normal set of global registers */
3690 static inline void change_pstate(uint32_t new_pstate
)
3692 uint32_t pstate_regs
, new_pstate_regs
;
3693 uint64_t *src
, *dst
;
3695 if (env
->def
->features
& CPU_FEATURE_GL
) {
3696 // PS_AG is not implemented in this case
3697 new_pstate
&= ~PS_AG
;
3700 pstate_regs
= env
->pstate
& 0xc01;
3701 new_pstate_regs
= new_pstate
& 0xc01;
3703 if (new_pstate_regs
!= pstate_regs
) {
3704 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3705 pstate_regs
, new_pstate_regs
);
3706 // Switch global register bank
3707 src
= get_gregset(new_pstate_regs
);
3708 dst
= get_gregset(pstate_regs
);
3709 memcpy32(dst
, env
->gregs
);
3710 memcpy32(env
->gregs
, src
);
3713 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3716 env
->pstate
= new_pstate
;
3719 void helper_wrpstate(target_ulong new_state
)
3721 change_pstate(new_state
& 0xf3f);
3723 #if !defined(CONFIG_USER_ONLY)
3724 if (cpu_interrupts_enabled(env
)) {
3725 cpu_check_irqs(env
);
3730 void helper_wrpil(target_ulong new_pil
)
3732 #if !defined(CONFIG_USER_ONLY)
3733 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3734 env
->psrpil
, (uint32_t)new_pil
);
3736 env
->psrpil
= new_pil
;
3738 if (cpu_interrupts_enabled(env
)) {
3739 cpu_check_irqs(env
);
3744 void helper_done(void)
3746 trap_state
* tsptr
= cpu_tsptr(env
);
3748 env
->pc
= tsptr
->tnpc
;
3749 env
->npc
= tsptr
->tnpc
+ 4;
3750 put_ccr(tsptr
->tstate
>> 32);
3751 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3752 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3753 put_cwp64(tsptr
->tstate
& 0xff);
3756 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
3758 #if !defined(CONFIG_USER_ONLY)
3759 if (cpu_interrupts_enabled(env
)) {
3760 cpu_check_irqs(env
);
3765 void helper_retry(void)
3767 trap_state
* tsptr
= cpu_tsptr(env
);
3769 env
->pc
= tsptr
->tpc
;
3770 env
->npc
= tsptr
->tnpc
;
3771 put_ccr(tsptr
->tstate
>> 32);
3772 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3773 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3774 put_cwp64(tsptr
->tstate
& 0xff);
3777 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
3779 #if !defined(CONFIG_USER_ONLY)
3780 if (cpu_interrupts_enabled(env
)) {
3781 cpu_check_irqs(env
);
3786 static void do_modify_softint(const char* operation
, uint32_t value
)
3788 if (env
->softint
!= value
) {
3789 env
->softint
= value
;
3790 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
3791 #if !defined(CONFIG_USER_ONLY)
3792 if (cpu_interrupts_enabled(env
)) {
3793 cpu_check_irqs(env
);
3799 void helper_set_softint(uint64_t value
)
3801 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
3804 void helper_clear_softint(uint64_t value
)
3806 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
3809 void helper_write_softint(uint64_t value
)
3811 do_modify_softint("helper_write_softint", (uint32_t)value
);
3815 void helper_flush(target_ulong addr
)
3818 tb_invalidate_page_range(addr
, addr
+ 8);
3821 #ifdef TARGET_SPARC64
3823 static const char * const excp_names
[0x80] = {
3824 [TT_TFAULT
] = "Instruction Access Fault",
3825 [TT_TMISS
] = "Instruction Access MMU Miss",
3826 [TT_CODE_ACCESS
] = "Instruction Access Error",
3827 [TT_ILL_INSN
] = "Illegal Instruction",
3828 [TT_PRIV_INSN
] = "Privileged Instruction",
3829 [TT_NFPU_INSN
] = "FPU Disabled",
3830 [TT_FP_EXCP
] = "FPU Exception",
3831 [TT_TOVF
] = "Tag Overflow",
3832 [TT_CLRWIN
] = "Clean Windows",
3833 [TT_DIV_ZERO
] = "Division By Zero",
3834 [TT_DFAULT
] = "Data Access Fault",
3835 [TT_DMISS
] = "Data Access MMU Miss",
3836 [TT_DATA_ACCESS
] = "Data Access Error",
3837 [TT_DPROT
] = "Data Protection Error",
3838 [TT_UNALIGNED
] = "Unaligned Memory Access",
3839 [TT_PRIV_ACT
] = "Privileged Action",
3840 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3841 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3842 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3843 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3844 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3845 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3846 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3847 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3848 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3849 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3850 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3851 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3852 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3853 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3854 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3858 trap_state
* cpu_tsptr(CPUState
* env
)
3860 return &env
->ts
[env
->tl
& MAXTL_MASK
];
3863 void do_interrupt(CPUState
*env
)
3865 int intno
= env
->exception_index
;
3869 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3873 if (intno
< 0 || intno
>= 0x180)
3875 else if (intno
>= 0x100)
3876 name
= "Trap Instruction";
3877 else if (intno
>= 0xc0)
3878 name
= "Window Fill";
3879 else if (intno
>= 0x80)
3880 name
= "Window Spill";
3882 name
= excp_names
[intno
];
3887 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
3888 " SP=%016" PRIx64
"\n",
3891 env
->npc
, env
->regwptr
[6]);
3892 log_cpu_state(env
, 0);
3899 ptr
= (uint8_t *)env
->pc
;
3900 for(i
= 0; i
< 16; i
++) {
3901 qemu_log(" %02x", ldub(ptr
+ i
));
3909 #if !defined(CONFIG_USER_ONLY)
3910 if (env
->tl
>= env
->maxtl
) {
3911 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3912 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
3916 if (env
->tl
< env
->maxtl
- 1) {
3919 env
->pstate
|= PS_RED
;
3920 if (env
->tl
< env
->maxtl
)
3923 tsptr
= cpu_tsptr(env
);
3925 tsptr
->tstate
= (get_ccr() << 32) |
3926 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
3928 tsptr
->tpc
= env
->pc
;
3929 tsptr
->tnpc
= env
->npc
;
3934 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
3938 case TT_TMISS
... TT_TMISS
+ 3:
3939 case TT_DMISS
... TT_DMISS
+ 3:
3940 case TT_DPROT
... TT_DPROT
+ 3:
3941 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
3944 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
3948 if (intno
== TT_CLRWIN
) {
3949 set_cwp(cwp_dec(env
->cwp
- 1));
3950 } else if ((intno
& 0x1c0) == TT_SPILL
) {
3951 set_cwp(cwp_dec(env
->cwp
- env
->cansave
- 2));
3952 } else if ((intno
& 0x1c0) == TT_FILL
) {
3953 set_cwp(cwp_inc(env
->cwp
+ 1));
3955 env
->tbr
&= ~0x7fffULL
;
3956 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
3958 env
->npc
= env
->pc
+ 4;
3959 env
->exception_index
= -1;
3963 static const char * const excp_names
[0x80] = {
3964 [TT_TFAULT
] = "Instruction Access Fault",
3965 [TT_ILL_INSN
] = "Illegal Instruction",
3966 [TT_PRIV_INSN
] = "Privileged Instruction",
3967 [TT_NFPU_INSN
] = "FPU Disabled",
3968 [TT_WIN_OVF
] = "Window Overflow",
3969 [TT_WIN_UNF
] = "Window Underflow",
3970 [TT_UNALIGNED
] = "Unaligned Memory Access",
3971 [TT_FP_EXCP
] = "FPU Exception",
3972 [TT_DFAULT
] = "Data Access Fault",
3973 [TT_TOVF
] = "Tag Overflow",
3974 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3975 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3976 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3977 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3978 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3979 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3980 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3981 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3982 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3983 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3984 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3985 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3986 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3987 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3988 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3989 [TT_TOVF
] = "Tag Overflow",
3990 [TT_CODE_ACCESS
] = "Instruction Access Error",
3991 [TT_DATA_ACCESS
] = "Data Access Error",
3992 [TT_DIV_ZERO
] = "Division By Zero",
3993 [TT_NCP_INSN
] = "Coprocessor Disabled",
3997 void do_interrupt(CPUState
*env
)
3999 int cwp
, intno
= env
->exception_index
;
4002 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
4006 if (intno
< 0 || intno
>= 0x100)
4008 else if (intno
>= 0x80)
4009 name
= "Trap Instruction";
4011 name
= excp_names
[intno
];
4016 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
4019 env
->npc
, env
->regwptr
[6]);
4020 log_cpu_state(env
, 0);
4027 ptr
= (uint8_t *)env
->pc
;
4028 for(i
= 0; i
< 16; i
++) {
4029 qemu_log(" %02x", ldub(ptr
+ i
));
4037 #if !defined(CONFIG_USER_ONLY)
4038 if (env
->psret
== 0) {
4039 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
4040 env
->exception_index
);
4045 cwp
= cwp_dec(env
->cwp
- 1);
4047 env
->regwptr
[9] = env
->pc
;
4048 env
->regwptr
[10] = env
->npc
;
4049 env
->psrps
= env
->psrs
;
4051 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
4053 env
->npc
= env
->pc
+ 4;
4054 env
->exception_index
= -1;
4058 #if !defined(CONFIG_USER_ONLY)
4060 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4063 #define MMUSUFFIX _mmu
4064 #define ALIGNED_ONLY
4067 #include "softmmu_template.h"
4070 #include "softmmu_template.h"
4073 #include "softmmu_template.h"
4076 #include "softmmu_template.h"
4078 /* XXX: make it generic ? */
4079 static void cpu_restore_state2(void *retaddr
)
4081 TranslationBlock
*tb
;
4085 /* now we have a real cpu fault */
4086 pc
= (unsigned long)retaddr
;
4087 tb
= tb_find_pc(pc
);
4089 /* the PC is inside the translated code. It means that we have
4090 a virtual CPU fault */
4091 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
4096 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4099 #ifdef DEBUG_UNALIGNED
4100 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
4101 "\n", addr
, env
->pc
);
4103 cpu_restore_state2(retaddr
);
4104 raise_exception(TT_UNALIGNED
);
4107 /* try to fill the TLB and return an exception if error. If retaddr is
4108 NULL, it means that the function was called in C code (i.e. not
4109 from generated code or from helper.c) */
4110 /* XXX: fix it to restore all registers */
4111 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
4114 CPUState
*saved_env
;
4116 /* XXX: hack to restore env in all cases, even if not called from
4119 env
= cpu_single_env
;
4121 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
4123 cpu_restore_state2(retaddr
);
4129 #endif /* !CONFIG_USER_ONLY */
4131 #ifndef TARGET_SPARC64
4132 #if !defined(CONFIG_USER_ONLY)
4133 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4134 int is_asi
, int size
)
4136 CPUState
*saved_env
;
4139 /* XXX: hack to restore env in all cases, even if not called from
4142 env
= cpu_single_env
;
4143 #ifdef DEBUG_UNASSIGNED
4145 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4146 " asi 0x%02x from " TARGET_FMT_lx
"\n",
4147 is_exec
? "exec" : is_write
? "write" : "read", size
,
4148 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
4150 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4151 " from " TARGET_FMT_lx
"\n",
4152 is_exec
? "exec" : is_write
? "write" : "read", size
,
4153 size
== 1 ? "" : "s", addr
, env
->pc
);
4155 /* Don't overwrite translation and access faults */
4156 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
4157 if ((fault_type
> 4) || (fault_type
== 0)) {
4158 env
->mmuregs
[3] = 0; /* Fault status register */
4160 env
->mmuregs
[3] |= 1 << 16;
4162 env
->mmuregs
[3] |= 1 << 5;
4164 env
->mmuregs
[3] |= 1 << 6;
4166 env
->mmuregs
[3] |= 1 << 7;
4167 env
->mmuregs
[3] |= (5 << 2) | 2;
4168 /* SuperSPARC will never place instruction fault addresses in the FAR */
4170 env
->mmuregs
[4] = addr
; /* Fault address register */
4173 /* overflow (same type fault was not read before another fault) */
4174 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
4175 env
->mmuregs
[3] |= 1;
4178 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
4180 raise_exception(TT_CODE_ACCESS
);
4182 raise_exception(TT_DATA_ACCESS
);
4185 /* flush neverland mappings created during no-fault mode,
4186 so the sequential MMU faults report proper fault types */
4187 if (env
->mmuregs
[0] & MMU_NF
) {
4195 #if defined(CONFIG_USER_ONLY)
4196 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
4197 int is_asi
, int size
)
4199 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4200 int is_asi
, int size
)
4203 CPUState
*saved_env
;
4205 /* XXX: hack to restore env in all cases, even if not called from
4208 env
= cpu_single_env
;
4210 #ifdef DEBUG_UNASSIGNED
4211 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
4212 "\n", addr
, env
->pc
);
4216 raise_exception(TT_CODE_ACCESS
);
4218 raise_exception(TT_DATA_ACCESS
);
4225 #ifdef TARGET_SPARC64
4226 void helper_tick_set_count(void *opaque
, uint64_t count
)
4228 #if !defined(CONFIG_USER_ONLY)
4229 cpu_tick_set_count(opaque
, count
);
4233 uint64_t helper_tick_get_count(void *opaque
)
4235 #if !defined(CONFIG_USER_ONLY)
4236 return cpu_tick_get_count(opaque
);
4242 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
4244 #if !defined(CONFIG_USER_ONLY)
4245 cpu_tick_set_limit(opaque
, limit
);