4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 #define DYNAMIC_PC 1 /* dynamic pc value */
38 #define JUMP_PC 2 /* dynamic pc value which takes only two values
39 according to jump_pc[T2] */
41 /* global register indexes */
42 static TCGv_ptr cpu_env
, cpu_regwptr
;
43 static TCGv cpu_cc_src
, cpu_cc_src2
, cpu_cc_dst
;
44 static TCGv_i32 cpu_cc_op
;
45 static TCGv_i32 cpu_psr
;
46 static TCGv cpu_fsr
, cpu_pc
, cpu_npc
, cpu_gregs
[8];
48 #ifndef CONFIG_USER_ONLY
51 static TCGv cpu_cond
, cpu_dst
;
53 static TCGv_i32 cpu_xcc
, cpu_asi
, cpu_fprs
;
55 static TCGv cpu_tick_cmpr
, cpu_stick_cmpr
, cpu_hstick_cmpr
;
56 static TCGv cpu_hintp
, cpu_htba
, cpu_hver
, cpu_ssr
, cpu_ver
;
57 static TCGv_i32 cpu_softint
;
61 /* local register indexes (only used inside old micro ops) */
63 static TCGv_i32 cpu_tmp32
;
64 static TCGv_i64 cpu_tmp64
;
65 /* Floating point registers */
66 static TCGv_i64 cpu_fpr
[TARGET_DPREGS
];
68 static target_ulong gen_opc_npc
[OPC_BUF_SIZE
];
69 static target_ulong gen_opc_jump_pc
[2];
71 #include "gen-icount.h"
73 typedef struct DisasContext
{
74 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
75 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
76 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
80 int address_mask_32bit
;
82 uint32_t cc_op
; /* current CC operation */
83 struct TranslationBlock
*tb
;
98 // This function uses non-native bit order
99 #define GET_FIELD(X, FROM, TO) \
100 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
102 // This function uses the order in the manuals, i.e. bit 0 is 2^0
103 #define GET_FIELD_SP(X, FROM, TO) \
104 GET_FIELD(X, 31 - (TO), 31 - (FROM))
106 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
107 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
109 #ifdef TARGET_SPARC64
110 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
111 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
113 #define DFPREG(r) (r & 0x1e)
114 #define QFPREG(r) (r & 0x1c)
117 #define UA2005_HTRAP_MASK 0xff
118 #define V8_TRAP_MASK 0x7f
120 static int sign_extend(int x
, int len
)
123 return (x
<< len
) >> len
;
126 #define IS_IMM (insn & (1<<13))
128 static inline TCGv_i32
get_temp_i32(DisasContext
*dc
)
131 assert(dc
->n_t32
< ARRAY_SIZE(dc
->t32
));
132 dc
->t32
[dc
->n_t32
++] = t
= tcg_temp_new_i32();
136 static inline TCGv
get_temp_tl(DisasContext
*dc
)
139 assert(dc
->n_ttl
< ARRAY_SIZE(dc
->ttl
));
140 dc
->ttl
[dc
->n_ttl
++] = t
= tcg_temp_new();
144 static inline void gen_update_fprs_dirty(int rd
)
146 #if defined(TARGET_SPARC64)
147 tcg_gen_ori_i32(cpu_fprs
, cpu_fprs
, (rd
< 32) ? 1 : 2);
151 /* floating point registers moves */
152 static TCGv_i32
gen_load_fpr_F(DisasContext
*dc
, unsigned int src
)
154 #if TCG_TARGET_REG_BITS == 32
156 return TCGV_LOW(cpu_fpr
[src
/ 2]);
158 return TCGV_HIGH(cpu_fpr
[src
/ 2]);
162 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr
[src
/ 2]));
164 TCGv_i32 ret
= get_temp_i32(dc
);
165 TCGv_i64 t
= tcg_temp_new_i64();
167 tcg_gen_shri_i64(t
, cpu_fpr
[src
/ 2], 32);
168 tcg_gen_trunc_i64_i32(ret
, t
);
169 tcg_temp_free_i64(t
);
176 static void gen_store_fpr_F(DisasContext
*dc
, unsigned int dst
, TCGv_i32 v
)
178 #if TCG_TARGET_REG_BITS == 32
180 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr
[dst
/ 2]), v
);
182 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr
[dst
/ 2]), v
);
185 TCGv_i64 t
= MAKE_TCGV_I64(GET_TCGV_I32(v
));
186 tcg_gen_deposit_i64(cpu_fpr
[dst
/ 2], cpu_fpr
[dst
/ 2], t
,
187 (dst
& 1 ? 0 : 32), 32);
189 gen_update_fprs_dirty(dst
);
192 static TCGv_i32
gen_dest_fpr_F(DisasContext
*dc
)
194 return get_temp_i32(dc
);
197 static TCGv_i64
gen_load_fpr_D(DisasContext
*dc
, unsigned int src
)
200 return cpu_fpr
[src
/ 2];
203 static void gen_store_fpr_D(DisasContext
*dc
, unsigned int dst
, TCGv_i64 v
)
206 tcg_gen_mov_i64(cpu_fpr
[dst
/ 2], v
);
207 gen_update_fprs_dirty(dst
);
210 static TCGv_i64
gen_dest_fpr_D(void)
215 static void gen_op_load_fpr_QT0(unsigned int src
)
217 tcg_gen_st_i64(cpu_fpr
[src
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
218 offsetof(CPU_QuadU
, ll
.upper
));
219 tcg_gen_st_i64(cpu_fpr
[src
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
220 offsetof(CPU_QuadU
, ll
.lower
));
223 static void gen_op_load_fpr_QT1(unsigned int src
)
225 tcg_gen_st_i64(cpu_fpr
[src
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt1
) +
226 offsetof(CPU_QuadU
, ll
.upper
));
227 tcg_gen_st_i64(cpu_fpr
[src
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt1
) +
228 offsetof(CPU_QuadU
, ll
.lower
));
231 static void gen_op_store_QT0_fpr(unsigned int dst
)
233 tcg_gen_ld_i64(cpu_fpr
[dst
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
234 offsetof(CPU_QuadU
, ll
.upper
));
235 tcg_gen_ld_i64(cpu_fpr
[dst
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
236 offsetof(CPU_QuadU
, ll
.lower
));
239 #ifdef TARGET_SPARC64
240 static void gen_move_Q(unsigned int rd
, unsigned int rs
)
245 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2], cpu_fpr
[rs
/ 2]);
246 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2 + 1], cpu_fpr
[rs
/ 2 + 1]);
247 gen_update_fprs_dirty(rd
);
252 #ifdef CONFIG_USER_ONLY
253 #define supervisor(dc) 0
254 #ifdef TARGET_SPARC64
255 #define hypervisor(dc) 0
258 #define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
259 #ifdef TARGET_SPARC64
260 #define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
265 #ifdef TARGET_SPARC64
267 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
269 #define AM_CHECK(dc) (1)
273 static inline void gen_address_mask(DisasContext
*dc
, TCGv addr
)
275 #ifdef TARGET_SPARC64
277 tcg_gen_andi_tl(addr
, addr
, 0xffffffffULL
);
281 static inline TCGv
gen_load_gpr(DisasContext
*dc
, int reg
)
283 if (reg
== 0 || reg
>= 8) {
284 TCGv t
= get_temp_tl(dc
);
286 tcg_gen_movi_tl(t
, 0);
288 tcg_gen_ld_tl(t
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
292 return cpu_gregs
[reg
];
296 static inline void gen_store_gpr(DisasContext
*dc
, int reg
, TCGv v
)
300 tcg_gen_mov_tl(cpu_gregs
[reg
], v
);
302 tcg_gen_st_tl(v
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
307 static inline TCGv
gen_dest_gpr(DisasContext
*dc
, int reg
)
309 if (reg
== 0 || reg
>= 8) {
310 return get_temp_tl(dc
);
312 return cpu_gregs
[reg
];
316 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
,
317 target_ulong pc
, target_ulong npc
)
319 TranslationBlock
*tb
;
322 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
323 (npc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
325 /* jump to same page: we can use a direct jump */
326 tcg_gen_goto_tb(tb_num
);
327 tcg_gen_movi_tl(cpu_pc
, pc
);
328 tcg_gen_movi_tl(cpu_npc
, npc
);
329 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
331 /* jump to another page: currently not optimized */
332 tcg_gen_movi_tl(cpu_pc
, pc
);
333 tcg_gen_movi_tl(cpu_npc
, npc
);
339 static inline void gen_mov_reg_N(TCGv reg
, TCGv_i32 src
)
341 tcg_gen_extu_i32_tl(reg
, src
);
342 tcg_gen_shri_tl(reg
, reg
, PSR_NEG_SHIFT
);
343 tcg_gen_andi_tl(reg
, reg
, 0x1);
346 static inline void gen_mov_reg_Z(TCGv reg
, TCGv_i32 src
)
348 tcg_gen_extu_i32_tl(reg
, src
);
349 tcg_gen_shri_tl(reg
, reg
, PSR_ZERO_SHIFT
);
350 tcg_gen_andi_tl(reg
, reg
, 0x1);
353 static inline void gen_mov_reg_V(TCGv reg
, TCGv_i32 src
)
355 tcg_gen_extu_i32_tl(reg
, src
);
356 tcg_gen_shri_tl(reg
, reg
, PSR_OVF_SHIFT
);
357 tcg_gen_andi_tl(reg
, reg
, 0x1);
360 static inline void gen_mov_reg_C(TCGv reg
, TCGv_i32 src
)
362 tcg_gen_extu_i32_tl(reg
, src
);
363 tcg_gen_shri_tl(reg
, reg
, PSR_CARRY_SHIFT
);
364 tcg_gen_andi_tl(reg
, reg
, 0x1);
367 static inline void gen_op_addi_cc(TCGv dst
, TCGv src1
, target_long src2
)
369 tcg_gen_mov_tl(cpu_cc_src
, src1
);
370 tcg_gen_movi_tl(cpu_cc_src2
, src2
);
371 tcg_gen_addi_tl(cpu_cc_dst
, cpu_cc_src
, src2
);
372 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
375 static inline void gen_op_add_cc(TCGv dst
, TCGv src1
, TCGv src2
)
377 tcg_gen_mov_tl(cpu_cc_src
, src1
);
378 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
379 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
380 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
383 static TCGv_i32
gen_add32_carry32(void)
385 TCGv_i32 carry_32
, cc_src1_32
, cc_src2_32
;
387 /* Carry is computed from a previous add: (dst < src) */
388 #if TARGET_LONG_BITS == 64
389 cc_src1_32
= tcg_temp_new_i32();
390 cc_src2_32
= tcg_temp_new_i32();
391 tcg_gen_trunc_i64_i32(cc_src1_32
, cpu_cc_dst
);
392 tcg_gen_trunc_i64_i32(cc_src2_32
, cpu_cc_src
);
394 cc_src1_32
= cpu_cc_dst
;
395 cc_src2_32
= cpu_cc_src
;
398 carry_32
= tcg_temp_new_i32();
399 tcg_gen_setcond_i32(TCG_COND_LTU
, carry_32
, cc_src1_32
, cc_src2_32
);
401 #if TARGET_LONG_BITS == 64
402 tcg_temp_free_i32(cc_src1_32
);
403 tcg_temp_free_i32(cc_src2_32
);
409 static TCGv_i32
gen_sub32_carry32(void)
411 TCGv_i32 carry_32
, cc_src1_32
, cc_src2_32
;
413 /* Carry is computed from a previous borrow: (src1 < src2) */
414 #if TARGET_LONG_BITS == 64
415 cc_src1_32
= tcg_temp_new_i32();
416 cc_src2_32
= tcg_temp_new_i32();
417 tcg_gen_trunc_i64_i32(cc_src1_32
, cpu_cc_src
);
418 tcg_gen_trunc_i64_i32(cc_src2_32
, cpu_cc_src2
);
420 cc_src1_32
= cpu_cc_src
;
421 cc_src2_32
= cpu_cc_src2
;
424 carry_32
= tcg_temp_new_i32();
425 tcg_gen_setcond_i32(TCG_COND_LTU
, carry_32
, cc_src1_32
, cc_src2_32
);
427 #if TARGET_LONG_BITS == 64
428 tcg_temp_free_i32(cc_src1_32
);
429 tcg_temp_free_i32(cc_src2_32
);
435 static void gen_op_addx_int(DisasContext
*dc
, TCGv dst
, TCGv src1
,
436 TCGv src2
, int update_cc
)
444 /* Carry is known to be zero. Fall back to plain ADD. */
446 gen_op_add_cc(dst
, src1
, src2
);
448 tcg_gen_add_tl(dst
, src1
, src2
);
455 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
457 /* For 32-bit hosts, we can re-use the host's hardware carry
458 generation by using an ADD2 opcode. We discard the low
459 part of the output. Ideally we'd combine this operation
460 with the add that generated the carry in the first place. */
461 TCGv dst_low
= tcg_temp_new();
462 tcg_gen_op6_i32(INDEX_op_add2_i32
, dst_low
, dst
,
463 cpu_cc_src
, src1
, cpu_cc_src2
, src2
);
464 tcg_temp_free(dst_low
);
468 carry_32
= gen_add32_carry32();
474 carry_32
= gen_sub32_carry32();
478 /* We need external help to produce the carry. */
479 carry_32
= tcg_temp_new_i32();
480 gen_helper_compute_C_icc(carry_32
, cpu_env
);
484 #if TARGET_LONG_BITS == 64
485 carry
= tcg_temp_new();
486 tcg_gen_extu_i32_i64(carry
, carry_32
);
491 tcg_gen_add_tl(dst
, src1
, src2
);
492 tcg_gen_add_tl(dst
, dst
, carry
);
494 tcg_temp_free_i32(carry_32
);
495 #if TARGET_LONG_BITS == 64
496 tcg_temp_free(carry
);
499 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
503 tcg_gen_mov_tl(cpu_cc_src
, src1
);
504 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
505 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
506 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADDX
);
507 dc
->cc_op
= CC_OP_ADDX
;
511 static inline void gen_op_subi_cc(TCGv dst
, TCGv src1
, target_long src2
, DisasContext
*dc
)
513 tcg_gen_mov_tl(cpu_cc_src
, src1
);
514 tcg_gen_movi_tl(cpu_cc_src2
, src2
);
516 tcg_gen_mov_tl(cpu_cc_dst
, src1
);
517 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
518 dc
->cc_op
= CC_OP_LOGIC
;
520 tcg_gen_subi_tl(cpu_cc_dst
, cpu_cc_src
, src2
);
521 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
522 dc
->cc_op
= CC_OP_SUB
;
524 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
527 static inline void gen_op_sub_cc(TCGv dst
, TCGv src1
, TCGv src2
)
529 tcg_gen_mov_tl(cpu_cc_src
, src1
);
530 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
531 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
532 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
535 static void gen_op_subx_int(DisasContext
*dc
, TCGv dst
, TCGv src1
,
536 TCGv src2
, int update_cc
)
544 /* Carry is known to be zero. Fall back to plain SUB. */
546 gen_op_sub_cc(dst
, src1
, src2
);
548 tcg_gen_sub_tl(dst
, src1
, src2
);
555 carry_32
= gen_add32_carry32();
561 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
563 /* For 32-bit hosts, we can re-use the host's hardware carry
564 generation by using a SUB2 opcode. We discard the low
565 part of the output. Ideally we'd combine this operation
566 with the add that generated the carry in the first place. */
567 TCGv dst_low
= tcg_temp_new();
568 tcg_gen_op6_i32(INDEX_op_sub2_i32
, dst_low
, dst
,
569 cpu_cc_src
, src1
, cpu_cc_src2
, src2
);
570 tcg_temp_free(dst_low
);
574 carry_32
= gen_sub32_carry32();
578 /* We need external help to produce the carry. */
579 carry_32
= tcg_temp_new_i32();
580 gen_helper_compute_C_icc(carry_32
, cpu_env
);
584 #if TARGET_LONG_BITS == 64
585 carry
= tcg_temp_new();
586 tcg_gen_extu_i32_i64(carry
, carry_32
);
591 tcg_gen_sub_tl(dst
, src1
, src2
);
592 tcg_gen_sub_tl(dst
, dst
, carry
);
594 tcg_temp_free_i32(carry_32
);
595 #if TARGET_LONG_BITS == 64
596 tcg_temp_free(carry
);
599 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
603 tcg_gen_mov_tl(cpu_cc_src
, src1
);
604 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
605 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
606 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUBX
);
607 dc
->cc_op
= CC_OP_SUBX
;
611 static inline void gen_op_mulscc(TCGv dst
, TCGv src1
, TCGv src2
)
615 r_temp
= tcg_temp_new();
621 zero
= tcg_const_tl(0);
622 tcg_gen_andi_tl(cpu_cc_src
, src1
, 0xffffffff);
623 tcg_gen_andi_tl(r_temp
, cpu_y
, 0x1);
624 tcg_gen_andi_tl(cpu_cc_src2
, src2
, 0xffffffff);
625 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_cc_src2
, r_temp
, zero
,
630 // env->y = (b2 << 31) | (env->y >> 1);
631 tcg_gen_andi_tl(r_temp
, cpu_cc_src
, 0x1);
632 tcg_gen_shli_tl(r_temp
, r_temp
, 31);
633 tcg_gen_shri_tl(cpu_tmp0
, cpu_y
, 1);
634 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0x7fffffff);
635 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, r_temp
);
636 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
639 gen_mov_reg_N(cpu_tmp0
, cpu_psr
);
640 gen_mov_reg_V(r_temp
, cpu_psr
);
641 tcg_gen_xor_tl(cpu_tmp0
, cpu_tmp0
, r_temp
);
642 tcg_temp_free(r_temp
);
644 // T0 = (b1 << 31) | (T0 >> 1);
646 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, 31);
647 tcg_gen_shri_tl(cpu_cc_src
, cpu_cc_src
, 1);
648 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
650 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
652 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
655 static inline void gen_op_multiply(TCGv dst
, TCGv src1
, TCGv src2
, int sign_ext
)
657 TCGv_i32 r_src1
, r_src2
;
658 TCGv_i64 r_temp
, r_temp2
;
660 r_src1
= tcg_temp_new_i32();
661 r_src2
= tcg_temp_new_i32();
663 tcg_gen_trunc_tl_i32(r_src1
, src1
);
664 tcg_gen_trunc_tl_i32(r_src2
, src2
);
666 r_temp
= tcg_temp_new_i64();
667 r_temp2
= tcg_temp_new_i64();
670 tcg_gen_ext_i32_i64(r_temp
, r_src2
);
671 tcg_gen_ext_i32_i64(r_temp2
, r_src1
);
673 tcg_gen_extu_i32_i64(r_temp
, r_src2
);
674 tcg_gen_extu_i32_i64(r_temp2
, r_src1
);
677 tcg_gen_mul_i64(r_temp2
, r_temp
, r_temp2
);
679 tcg_gen_shri_i64(r_temp
, r_temp2
, 32);
680 tcg_gen_trunc_i64_tl(cpu_tmp0
, r_temp
);
681 tcg_temp_free_i64(r_temp
);
682 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
684 tcg_gen_trunc_i64_tl(dst
, r_temp2
);
686 tcg_temp_free_i64(r_temp2
);
688 tcg_temp_free_i32(r_src1
);
689 tcg_temp_free_i32(r_src2
);
692 static inline void gen_op_umul(TCGv dst
, TCGv src1
, TCGv src2
)
694 /* zero-extend truncated operands before multiplication */
695 gen_op_multiply(dst
, src1
, src2
, 0);
698 static inline void gen_op_smul(TCGv dst
, TCGv src1
, TCGv src2
)
700 /* sign-extend truncated operands before multiplication */
701 gen_op_multiply(dst
, src1
, src2
, 1);
705 static inline void gen_op_eval_ba(TCGv dst
)
707 tcg_gen_movi_tl(dst
, 1);
711 static inline void gen_op_eval_be(TCGv dst
, TCGv_i32 src
)
713 gen_mov_reg_Z(dst
, src
);
717 static inline void gen_op_eval_ble(TCGv dst
, TCGv_i32 src
)
719 gen_mov_reg_N(cpu_tmp0
, src
);
720 gen_mov_reg_V(dst
, src
);
721 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
722 gen_mov_reg_Z(cpu_tmp0
, src
);
723 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
727 static inline void gen_op_eval_bl(TCGv dst
, TCGv_i32 src
)
729 gen_mov_reg_V(cpu_tmp0
, src
);
730 gen_mov_reg_N(dst
, src
);
731 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
735 static inline void gen_op_eval_bleu(TCGv dst
, TCGv_i32 src
)
737 gen_mov_reg_Z(cpu_tmp0
, src
);
738 gen_mov_reg_C(dst
, src
);
739 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
743 static inline void gen_op_eval_bcs(TCGv dst
, TCGv_i32 src
)
745 gen_mov_reg_C(dst
, src
);
749 static inline void gen_op_eval_bvs(TCGv dst
, TCGv_i32 src
)
751 gen_mov_reg_V(dst
, src
);
755 static inline void gen_op_eval_bn(TCGv dst
)
757 tcg_gen_movi_tl(dst
, 0);
761 static inline void gen_op_eval_bneg(TCGv dst
, TCGv_i32 src
)
763 gen_mov_reg_N(dst
, src
);
767 static inline void gen_op_eval_bne(TCGv dst
, TCGv_i32 src
)
769 gen_mov_reg_Z(dst
, src
);
770 tcg_gen_xori_tl(dst
, dst
, 0x1);
774 static inline void gen_op_eval_bg(TCGv dst
, TCGv_i32 src
)
776 gen_mov_reg_N(cpu_tmp0
, src
);
777 gen_mov_reg_V(dst
, src
);
778 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
779 gen_mov_reg_Z(cpu_tmp0
, src
);
780 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
781 tcg_gen_xori_tl(dst
, dst
, 0x1);
785 static inline void gen_op_eval_bge(TCGv dst
, TCGv_i32 src
)
787 gen_mov_reg_V(cpu_tmp0
, src
);
788 gen_mov_reg_N(dst
, src
);
789 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
790 tcg_gen_xori_tl(dst
, dst
, 0x1);
794 static inline void gen_op_eval_bgu(TCGv dst
, TCGv_i32 src
)
796 gen_mov_reg_Z(cpu_tmp0
, src
);
797 gen_mov_reg_C(dst
, src
);
798 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
799 tcg_gen_xori_tl(dst
, dst
, 0x1);
803 static inline void gen_op_eval_bcc(TCGv dst
, TCGv_i32 src
)
805 gen_mov_reg_C(dst
, src
);
806 tcg_gen_xori_tl(dst
, dst
, 0x1);
810 static inline void gen_op_eval_bpos(TCGv dst
, TCGv_i32 src
)
812 gen_mov_reg_N(dst
, src
);
813 tcg_gen_xori_tl(dst
, dst
, 0x1);
817 static inline void gen_op_eval_bvc(TCGv dst
, TCGv_i32 src
)
819 gen_mov_reg_V(dst
, src
);
820 tcg_gen_xori_tl(dst
, dst
, 0x1);
824 FPSR bit field FCC1 | FCC0:
830 static inline void gen_mov_reg_FCC0(TCGv reg
, TCGv src
,
831 unsigned int fcc_offset
)
833 tcg_gen_shri_tl(reg
, src
, FSR_FCC0_SHIFT
+ fcc_offset
);
834 tcg_gen_andi_tl(reg
, reg
, 0x1);
837 static inline void gen_mov_reg_FCC1(TCGv reg
, TCGv src
,
838 unsigned int fcc_offset
)
840 tcg_gen_shri_tl(reg
, src
, FSR_FCC1_SHIFT
+ fcc_offset
);
841 tcg_gen_andi_tl(reg
, reg
, 0x1);
845 static inline void gen_op_eval_fbne(TCGv dst
, TCGv src
,
846 unsigned int fcc_offset
)
848 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
849 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
850 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
853 // 1 or 2: FCC0 ^ FCC1
854 static inline void gen_op_eval_fblg(TCGv dst
, TCGv src
,
855 unsigned int fcc_offset
)
857 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
858 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
859 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
863 static inline void gen_op_eval_fbul(TCGv dst
, TCGv src
,
864 unsigned int fcc_offset
)
866 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
870 static inline void gen_op_eval_fbl(TCGv dst
, TCGv src
,
871 unsigned int fcc_offset
)
873 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
874 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
875 tcg_gen_xori_tl(cpu_tmp0
, cpu_tmp0
, 0x1);
876 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
880 static inline void gen_op_eval_fbug(TCGv dst
, TCGv src
,
881 unsigned int fcc_offset
)
883 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
887 static inline void gen_op_eval_fbg(TCGv dst
, TCGv src
,
888 unsigned int fcc_offset
)
890 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
891 tcg_gen_xori_tl(dst
, dst
, 0x1);
892 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
893 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
897 static inline void gen_op_eval_fbu(TCGv dst
, TCGv src
,
898 unsigned int fcc_offset
)
900 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
901 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
902 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
906 static inline void gen_op_eval_fbe(TCGv dst
, TCGv src
,
907 unsigned int fcc_offset
)
909 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
910 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
911 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
912 tcg_gen_xori_tl(dst
, dst
, 0x1);
915 // 0 or 3: !(FCC0 ^ FCC1)
916 static inline void gen_op_eval_fbue(TCGv dst
, TCGv src
,
917 unsigned int fcc_offset
)
919 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
920 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
921 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
922 tcg_gen_xori_tl(dst
, dst
, 0x1);
926 static inline void gen_op_eval_fbge(TCGv dst
, TCGv src
,
927 unsigned int fcc_offset
)
929 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
930 tcg_gen_xori_tl(dst
, dst
, 0x1);
933 // !1: !(FCC0 & !FCC1)
934 static inline void gen_op_eval_fbuge(TCGv dst
, TCGv src
,
935 unsigned int fcc_offset
)
937 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
938 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
939 tcg_gen_xori_tl(cpu_tmp0
, cpu_tmp0
, 0x1);
940 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
941 tcg_gen_xori_tl(dst
, dst
, 0x1);
945 static inline void gen_op_eval_fble(TCGv dst
, TCGv src
,
946 unsigned int fcc_offset
)
948 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
949 tcg_gen_xori_tl(dst
, dst
, 0x1);
952 // !2: !(!FCC0 & FCC1)
953 static inline void gen_op_eval_fbule(TCGv dst
, TCGv src
,
954 unsigned int fcc_offset
)
956 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
957 tcg_gen_xori_tl(dst
, dst
, 0x1);
958 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
959 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
960 tcg_gen_xori_tl(dst
, dst
, 0x1);
963 // !3: !(FCC0 & FCC1)
964 static inline void gen_op_eval_fbo(TCGv dst
, TCGv src
,
965 unsigned int fcc_offset
)
967 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
968 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
969 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
970 tcg_gen_xori_tl(dst
, dst
, 0x1);
973 static inline void gen_branch2(DisasContext
*dc
, target_ulong pc1
,
974 target_ulong pc2
, TCGv r_cond
)
978 l1
= gen_new_label();
980 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
982 gen_goto_tb(dc
, 0, pc1
, pc1
+ 4);
985 gen_goto_tb(dc
, 1, pc2
, pc2
+ 4);
988 static inline void gen_branch_a(DisasContext
*dc
, target_ulong pc1
,
989 target_ulong pc2
, TCGv r_cond
)
993 l1
= gen_new_label();
995 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
997 gen_goto_tb(dc
, 0, pc2
, pc1
);
1000 gen_goto_tb(dc
, 1, pc2
+ 4, pc2
+ 8);
1003 static inline void gen_generic_branch(DisasContext
*dc
)
1005 TCGv npc0
= tcg_const_tl(dc
->jump_pc
[0]);
1006 TCGv npc1
= tcg_const_tl(dc
->jump_pc
[1]);
1007 TCGv zero
= tcg_const_tl(0);
1009 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_npc
, cpu_cond
, zero
, npc0
, npc1
);
1011 tcg_temp_free(npc0
);
1012 tcg_temp_free(npc1
);
1013 tcg_temp_free(zero
);
1016 /* call this function before using the condition register as it may
1017 have been set for a jump */
1018 static inline void flush_cond(DisasContext
*dc
)
1020 if (dc
->npc
== JUMP_PC
) {
1021 gen_generic_branch(dc
);
1022 dc
->npc
= DYNAMIC_PC
;
1026 static inline void save_npc(DisasContext
*dc
)
1028 if (dc
->npc
== JUMP_PC
) {
1029 gen_generic_branch(dc
);
1030 dc
->npc
= DYNAMIC_PC
;
1031 } else if (dc
->npc
!= DYNAMIC_PC
) {
1032 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
1036 static inline void update_psr(DisasContext
*dc
)
1038 if (dc
->cc_op
!= CC_OP_FLAGS
) {
1039 dc
->cc_op
= CC_OP_FLAGS
;
1040 gen_helper_compute_psr(cpu_env
);
1044 static inline void save_state(DisasContext
*dc
)
1046 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1050 static inline void gen_mov_pc_npc(DisasContext
*dc
)
1052 if (dc
->npc
== JUMP_PC
) {
1053 gen_generic_branch(dc
);
1054 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1055 dc
->pc
= DYNAMIC_PC
;
1056 } else if (dc
->npc
== DYNAMIC_PC
) {
1057 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1058 dc
->pc
= DYNAMIC_PC
;
1064 static inline void gen_op_next_insn(void)
1066 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1067 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
1070 static void free_compare(DisasCompare
*cmp
)
1073 tcg_temp_free(cmp
->c1
);
1076 tcg_temp_free(cmp
->c2
);
1080 static void gen_compare(DisasCompare
*cmp
, bool xcc
, unsigned int cond
,
1083 static int subcc_cond
[16] = {
1099 -1, /* no overflow */
1102 static int logic_cond
[16] = {
1104 TCG_COND_EQ
, /* eq: Z */
1105 TCG_COND_LE
, /* le: Z | (N ^ V) -> Z | N */
1106 TCG_COND_LT
, /* lt: N ^ V -> N */
1107 TCG_COND_EQ
, /* leu: C | Z -> Z */
1108 TCG_COND_NEVER
, /* ltu: C -> 0 */
1109 TCG_COND_LT
, /* neg: N */
1110 TCG_COND_NEVER
, /* vs: V -> 0 */
1112 TCG_COND_NE
, /* ne: !Z */
1113 TCG_COND_GT
, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1114 TCG_COND_GE
, /* ge: !(N ^ V) -> !N */
1115 TCG_COND_NE
, /* gtu: !(C | Z) -> !Z */
1116 TCG_COND_ALWAYS
, /* geu: !C -> 1 */
1117 TCG_COND_GE
, /* pos: !N */
1118 TCG_COND_ALWAYS
, /* vc: !V -> 1 */
1124 #ifdef TARGET_SPARC64
1134 switch (dc
->cc_op
) {
1136 cmp
->cond
= logic_cond
[cond
];
1138 cmp
->is_bool
= false;
1140 cmp
->c2
= tcg_const_tl(0);
1141 #ifdef TARGET_SPARC64
1144 cmp
->c1
= tcg_temp_new();
1145 tcg_gen_ext32s_tl(cmp
->c1
, cpu_cc_dst
);
1150 cmp
->c1
= cpu_cc_dst
;
1157 cmp
->cond
= (cond
== 6 ? TCG_COND_LT
: TCG_COND_GE
);
1158 goto do_compare_dst_0
;
1160 case 7: /* overflow */
1161 case 15: /* !overflow */
1165 cmp
->cond
= subcc_cond
[cond
];
1166 cmp
->is_bool
= false;
1167 #ifdef TARGET_SPARC64
1169 /* Note that sign-extension works for unsigned compares as
1170 long as both operands are sign-extended. */
1171 cmp
->g1
= cmp
->g2
= false;
1172 cmp
->c1
= tcg_temp_new();
1173 cmp
->c2
= tcg_temp_new();
1174 tcg_gen_ext32s_tl(cmp
->c1
, cpu_cc_src
);
1175 tcg_gen_ext32s_tl(cmp
->c2
, cpu_cc_src2
);
1179 cmp
->g1
= cmp
->g2
= true;
1180 cmp
->c1
= cpu_cc_src
;
1181 cmp
->c2
= cpu_cc_src2
;
1188 gen_helper_compute_psr(cpu_env
);
1189 dc
->cc_op
= CC_OP_FLAGS
;
1193 /* We're going to generate a boolean result. */
1194 cmp
->cond
= TCG_COND_NE
;
1195 cmp
->is_bool
= true;
1196 cmp
->g1
= cmp
->g2
= false;
1197 cmp
->c1
= r_dst
= tcg_temp_new();
1198 cmp
->c2
= tcg_const_tl(0);
1202 gen_op_eval_bn(r_dst
);
1205 gen_op_eval_be(r_dst
, r_src
);
1208 gen_op_eval_ble(r_dst
, r_src
);
1211 gen_op_eval_bl(r_dst
, r_src
);
1214 gen_op_eval_bleu(r_dst
, r_src
);
1217 gen_op_eval_bcs(r_dst
, r_src
);
1220 gen_op_eval_bneg(r_dst
, r_src
);
1223 gen_op_eval_bvs(r_dst
, r_src
);
1226 gen_op_eval_ba(r_dst
);
1229 gen_op_eval_bne(r_dst
, r_src
);
1232 gen_op_eval_bg(r_dst
, r_src
);
1235 gen_op_eval_bge(r_dst
, r_src
);
1238 gen_op_eval_bgu(r_dst
, r_src
);
1241 gen_op_eval_bcc(r_dst
, r_src
);
1244 gen_op_eval_bpos(r_dst
, r_src
);
1247 gen_op_eval_bvc(r_dst
, r_src
);
1254 static void gen_fcompare(DisasCompare
*cmp
, unsigned int cc
, unsigned int cond
)
1256 unsigned int offset
;
1259 /* For now we still generate a straight boolean result. */
1260 cmp
->cond
= TCG_COND_NE
;
1261 cmp
->is_bool
= true;
1262 cmp
->g1
= cmp
->g2
= false;
1263 cmp
->c1
= r_dst
= tcg_temp_new();
1264 cmp
->c2
= tcg_const_tl(0);
1284 gen_op_eval_bn(r_dst
);
1287 gen_op_eval_fbne(r_dst
, cpu_fsr
, offset
);
1290 gen_op_eval_fblg(r_dst
, cpu_fsr
, offset
);
1293 gen_op_eval_fbul(r_dst
, cpu_fsr
, offset
);
1296 gen_op_eval_fbl(r_dst
, cpu_fsr
, offset
);
1299 gen_op_eval_fbug(r_dst
, cpu_fsr
, offset
);
1302 gen_op_eval_fbg(r_dst
, cpu_fsr
, offset
);
1305 gen_op_eval_fbu(r_dst
, cpu_fsr
, offset
);
1308 gen_op_eval_ba(r_dst
);
1311 gen_op_eval_fbe(r_dst
, cpu_fsr
, offset
);
1314 gen_op_eval_fbue(r_dst
, cpu_fsr
, offset
);
1317 gen_op_eval_fbge(r_dst
, cpu_fsr
, offset
);
1320 gen_op_eval_fbuge(r_dst
, cpu_fsr
, offset
);
1323 gen_op_eval_fble(r_dst
, cpu_fsr
, offset
);
1326 gen_op_eval_fbule(r_dst
, cpu_fsr
, offset
);
1329 gen_op_eval_fbo(r_dst
, cpu_fsr
, offset
);
1334 static void gen_cond(TCGv r_dst
, unsigned int cc
, unsigned int cond
,
1338 gen_compare(&cmp
, cc
, cond
, dc
);
1340 /* The interface is to return a boolean in r_dst. */
1342 tcg_gen_mov_tl(r_dst
, cmp
.c1
);
1344 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1350 static void gen_fcond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1353 gen_fcompare(&cmp
, cc
, cond
);
1355 /* The interface is to return a boolean in r_dst. */
1357 tcg_gen_mov_tl(r_dst
, cmp
.c1
);
1359 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1365 #ifdef TARGET_SPARC64
1367 static const int gen_tcg_cond_reg
[8] = {
1378 static void gen_compare_reg(DisasCompare
*cmp
, int cond
, TCGv r_src
)
1380 cmp
->cond
= tcg_invert_cond(gen_tcg_cond_reg
[cond
]);
1381 cmp
->is_bool
= false;
1385 cmp
->c2
= tcg_const_tl(0);
1388 static inline void gen_cond_reg(TCGv r_dst
, int cond
, TCGv r_src
)
1391 gen_compare_reg(&cmp
, cond
, r_src
);
1393 /* The interface is to return a boolean in r_dst. */
1394 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1400 static void do_branch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
)
1402 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1403 target_ulong target
= dc
->pc
+ offset
;
1405 #ifdef TARGET_SPARC64
1406 if (unlikely(AM_CHECK(dc
))) {
1407 target
&= 0xffffffffULL
;
1411 /* unconditional not taken */
1413 dc
->pc
= dc
->npc
+ 4;
1414 dc
->npc
= dc
->pc
+ 4;
1417 dc
->npc
= dc
->pc
+ 4;
1419 } else if (cond
== 0x8) {
1420 /* unconditional taken */
1423 dc
->npc
= dc
->pc
+ 4;
1427 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1431 gen_cond(cpu_cond
, cc
, cond
, dc
);
1433 gen_branch_a(dc
, target
, dc
->npc
, cpu_cond
);
1437 dc
->jump_pc
[0] = target
;
1438 if (unlikely(dc
->npc
== DYNAMIC_PC
)) {
1439 dc
->jump_pc
[1] = DYNAMIC_PC
;
1440 tcg_gen_addi_tl(cpu_pc
, cpu_npc
, 4);
1442 dc
->jump_pc
[1] = dc
->npc
+ 4;
1449 static void do_fbranch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
)
1451 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1452 target_ulong target
= dc
->pc
+ offset
;
1454 #ifdef TARGET_SPARC64
1455 if (unlikely(AM_CHECK(dc
))) {
1456 target
&= 0xffffffffULL
;
1460 /* unconditional not taken */
1462 dc
->pc
= dc
->npc
+ 4;
1463 dc
->npc
= dc
->pc
+ 4;
1466 dc
->npc
= dc
->pc
+ 4;
1468 } else if (cond
== 0x8) {
1469 /* unconditional taken */
1472 dc
->npc
= dc
->pc
+ 4;
1476 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1480 gen_fcond(cpu_cond
, cc
, cond
);
1482 gen_branch_a(dc
, target
, dc
->npc
, cpu_cond
);
1486 dc
->jump_pc
[0] = target
;
1487 if (unlikely(dc
->npc
== DYNAMIC_PC
)) {
1488 dc
->jump_pc
[1] = DYNAMIC_PC
;
1489 tcg_gen_addi_tl(cpu_pc
, cpu_npc
, 4);
1491 dc
->jump_pc
[1] = dc
->npc
+ 4;
1498 #ifdef TARGET_SPARC64
1499 static void do_branch_reg(DisasContext
*dc
, int32_t offset
, uint32_t insn
,
1502 unsigned int cond
= GET_FIELD_SP(insn
, 25, 27), a
= (insn
& (1 << 29));
1503 target_ulong target
= dc
->pc
+ offset
;
1505 if (unlikely(AM_CHECK(dc
))) {
1506 target
&= 0xffffffffULL
;
1509 gen_cond_reg(cpu_cond
, cond
, r_reg
);
1511 gen_branch_a(dc
, target
, dc
->npc
, cpu_cond
);
1515 dc
->jump_pc
[0] = target
;
1516 if (unlikely(dc
->npc
== DYNAMIC_PC
)) {
1517 dc
->jump_pc
[1] = DYNAMIC_PC
;
1518 tcg_gen_addi_tl(cpu_pc
, cpu_npc
, 4);
1520 dc
->jump_pc
[1] = dc
->npc
+ 4;
1526 static inline void gen_op_fcmps(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1530 gen_helper_fcmps(cpu_env
, r_rs1
, r_rs2
);
1533 gen_helper_fcmps_fcc1(cpu_env
, r_rs1
, r_rs2
);
1536 gen_helper_fcmps_fcc2(cpu_env
, r_rs1
, r_rs2
);
1539 gen_helper_fcmps_fcc3(cpu_env
, r_rs1
, r_rs2
);
1544 static inline void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1548 gen_helper_fcmpd(cpu_env
, r_rs1
, r_rs2
);
1551 gen_helper_fcmpd_fcc1(cpu_env
, r_rs1
, r_rs2
);
1554 gen_helper_fcmpd_fcc2(cpu_env
, r_rs1
, r_rs2
);
1557 gen_helper_fcmpd_fcc3(cpu_env
, r_rs1
, r_rs2
);
1562 static inline void gen_op_fcmpq(int fccno
)
1566 gen_helper_fcmpq(cpu_env
);
1569 gen_helper_fcmpq_fcc1(cpu_env
);
1572 gen_helper_fcmpq_fcc2(cpu_env
);
1575 gen_helper_fcmpq_fcc3(cpu_env
);
1580 static inline void gen_op_fcmpes(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1584 gen_helper_fcmpes(cpu_env
, r_rs1
, r_rs2
);
1587 gen_helper_fcmpes_fcc1(cpu_env
, r_rs1
, r_rs2
);
1590 gen_helper_fcmpes_fcc2(cpu_env
, r_rs1
, r_rs2
);
1593 gen_helper_fcmpes_fcc3(cpu_env
, r_rs1
, r_rs2
);
1598 static inline void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1602 gen_helper_fcmped(cpu_env
, r_rs1
, r_rs2
);
1605 gen_helper_fcmped_fcc1(cpu_env
, r_rs1
, r_rs2
);
1608 gen_helper_fcmped_fcc2(cpu_env
, r_rs1
, r_rs2
);
1611 gen_helper_fcmped_fcc3(cpu_env
, r_rs1
, r_rs2
);
1616 static inline void gen_op_fcmpeq(int fccno
)
1620 gen_helper_fcmpeq(cpu_env
);
1623 gen_helper_fcmpeq_fcc1(cpu_env
);
1626 gen_helper_fcmpeq_fcc2(cpu_env
);
1629 gen_helper_fcmpeq_fcc3(cpu_env
);
1636 static inline void gen_op_fcmps(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1638 gen_helper_fcmps(cpu_env
, r_rs1
, r_rs2
);
1641 static inline void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1643 gen_helper_fcmpd(cpu_env
, r_rs1
, r_rs2
);
1646 static inline void gen_op_fcmpq(int fccno
)
1648 gen_helper_fcmpq(cpu_env
);
1651 static inline void gen_op_fcmpes(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1653 gen_helper_fcmpes(cpu_env
, r_rs1
, r_rs2
);
1656 static inline void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1658 gen_helper_fcmped(cpu_env
, r_rs1
, r_rs2
);
1661 static inline void gen_op_fcmpeq(int fccno
)
1663 gen_helper_fcmpeq(cpu_env
);
1667 static inline void gen_op_fpexception_im(int fsr_flags
)
1671 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_NMASK
);
1672 tcg_gen_ori_tl(cpu_fsr
, cpu_fsr
, fsr_flags
);
1673 r_const
= tcg_const_i32(TT_FP_EXCP
);
1674 gen_helper_raise_exception(cpu_env
, r_const
);
1675 tcg_temp_free_i32(r_const
);
1678 static int gen_trap_ifnofpu(DisasContext
*dc
)
1680 #if !defined(CONFIG_USER_ONLY)
1681 if (!dc
->fpu_enabled
) {
1685 r_const
= tcg_const_i32(TT_NFPU_INSN
);
1686 gen_helper_raise_exception(cpu_env
, r_const
);
1687 tcg_temp_free_i32(r_const
);
1695 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1697 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_CEXC_NMASK
);
1700 static inline void gen_fop_FF(DisasContext
*dc
, int rd
, int rs
,
1701 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i32
))
1705 src
= gen_load_fpr_F(dc
, rs
);
1706 dst
= gen_dest_fpr_F(dc
);
1708 gen(dst
, cpu_env
, src
);
1710 gen_store_fpr_F(dc
, rd
, dst
);
1713 static inline void gen_ne_fop_FF(DisasContext
*dc
, int rd
, int rs
,
1714 void (*gen
)(TCGv_i32
, TCGv_i32
))
1718 src
= gen_load_fpr_F(dc
, rs
);
1719 dst
= gen_dest_fpr_F(dc
);
1723 gen_store_fpr_F(dc
, rd
, dst
);
1726 static inline void gen_fop_FFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1727 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
))
1729 TCGv_i32 dst
, src1
, src2
;
1731 src1
= gen_load_fpr_F(dc
, rs1
);
1732 src2
= gen_load_fpr_F(dc
, rs2
);
1733 dst
= gen_dest_fpr_F(dc
);
1735 gen(dst
, cpu_env
, src1
, src2
);
1737 gen_store_fpr_F(dc
, rd
, dst
);
1740 #ifdef TARGET_SPARC64
1741 static inline void gen_ne_fop_FFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1742 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
1744 TCGv_i32 dst
, src1
, src2
;
1746 src1
= gen_load_fpr_F(dc
, rs1
);
1747 src2
= gen_load_fpr_F(dc
, rs2
);
1748 dst
= gen_dest_fpr_F(dc
);
1750 gen(dst
, src1
, src2
);
1752 gen_store_fpr_F(dc
, rd
, dst
);
1756 static inline void gen_fop_DD(DisasContext
*dc
, int rd
, int rs
,
1757 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i64
))
1761 src
= gen_load_fpr_D(dc
, rs
);
1762 dst
= gen_dest_fpr_D();
1764 gen(dst
, cpu_env
, src
);
1766 gen_store_fpr_D(dc
, rd
, dst
);
1769 #ifdef TARGET_SPARC64
1770 static inline void gen_ne_fop_DD(DisasContext
*dc
, int rd
, int rs
,
1771 void (*gen
)(TCGv_i64
, TCGv_i64
))
1775 src
= gen_load_fpr_D(dc
, rs
);
1776 dst
= gen_dest_fpr_D();
1780 gen_store_fpr_D(dc
, rd
, dst
);
1784 static inline void gen_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1785 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
))
1787 TCGv_i64 dst
, src1
, src2
;
1789 src1
= gen_load_fpr_D(dc
, rs1
);
1790 src2
= gen_load_fpr_D(dc
, rs2
);
1791 dst
= gen_dest_fpr_D();
1793 gen(dst
, cpu_env
, src1
, src2
);
1795 gen_store_fpr_D(dc
, rd
, dst
);
1798 #ifdef TARGET_SPARC64
1799 static inline void gen_ne_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1800 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
))
1802 TCGv_i64 dst
, src1
, src2
;
1804 src1
= gen_load_fpr_D(dc
, rs1
);
1805 src2
= gen_load_fpr_D(dc
, rs2
);
1806 dst
= gen_dest_fpr_D();
1808 gen(dst
, src1
, src2
);
1810 gen_store_fpr_D(dc
, rd
, dst
);
1813 static inline void gen_gsr_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1814 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
1816 TCGv_i64 dst
, src1
, src2
;
1818 src1
= gen_load_fpr_D(dc
, rs1
);
1819 src2
= gen_load_fpr_D(dc
, rs2
);
1820 dst
= gen_dest_fpr_D();
1822 gen(dst
, cpu_gsr
, src1
, src2
);
1824 gen_store_fpr_D(dc
, rd
, dst
);
1827 static inline void gen_ne_fop_DDDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1828 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
1830 TCGv_i64 dst
, src0
, src1
, src2
;
1832 src1
= gen_load_fpr_D(dc
, rs1
);
1833 src2
= gen_load_fpr_D(dc
, rs2
);
1834 src0
= gen_load_fpr_D(dc
, rd
);
1835 dst
= gen_dest_fpr_D();
1837 gen(dst
, src0
, src1
, src2
);
1839 gen_store_fpr_D(dc
, rd
, dst
);
1843 static inline void gen_fop_QQ(DisasContext
*dc
, int rd
, int rs
,
1844 void (*gen
)(TCGv_ptr
))
1846 gen_op_load_fpr_QT1(QFPREG(rs
));
1850 gen_op_store_QT0_fpr(QFPREG(rd
));
1851 gen_update_fprs_dirty(QFPREG(rd
));
1854 #ifdef TARGET_SPARC64
1855 static inline void gen_ne_fop_QQ(DisasContext
*dc
, int rd
, int rs
,
1856 void (*gen
)(TCGv_ptr
))
1858 gen_op_load_fpr_QT1(QFPREG(rs
));
1862 gen_op_store_QT0_fpr(QFPREG(rd
));
1863 gen_update_fprs_dirty(QFPREG(rd
));
1867 static inline void gen_fop_QQQ(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1868 void (*gen
)(TCGv_ptr
))
1870 gen_op_load_fpr_QT0(QFPREG(rs1
));
1871 gen_op_load_fpr_QT1(QFPREG(rs2
));
1875 gen_op_store_QT0_fpr(QFPREG(rd
));
1876 gen_update_fprs_dirty(QFPREG(rd
));
1879 static inline void gen_fop_DFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1880 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
, TCGv_i32
))
1883 TCGv_i32 src1
, src2
;
1885 src1
= gen_load_fpr_F(dc
, rs1
);
1886 src2
= gen_load_fpr_F(dc
, rs2
);
1887 dst
= gen_dest_fpr_D();
1889 gen(dst
, cpu_env
, src1
, src2
);
1891 gen_store_fpr_D(dc
, rd
, dst
);
1894 static inline void gen_fop_QDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1895 void (*gen
)(TCGv_ptr
, TCGv_i64
, TCGv_i64
))
1897 TCGv_i64 src1
, src2
;
1899 src1
= gen_load_fpr_D(dc
, rs1
);
1900 src2
= gen_load_fpr_D(dc
, rs2
);
1902 gen(cpu_env
, src1
, src2
);
1904 gen_op_store_QT0_fpr(QFPREG(rd
));
1905 gen_update_fprs_dirty(QFPREG(rd
));
1908 #ifdef TARGET_SPARC64
1909 static inline void gen_fop_DF(DisasContext
*dc
, int rd
, int rs
,
1910 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
))
1915 src
= gen_load_fpr_F(dc
, rs
);
1916 dst
= gen_dest_fpr_D();
1918 gen(dst
, cpu_env
, src
);
1920 gen_store_fpr_D(dc
, rd
, dst
);
1924 static inline void gen_ne_fop_DF(DisasContext
*dc
, int rd
, int rs
,
1925 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
))
1930 src
= gen_load_fpr_F(dc
, rs
);
1931 dst
= gen_dest_fpr_D();
1933 gen(dst
, cpu_env
, src
);
1935 gen_store_fpr_D(dc
, rd
, dst
);
1938 static inline void gen_fop_FD(DisasContext
*dc
, int rd
, int rs
,
1939 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i64
))
1944 src
= gen_load_fpr_D(dc
, rs
);
1945 dst
= gen_dest_fpr_F(dc
);
1947 gen(dst
, cpu_env
, src
);
1949 gen_store_fpr_F(dc
, rd
, dst
);
1952 static inline void gen_fop_FQ(DisasContext
*dc
, int rd
, int rs
,
1953 void (*gen
)(TCGv_i32
, TCGv_ptr
))
1957 gen_op_load_fpr_QT1(QFPREG(rs
));
1958 dst
= gen_dest_fpr_F(dc
);
1962 gen_store_fpr_F(dc
, rd
, dst
);
1965 static inline void gen_fop_DQ(DisasContext
*dc
, int rd
, int rs
,
1966 void (*gen
)(TCGv_i64
, TCGv_ptr
))
1970 gen_op_load_fpr_QT1(QFPREG(rs
));
1971 dst
= gen_dest_fpr_D();
1975 gen_store_fpr_D(dc
, rd
, dst
);
1978 static inline void gen_ne_fop_QF(DisasContext
*dc
, int rd
, int rs
,
1979 void (*gen
)(TCGv_ptr
, TCGv_i32
))
1983 src
= gen_load_fpr_F(dc
, rs
);
1987 gen_op_store_QT0_fpr(QFPREG(rd
));
1988 gen_update_fprs_dirty(QFPREG(rd
));
1991 static inline void gen_ne_fop_QD(DisasContext
*dc
, int rd
, int rs
,
1992 void (*gen
)(TCGv_ptr
, TCGv_i64
))
1996 src
= gen_load_fpr_D(dc
, rs
);
2000 gen_op_store_QT0_fpr(QFPREG(rd
));
2001 gen_update_fprs_dirty(QFPREG(rd
));
2005 #ifdef TARGET_SPARC64
2006 static inline TCGv_i32
gen_get_asi(int insn
, TCGv r_addr
)
2012 r_asi
= tcg_temp_new_i32();
2013 tcg_gen_mov_i32(r_asi
, cpu_asi
);
2015 asi
= GET_FIELD(insn
, 19, 26);
2016 r_asi
= tcg_const_i32(asi
);
2021 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
2024 TCGv_i32 r_asi
, r_size
, r_sign
;
2026 r_asi
= gen_get_asi(insn
, addr
);
2027 r_size
= tcg_const_i32(size
);
2028 r_sign
= tcg_const_i32(sign
);
2029 gen_helper_ld_asi(dst
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2030 tcg_temp_free_i32(r_sign
);
2031 tcg_temp_free_i32(r_size
);
2032 tcg_temp_free_i32(r_asi
);
2035 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
2037 TCGv_i32 r_asi
, r_size
;
2039 r_asi
= gen_get_asi(insn
, addr
);
2040 r_size
= tcg_const_i32(size
);
2041 gen_helper_st_asi(cpu_env
, addr
, src
, r_asi
, r_size
);
2042 tcg_temp_free_i32(r_size
);
2043 tcg_temp_free_i32(r_asi
);
2046 static inline void gen_ldf_asi(TCGv addr
, int insn
, int size
, int rd
)
2048 TCGv_i32 r_asi
, r_size
, r_rd
;
2050 r_asi
= gen_get_asi(insn
, addr
);
2051 r_size
= tcg_const_i32(size
);
2052 r_rd
= tcg_const_i32(rd
);
2053 gen_helper_ldf_asi(cpu_env
, addr
, r_asi
, r_size
, r_rd
);
2054 tcg_temp_free_i32(r_rd
);
2055 tcg_temp_free_i32(r_size
);
2056 tcg_temp_free_i32(r_asi
);
2059 static inline void gen_stf_asi(TCGv addr
, int insn
, int size
, int rd
)
2061 TCGv_i32 r_asi
, r_size
, r_rd
;
2063 r_asi
= gen_get_asi(insn
, addr
);
2064 r_size
= tcg_const_i32(size
);
2065 r_rd
= tcg_const_i32(rd
);
2066 gen_helper_stf_asi(cpu_env
, addr
, r_asi
, r_size
, r_rd
);
2067 tcg_temp_free_i32(r_rd
);
2068 tcg_temp_free_i32(r_size
);
2069 tcg_temp_free_i32(r_asi
);
2072 static inline void gen_swap_asi(TCGv dst
, TCGv src
, TCGv addr
, int insn
)
2074 TCGv_i32 r_asi
, r_size
, r_sign
;
2076 r_asi
= gen_get_asi(insn
, addr
);
2077 r_size
= tcg_const_i32(4);
2078 r_sign
= tcg_const_i32(0);
2079 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2080 tcg_temp_free_i32(r_sign
);
2081 gen_helper_st_asi(cpu_env
, addr
, src
, r_asi
, r_size
);
2082 tcg_temp_free_i32(r_size
);
2083 tcg_temp_free_i32(r_asi
);
2084 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
2087 static inline void gen_ldda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2090 TCGv_i32 r_asi
, r_rd
;
2092 r_asi
= gen_get_asi(insn
, addr
);
2093 r_rd
= tcg_const_i32(rd
);
2094 gen_helper_ldda_asi(cpu_env
, addr
, r_asi
, r_rd
);
2095 tcg_temp_free_i32(r_rd
);
2096 tcg_temp_free_i32(r_asi
);
2099 static inline void gen_stda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2102 TCGv_i32 r_asi
, r_size
;
2103 TCGv lo
= gen_load_gpr(dc
, rd
+ 1);
2105 tcg_gen_concat_tl_i64(cpu_tmp64
, lo
, hi
);
2106 r_asi
= gen_get_asi(insn
, addr
);
2107 r_size
= tcg_const_i32(8);
2108 gen_helper_st_asi(cpu_env
, addr
, cpu_tmp64
, r_asi
, r_size
);
2109 tcg_temp_free_i32(r_size
);
2110 tcg_temp_free_i32(r_asi
);
2113 static inline void gen_cas_asi(DisasContext
*dc
, TCGv addr
,
2114 TCGv val2
, int insn
, int rd
)
2116 TCGv val1
= gen_load_gpr(dc
, rd
);
2117 TCGv dst
= gen_dest_gpr(dc
, rd
);
2118 TCGv_i32 r_asi
= gen_get_asi(insn
, addr
);
2120 gen_helper_cas_asi(dst
, cpu_env
, addr
, val1
, val2
, r_asi
);
2121 tcg_temp_free_i32(r_asi
);
2122 gen_store_gpr(dc
, rd
, dst
);
2125 static inline void gen_casx_asi(DisasContext
*dc
, TCGv addr
,
2126 TCGv val2
, int insn
, int rd
)
2128 TCGv val1
= gen_load_gpr(dc
, rd
);
2129 TCGv dst
= gen_dest_gpr(dc
, rd
);
2130 TCGv_i32 r_asi
= gen_get_asi(insn
, addr
);
2132 gen_helper_casx_asi(dst
, cpu_env
, addr
, val1
, val2
, r_asi
);
2133 tcg_temp_free_i32(r_asi
);
2134 gen_store_gpr(dc
, rd
, dst
);
2137 #elif !defined(CONFIG_USER_ONLY)
2139 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
2142 TCGv_i32 r_asi
, r_size
, r_sign
;
2144 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2145 r_size
= tcg_const_i32(size
);
2146 r_sign
= tcg_const_i32(sign
);
2147 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2148 tcg_temp_free(r_sign
);
2149 tcg_temp_free(r_size
);
2150 tcg_temp_free(r_asi
);
2151 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
2154 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
2156 TCGv_i32 r_asi
, r_size
;
2158 tcg_gen_extu_tl_i64(cpu_tmp64
, src
);
2159 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2160 r_size
= tcg_const_i32(size
);
2161 gen_helper_st_asi(cpu_env
, addr
, cpu_tmp64
, r_asi
, r_size
);
2162 tcg_temp_free(r_size
);
2163 tcg_temp_free(r_asi
);
2166 static inline void gen_swap_asi(TCGv dst
, TCGv src
, TCGv addr
, int insn
)
2168 TCGv_i32 r_asi
, r_size
, r_sign
;
2171 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2172 r_size
= tcg_const_i32(4);
2173 r_sign
= tcg_const_i32(0);
2174 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2175 tcg_temp_free(r_sign
);
2176 r_val
= tcg_temp_new_i64();
2177 tcg_gen_extu_tl_i64(r_val
, src
);
2178 gen_helper_st_asi(cpu_env
, addr
, r_val
, r_asi
, r_size
);
2179 tcg_temp_free_i64(r_val
);
2180 tcg_temp_free(r_size
);
2181 tcg_temp_free(r_asi
);
2182 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
2185 static inline void gen_ldda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2188 TCGv_i32 r_asi
, r_size
, r_sign
;
2191 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2192 r_size
= tcg_const_i32(8);
2193 r_sign
= tcg_const_i32(0);
2194 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2195 tcg_temp_free(r_sign
);
2196 tcg_temp_free(r_size
);
2197 tcg_temp_free(r_asi
);
2199 t
= gen_dest_gpr(dc
, rd
+ 1);
2200 tcg_gen_trunc_i64_tl(t
, cpu_tmp64
);
2201 gen_store_gpr(dc
, rd
+ 1, t
);
2203 tcg_gen_shri_i64(cpu_tmp64
, cpu_tmp64
, 32);
2204 tcg_gen_trunc_i64_tl(hi
, cpu_tmp64
);
2205 gen_store_gpr(dc
, rd
, hi
);
2208 static inline void gen_stda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2211 TCGv_i32 r_asi
, r_size
;
2212 TCGv lo
= gen_load_gpr(dc
, rd
+ 1);
2214 tcg_gen_concat_tl_i64(cpu_tmp64
, lo
, hi
);
2215 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2216 r_size
= tcg_const_i32(8);
2217 gen_helper_st_asi(cpu_env
, addr
, cpu_tmp64
, r_asi
, r_size
);
2218 tcg_temp_free(r_size
);
2219 tcg_temp_free(r_asi
);
2223 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2224 static inline void gen_ldstub_asi(TCGv dst
, TCGv addr
, int insn
)
2227 TCGv_i32 r_asi
, r_size
;
2229 gen_ld_asi(dst
, addr
, insn
, 1, 0);
2231 r_val
= tcg_const_i64(0xffULL
);
2232 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2233 r_size
= tcg_const_i32(1);
2234 gen_helper_st_asi(cpu_env
, addr
, r_val
, r_asi
, r_size
);
2235 tcg_temp_free_i32(r_size
);
2236 tcg_temp_free_i32(r_asi
);
2237 tcg_temp_free_i64(r_val
);
2241 static TCGv
get_src1(DisasContext
*dc
, unsigned int insn
)
2243 unsigned int rs1
= GET_FIELD(insn
, 13, 17);
2244 return gen_load_gpr(dc
, rs1
);
2247 static TCGv
get_src2(DisasContext
*dc
, unsigned int insn
)
2249 if (IS_IMM
) { /* immediate */
2250 target_long simm
= GET_FIELDs(insn
, 19, 31);
2251 TCGv t
= get_temp_tl(dc
);
2252 tcg_gen_movi_tl(t
, simm
);
2254 } else { /* register */
2255 unsigned int rs2
= GET_FIELD(insn
, 27, 31);
2256 return gen_load_gpr(dc
, rs2
);
2260 #ifdef TARGET_SPARC64
2261 static void gen_fmovs(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2263 TCGv_i32 c32
, zero
, dst
, s1
, s2
;
2265 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2266 or fold the comparison down to 32 bits and use movcond_i32. Choose
2268 c32
= tcg_temp_new_i32();
2270 tcg_gen_trunc_i64_i32(c32
, cmp
->c1
);
2272 TCGv_i64 c64
= tcg_temp_new_i64();
2273 tcg_gen_setcond_i64(cmp
->cond
, c64
, cmp
->c1
, cmp
->c2
);
2274 tcg_gen_trunc_i64_i32(c32
, c64
);
2275 tcg_temp_free_i64(c64
);
2278 s1
= gen_load_fpr_F(dc
, rs
);
2279 s2
= gen_load_fpr_F(dc
, rd
);
2280 dst
= gen_dest_fpr_F(dc
);
2281 zero
= tcg_const_i32(0);
2283 tcg_gen_movcond_i32(TCG_COND_NE
, dst
, c32
, zero
, s1
, s2
);
2285 tcg_temp_free_i32(c32
);
2286 tcg_temp_free_i32(zero
);
2287 gen_store_fpr_F(dc
, rd
, dst
);
2290 static void gen_fmovd(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2292 TCGv_i64 dst
= gen_dest_fpr_D();
2293 tcg_gen_movcond_i64(cmp
->cond
, dst
, cmp
->c1
, cmp
->c2
,
2294 gen_load_fpr_D(dc
, rs
),
2295 gen_load_fpr_D(dc
, rd
));
2296 gen_store_fpr_D(dc
, rd
, dst
);
2299 static void gen_fmovq(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2301 int qd
= QFPREG(rd
);
2302 int qs
= QFPREG(rs
);
2304 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2], cmp
->c1
, cmp
->c2
,
2305 cpu_fpr
[qs
/ 2], cpu_fpr
[qd
/ 2]);
2306 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2 + 1], cmp
->c1
, cmp
->c2
,
2307 cpu_fpr
[qs
/ 2 + 1], cpu_fpr
[qd
/ 2 + 1]);
2309 gen_update_fprs_dirty(qd
);
2312 static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr
, TCGv_ptr cpu_env
)
2314 TCGv_i32 r_tl
= tcg_temp_new_i32();
2316 /* load env->tl into r_tl */
2317 tcg_gen_ld_i32(r_tl
, cpu_env
, offsetof(CPUSPARCState
, tl
));
2319 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2320 tcg_gen_andi_i32(r_tl
, r_tl
, MAXTL_MASK
);
2322 /* calculate offset to current trap state from env->ts, reuse r_tl */
2323 tcg_gen_muli_i32(r_tl
, r_tl
, sizeof (trap_state
));
2324 tcg_gen_addi_ptr(r_tsptr
, cpu_env
, offsetof(CPUSPARCState
, ts
));
2326 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2328 TCGv_ptr r_tl_tmp
= tcg_temp_new_ptr();
2329 tcg_gen_ext_i32_ptr(r_tl_tmp
, r_tl
);
2330 tcg_gen_add_ptr(r_tsptr
, r_tsptr
, r_tl_tmp
);
2331 tcg_temp_free_ptr(r_tl_tmp
);
2334 tcg_temp_free_i32(r_tl
);
2337 static void gen_edge(DisasContext
*dc
, TCGv dst
, TCGv s1
, TCGv s2
,
2338 int width
, bool cc
, bool left
)
2340 TCGv lo1
, lo2
, t1
, t2
;
2341 uint64_t amask
, tabl
, tabr
;
2342 int shift
, imask
, omask
;
2345 tcg_gen_mov_tl(cpu_cc_src
, s1
);
2346 tcg_gen_mov_tl(cpu_cc_src2
, s2
);
2347 tcg_gen_sub_tl(cpu_cc_dst
, s1
, s2
);
2348 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
2349 dc
->cc_op
= CC_OP_SUB
;
2352 /* Theory of operation: there are two tables, left and right (not to
2353 be confused with the left and right versions of the opcode). These
2354 are indexed by the low 3 bits of the inputs. To make things "easy",
2355 these tables are loaded into two constants, TABL and TABR below.
2356 The operation index = (input & imask) << shift calculates the index
2357 into the constant, while val = (table >> index) & omask calculates
2358 the value we're looking for. */
2365 tabl
= 0x80c0e0f0f8fcfeffULL
;
2366 tabr
= 0xff7f3f1f0f070301ULL
;
2368 tabl
= 0x0103070f1f3f7fffULL
;
2369 tabr
= 0xfffefcf8f0e0c080ULL
;
2389 tabl
= (2 << 2) | 3;
2390 tabr
= (3 << 2) | 1;
2392 tabl
= (1 << 2) | 3;
2393 tabr
= (3 << 2) | 2;
2400 lo1
= tcg_temp_new();
2401 lo2
= tcg_temp_new();
2402 tcg_gen_andi_tl(lo1
, s1
, imask
);
2403 tcg_gen_andi_tl(lo2
, s2
, imask
);
2404 tcg_gen_shli_tl(lo1
, lo1
, shift
);
2405 tcg_gen_shli_tl(lo2
, lo2
, shift
);
2407 t1
= tcg_const_tl(tabl
);
2408 t2
= tcg_const_tl(tabr
);
2409 tcg_gen_shr_tl(lo1
, t1
, lo1
);
2410 tcg_gen_shr_tl(lo2
, t2
, lo2
);
2411 tcg_gen_andi_tl(dst
, lo1
, omask
);
2412 tcg_gen_andi_tl(lo2
, lo2
, omask
);
2416 amask
&= 0xffffffffULL
;
2418 tcg_gen_andi_tl(s1
, s1
, amask
);
2419 tcg_gen_andi_tl(s2
, s2
, amask
);
2421 /* We want to compute
2422 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2423 We've already done dst = lo1, so this reduces to
2424 dst &= (s1 == s2 ? -1 : lo2)
2429 tcg_gen_setcond_tl(TCG_COND_EQ
, t1
, s1
, s2
);
2430 tcg_gen_neg_tl(t1
, t1
);
2431 tcg_gen_or_tl(lo2
, lo2
, t1
);
2432 tcg_gen_and_tl(dst
, dst
, lo2
);
2440 static void gen_alignaddr(TCGv dst
, TCGv s1
, TCGv s2
, bool left
)
2442 TCGv tmp
= tcg_temp_new();
2444 tcg_gen_add_tl(tmp
, s1
, s2
);
2445 tcg_gen_andi_tl(dst
, tmp
, -8);
2447 tcg_gen_neg_tl(tmp
, tmp
);
2449 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, tmp
, 0, 3);
2454 static void gen_faligndata(TCGv dst
, TCGv gsr
, TCGv s1
, TCGv s2
)
2458 t1
= tcg_temp_new();
2459 t2
= tcg_temp_new();
2460 shift
= tcg_temp_new();
2462 tcg_gen_andi_tl(shift
, gsr
, 7);
2463 tcg_gen_shli_tl(shift
, shift
, 3);
2464 tcg_gen_shl_tl(t1
, s1
, shift
);
2466 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2467 shift of (up to 63) followed by a constant shift of 1. */
2468 tcg_gen_xori_tl(shift
, shift
, 63);
2469 tcg_gen_shr_tl(t2
, s2
, shift
);
2470 tcg_gen_shri_tl(t2
, t2
, 1);
2472 tcg_gen_or_tl(dst
, t1
, t2
);
2476 tcg_temp_free(shift
);
2480 #define CHECK_IU_FEATURE(dc, FEATURE) \
2481 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2483 #define CHECK_FPU_FEATURE(dc, FEATURE) \
2484 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2487 /* before an instruction, dc->pc must be static */
2488 static void disas_sparc_insn(DisasContext
* dc
, unsigned int insn
)
2490 unsigned int opc
, rs1
, rs2
, rd
;
2491 TCGv cpu_src1
, cpu_src2
;
2492 TCGv_i32 cpu_src1_32
, cpu_src2_32
, cpu_dst_32
;
2493 TCGv_i64 cpu_src1_64
, cpu_src2_64
, cpu_dst_64
;
2496 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2497 tcg_gen_debug_insn_start(dc
->pc
);
2500 opc
= GET_FIELD(insn
, 0, 1);
2502 rd
= GET_FIELD(insn
, 2, 6);
2505 case 0: /* branches/sethi */
2507 unsigned int xop
= GET_FIELD(insn
, 7, 9);
2510 #ifdef TARGET_SPARC64
2511 case 0x1: /* V9 BPcc */
2515 target
= GET_FIELD_SP(insn
, 0, 18);
2516 target
= sign_extend(target
, 19);
2518 cc
= GET_FIELD_SP(insn
, 20, 21);
2520 do_branch(dc
, target
, insn
, 0);
2522 do_branch(dc
, target
, insn
, 1);
2527 case 0x3: /* V9 BPr */
2529 target
= GET_FIELD_SP(insn
, 0, 13) |
2530 (GET_FIELD_SP(insn
, 20, 21) << 14);
2531 target
= sign_extend(target
, 16);
2533 cpu_src1
= get_src1(dc
, insn
);
2534 do_branch_reg(dc
, target
, insn
, cpu_src1
);
2537 case 0x5: /* V9 FBPcc */
2539 int cc
= GET_FIELD_SP(insn
, 20, 21);
2540 if (gen_trap_ifnofpu(dc
)) {
2543 target
= GET_FIELD_SP(insn
, 0, 18);
2544 target
= sign_extend(target
, 19);
2546 do_fbranch(dc
, target
, insn
, cc
);
2550 case 0x7: /* CBN+x */
2555 case 0x2: /* BN+x */
2557 target
= GET_FIELD(insn
, 10, 31);
2558 target
= sign_extend(target
, 22);
2560 do_branch(dc
, target
, insn
, 0);
2563 case 0x6: /* FBN+x */
2565 if (gen_trap_ifnofpu(dc
)) {
2568 target
= GET_FIELD(insn
, 10, 31);
2569 target
= sign_extend(target
, 22);
2571 do_fbranch(dc
, target
, insn
, 0);
2574 case 0x4: /* SETHI */
2575 /* Special-case %g0 because that's the canonical nop. */
2577 uint32_t value
= GET_FIELD(insn
, 10, 31);
2578 TCGv t
= gen_dest_gpr(dc
, rd
);
2579 tcg_gen_movi_tl(t
, value
<< 10);
2580 gen_store_gpr(dc
, rd
, t
);
2583 case 0x0: /* UNIMPL */
2592 target_long target
= GET_FIELDs(insn
, 2, 31) << 2;
2593 TCGv o7
= gen_dest_gpr(dc
, 15);
2595 tcg_gen_movi_tl(o7
, dc
->pc
);
2596 gen_store_gpr(dc
, 15, o7
);
2599 #ifdef TARGET_SPARC64
2600 if (unlikely(AM_CHECK(dc
))) {
2601 target
&= 0xffffffffULL
;
2607 case 2: /* FPU & Logical Operations */
2609 unsigned int xop
= GET_FIELD(insn
, 7, 12);
2610 if (xop
== 0x3a) { /* generate trap */
2611 int cond
= GET_FIELD(insn
, 3, 6);
2623 /* Conditional trap. */
2625 #ifdef TARGET_SPARC64
2627 int cc
= GET_FIELD_SP(insn
, 11, 12);
2629 gen_compare(&cmp
, 0, cond
, dc
);
2630 } else if (cc
== 2) {
2631 gen_compare(&cmp
, 1, cond
, dc
);
2636 gen_compare(&cmp
, 0, cond
, dc
);
2638 l1
= gen_new_label();
2639 tcg_gen_brcond_tl(tcg_invert_cond(cmp
.cond
),
2640 cmp
.c1
, cmp
.c2
, l1
);
2644 mask
= ((dc
->def
->features
& CPU_FEATURE_HYPV
) && supervisor(dc
)
2645 ? UA2005_HTRAP_MASK
: V8_TRAP_MASK
);
2647 /* Don't use the normal temporaries, as they may well have
2648 gone out of scope with the branch above. While we're
2649 doing that we might as well pre-truncate to 32-bit. */
2650 trap
= tcg_temp_new_i32();
2652 rs1
= GET_FIELD_SP(insn
, 14, 18);
2654 rs2
= GET_FIELD_SP(insn
, 0, 6);
2656 tcg_gen_movi_i32(trap
, (rs2
& mask
) + TT_TRAP
);
2657 /* Signal that the trap value is fully constant. */
2660 TCGv t1
= gen_load_gpr(dc
, rs1
);
2661 tcg_gen_trunc_tl_i32(trap
, t1
);
2662 tcg_gen_addi_i32(trap
, trap
, rs2
);
2666 rs2
= GET_FIELD_SP(insn
, 0, 4);
2667 t1
= gen_load_gpr(dc
, rs1
);
2668 t2
= gen_load_gpr(dc
, rs2
);
2669 tcg_gen_add_tl(t1
, t1
, t2
);
2670 tcg_gen_trunc_tl_i32(trap
, t1
);
2673 tcg_gen_andi_i32(trap
, trap
, mask
);
2674 tcg_gen_addi_i32(trap
, trap
, TT_TRAP
);
2677 gen_helper_raise_exception(cpu_env
, trap
);
2678 tcg_temp_free_i32(trap
);
2681 /* An unconditional trap ends the TB. */
2685 /* A conditional trap falls through to the next insn. */
2689 } else if (xop
== 0x28) {
2690 rs1
= GET_FIELD(insn
, 13, 17);
2693 #ifndef TARGET_SPARC64
2694 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2695 manual, rdy on the microSPARC
2697 case 0x0f: /* stbar in the SPARCv8 manual,
2698 rdy on the microSPARC II */
2699 case 0x10 ... 0x1f: /* implementation-dependent in the
2700 SPARCv8 manual, rdy on the
2703 if (rs1
== 0x11 && dc
->def
->features
& CPU_FEATURE_ASR17
) {
2704 TCGv t
= gen_dest_gpr(dc
, rd
);
2705 /* Read Asr17 for a Leon3 monoprocessor */
2706 tcg_gen_movi_tl(t
, (1 << 8) | (dc
->def
->nwindows
- 1));
2707 gen_store_gpr(dc
, rd
, t
);
2711 gen_store_gpr(dc
, rd
, cpu_y
);
2713 #ifdef TARGET_SPARC64
2714 case 0x2: /* V9 rdccr */
2716 gen_helper_rdccr(cpu_dst
, cpu_env
);
2717 gen_store_gpr(dc
, rd
, cpu_dst
);
2719 case 0x3: /* V9 rdasi */
2720 tcg_gen_ext_i32_tl(cpu_dst
, cpu_asi
);
2721 gen_store_gpr(dc
, rd
, cpu_dst
);
2723 case 0x4: /* V9 rdtick */
2727 r_tickptr
= tcg_temp_new_ptr();
2728 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2729 offsetof(CPUSPARCState
, tick
));
2730 gen_helper_tick_get_count(cpu_dst
, r_tickptr
);
2731 tcg_temp_free_ptr(r_tickptr
);
2732 gen_store_gpr(dc
, rd
, cpu_dst
);
2735 case 0x5: /* V9 rdpc */
2737 TCGv t
= gen_dest_gpr(dc
, rd
);
2738 if (unlikely(AM_CHECK(dc
))) {
2739 tcg_gen_movi_tl(t
, dc
->pc
& 0xffffffffULL
);
2741 tcg_gen_movi_tl(t
, dc
->pc
);
2743 gen_store_gpr(dc
, rd
, t
);
2746 case 0x6: /* V9 rdfprs */
2747 tcg_gen_ext_i32_tl(cpu_dst
, cpu_fprs
);
2748 gen_store_gpr(dc
, rd
, cpu_dst
);
2750 case 0xf: /* V9 membar */
2751 break; /* no effect */
2752 case 0x13: /* Graphics Status */
2753 if (gen_trap_ifnofpu(dc
)) {
2756 gen_store_gpr(dc
, rd
, cpu_gsr
);
2758 case 0x16: /* Softint */
2759 tcg_gen_ext_i32_tl(cpu_dst
, cpu_softint
);
2760 gen_store_gpr(dc
, rd
, cpu_dst
);
2762 case 0x17: /* Tick compare */
2763 gen_store_gpr(dc
, rd
, cpu_tick_cmpr
);
2765 case 0x18: /* System tick */
2769 r_tickptr
= tcg_temp_new_ptr();
2770 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2771 offsetof(CPUSPARCState
, stick
));
2772 gen_helper_tick_get_count(cpu_dst
, r_tickptr
);
2773 tcg_temp_free_ptr(r_tickptr
);
2774 gen_store_gpr(dc
, rd
, cpu_dst
);
2777 case 0x19: /* System tick compare */
2778 gen_store_gpr(dc
, rd
, cpu_stick_cmpr
);
2780 case 0x10: /* Performance Control */
2781 case 0x11: /* Performance Instrumentation Counter */
2782 case 0x12: /* Dispatch Control */
2783 case 0x14: /* Softint set, WO */
2784 case 0x15: /* Softint clear, WO */
2789 #if !defined(CONFIG_USER_ONLY)
2790 } else if (xop
== 0x29) { /* rdpsr / UA2005 rdhpr */
2791 #ifndef TARGET_SPARC64
2792 if (!supervisor(dc
)) {
2796 gen_helper_rdpsr(cpu_dst
, cpu_env
);
2798 CHECK_IU_FEATURE(dc
, HYPV
);
2799 if (!hypervisor(dc
))
2801 rs1
= GET_FIELD(insn
, 13, 17);
2804 // gen_op_rdhpstate();
2807 // gen_op_rdhtstate();
2810 tcg_gen_mov_tl(cpu_dst
, cpu_hintp
);
2813 tcg_gen_mov_tl(cpu_dst
, cpu_htba
);
2816 tcg_gen_mov_tl(cpu_dst
, cpu_hver
);
2818 case 31: // hstick_cmpr
2819 tcg_gen_mov_tl(cpu_dst
, cpu_hstick_cmpr
);
2825 gen_store_gpr(dc
, rd
, cpu_dst
);
2827 } else if (xop
== 0x2a) { /* rdwim / V9 rdpr */
2828 if (!supervisor(dc
))
2830 #ifdef TARGET_SPARC64
2831 rs1
= GET_FIELD(insn
, 13, 17);
2837 r_tsptr
= tcg_temp_new_ptr();
2838 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2839 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2840 offsetof(trap_state
, tpc
));
2841 tcg_temp_free_ptr(r_tsptr
);
2848 r_tsptr
= tcg_temp_new_ptr();
2849 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2850 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2851 offsetof(trap_state
, tnpc
));
2852 tcg_temp_free_ptr(r_tsptr
);
2859 r_tsptr
= tcg_temp_new_ptr();
2860 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2861 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2862 offsetof(trap_state
, tstate
));
2863 tcg_temp_free_ptr(r_tsptr
);
2868 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
2870 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2871 tcg_gen_ld32s_tl(cpu_tmp0
, r_tsptr
,
2872 offsetof(trap_state
, tt
));
2873 tcg_temp_free_ptr(r_tsptr
);
2880 r_tickptr
= tcg_temp_new_ptr();
2881 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2882 offsetof(CPUSPARCState
, tick
));
2883 gen_helper_tick_get_count(cpu_tmp0
, r_tickptr
);
2884 tcg_temp_free_ptr(r_tickptr
);
2888 tcg_gen_mov_tl(cpu_tmp0
, cpu_tbr
);
2891 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2892 offsetof(CPUSPARCState
, pstate
));
2895 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2896 offsetof(CPUSPARCState
, tl
));
2899 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2900 offsetof(CPUSPARCState
, psrpil
));
2903 gen_helper_rdcwp(cpu_tmp0
, cpu_env
);
2906 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2907 offsetof(CPUSPARCState
, cansave
));
2909 case 11: // canrestore
2910 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2911 offsetof(CPUSPARCState
, canrestore
));
2913 case 12: // cleanwin
2914 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2915 offsetof(CPUSPARCState
, cleanwin
));
2917 case 13: // otherwin
2918 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2919 offsetof(CPUSPARCState
, otherwin
));
2922 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2923 offsetof(CPUSPARCState
, wstate
));
2925 case 16: // UA2005 gl
2926 CHECK_IU_FEATURE(dc
, GL
);
2927 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2928 offsetof(CPUSPARCState
, gl
));
2930 case 26: // UA2005 strand status
2931 CHECK_IU_FEATURE(dc
, HYPV
);
2932 if (!hypervisor(dc
))
2934 tcg_gen_mov_tl(cpu_tmp0
, cpu_ssr
);
2937 tcg_gen_mov_tl(cpu_tmp0
, cpu_ver
);
2944 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_wim
);
2946 gen_store_gpr(dc
, rd
, cpu_tmp0
);
2948 } else if (xop
== 0x2b) { /* rdtbr / V9 flushw */
2949 #ifdef TARGET_SPARC64
2951 gen_helper_flushw(cpu_env
);
2953 if (!supervisor(dc
))
2955 gen_store_gpr(dc
, rd
, cpu_tbr
);
2959 } else if (xop
== 0x34) { /* FPU Operations */
2960 if (gen_trap_ifnofpu(dc
)) {
2963 gen_op_clear_ieee_excp_and_FTT();
2964 rs1
= GET_FIELD(insn
, 13, 17);
2965 rs2
= GET_FIELD(insn
, 27, 31);
2966 xop
= GET_FIELD(insn
, 18, 26);
2969 case 0x1: /* fmovs */
2970 cpu_src1_32
= gen_load_fpr_F(dc
, rs2
);
2971 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
2973 case 0x5: /* fnegs */
2974 gen_ne_fop_FF(dc
, rd
, rs2
, gen_helper_fnegs
);
2976 case 0x9: /* fabss */
2977 gen_ne_fop_FF(dc
, rd
, rs2
, gen_helper_fabss
);
2979 case 0x29: /* fsqrts */
2980 CHECK_FPU_FEATURE(dc
, FSQRT
);
2981 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fsqrts
);
2983 case 0x2a: /* fsqrtd */
2984 CHECK_FPU_FEATURE(dc
, FSQRT
);
2985 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fsqrtd
);
2987 case 0x2b: /* fsqrtq */
2988 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2989 gen_fop_QQ(dc
, rd
, rs2
, gen_helper_fsqrtq
);
2991 case 0x41: /* fadds */
2992 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fadds
);
2994 case 0x42: /* faddd */
2995 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_faddd
);
2997 case 0x43: /* faddq */
2998 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2999 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_faddq
);
3001 case 0x45: /* fsubs */
3002 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fsubs
);
3004 case 0x46: /* fsubd */
3005 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fsubd
);
3007 case 0x47: /* fsubq */
3008 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3009 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fsubq
);
3011 case 0x49: /* fmuls */
3012 CHECK_FPU_FEATURE(dc
, FMUL
);
3013 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fmuls
);
3015 case 0x4a: /* fmuld */
3016 CHECK_FPU_FEATURE(dc
, FMUL
);
3017 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld
);
3019 case 0x4b: /* fmulq */
3020 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3021 CHECK_FPU_FEATURE(dc
, FMUL
);
3022 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fmulq
);
3024 case 0x4d: /* fdivs */
3025 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fdivs
);
3027 case 0x4e: /* fdivd */
3028 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fdivd
);
3030 case 0x4f: /* fdivq */
3031 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3032 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fdivq
);
3034 case 0x69: /* fsmuld */
3035 CHECK_FPU_FEATURE(dc
, FSMULD
);
3036 gen_fop_DFF(dc
, rd
, rs1
, rs2
, gen_helper_fsmuld
);
3038 case 0x6e: /* fdmulq */
3039 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3040 gen_fop_QDD(dc
, rd
, rs1
, rs2
, gen_helper_fdmulq
);
3042 case 0xc4: /* fitos */
3043 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fitos
);
3045 case 0xc6: /* fdtos */
3046 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fdtos
);
3048 case 0xc7: /* fqtos */
3049 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3050 gen_fop_FQ(dc
, rd
, rs2
, gen_helper_fqtos
);
3052 case 0xc8: /* fitod */
3053 gen_ne_fop_DF(dc
, rd
, rs2
, gen_helper_fitod
);
3055 case 0xc9: /* fstod */
3056 gen_ne_fop_DF(dc
, rd
, rs2
, gen_helper_fstod
);
3058 case 0xcb: /* fqtod */
3059 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3060 gen_fop_DQ(dc
, rd
, rs2
, gen_helper_fqtod
);
3062 case 0xcc: /* fitoq */
3063 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3064 gen_ne_fop_QF(dc
, rd
, rs2
, gen_helper_fitoq
);
3066 case 0xcd: /* fstoq */
3067 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3068 gen_ne_fop_QF(dc
, rd
, rs2
, gen_helper_fstoq
);
3070 case 0xce: /* fdtoq */
3071 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3072 gen_ne_fop_QD(dc
, rd
, rs2
, gen_helper_fdtoq
);
3074 case 0xd1: /* fstoi */
3075 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fstoi
);
3077 case 0xd2: /* fdtoi */
3078 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fdtoi
);
3080 case 0xd3: /* fqtoi */
3081 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3082 gen_fop_FQ(dc
, rd
, rs2
, gen_helper_fqtoi
);
3084 #ifdef TARGET_SPARC64
3085 case 0x2: /* V9 fmovd */
3086 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
3087 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
3089 case 0x3: /* V9 fmovq */
3090 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3091 gen_move_Q(rd
, rs2
);
3093 case 0x6: /* V9 fnegd */
3094 gen_ne_fop_DD(dc
, rd
, rs2
, gen_helper_fnegd
);
3096 case 0x7: /* V9 fnegq */
3097 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3098 gen_ne_fop_QQ(dc
, rd
, rs2
, gen_helper_fnegq
);
3100 case 0xa: /* V9 fabsd */
3101 gen_ne_fop_DD(dc
, rd
, rs2
, gen_helper_fabsd
);
3103 case 0xb: /* V9 fabsq */
3104 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3105 gen_ne_fop_QQ(dc
, rd
, rs2
, gen_helper_fabsq
);
3107 case 0x81: /* V9 fstox */
3108 gen_fop_DF(dc
, rd
, rs2
, gen_helper_fstox
);
3110 case 0x82: /* V9 fdtox */
3111 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fdtox
);
3113 case 0x83: /* V9 fqtox */
3114 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3115 gen_fop_DQ(dc
, rd
, rs2
, gen_helper_fqtox
);
3117 case 0x84: /* V9 fxtos */
3118 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fxtos
);
3120 case 0x88: /* V9 fxtod */
3121 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fxtod
);
3123 case 0x8c: /* V9 fxtoq */
3124 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3125 gen_ne_fop_QD(dc
, rd
, rs2
, gen_helper_fxtoq
);
3131 } else if (xop
== 0x35) { /* FPU Operations */
3132 #ifdef TARGET_SPARC64
3135 if (gen_trap_ifnofpu(dc
)) {
3138 gen_op_clear_ieee_excp_and_FTT();
3139 rs1
= GET_FIELD(insn
, 13, 17);
3140 rs2
= GET_FIELD(insn
, 27, 31);
3141 xop
= GET_FIELD(insn
, 18, 26);
3144 #ifdef TARGET_SPARC64
3148 cond = GET_FIELD_SP(insn, 14, 17); \
3149 cpu_src1 = get_src1(dc, insn); \
3150 gen_compare_reg(&cmp, cond, cpu_src1); \
3151 gen_fmov##sz(dc, &cmp, rd, rs2); \
3152 free_compare(&cmp); \
3155 if ((xop
& 0x11f) == 0x005) { /* V9 fmovsr */
3158 } else if ((xop
& 0x11f) == 0x006) { // V9 fmovdr
3161 } else if ((xop
& 0x11f) == 0x007) { // V9 fmovqr
3162 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3169 #ifdef TARGET_SPARC64
3170 #define FMOVCC(fcc, sz) \
3173 cond = GET_FIELD_SP(insn, 14, 17); \
3174 gen_fcompare(&cmp, fcc, cond); \
3175 gen_fmov##sz(dc, &cmp, rd, rs2); \
3176 free_compare(&cmp); \
3179 case 0x001: /* V9 fmovscc %fcc0 */
3182 case 0x002: /* V9 fmovdcc %fcc0 */
3185 case 0x003: /* V9 fmovqcc %fcc0 */
3186 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3189 case 0x041: /* V9 fmovscc %fcc1 */
3192 case 0x042: /* V9 fmovdcc %fcc1 */
3195 case 0x043: /* V9 fmovqcc %fcc1 */
3196 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3199 case 0x081: /* V9 fmovscc %fcc2 */
3202 case 0x082: /* V9 fmovdcc %fcc2 */
3205 case 0x083: /* V9 fmovqcc %fcc2 */
3206 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3209 case 0x0c1: /* V9 fmovscc %fcc3 */
3212 case 0x0c2: /* V9 fmovdcc %fcc3 */
3215 case 0x0c3: /* V9 fmovqcc %fcc3 */
3216 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3220 #define FMOVCC(xcc, sz) \
3223 cond = GET_FIELD_SP(insn, 14, 17); \
3224 gen_compare(&cmp, xcc, cond, dc); \
3225 gen_fmov##sz(dc, &cmp, rd, rs2); \
3226 free_compare(&cmp); \
3229 case 0x101: /* V9 fmovscc %icc */
3232 case 0x102: /* V9 fmovdcc %icc */
3235 case 0x103: /* V9 fmovqcc %icc */
3236 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3239 case 0x181: /* V9 fmovscc %xcc */
3242 case 0x182: /* V9 fmovdcc %xcc */
3245 case 0x183: /* V9 fmovqcc %xcc */
3246 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3251 case 0x51: /* fcmps, V9 %fcc */
3252 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
3253 cpu_src2_32
= gen_load_fpr_F(dc
, rs2
);
3254 gen_op_fcmps(rd
& 3, cpu_src1_32
, cpu_src2_32
);
3256 case 0x52: /* fcmpd, V9 %fcc */
3257 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
3258 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
3259 gen_op_fcmpd(rd
& 3, cpu_src1_64
, cpu_src2_64
);
3261 case 0x53: /* fcmpq, V9 %fcc */
3262 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3263 gen_op_load_fpr_QT0(QFPREG(rs1
));
3264 gen_op_load_fpr_QT1(QFPREG(rs2
));
3265 gen_op_fcmpq(rd
& 3);
3267 case 0x55: /* fcmpes, V9 %fcc */
3268 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
3269 cpu_src2_32
= gen_load_fpr_F(dc
, rs2
);
3270 gen_op_fcmpes(rd
& 3, cpu_src1_32
, cpu_src2_32
);
3272 case 0x56: /* fcmped, V9 %fcc */
3273 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
3274 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
3275 gen_op_fcmped(rd
& 3, cpu_src1_64
, cpu_src2_64
);
3277 case 0x57: /* fcmpeq, V9 %fcc */
3278 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3279 gen_op_load_fpr_QT0(QFPREG(rs1
));
3280 gen_op_load_fpr_QT1(QFPREG(rs2
));
3281 gen_op_fcmpeq(rd
& 3);
3286 } else if (xop
== 0x2) {
3287 TCGv dst
= gen_dest_gpr(dc
, rd
);
3288 rs1
= GET_FIELD(insn
, 13, 17);
3290 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
3291 if (IS_IMM
) { /* immediate */
3292 simm
= GET_FIELDs(insn
, 19, 31);
3293 tcg_gen_movi_tl(dst
, simm
);
3294 gen_store_gpr(dc
, rd
, dst
);
3295 } else { /* register */
3296 rs2
= GET_FIELD(insn
, 27, 31);
3298 tcg_gen_movi_tl(dst
, 0);
3299 gen_store_gpr(dc
, rd
, dst
);
3301 cpu_src2
= gen_load_gpr(dc
, rs2
);
3302 gen_store_gpr(dc
, rd
, cpu_src2
);
3306 cpu_src1
= get_src1(dc
, insn
);
3307 if (IS_IMM
) { /* immediate */
3308 simm
= GET_FIELDs(insn
, 19, 31);
3309 tcg_gen_ori_tl(dst
, cpu_src1
, simm
);
3310 gen_store_gpr(dc
, rd
, dst
);
3311 } else { /* register */
3312 rs2
= GET_FIELD(insn
, 27, 31);
3314 /* mov shortcut: or x, %g0, y -> mov x, y */
3315 gen_store_gpr(dc
, rd
, cpu_src1
);
3317 cpu_src2
= gen_load_gpr(dc
, rs2
);
3318 tcg_gen_or_tl(dst
, cpu_src1
, cpu_src2
);
3319 gen_store_gpr(dc
, rd
, dst
);
3323 #ifdef TARGET_SPARC64
3324 } else if (xop
== 0x25) { /* sll, V9 sllx */
3325 cpu_src1
= get_src1(dc
, insn
);
3326 if (IS_IMM
) { /* immediate */
3327 simm
= GET_FIELDs(insn
, 20, 31);
3328 if (insn
& (1 << 12)) {
3329 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3331 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, simm
& 0x1f);
3333 } else { /* register */
3334 rs2
= GET_FIELD(insn
, 27, 31);
3335 cpu_src2
= gen_load_gpr(dc
, rs2
);
3336 if (insn
& (1 << 12)) {
3337 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3339 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3341 tcg_gen_shl_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3343 gen_store_gpr(dc
, rd
, cpu_dst
);
3344 } else if (xop
== 0x26) { /* srl, V9 srlx */
3345 cpu_src1
= get_src1(dc
, insn
);
3346 if (IS_IMM
) { /* immediate */
3347 simm
= GET_FIELDs(insn
, 20, 31);
3348 if (insn
& (1 << 12)) {
3349 tcg_gen_shri_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3351 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3352 tcg_gen_shri_i64(cpu_dst
, cpu_dst
, simm
& 0x1f);
3354 } else { /* register */
3355 rs2
= GET_FIELD(insn
, 27, 31);
3356 cpu_src2
= gen_load_gpr(dc
, rs2
);
3357 if (insn
& (1 << 12)) {
3358 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3359 tcg_gen_shr_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3361 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3362 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3363 tcg_gen_shr_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
3366 gen_store_gpr(dc
, rd
, cpu_dst
);
3367 } else if (xop
== 0x27) { /* sra, V9 srax */
3368 cpu_src1
= get_src1(dc
, insn
);
3369 if (IS_IMM
) { /* immediate */
3370 simm
= GET_FIELDs(insn
, 20, 31);
3371 if (insn
& (1 << 12)) {
3372 tcg_gen_sari_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3374 tcg_gen_ext32s_i64(cpu_dst
, cpu_src1
);
3375 tcg_gen_sari_i64(cpu_dst
, cpu_dst
, simm
& 0x1f);
3377 } else { /* register */
3378 rs2
= GET_FIELD(insn
, 27, 31);
3379 cpu_src2
= gen_load_gpr(dc
, rs2
);
3380 if (insn
& (1 << 12)) {
3381 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3382 tcg_gen_sar_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3384 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3385 tcg_gen_ext32s_i64(cpu_dst
, cpu_src1
);
3386 tcg_gen_sar_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
3389 gen_store_gpr(dc
, rd
, cpu_dst
);
3391 } else if (xop
< 0x36) {
3393 cpu_src1
= get_src1(dc
, insn
);
3394 cpu_src2
= get_src2(dc
, insn
);
3395 switch (xop
& ~0x10) {
3398 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3399 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3400 dc
->cc_op
= CC_OP_ADD
;
3402 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3406 tcg_gen_and_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3408 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3409 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3410 dc
->cc_op
= CC_OP_LOGIC
;
3414 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3416 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3417 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3418 dc
->cc_op
= CC_OP_LOGIC
;
3422 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3424 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3425 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3426 dc
->cc_op
= CC_OP_LOGIC
;
3431 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3432 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
3433 dc
->cc_op
= CC_OP_SUB
;
3435 tcg_gen_sub_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3438 case 0x5: /* andn */
3439 tcg_gen_andc_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3441 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3442 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3443 dc
->cc_op
= CC_OP_LOGIC
;
3447 tcg_gen_orc_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3449 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3450 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3451 dc
->cc_op
= CC_OP_LOGIC
;
3454 case 0x7: /* xorn */
3455 tcg_gen_eqv_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3457 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3458 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3459 dc
->cc_op
= CC_OP_LOGIC
;
3462 case 0x8: /* addx, V9 addc */
3463 gen_op_addx_int(dc
, cpu_dst
, cpu_src1
, cpu_src2
,
3466 #ifdef TARGET_SPARC64
3467 case 0x9: /* V9 mulx */
3468 tcg_gen_mul_i64(cpu_dst
, cpu_src1
, cpu_src2
);
3471 case 0xa: /* umul */
3472 CHECK_IU_FEATURE(dc
, MUL
);
3473 gen_op_umul(cpu_dst
, cpu_src1
, cpu_src2
);
3475 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3476 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3477 dc
->cc_op
= CC_OP_LOGIC
;
3480 case 0xb: /* smul */
3481 CHECK_IU_FEATURE(dc
, MUL
);
3482 gen_op_smul(cpu_dst
, cpu_src1
, cpu_src2
);
3484 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3485 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3486 dc
->cc_op
= CC_OP_LOGIC
;
3489 case 0xc: /* subx, V9 subc */
3490 gen_op_subx_int(dc
, cpu_dst
, cpu_src1
, cpu_src2
,
3493 #ifdef TARGET_SPARC64
3494 case 0xd: /* V9 udivx */
3495 gen_helper_udivx(cpu_dst
, cpu_env
, cpu_src1
, cpu_src2
);
3498 case 0xe: /* udiv */
3499 CHECK_IU_FEATURE(dc
, DIV
);
3501 gen_helper_udiv_cc(cpu_dst
, cpu_env
, cpu_src1
,
3503 dc
->cc_op
= CC_OP_DIV
;
3505 gen_helper_udiv(cpu_dst
, cpu_env
, cpu_src1
,
3509 case 0xf: /* sdiv */
3510 CHECK_IU_FEATURE(dc
, DIV
);
3512 gen_helper_sdiv_cc(cpu_dst
, cpu_env
, cpu_src1
,
3514 dc
->cc_op
= CC_OP_DIV
;
3516 gen_helper_sdiv(cpu_dst
, cpu_env
, cpu_src1
,
3523 gen_store_gpr(dc
, rd
, cpu_dst
);
3525 cpu_src1
= get_src1(dc
, insn
);
3526 cpu_src2
= get_src2(dc
, insn
);
3528 case 0x20: /* taddcc */
3529 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3530 gen_store_gpr(dc
, rd
, cpu_dst
);
3531 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_TADD
);
3532 dc
->cc_op
= CC_OP_TADD
;
3534 case 0x21: /* tsubcc */
3535 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3536 gen_store_gpr(dc
, rd
, cpu_dst
);
3537 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_TSUB
);
3538 dc
->cc_op
= CC_OP_TSUB
;
3540 case 0x22: /* taddcctv */
3541 gen_helper_taddcctv(cpu_dst
, cpu_env
,
3542 cpu_src1
, cpu_src2
);
3543 gen_store_gpr(dc
, rd
, cpu_dst
);
3544 dc
->cc_op
= CC_OP_TADDTV
;
3546 case 0x23: /* tsubcctv */
3547 gen_helper_tsubcctv(cpu_dst
, cpu_env
,
3548 cpu_src1
, cpu_src2
);
3549 gen_store_gpr(dc
, rd
, cpu_dst
);
3550 dc
->cc_op
= CC_OP_TSUBTV
;
3552 case 0x24: /* mulscc */
3554 gen_op_mulscc(cpu_dst
, cpu_src1
, cpu_src2
);
3555 gen_store_gpr(dc
, rd
, cpu_dst
);
3556 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3557 dc
->cc_op
= CC_OP_ADD
;
3559 #ifndef TARGET_SPARC64
3560 case 0x25: /* sll */
3561 if (IS_IMM
) { /* immediate */
3562 simm
= GET_FIELDs(insn
, 20, 31);
3563 tcg_gen_shli_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3564 } else { /* register */
3565 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3566 tcg_gen_shl_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3568 gen_store_gpr(dc
, rd
, cpu_dst
);
3570 case 0x26: /* srl */
3571 if (IS_IMM
) { /* immediate */
3572 simm
= GET_FIELDs(insn
, 20, 31);
3573 tcg_gen_shri_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3574 } else { /* register */
3575 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3576 tcg_gen_shr_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3578 gen_store_gpr(dc
, rd
, cpu_dst
);
3580 case 0x27: /* sra */
3581 if (IS_IMM
) { /* immediate */
3582 simm
= GET_FIELDs(insn
, 20, 31);
3583 tcg_gen_sari_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3584 } else { /* register */
3585 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3586 tcg_gen_sar_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3588 gen_store_gpr(dc
, rd
, cpu_dst
);
3595 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3596 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
3598 #ifndef TARGET_SPARC64
3599 case 0x01 ... 0x0f: /* undefined in the
3603 case 0x10 ... 0x1f: /* implementation-dependent
3609 case 0x2: /* V9 wrccr */
3610 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3611 gen_helper_wrccr(cpu_env
, cpu_dst
);
3612 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_FLAGS
);
3613 dc
->cc_op
= CC_OP_FLAGS
;
3615 case 0x3: /* V9 wrasi */
3616 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3617 tcg_gen_andi_tl(cpu_dst
, cpu_dst
, 0xff);
3618 tcg_gen_trunc_tl_i32(cpu_asi
, cpu_dst
);
3620 case 0x6: /* V9 wrfprs */
3621 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3622 tcg_gen_trunc_tl_i32(cpu_fprs
, cpu_dst
);
3628 case 0xf: /* V9 sir, nop if user */
3629 #if !defined(CONFIG_USER_ONLY)
3630 if (supervisor(dc
)) {
3635 case 0x13: /* Graphics Status */
3636 if (gen_trap_ifnofpu(dc
)) {
3639 tcg_gen_xor_tl(cpu_gsr
, cpu_src1
, cpu_src2
);
3641 case 0x14: /* Softint set */
3642 if (!supervisor(dc
))
3644 tcg_gen_xor_tl(cpu_tmp64
, cpu_src1
, cpu_src2
);
3645 gen_helper_set_softint(cpu_env
, cpu_tmp64
);
3647 case 0x15: /* Softint clear */
3648 if (!supervisor(dc
))
3650 tcg_gen_xor_tl(cpu_tmp64
, cpu_src1
, cpu_src2
);
3651 gen_helper_clear_softint(cpu_env
, cpu_tmp64
);
3653 case 0x16: /* Softint write */
3654 if (!supervisor(dc
))
3656 tcg_gen_xor_tl(cpu_tmp64
, cpu_src1
, cpu_src2
);
3657 gen_helper_write_softint(cpu_env
, cpu_tmp64
);
3659 case 0x17: /* Tick compare */
3660 #if !defined(CONFIG_USER_ONLY)
3661 if (!supervisor(dc
))
3667 tcg_gen_xor_tl(cpu_tick_cmpr
, cpu_src1
,
3669 r_tickptr
= tcg_temp_new_ptr();
3670 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3671 offsetof(CPUSPARCState
, tick
));
3672 gen_helper_tick_set_limit(r_tickptr
,
3674 tcg_temp_free_ptr(r_tickptr
);
3677 case 0x18: /* System tick */
3678 #if !defined(CONFIG_USER_ONLY)
3679 if (!supervisor(dc
))
3685 tcg_gen_xor_tl(cpu_dst
, cpu_src1
,
3687 r_tickptr
= tcg_temp_new_ptr();
3688 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3689 offsetof(CPUSPARCState
, stick
));
3690 gen_helper_tick_set_count(r_tickptr
,
3692 tcg_temp_free_ptr(r_tickptr
);
3695 case 0x19: /* System tick compare */
3696 #if !defined(CONFIG_USER_ONLY)
3697 if (!supervisor(dc
))
3703 tcg_gen_xor_tl(cpu_stick_cmpr
, cpu_src1
,
3705 r_tickptr
= tcg_temp_new_ptr();
3706 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3707 offsetof(CPUSPARCState
, stick
));
3708 gen_helper_tick_set_limit(r_tickptr
,
3710 tcg_temp_free_ptr(r_tickptr
);
3714 case 0x10: /* Performance Control */
3715 case 0x11: /* Performance Instrumentation
3717 case 0x12: /* Dispatch Control */
3724 #if !defined(CONFIG_USER_ONLY)
3725 case 0x31: /* wrpsr, V9 saved, restored */
3727 if (!supervisor(dc
))
3729 #ifdef TARGET_SPARC64
3732 gen_helper_saved(cpu_env
);
3735 gen_helper_restored(cpu_env
);
3737 case 2: /* UA2005 allclean */
3738 case 3: /* UA2005 otherw */
3739 case 4: /* UA2005 normalw */
3740 case 5: /* UA2005 invalw */
3746 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3747 gen_helper_wrpsr(cpu_env
, cpu_dst
);
3748 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_FLAGS
);
3749 dc
->cc_op
= CC_OP_FLAGS
;
3757 case 0x32: /* wrwim, V9 wrpr */
3759 if (!supervisor(dc
))
3761 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3762 #ifdef TARGET_SPARC64
3768 r_tsptr
= tcg_temp_new_ptr();
3769 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3770 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3771 offsetof(trap_state
, tpc
));
3772 tcg_temp_free_ptr(r_tsptr
);
3779 r_tsptr
= tcg_temp_new_ptr();
3780 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3781 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3782 offsetof(trap_state
, tnpc
));
3783 tcg_temp_free_ptr(r_tsptr
);
3790 r_tsptr
= tcg_temp_new_ptr();
3791 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3792 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3793 offsetof(trap_state
,
3795 tcg_temp_free_ptr(r_tsptr
);
3802 r_tsptr
= tcg_temp_new_ptr();
3803 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3804 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3805 tcg_gen_st_i32(cpu_tmp32
, r_tsptr
,
3806 offsetof(trap_state
, tt
));
3807 tcg_temp_free_ptr(r_tsptr
);
3814 r_tickptr
= tcg_temp_new_ptr();
3815 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3816 offsetof(CPUSPARCState
, tick
));
3817 gen_helper_tick_set_count(r_tickptr
,
3819 tcg_temp_free_ptr(r_tickptr
);
3823 tcg_gen_mov_tl(cpu_tbr
, cpu_tmp0
);
3827 gen_helper_wrpstate(cpu_env
, cpu_tmp0
);
3828 dc
->npc
= DYNAMIC_PC
;
3832 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3833 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3834 offsetof(CPUSPARCState
, tl
));
3835 dc
->npc
= DYNAMIC_PC
;
3838 gen_helper_wrpil(cpu_env
, cpu_tmp0
);
3841 gen_helper_wrcwp(cpu_env
, cpu_tmp0
);
3844 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3845 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3846 offsetof(CPUSPARCState
,
3849 case 11: // canrestore
3850 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3851 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3852 offsetof(CPUSPARCState
,
3855 case 12: // cleanwin
3856 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3857 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3858 offsetof(CPUSPARCState
,
3861 case 13: // otherwin
3862 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3863 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3864 offsetof(CPUSPARCState
,
3868 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3869 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3870 offsetof(CPUSPARCState
,
3873 case 16: // UA2005 gl
3874 CHECK_IU_FEATURE(dc
, GL
);
3875 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3876 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3877 offsetof(CPUSPARCState
, gl
));
3879 case 26: // UA2005 strand status
3880 CHECK_IU_FEATURE(dc
, HYPV
);
3881 if (!hypervisor(dc
))
3883 tcg_gen_mov_tl(cpu_ssr
, cpu_tmp0
);
3889 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3890 if (dc
->def
->nwindows
!= 32)
3891 tcg_gen_andi_tl(cpu_tmp32
, cpu_tmp32
,
3892 (1 << dc
->def
->nwindows
) - 1);
3893 tcg_gen_mov_i32(cpu_wim
, cpu_tmp32
);
3897 case 0x33: /* wrtbr, UA2005 wrhpr */
3899 #ifndef TARGET_SPARC64
3900 if (!supervisor(dc
))
3902 tcg_gen_xor_tl(cpu_tbr
, cpu_src1
, cpu_src2
);
3904 CHECK_IU_FEATURE(dc
, HYPV
);
3905 if (!hypervisor(dc
))
3907 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3910 // XXX gen_op_wrhpstate();
3917 // XXX gen_op_wrhtstate();
3920 tcg_gen_mov_tl(cpu_hintp
, cpu_tmp0
);
3923 tcg_gen_mov_tl(cpu_htba
, cpu_tmp0
);
3925 case 31: // hstick_cmpr
3929 tcg_gen_mov_tl(cpu_hstick_cmpr
, cpu_tmp0
);
3930 r_tickptr
= tcg_temp_new_ptr();
3931 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3932 offsetof(CPUSPARCState
, hstick
));
3933 gen_helper_tick_set_limit(r_tickptr
,
3935 tcg_temp_free_ptr(r_tickptr
);
3938 case 6: // hver readonly
3946 #ifdef TARGET_SPARC64
3947 case 0x2c: /* V9 movcc */
3949 int cc
= GET_FIELD_SP(insn
, 11, 12);
3950 int cond
= GET_FIELD_SP(insn
, 14, 17);
3954 if (insn
& (1 << 18)) {
3956 gen_compare(&cmp
, 0, cond
, dc
);
3957 } else if (cc
== 2) {
3958 gen_compare(&cmp
, 1, cond
, dc
);
3963 gen_fcompare(&cmp
, cc
, cond
);
3966 /* The get_src2 above loaded the normal 13-bit
3967 immediate field, not the 11-bit field we have
3968 in movcc. But it did handle the reg case. */
3970 simm
= GET_FIELD_SPs(insn
, 0, 10);
3971 tcg_gen_movi_tl(cpu_src2
, simm
);
3974 dst
= gen_load_gpr(dc
, rd
);
3975 tcg_gen_movcond_tl(cmp
.cond
, dst
,
3979 gen_store_gpr(dc
, rd
, dst
);
3982 case 0x2d: /* V9 sdivx */
3983 gen_helper_sdivx(cpu_dst
, cpu_env
, cpu_src1
, cpu_src2
);
3984 gen_store_gpr(dc
, rd
, cpu_dst
);
3986 case 0x2e: /* V9 popc */
3987 gen_helper_popc(cpu_dst
, cpu_src2
);
3988 gen_store_gpr(dc
, rd
, cpu_dst
);
3990 case 0x2f: /* V9 movr */
3992 int cond
= GET_FIELD_SP(insn
, 10, 12);
3996 gen_compare_reg(&cmp
, cond
, cpu_src1
);
3998 /* The get_src2 above loaded the normal 13-bit
3999 immediate field, not the 10-bit field we have
4000 in movr. But it did handle the reg case. */
4002 simm
= GET_FIELD_SPs(insn
, 0, 9);
4003 tcg_gen_movi_tl(cpu_src2
, simm
);
4006 dst
= gen_load_gpr(dc
, rd
);
4007 tcg_gen_movcond_tl(cmp
.cond
, dst
,
4011 gen_store_gpr(dc
, rd
, dst
);
4019 } else if (xop
== 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4020 #ifdef TARGET_SPARC64
4021 int opf
= GET_FIELD_SP(insn
, 5, 13);
4022 rs1
= GET_FIELD(insn
, 13, 17);
4023 rs2
= GET_FIELD(insn
, 27, 31);
4024 if (gen_trap_ifnofpu(dc
)) {
4029 case 0x000: /* VIS I edge8cc */
4030 CHECK_FPU_FEATURE(dc
, VIS1
);
4031 cpu_src1
= gen_load_gpr(dc
, rs1
);
4032 cpu_src2
= gen_load_gpr(dc
, rs2
);
4033 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 1, 0);
4034 gen_store_gpr(dc
, rd
, cpu_dst
);
4036 case 0x001: /* VIS II edge8n */
4037 CHECK_FPU_FEATURE(dc
, VIS2
);
4038 cpu_src1
= gen_load_gpr(dc
, rs1
);
4039 cpu_src2
= gen_load_gpr(dc
, rs2
);
4040 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 0, 0);
4041 gen_store_gpr(dc
, rd
, cpu_dst
);
4043 case 0x002: /* VIS I edge8lcc */
4044 CHECK_FPU_FEATURE(dc
, VIS1
);
4045 cpu_src1
= gen_load_gpr(dc
, rs1
);
4046 cpu_src2
= gen_load_gpr(dc
, rs2
);
4047 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 1, 1);
4048 gen_store_gpr(dc
, rd
, cpu_dst
);
4050 case 0x003: /* VIS II edge8ln */
4051 CHECK_FPU_FEATURE(dc
, VIS2
);
4052 cpu_src1
= gen_load_gpr(dc
, rs1
);
4053 cpu_src2
= gen_load_gpr(dc
, rs2
);
4054 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 0, 1);
4055 gen_store_gpr(dc
, rd
, cpu_dst
);
4057 case 0x004: /* VIS I edge16cc */
4058 CHECK_FPU_FEATURE(dc
, VIS1
);
4059 cpu_src1
= gen_load_gpr(dc
, rs1
);
4060 cpu_src2
= gen_load_gpr(dc
, rs2
);
4061 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 1, 0);
4062 gen_store_gpr(dc
, rd
, cpu_dst
);
4064 case 0x005: /* VIS II edge16n */
4065 CHECK_FPU_FEATURE(dc
, VIS2
);
4066 cpu_src1
= gen_load_gpr(dc
, rs1
);
4067 cpu_src2
= gen_load_gpr(dc
, rs2
);
4068 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 0, 0);
4069 gen_store_gpr(dc
, rd
, cpu_dst
);
4071 case 0x006: /* VIS I edge16lcc */
4072 CHECK_FPU_FEATURE(dc
, VIS1
);
4073 cpu_src1
= gen_load_gpr(dc
, rs1
);
4074 cpu_src2
= gen_load_gpr(dc
, rs2
);
4075 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 1, 1);
4076 gen_store_gpr(dc
, rd
, cpu_dst
);
4078 case 0x007: /* VIS II edge16ln */
4079 CHECK_FPU_FEATURE(dc
, VIS2
);
4080 cpu_src1
= gen_load_gpr(dc
, rs1
);
4081 cpu_src2
= gen_load_gpr(dc
, rs2
);
4082 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 0, 1);
4083 gen_store_gpr(dc
, rd
, cpu_dst
);
4085 case 0x008: /* VIS I edge32cc */
4086 CHECK_FPU_FEATURE(dc
, VIS1
);
4087 cpu_src1
= gen_load_gpr(dc
, rs1
);
4088 cpu_src2
= gen_load_gpr(dc
, rs2
);
4089 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 1, 0);
4090 gen_store_gpr(dc
, rd
, cpu_dst
);
4092 case 0x009: /* VIS II edge32n */
4093 CHECK_FPU_FEATURE(dc
, VIS2
);
4094 cpu_src1
= gen_load_gpr(dc
, rs1
);
4095 cpu_src2
= gen_load_gpr(dc
, rs2
);
4096 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 0, 0);
4097 gen_store_gpr(dc
, rd
, cpu_dst
);
4099 case 0x00a: /* VIS I edge32lcc */
4100 CHECK_FPU_FEATURE(dc
, VIS1
);
4101 cpu_src1
= gen_load_gpr(dc
, rs1
);
4102 cpu_src2
= gen_load_gpr(dc
, rs2
);
4103 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 1, 1);
4104 gen_store_gpr(dc
, rd
, cpu_dst
);
4106 case 0x00b: /* VIS II edge32ln */
4107 CHECK_FPU_FEATURE(dc
, VIS2
);
4108 cpu_src1
= gen_load_gpr(dc
, rs1
);
4109 cpu_src2
= gen_load_gpr(dc
, rs2
);
4110 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 0, 1);
4111 gen_store_gpr(dc
, rd
, cpu_dst
);
4113 case 0x010: /* VIS I array8 */
4114 CHECK_FPU_FEATURE(dc
, VIS1
);
4115 cpu_src1
= gen_load_gpr(dc
, rs1
);
4116 cpu_src2
= gen_load_gpr(dc
, rs2
);
4117 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4118 gen_store_gpr(dc
, rd
, cpu_dst
);
4120 case 0x012: /* VIS I array16 */
4121 CHECK_FPU_FEATURE(dc
, VIS1
);
4122 cpu_src1
= gen_load_gpr(dc
, rs1
);
4123 cpu_src2
= gen_load_gpr(dc
, rs2
);
4124 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4125 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 1);
4126 gen_store_gpr(dc
, rd
, cpu_dst
);
4128 case 0x014: /* VIS I array32 */
4129 CHECK_FPU_FEATURE(dc
, VIS1
);
4130 cpu_src1
= gen_load_gpr(dc
, rs1
);
4131 cpu_src2
= gen_load_gpr(dc
, rs2
);
4132 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4133 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 2);
4134 gen_store_gpr(dc
, rd
, cpu_dst
);
4136 case 0x018: /* VIS I alignaddr */
4137 CHECK_FPU_FEATURE(dc
, VIS1
);
4138 cpu_src1
= gen_load_gpr(dc
, rs1
);
4139 cpu_src2
= gen_load_gpr(dc
, rs2
);
4140 gen_alignaddr(cpu_dst
, cpu_src1
, cpu_src2
, 0);
4141 gen_store_gpr(dc
, rd
, cpu_dst
);
4143 case 0x01a: /* VIS I alignaddrl */
4144 CHECK_FPU_FEATURE(dc
, VIS1
);
4145 cpu_src1
= gen_load_gpr(dc
, rs1
);
4146 cpu_src2
= gen_load_gpr(dc
, rs2
);
4147 gen_alignaddr(cpu_dst
, cpu_src1
, cpu_src2
, 1);
4148 gen_store_gpr(dc
, rd
, cpu_dst
);
4150 case 0x019: /* VIS II bmask */
4151 CHECK_FPU_FEATURE(dc
, VIS2
);
4152 cpu_src1
= gen_load_gpr(dc
, rs1
);
4153 cpu_src2
= gen_load_gpr(dc
, rs2
);
4154 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4155 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, cpu_dst
, 32, 32);
4156 gen_store_gpr(dc
, rd
, cpu_dst
);
4158 case 0x020: /* VIS I fcmple16 */
4159 CHECK_FPU_FEATURE(dc
, VIS1
);
4160 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4161 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4162 gen_helper_fcmple16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4163 gen_store_gpr(dc
, rd
, cpu_dst
);
4165 case 0x022: /* VIS I fcmpne16 */
4166 CHECK_FPU_FEATURE(dc
, VIS1
);
4167 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4168 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4169 gen_helper_fcmpne16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4170 gen_store_gpr(dc
, rd
, cpu_dst
);
4172 case 0x024: /* VIS I fcmple32 */
4173 CHECK_FPU_FEATURE(dc
, VIS1
);
4174 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4175 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4176 gen_helper_fcmple32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4177 gen_store_gpr(dc
, rd
, cpu_dst
);
4179 case 0x026: /* VIS I fcmpne32 */
4180 CHECK_FPU_FEATURE(dc
, VIS1
);
4181 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4182 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4183 gen_helper_fcmpne32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4184 gen_store_gpr(dc
, rd
, cpu_dst
);
4186 case 0x028: /* VIS I fcmpgt16 */
4187 CHECK_FPU_FEATURE(dc
, VIS1
);
4188 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4189 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4190 gen_helper_fcmpgt16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4191 gen_store_gpr(dc
, rd
, cpu_dst
);
4193 case 0x02a: /* VIS I fcmpeq16 */
4194 CHECK_FPU_FEATURE(dc
, VIS1
);
4195 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4196 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4197 gen_helper_fcmpeq16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4198 gen_store_gpr(dc
, rd
, cpu_dst
);
4200 case 0x02c: /* VIS I fcmpgt32 */
4201 CHECK_FPU_FEATURE(dc
, VIS1
);
4202 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4203 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4204 gen_helper_fcmpgt32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4205 gen_store_gpr(dc
, rd
, cpu_dst
);
4207 case 0x02e: /* VIS I fcmpeq32 */
4208 CHECK_FPU_FEATURE(dc
, VIS1
);
4209 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4210 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4211 gen_helper_fcmpeq32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4212 gen_store_gpr(dc
, rd
, cpu_dst
);
4214 case 0x031: /* VIS I fmul8x16 */
4215 CHECK_FPU_FEATURE(dc
, VIS1
);
4216 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16
);
4218 case 0x033: /* VIS I fmul8x16au */
4219 CHECK_FPU_FEATURE(dc
, VIS1
);
4220 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16au
);
4222 case 0x035: /* VIS I fmul8x16al */
4223 CHECK_FPU_FEATURE(dc
, VIS1
);
4224 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16al
);
4226 case 0x036: /* VIS I fmul8sux16 */
4227 CHECK_FPU_FEATURE(dc
, VIS1
);
4228 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8sux16
);
4230 case 0x037: /* VIS I fmul8ulx16 */
4231 CHECK_FPU_FEATURE(dc
, VIS1
);
4232 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8ulx16
);
4234 case 0x038: /* VIS I fmuld8sux16 */
4235 CHECK_FPU_FEATURE(dc
, VIS1
);
4236 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld8sux16
);
4238 case 0x039: /* VIS I fmuld8ulx16 */
4239 CHECK_FPU_FEATURE(dc
, VIS1
);
4240 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld8ulx16
);
4242 case 0x03a: /* VIS I fpack32 */
4243 CHECK_FPU_FEATURE(dc
, VIS1
);
4244 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpack32
);
4246 case 0x03b: /* VIS I fpack16 */
4247 CHECK_FPU_FEATURE(dc
, VIS1
);
4248 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4249 cpu_dst_32
= gen_dest_fpr_F(dc
);
4250 gen_helper_fpack16(cpu_dst_32
, cpu_gsr
, cpu_src1_64
);
4251 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4253 case 0x03d: /* VIS I fpackfix */
4254 CHECK_FPU_FEATURE(dc
, VIS1
);
4255 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4256 cpu_dst_32
= gen_dest_fpr_F(dc
);
4257 gen_helper_fpackfix(cpu_dst_32
, cpu_gsr
, cpu_src1_64
);
4258 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4260 case 0x03e: /* VIS I pdist */
4261 CHECK_FPU_FEATURE(dc
, VIS1
);
4262 gen_ne_fop_DDDD(dc
, rd
, rs1
, rs2
, gen_helper_pdist
);
4264 case 0x048: /* VIS I faligndata */
4265 CHECK_FPU_FEATURE(dc
, VIS1
);
4266 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_faligndata
);
4268 case 0x04b: /* VIS I fpmerge */
4269 CHECK_FPU_FEATURE(dc
, VIS1
);
4270 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpmerge
);
4272 case 0x04c: /* VIS II bshuffle */
4273 CHECK_FPU_FEATURE(dc
, VIS2
);
4274 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_bshuffle
);
4276 case 0x04d: /* VIS I fexpand */
4277 CHECK_FPU_FEATURE(dc
, VIS1
);
4278 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fexpand
);
4280 case 0x050: /* VIS I fpadd16 */
4281 CHECK_FPU_FEATURE(dc
, VIS1
);
4282 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpadd16
);
4284 case 0x051: /* VIS I fpadd16s */
4285 CHECK_FPU_FEATURE(dc
, VIS1
);
4286 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fpadd16s
);
4288 case 0x052: /* VIS I fpadd32 */
4289 CHECK_FPU_FEATURE(dc
, VIS1
);
4290 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpadd32
);
4292 case 0x053: /* VIS I fpadd32s */
4293 CHECK_FPU_FEATURE(dc
, VIS1
);
4294 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_add_i32
);
4296 case 0x054: /* VIS I fpsub16 */
4297 CHECK_FPU_FEATURE(dc
, VIS1
);
4298 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpsub16
);
4300 case 0x055: /* VIS I fpsub16s */
4301 CHECK_FPU_FEATURE(dc
, VIS1
);
4302 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fpsub16s
);
4304 case 0x056: /* VIS I fpsub32 */
4305 CHECK_FPU_FEATURE(dc
, VIS1
);
4306 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpsub32
);
4308 case 0x057: /* VIS I fpsub32s */
4309 CHECK_FPU_FEATURE(dc
, VIS1
);
4310 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_sub_i32
);
4312 case 0x060: /* VIS I fzero */
4313 CHECK_FPU_FEATURE(dc
, VIS1
);
4314 cpu_dst_64
= gen_dest_fpr_D();
4315 tcg_gen_movi_i64(cpu_dst_64
, 0);
4316 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4318 case 0x061: /* VIS I fzeros */
4319 CHECK_FPU_FEATURE(dc
, VIS1
);
4320 cpu_dst_32
= gen_dest_fpr_F(dc
);
4321 tcg_gen_movi_i32(cpu_dst_32
, 0);
4322 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4324 case 0x062: /* VIS I fnor */
4325 CHECK_FPU_FEATURE(dc
, VIS1
);
4326 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_nor_i64
);
4328 case 0x063: /* VIS I fnors */
4329 CHECK_FPU_FEATURE(dc
, VIS1
);
4330 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_nor_i32
);
4332 case 0x064: /* VIS I fandnot2 */
4333 CHECK_FPU_FEATURE(dc
, VIS1
);
4334 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_andc_i64
);
4336 case 0x065: /* VIS I fandnot2s */
4337 CHECK_FPU_FEATURE(dc
, VIS1
);
4338 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_andc_i32
);
4340 case 0x066: /* VIS I fnot2 */
4341 CHECK_FPU_FEATURE(dc
, VIS1
);
4342 gen_ne_fop_DD(dc
, rd
, rs2
, tcg_gen_not_i64
);
4344 case 0x067: /* VIS I fnot2s */
4345 CHECK_FPU_FEATURE(dc
, VIS1
);
4346 gen_ne_fop_FF(dc
, rd
, rs2
, tcg_gen_not_i32
);
4348 case 0x068: /* VIS I fandnot1 */
4349 CHECK_FPU_FEATURE(dc
, VIS1
);
4350 gen_ne_fop_DDD(dc
, rd
, rs2
, rs1
, tcg_gen_andc_i64
);
4352 case 0x069: /* VIS I fandnot1s */
4353 CHECK_FPU_FEATURE(dc
, VIS1
);
4354 gen_ne_fop_FFF(dc
, rd
, rs2
, rs1
, tcg_gen_andc_i32
);
4356 case 0x06a: /* VIS I fnot1 */
4357 CHECK_FPU_FEATURE(dc
, VIS1
);
4358 gen_ne_fop_DD(dc
, rd
, rs1
, tcg_gen_not_i64
);
4360 case 0x06b: /* VIS I fnot1s */
4361 CHECK_FPU_FEATURE(dc
, VIS1
);
4362 gen_ne_fop_FF(dc
, rd
, rs1
, tcg_gen_not_i32
);
4364 case 0x06c: /* VIS I fxor */
4365 CHECK_FPU_FEATURE(dc
, VIS1
);
4366 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_xor_i64
);
4368 case 0x06d: /* VIS I fxors */
4369 CHECK_FPU_FEATURE(dc
, VIS1
);
4370 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_xor_i32
);
4372 case 0x06e: /* VIS I fnand */
4373 CHECK_FPU_FEATURE(dc
, VIS1
);
4374 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_nand_i64
);
4376 case 0x06f: /* VIS I fnands */
4377 CHECK_FPU_FEATURE(dc
, VIS1
);
4378 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_nand_i32
);
4380 case 0x070: /* VIS I fand */
4381 CHECK_FPU_FEATURE(dc
, VIS1
);
4382 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_and_i64
);
4384 case 0x071: /* VIS I fands */
4385 CHECK_FPU_FEATURE(dc
, VIS1
);
4386 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_and_i32
);
4388 case 0x072: /* VIS I fxnor */
4389 CHECK_FPU_FEATURE(dc
, VIS1
);
4390 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_eqv_i64
);
4392 case 0x073: /* VIS I fxnors */
4393 CHECK_FPU_FEATURE(dc
, VIS1
);
4394 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_eqv_i32
);
4396 case 0x074: /* VIS I fsrc1 */
4397 CHECK_FPU_FEATURE(dc
, VIS1
);
4398 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4399 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
4401 case 0x075: /* VIS I fsrc1s */
4402 CHECK_FPU_FEATURE(dc
, VIS1
);
4403 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
4404 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
4406 case 0x076: /* VIS I fornot2 */
4407 CHECK_FPU_FEATURE(dc
, VIS1
);
4408 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_orc_i64
);
4410 case 0x077: /* VIS I fornot2s */
4411 CHECK_FPU_FEATURE(dc
, VIS1
);
4412 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_orc_i32
);
4414 case 0x078: /* VIS I fsrc2 */
4415 CHECK_FPU_FEATURE(dc
, VIS1
);
4416 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4417 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
4419 case 0x079: /* VIS I fsrc2s */
4420 CHECK_FPU_FEATURE(dc
, VIS1
);
4421 cpu_src1_32
= gen_load_fpr_F(dc
, rs2
);
4422 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
4424 case 0x07a: /* VIS I fornot1 */
4425 CHECK_FPU_FEATURE(dc
, VIS1
);
4426 gen_ne_fop_DDD(dc
, rd
, rs2
, rs1
, tcg_gen_orc_i64
);
4428 case 0x07b: /* VIS I fornot1s */
4429 CHECK_FPU_FEATURE(dc
, VIS1
);
4430 gen_ne_fop_FFF(dc
, rd
, rs2
, rs1
, tcg_gen_orc_i32
);
4432 case 0x07c: /* VIS I for */
4433 CHECK_FPU_FEATURE(dc
, VIS1
);
4434 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_or_i64
);
4436 case 0x07d: /* VIS I fors */
4437 CHECK_FPU_FEATURE(dc
, VIS1
);
4438 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_or_i32
);
4440 case 0x07e: /* VIS I fone */
4441 CHECK_FPU_FEATURE(dc
, VIS1
);
4442 cpu_dst_64
= gen_dest_fpr_D();
4443 tcg_gen_movi_i64(cpu_dst_64
, -1);
4444 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4446 case 0x07f: /* VIS I fones */
4447 CHECK_FPU_FEATURE(dc
, VIS1
);
4448 cpu_dst_32
= gen_dest_fpr_F(dc
);
4449 tcg_gen_movi_i32(cpu_dst_32
, -1);
4450 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4452 case 0x080: /* VIS I shutdown */
4453 case 0x081: /* VIS II siam */
4462 } else if (xop
== 0x37) { /* V8 CPop2, V9 impdep2 */
4463 #ifdef TARGET_SPARC64
4468 #ifdef TARGET_SPARC64
4469 } else if (xop
== 0x39) { /* V9 return */
4473 cpu_src1
= get_src1(dc
, insn
);
4474 if (IS_IMM
) { /* immediate */
4475 simm
= GET_FIELDs(insn
, 19, 31);
4476 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, simm
);
4477 } else { /* register */
4478 rs2
= GET_FIELD(insn
, 27, 31);
4480 cpu_src2
= gen_load_gpr(dc
, rs2
);
4481 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4483 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
4486 gen_helper_restore(cpu_env
);
4488 r_const
= tcg_const_i32(3);
4489 gen_helper_check_align(cpu_env
, cpu_dst
, r_const
);
4490 tcg_temp_free_i32(r_const
);
4491 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4492 dc
->npc
= DYNAMIC_PC
;
4496 cpu_src1
= get_src1(dc
, insn
);
4497 if (IS_IMM
) { /* immediate */
4498 simm
= GET_FIELDs(insn
, 19, 31);
4499 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, simm
);
4500 } else { /* register */
4501 rs2
= GET_FIELD(insn
, 27, 31);
4503 cpu_src2
= gen_load_gpr(dc
, rs2
);
4504 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4506 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
4510 case 0x38: /* jmpl */
4515 t
= gen_dest_gpr(dc
, rd
);
4516 tcg_gen_movi_tl(t
, dc
->pc
);
4517 gen_store_gpr(dc
, rd
, t
);
4519 r_const
= tcg_const_i32(3);
4520 gen_helper_check_align(cpu_env
, cpu_dst
, r_const
);
4521 tcg_temp_free_i32(r_const
);
4522 gen_address_mask(dc
, cpu_dst
);
4523 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4524 dc
->npc
= DYNAMIC_PC
;
4527 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4528 case 0x39: /* rett, V9 return */
4532 if (!supervisor(dc
))
4535 r_const
= tcg_const_i32(3);
4536 gen_helper_check_align(cpu_env
, cpu_dst
, r_const
);
4537 tcg_temp_free_i32(r_const
);
4538 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4539 dc
->npc
= DYNAMIC_PC
;
4540 gen_helper_rett(cpu_env
);
4544 case 0x3b: /* flush */
4545 if (!((dc
)->def
->features
& CPU_FEATURE_FLUSH
))
4549 case 0x3c: /* save */
4551 gen_helper_save(cpu_env
);
4552 gen_store_gpr(dc
, rd
, cpu_dst
);
4554 case 0x3d: /* restore */
4556 gen_helper_restore(cpu_env
);
4557 gen_store_gpr(dc
, rd
, cpu_dst
);
4559 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4560 case 0x3e: /* V9 done/retry */
4564 if (!supervisor(dc
))
4566 dc
->npc
= DYNAMIC_PC
;
4567 dc
->pc
= DYNAMIC_PC
;
4568 gen_helper_done(cpu_env
);
4571 if (!supervisor(dc
))
4573 dc
->npc
= DYNAMIC_PC
;
4574 dc
->pc
= DYNAMIC_PC
;
4575 gen_helper_retry(cpu_env
);
4590 case 3: /* load/store instructions */
4592 unsigned int xop
= GET_FIELD(insn
, 7, 12);
4593 /* ??? gen_address_mask prevents us from using a source
4594 register directly. Always generate a temporary. */
4595 TCGv cpu_addr
= get_temp_tl(dc
);
4597 tcg_gen_mov_tl(cpu_addr
, get_src1(dc
, insn
));
4598 if (xop
== 0x3c || xop
== 0x3e) {
4599 /* V9 casa/casxa : no offset */
4600 } else if (IS_IMM
) { /* immediate */
4601 simm
= GET_FIELDs(insn
, 19, 31);
4603 tcg_gen_addi_tl(cpu_addr
, cpu_addr
, simm
);
4605 } else { /* register */
4606 rs2
= GET_FIELD(insn
, 27, 31);
4608 tcg_gen_add_tl(cpu_addr
, cpu_addr
, gen_load_gpr(dc
, rs2
));
4611 if (xop
< 4 || (xop
> 7 && xop
< 0x14 && xop
!= 0x0e) ||
4612 (xop
> 0x17 && xop
<= 0x1d ) ||
4613 (xop
> 0x2c && xop
<= 0x33) || xop
== 0x1f || xop
== 0x3d) {
4614 TCGv cpu_val
= gen_dest_gpr(dc
, rd
);
4617 case 0x0: /* ld, V9 lduw, load unsigned word */
4618 gen_address_mask(dc
, cpu_addr
);
4619 tcg_gen_qemu_ld32u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4621 case 0x1: /* ldub, load unsigned byte */
4622 gen_address_mask(dc
, cpu_addr
);
4623 tcg_gen_qemu_ld8u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4625 case 0x2: /* lduh, load unsigned halfword */
4626 gen_address_mask(dc
, cpu_addr
);
4627 tcg_gen_qemu_ld16u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4629 case 0x3: /* ldd, load double word */
4636 r_const
= tcg_const_i32(7);
4637 /* XXX remove alignment check */
4638 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
4639 tcg_temp_free_i32(r_const
);
4640 gen_address_mask(dc
, cpu_addr
);
4641 tcg_gen_qemu_ld64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4642 tcg_gen_trunc_i64_tl(cpu_tmp0
, cpu_tmp64
);
4643 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffffULL
);
4644 gen_store_gpr(dc
, rd
+ 1, cpu_tmp0
);
4645 tcg_gen_shri_i64(cpu_tmp64
, cpu_tmp64
, 32);
4646 tcg_gen_trunc_i64_tl(cpu_val
, cpu_tmp64
);
4647 tcg_gen_andi_tl(cpu_val
, cpu_val
, 0xffffffffULL
);
4650 case 0x9: /* ldsb, load signed byte */
4651 gen_address_mask(dc
, cpu_addr
);
4652 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4654 case 0xa: /* ldsh, load signed halfword */
4655 gen_address_mask(dc
, cpu_addr
);
4656 tcg_gen_qemu_ld16s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4658 case 0xd: /* ldstub -- XXX: should be atomically */
4662 gen_address_mask(dc
, cpu_addr
);
4663 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4664 r_const
= tcg_const_tl(0xff);
4665 tcg_gen_qemu_st8(r_const
, cpu_addr
, dc
->mem_idx
);
4666 tcg_temp_free(r_const
);
4669 case 0x0f: /* swap, swap register with memory. Also
4671 CHECK_IU_FEATURE(dc
, SWAP
);
4672 cpu_src1
= gen_load_gpr(dc
, rd
);
4673 gen_address_mask(dc
, cpu_addr
);
4674 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4675 tcg_gen_qemu_st32(cpu_src1
, cpu_addr
, dc
->mem_idx
);
4676 tcg_gen_mov_tl(cpu_val
, cpu_tmp0
);
4678 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4679 case 0x10: /* lda, V9 lduwa, load word alternate */
4680 #ifndef TARGET_SPARC64
4683 if (!supervisor(dc
))
4687 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 0);
4689 case 0x11: /* lduba, load unsigned byte alternate */
4690 #ifndef TARGET_SPARC64
4693 if (!supervisor(dc
))
4697 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 0);
4699 case 0x12: /* lduha, load unsigned halfword alternate */
4700 #ifndef TARGET_SPARC64
4703 if (!supervisor(dc
))
4707 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 0);
4709 case 0x13: /* ldda, load double word alternate */
4710 #ifndef TARGET_SPARC64
4713 if (!supervisor(dc
))
4719 gen_ldda_asi(dc
, cpu_val
, cpu_addr
, insn
, rd
);
4721 case 0x19: /* ldsba, load signed byte alternate */
4722 #ifndef TARGET_SPARC64
4725 if (!supervisor(dc
))
4729 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 1);
4731 case 0x1a: /* ldsha, load signed halfword alternate */
4732 #ifndef TARGET_SPARC64
4735 if (!supervisor(dc
))
4739 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 1);
4741 case 0x1d: /* ldstuba -- XXX: should be atomically */
4742 #ifndef TARGET_SPARC64
4745 if (!supervisor(dc
))
4749 gen_ldstub_asi(cpu_val
, cpu_addr
, insn
);
4751 case 0x1f: /* swapa, swap reg with alt. memory. Also
4753 CHECK_IU_FEATURE(dc
, SWAP
);
4754 #ifndef TARGET_SPARC64
4757 if (!supervisor(dc
))
4761 cpu_src1
= gen_load_gpr(dc
, rd
);
4762 gen_swap_asi(cpu_val
, cpu_src1
, cpu_addr
, insn
);
4765 #ifndef TARGET_SPARC64
4766 case 0x30: /* ldc */
4767 case 0x31: /* ldcsr */
4768 case 0x33: /* lddc */
4772 #ifdef TARGET_SPARC64
4773 case 0x08: /* V9 ldsw */
4774 gen_address_mask(dc
, cpu_addr
);
4775 tcg_gen_qemu_ld32s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4777 case 0x0b: /* V9 ldx */
4778 gen_address_mask(dc
, cpu_addr
);
4779 tcg_gen_qemu_ld64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4781 case 0x18: /* V9 ldswa */
4783 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 1);
4785 case 0x1b: /* V9 ldxa */
4787 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 8, 0);
4789 case 0x2d: /* V9 prefetch, no effect */
4791 case 0x30: /* V9 ldfa */
4792 if (gen_trap_ifnofpu(dc
)) {
4796 gen_ldf_asi(cpu_addr
, insn
, 4, rd
);
4797 gen_update_fprs_dirty(rd
);
4799 case 0x33: /* V9 lddfa */
4800 if (gen_trap_ifnofpu(dc
)) {
4804 gen_ldf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
4805 gen_update_fprs_dirty(DFPREG(rd
));
4807 case 0x3d: /* V9 prefetcha, no effect */
4809 case 0x32: /* V9 ldqfa */
4810 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4811 if (gen_trap_ifnofpu(dc
)) {
4815 gen_ldf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
4816 gen_update_fprs_dirty(QFPREG(rd
));
4822 gen_store_gpr(dc
, rd
, cpu_val
);
4823 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4826 } else if (xop
>= 0x20 && xop
< 0x24) {
4827 if (gen_trap_ifnofpu(dc
)) {
4832 case 0x20: /* ldf, load fpreg */
4833 gen_address_mask(dc
, cpu_addr
);
4834 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4835 cpu_dst_32
= gen_dest_fpr_F(dc
);
4836 tcg_gen_trunc_tl_i32(cpu_dst_32
, cpu_tmp0
);
4837 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4839 case 0x21: /* ldfsr, V9 ldxfsr */
4840 #ifdef TARGET_SPARC64
4841 gen_address_mask(dc
, cpu_addr
);
4843 tcg_gen_qemu_ld64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4844 gen_helper_ldxfsr(cpu_env
, cpu_tmp64
);
4846 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4847 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
4848 gen_helper_ldfsr(cpu_env
, cpu_tmp32
);
4852 tcg_gen_qemu_ld32u(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4853 gen_helper_ldfsr(cpu_env
, cpu_tmp32
);
4857 case 0x22: /* ldqf, load quad fpreg */
4861 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4862 r_const
= tcg_const_i32(dc
->mem_idx
);
4863 gen_address_mask(dc
, cpu_addr
);
4864 gen_helper_ldqf(cpu_env
, cpu_addr
, r_const
);
4865 tcg_temp_free_i32(r_const
);
4866 gen_op_store_QT0_fpr(QFPREG(rd
));
4867 gen_update_fprs_dirty(QFPREG(rd
));
4870 case 0x23: /* lddf, load double fpreg */
4871 gen_address_mask(dc
, cpu_addr
);
4872 cpu_dst_64
= gen_dest_fpr_D();
4873 tcg_gen_qemu_ld64(cpu_dst_64
, cpu_addr
, dc
->mem_idx
);
4874 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4879 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18) ||
4880 xop
== 0xe || xop
== 0x1e) {
4881 TCGv cpu_val
= gen_load_gpr(dc
, rd
);
4884 case 0x4: /* st, store word */
4885 gen_address_mask(dc
, cpu_addr
);
4886 tcg_gen_qemu_st32(cpu_val
, cpu_addr
, dc
->mem_idx
);
4888 case 0x5: /* stb, store byte */
4889 gen_address_mask(dc
, cpu_addr
);
4890 tcg_gen_qemu_st8(cpu_val
, cpu_addr
, dc
->mem_idx
);
4892 case 0x6: /* sth, store halfword */
4893 gen_address_mask(dc
, cpu_addr
);
4894 tcg_gen_qemu_st16(cpu_val
, cpu_addr
, dc
->mem_idx
);
4896 case 0x7: /* std, store double word */
4904 gen_address_mask(dc
, cpu_addr
);
4905 r_const
= tcg_const_i32(7);
4906 /* XXX remove alignment check */
4907 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
4908 tcg_temp_free_i32(r_const
);
4909 lo
= gen_load_gpr(dc
, rd
+ 1);
4910 tcg_gen_concat_tl_i64(cpu_tmp64
, lo
, cpu_val
);
4911 tcg_gen_qemu_st64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4914 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4915 case 0x14: /* sta, V9 stwa, store word alternate */
4916 #ifndef TARGET_SPARC64
4919 if (!supervisor(dc
))
4923 gen_st_asi(cpu_val
, cpu_addr
, insn
, 4);
4924 dc
->npc
= DYNAMIC_PC
;
4926 case 0x15: /* stba, store byte alternate */
4927 #ifndef TARGET_SPARC64
4930 if (!supervisor(dc
))
4934 gen_st_asi(cpu_val
, cpu_addr
, insn
, 1);
4935 dc
->npc
= DYNAMIC_PC
;
4937 case 0x16: /* stha, store halfword alternate */
4938 #ifndef TARGET_SPARC64
4941 if (!supervisor(dc
))
4945 gen_st_asi(cpu_val
, cpu_addr
, insn
, 2);
4946 dc
->npc
= DYNAMIC_PC
;
4948 case 0x17: /* stda, store double word alternate */
4949 #ifndef TARGET_SPARC64
4952 if (!supervisor(dc
))
4959 gen_stda_asi(dc
, cpu_val
, cpu_addr
, insn
, rd
);
4963 #ifdef TARGET_SPARC64
4964 case 0x0e: /* V9 stx */
4965 gen_address_mask(dc
, cpu_addr
);
4966 tcg_gen_qemu_st64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4968 case 0x1e: /* V9 stxa */
4970 gen_st_asi(cpu_val
, cpu_addr
, insn
, 8);
4971 dc
->npc
= DYNAMIC_PC
;
4977 } else if (xop
> 0x23 && xop
< 0x28) {
4978 if (gen_trap_ifnofpu(dc
)) {
4983 case 0x24: /* stf, store fpreg */
4984 gen_address_mask(dc
, cpu_addr
);
4985 cpu_src1_32
= gen_load_fpr_F(dc
, rd
);
4986 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_src1_32
);
4987 tcg_gen_qemu_st32(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4989 case 0x25: /* stfsr, V9 stxfsr */
4990 #ifdef TARGET_SPARC64
4991 gen_address_mask(dc
, cpu_addr
);
4992 tcg_gen_ld_i64(cpu_tmp64
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
4994 tcg_gen_qemu_st64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4996 tcg_gen_qemu_st32(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4998 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
4999 tcg_gen_qemu_st32(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
5003 #ifdef TARGET_SPARC64
5004 /* V9 stqf, store quad fpreg */
5008 CHECK_FPU_FEATURE(dc
, FLOAT128
);
5009 gen_op_load_fpr_QT0(QFPREG(rd
));
5010 r_const
= tcg_const_i32(dc
->mem_idx
);
5011 gen_address_mask(dc
, cpu_addr
);
5012 gen_helper_stqf(cpu_env
, cpu_addr
, r_const
);
5013 tcg_temp_free_i32(r_const
);
5016 #else /* !TARGET_SPARC64 */
5017 /* stdfq, store floating point queue */
5018 #if defined(CONFIG_USER_ONLY)
5021 if (!supervisor(dc
))
5023 if (gen_trap_ifnofpu(dc
)) {
5029 case 0x27: /* stdf, store double fpreg */
5030 gen_address_mask(dc
, cpu_addr
);
5031 cpu_src1_64
= gen_load_fpr_D(dc
, rd
);
5032 tcg_gen_qemu_st64(cpu_src1_64
, cpu_addr
, dc
->mem_idx
);
5037 } else if (xop
> 0x33 && xop
< 0x3f) {
5040 #ifdef TARGET_SPARC64
5041 case 0x34: /* V9 stfa */
5042 if (gen_trap_ifnofpu(dc
)) {
5045 gen_stf_asi(cpu_addr
, insn
, 4, rd
);
5047 case 0x36: /* V9 stqfa */
5051 CHECK_FPU_FEATURE(dc
, FLOAT128
);
5052 if (gen_trap_ifnofpu(dc
)) {
5055 r_const
= tcg_const_i32(7);
5056 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
5057 tcg_temp_free_i32(r_const
);
5058 gen_stf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
5061 case 0x37: /* V9 stdfa */
5062 if (gen_trap_ifnofpu(dc
)) {
5065 gen_stf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
5067 case 0x3c: /* V9 casa */
5068 rs2
= GET_FIELD(insn
, 27, 31);
5069 cpu_src2
= gen_load_gpr(dc
, rs2
);
5070 gen_cas_asi(dc
, cpu_addr
, cpu_src2
, insn
, rd
);
5072 case 0x3e: /* V9 casxa */
5073 rs2
= GET_FIELD(insn
, 27, 31);
5074 cpu_src2
= gen_load_gpr(dc
, rs2
);
5075 gen_casx_asi(dc
, cpu_addr
, cpu_src2
, insn
, rd
);
5078 case 0x34: /* stc */
5079 case 0x35: /* stcsr */
5080 case 0x36: /* stdcq */
5081 case 0x37: /* stdc */
5093 /* default case for non jump instructions */
5094 if (dc
->npc
== DYNAMIC_PC
) {
5095 dc
->pc
= DYNAMIC_PC
;
5097 } else if (dc
->npc
== JUMP_PC
) {
5098 /* we can do a static jump */
5099 gen_branch2(dc
, dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_cond
);
5103 dc
->npc
= dc
->npc
+ 4;
5112 r_const
= tcg_const_i32(TT_ILL_INSN
);
5113 gen_helper_raise_exception(cpu_env
, r_const
);
5114 tcg_temp_free_i32(r_const
);
5123 r_const
= tcg_const_i32(TT_UNIMP_FLUSH
);
5124 gen_helper_raise_exception(cpu_env
, r_const
);
5125 tcg_temp_free_i32(r_const
);
5129 #if !defined(CONFIG_USER_ONLY)
5135 r_const
= tcg_const_i32(TT_PRIV_INSN
);
5136 gen_helper_raise_exception(cpu_env
, r_const
);
5137 tcg_temp_free_i32(r_const
);
5144 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP
);
5147 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
5150 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR
);
5154 #ifndef TARGET_SPARC64
5160 r_const
= tcg_const_i32(TT_NCP_INSN
);
5161 gen_helper_raise_exception(cpu_env
, r_const
);
5162 tcg_temp_free(r_const
);
5168 if (dc
->n_t32
!= 0) {
5170 for (i
= dc
->n_t32
- 1; i
>= 0; --i
) {
5171 tcg_temp_free_i32(dc
->t32
[i
]);
5175 if (dc
->n_ttl
!= 0) {
5177 for (i
= dc
->n_ttl
- 1; i
>= 0; --i
) {
5178 tcg_temp_free(dc
->ttl
[i
]);
5184 static inline void gen_intermediate_code_internal(TranslationBlock
* tb
,
5185 int spc
, CPUSPARCState
*env
)
5187 target_ulong pc_start
, last_pc
;
5188 uint16_t *gen_opc_end
;
5189 DisasContext dc1
, *dc
= &dc1
;
5196 memset(dc
, 0, sizeof(DisasContext
));
5201 dc
->npc
= (target_ulong
) tb
->cs_base
;
5202 dc
->cc_op
= CC_OP_DYNAMIC
;
5203 dc
->mem_idx
= cpu_mmu_index(env
);
5205 dc
->fpu_enabled
= tb_fpu_enabled(tb
->flags
);
5206 dc
->address_mask_32bit
= tb_am_enabled(tb
->flags
);
5207 dc
->singlestep
= (env
->singlestep_enabled
|| singlestep
);
5208 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
5211 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
5213 max_insns
= CF_COUNT_MASK
;
5216 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
5217 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
5218 if (bp
->pc
== dc
->pc
) {
5219 if (dc
->pc
!= pc_start
)
5221 gen_helper_debug(cpu_env
);
5229 qemu_log("Search PC...\n");
5230 j
= gen_opc_ptr
- gen_opc_buf
;
5234 gen_opc_instr_start
[lj
++] = 0;
5235 gen_opc_pc
[lj
] = dc
->pc
;
5236 gen_opc_npc
[lj
] = dc
->npc
;
5237 gen_opc_instr_start
[lj
] = 1;
5238 gen_opc_icount
[lj
] = num_insns
;
5241 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
5244 insn
= cpu_ldl_code(env
, dc
->pc
);
5246 cpu_tmp0
= tcg_temp_new();
5247 cpu_tmp32
= tcg_temp_new_i32();
5248 cpu_tmp64
= tcg_temp_new_i64();
5249 cpu_dst
= tcg_temp_new();
5251 disas_sparc_insn(dc
, insn
);
5254 tcg_temp_free(cpu_dst
);
5255 tcg_temp_free_i64(cpu_tmp64
);
5256 tcg_temp_free_i32(cpu_tmp32
);
5257 tcg_temp_free(cpu_tmp0
);
5261 /* if the next PC is different, we abort now */
5262 if (dc
->pc
!= (last_pc
+ 4))
5264 /* if we reach a page boundary, we stop generation so that the
5265 PC of a TT_TFAULT exception is always in the right page */
5266 if ((dc
->pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
5268 /* if single step mode, we generate only one instruction and
5269 generate an exception */
5270 if (dc
->singlestep
) {
5273 } while ((gen_opc_ptr
< gen_opc_end
) &&
5274 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32) &&
5275 num_insns
< max_insns
);
5278 if (tb
->cflags
& CF_LAST_IO
) {
5282 if (dc
->pc
!= DYNAMIC_PC
&&
5283 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
5284 /* static PC and NPC: we can use direct chaining */
5285 gen_goto_tb(dc
, 0, dc
->pc
, dc
->npc
);
5287 if (dc
->pc
!= DYNAMIC_PC
) {
5288 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
5294 gen_icount_end(tb
, num_insns
);
5295 *gen_opc_ptr
= INDEX_op_end
;
5297 j
= gen_opc_ptr
- gen_opc_buf
;
5300 gen_opc_instr_start
[lj
++] = 0;
5304 gen_opc_jump_pc
[0] = dc
->jump_pc
[0];
5305 gen_opc_jump_pc
[1] = dc
->jump_pc
[1];
5307 tb
->size
= last_pc
+ 4 - pc_start
;
5308 tb
->icount
= num_insns
;
5311 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
5312 qemu_log("--------------\n");
5313 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5314 log_target_disas(pc_start
, last_pc
+ 4 - pc_start
, 0);
5320 void gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
5322 gen_intermediate_code_internal(tb
, 0, env
);
5325 void gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
5327 gen_intermediate_code_internal(tb
, 1, env
);
5330 void gen_intermediate_code_init(CPUSPARCState
*env
)
5334 static const char * const gregnames
[8] = {
5335 NULL
, // g0 not used
5344 static const char * const fregnames
[32] = {
5345 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5346 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5347 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5348 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5351 /* init various static tables */
5355 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
5356 cpu_regwptr
= tcg_global_mem_new_ptr(TCG_AREG0
,
5357 offsetof(CPUSPARCState
, regwptr
),
5359 #ifdef TARGET_SPARC64
5360 cpu_xcc
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, xcc
),
5362 cpu_asi
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, asi
),
5364 cpu_fprs
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, fprs
),
5366 cpu_gsr
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, gsr
),
5368 cpu_tick_cmpr
= tcg_global_mem_new(TCG_AREG0
,
5369 offsetof(CPUSPARCState
, tick_cmpr
),
5371 cpu_stick_cmpr
= tcg_global_mem_new(TCG_AREG0
,
5372 offsetof(CPUSPARCState
, stick_cmpr
),
5374 cpu_hstick_cmpr
= tcg_global_mem_new(TCG_AREG0
,
5375 offsetof(CPUSPARCState
, hstick_cmpr
),
5377 cpu_hintp
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, hintp
),
5379 cpu_htba
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, htba
),
5381 cpu_hver
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, hver
),
5383 cpu_ssr
= tcg_global_mem_new(TCG_AREG0
,
5384 offsetof(CPUSPARCState
, ssr
), "ssr");
5385 cpu_ver
= tcg_global_mem_new(TCG_AREG0
,
5386 offsetof(CPUSPARCState
, version
), "ver");
5387 cpu_softint
= tcg_global_mem_new_i32(TCG_AREG0
,
5388 offsetof(CPUSPARCState
, softint
),
5391 cpu_wim
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, wim
),
5394 cpu_cond
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, cond
),
5396 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, cc_src
),
5398 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
,
5399 offsetof(CPUSPARCState
, cc_src2
),
5401 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, cc_dst
),
5403 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, cc_op
),
5405 cpu_psr
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, psr
),
5407 cpu_fsr
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, fsr
),
5409 cpu_pc
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, pc
),
5411 cpu_npc
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, npc
),
5413 cpu_y
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, y
), "y");
5414 #ifndef CONFIG_USER_ONLY
5415 cpu_tbr
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, tbr
),
5418 for (i
= 1; i
< 8; i
++) {
5419 cpu_gregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
5420 offsetof(CPUSPARCState
, gregs
[i
]),
5423 for (i
= 0; i
< TARGET_DPREGS
; i
++) {
5424 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
5425 offsetof(CPUSPARCState
, fpr
[i
]),
5429 /* register helpers */
5431 #define GEN_HELPER 2
5436 void restore_state_to_opc(CPUSPARCState
*env
, TranslationBlock
*tb
, int pc_pos
)
5439 env
->pc
= gen_opc_pc
[pc_pos
];
5440 npc
= gen_opc_npc
[pc_pos
];
5442 /* dynamic NPC: already stored */
5443 } else if (npc
== 2) {
5444 /* jump PC: use 'cond' and the jump targets of the translation */
5446 env
->npc
= gen_opc_jump_pc
[0];
5448 env
->npc
= gen_opc_jump_pc
[1];