4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 #define DYNAMIC_PC 1 /* dynamic pc value */
37 #define JUMP_PC 2 /* dynamic pc value which takes only two values
38 according to jump_pc[T2] */
40 /* global register indexes */
41 static TCGv cpu_env
, cpu_regwptr
;
42 static TCGv cpu_cc_src
, cpu_cc_src2
, cpu_cc_dst
;
43 static TCGv cpu_psr
, cpu_fsr
, cpu_pc
, cpu_npc
, cpu_gregs
[8];
44 static TCGv cpu_cond
, cpu_src1
, cpu_src2
, cpu_dst
, cpu_addr
, cpu_val
;
48 /* local register indexes (only used inside old micro ops) */
49 static TCGv cpu_tmp0
, cpu_tmp32
, cpu_tmp64
;
51 #include "gen-icount.h"
53 typedef struct DisasContext
{
54 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
55 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
56 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
60 int address_mask_32bit
;
61 struct TranslationBlock
*tb
;
65 // This function uses non-native bit order
66 #define GET_FIELD(X, FROM, TO) \
67 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
69 // This function uses the order in the manuals, i.e. bit 0 is 2^0
70 #define GET_FIELD_SP(X, FROM, TO) \
71 GET_FIELD(X, 31 - (TO), 31 - (FROM))
73 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
74 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
78 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
79 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
82 #define DFPREG(r) (r & 0x1e)
83 #define QFPREG(r) (r & 0x1c)
86 static int sign_extend(int x
, int len
)
89 return (x
<< len
) >> len
;
92 #define IS_IMM (insn & (1<<13))
94 /* floating point registers moves */
95 static void gen_op_load_fpr_FT0(unsigned int src
)
97 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
]));
98 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, ft0
));
101 static void gen_op_load_fpr_FT1(unsigned int src
)
103 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
]));
104 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, ft1
));
107 static void gen_op_store_FT0_fpr(unsigned int dst
)
109 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, ft0
));
110 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
]));
113 static void gen_op_load_fpr_DT0(unsigned int src
)
115 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
]));
116 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, dt0
) +
117 offsetof(CPU_DoubleU
, l
.upper
));
118 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 1]));
119 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, dt0
) +
120 offsetof(CPU_DoubleU
, l
.lower
));
123 static void gen_op_load_fpr_DT1(unsigned int src
)
125 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
]));
126 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, dt1
) +
127 offsetof(CPU_DoubleU
, l
.upper
));
128 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 1]));
129 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, dt1
) +
130 offsetof(CPU_DoubleU
, l
.lower
));
133 static void gen_op_store_DT0_fpr(unsigned int dst
)
135 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, dt0
) +
136 offsetof(CPU_DoubleU
, l
.upper
));
137 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
]));
138 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, dt0
) +
139 offsetof(CPU_DoubleU
, l
.lower
));
140 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
+ 1]));
143 static void gen_op_load_fpr_QT0(unsigned int src
)
145 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
]));
146 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
147 offsetof(CPU_QuadU
, l
.upmost
));
148 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 1]));
149 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
150 offsetof(CPU_QuadU
, l
.upper
));
151 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 2]));
152 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
153 offsetof(CPU_QuadU
, l
.lower
));
154 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 3]));
155 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
156 offsetof(CPU_QuadU
, l
.lowest
));
159 static void gen_op_load_fpr_QT1(unsigned int src
)
161 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
]));
162 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt1
) +
163 offsetof(CPU_QuadU
, l
.upmost
));
164 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 1]));
165 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt1
) +
166 offsetof(CPU_QuadU
, l
.upper
));
167 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 2]));
168 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt1
) +
169 offsetof(CPU_QuadU
, l
.lower
));
170 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[src
+ 3]));
171 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt1
) +
172 offsetof(CPU_QuadU
, l
.lowest
));
175 static void gen_op_store_QT0_fpr(unsigned int dst
)
177 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
178 offsetof(CPU_QuadU
, l
.upmost
));
179 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
]));
180 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
181 offsetof(CPU_QuadU
, l
.upper
));
182 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
+ 1]));
183 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
184 offsetof(CPU_QuadU
, l
.lower
));
185 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
+ 2]));
186 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, qt0
) +
187 offsetof(CPU_QuadU
, l
.lowest
));
188 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fpr
[dst
+ 3]));
192 #ifdef CONFIG_USER_ONLY
193 #define supervisor(dc) 0
194 #ifdef TARGET_SPARC64
195 #define hypervisor(dc) 0
198 #define supervisor(dc) (dc->mem_idx >= 1)
199 #ifdef TARGET_SPARC64
200 #define hypervisor(dc) (dc->mem_idx == 2)
205 #ifdef TARGET_SPARC64
207 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
209 #define AM_CHECK(dc) (1)
213 static inline void gen_address_mask(DisasContext
*dc
, TCGv addr
)
215 #ifdef TARGET_SPARC64
217 tcg_gen_andi_tl(addr
, addr
, 0xffffffffULL
);
221 static inline void gen_movl_reg_TN(int reg
, TCGv tn
)
224 tcg_gen_movi_tl(tn
, 0);
226 tcg_gen_mov_tl(tn
, cpu_gregs
[reg
]);
228 tcg_gen_ld_tl(tn
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
232 static inline void gen_movl_TN_reg(int reg
, TCGv tn
)
237 tcg_gen_mov_tl(cpu_gregs
[reg
], tn
);
239 tcg_gen_st_tl(tn
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
243 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
,
244 target_ulong pc
, target_ulong npc
)
246 TranslationBlock
*tb
;
249 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
250 (npc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
)) {
251 /* jump to same page: we can use a direct jump */
252 tcg_gen_goto_tb(tb_num
);
253 tcg_gen_movi_tl(cpu_pc
, pc
);
254 tcg_gen_movi_tl(cpu_npc
, npc
);
255 tcg_gen_exit_tb((long)tb
+ tb_num
);
257 /* jump to another page: currently not optimized */
258 tcg_gen_movi_tl(cpu_pc
, pc
);
259 tcg_gen_movi_tl(cpu_npc
, npc
);
265 static inline void gen_mov_reg_N(TCGv reg
, TCGv src
)
267 tcg_gen_extu_i32_tl(reg
, src
);
268 tcg_gen_shri_tl(reg
, reg
, PSR_NEG_SHIFT
);
269 tcg_gen_andi_tl(reg
, reg
, 0x1);
272 static inline void gen_mov_reg_Z(TCGv reg
, TCGv src
)
274 tcg_gen_extu_i32_tl(reg
, src
);
275 tcg_gen_shri_tl(reg
, reg
, PSR_ZERO_SHIFT
);
276 tcg_gen_andi_tl(reg
, reg
, 0x1);
279 static inline void gen_mov_reg_V(TCGv reg
, TCGv src
)
281 tcg_gen_extu_i32_tl(reg
, src
);
282 tcg_gen_shri_tl(reg
, reg
, PSR_OVF_SHIFT
);
283 tcg_gen_andi_tl(reg
, reg
, 0x1);
286 static inline void gen_mov_reg_C(TCGv reg
, TCGv src
)
288 tcg_gen_extu_i32_tl(reg
, src
);
289 tcg_gen_shri_tl(reg
, reg
, PSR_CARRY_SHIFT
);
290 tcg_gen_andi_tl(reg
, reg
, 0x1);
293 static inline void gen_cc_clear_icc(void)
295 tcg_gen_movi_i32(cpu_psr
, 0);
298 #ifdef TARGET_SPARC64
299 static inline void gen_cc_clear_xcc(void)
301 tcg_gen_movi_i32(cpu_xcc
, 0);
307 env->psr |= PSR_ZERO;
308 if ((int32_t) T0 < 0)
311 static inline void gen_cc_NZ_icc(TCGv dst
)
316 l1
= gen_new_label();
317 l2
= gen_new_label();
318 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
319 tcg_gen_andi_tl(r_temp
, dst
, 0xffffffffULL
);
320 tcg_gen_brcondi_tl(TCG_COND_NE
, r_temp
, 0, l1
);
321 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_ZERO
);
323 tcg_gen_ext_i32_tl(r_temp
, dst
);
324 tcg_gen_brcondi_tl(TCG_COND_GE
, r_temp
, 0, l2
);
325 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_NEG
);
327 tcg_temp_free(r_temp
);
330 #ifdef TARGET_SPARC64
331 static inline void gen_cc_NZ_xcc(TCGv dst
)
335 l1
= gen_new_label();
336 l2
= gen_new_label();
337 tcg_gen_brcondi_tl(TCG_COND_NE
, dst
, 0, l1
);
338 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_ZERO
);
340 tcg_gen_brcondi_tl(TCG_COND_GE
, dst
, 0, l2
);
341 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_NEG
);
348 env->psr |= PSR_CARRY;
350 static inline void gen_cc_C_add_icc(TCGv dst
, TCGv src1
)
352 TCGv r_temp1
, r_temp2
;
355 l1
= gen_new_label();
356 r_temp1
= tcg_temp_new(TCG_TYPE_TL
);
357 r_temp2
= tcg_temp_new(TCG_TYPE_TL
);
358 tcg_gen_andi_tl(r_temp1
, dst
, 0xffffffffULL
);
359 tcg_gen_andi_tl(r_temp2
, src1
, 0xffffffffULL
);
360 tcg_gen_brcond_tl(TCG_COND_GEU
, r_temp1
, r_temp2
, l1
);
361 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_CARRY
);
363 tcg_temp_free(r_temp1
);
364 tcg_temp_free(r_temp2
);
367 #ifdef TARGET_SPARC64
368 static inline void gen_cc_C_add_xcc(TCGv dst
, TCGv src1
)
372 l1
= gen_new_label();
373 tcg_gen_brcond_tl(TCG_COND_GEU
, dst
, src1
, l1
);
374 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_CARRY
);
380 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
383 static inline void gen_cc_V_add_icc(TCGv dst
, TCGv src1
, TCGv src2
)
387 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
388 tcg_gen_xor_tl(r_temp
, src1
, src2
);
389 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
390 tcg_gen_xor_tl(cpu_tmp0
, src1
, dst
);
391 tcg_gen_and_tl(r_temp
, r_temp
, cpu_tmp0
);
392 tcg_gen_andi_tl(r_temp
, r_temp
, (1ULL << 31));
393 tcg_gen_shri_tl(r_temp
, r_temp
, 31 - PSR_OVF_SHIFT
);
394 tcg_gen_trunc_tl_i32(cpu_tmp32
, r_temp
);
395 tcg_temp_free(r_temp
);
396 tcg_gen_or_i32(cpu_psr
, cpu_psr
, cpu_tmp32
);
399 #ifdef TARGET_SPARC64
400 static inline void gen_cc_V_add_xcc(TCGv dst
, TCGv src1
, TCGv src2
)
404 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
405 tcg_gen_xor_tl(r_temp
, src1
, src2
);
406 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
407 tcg_gen_xor_tl(cpu_tmp0
, src1
, dst
);
408 tcg_gen_and_tl(r_temp
, r_temp
, cpu_tmp0
);
409 tcg_gen_andi_tl(r_temp
, r_temp
, (1ULL << 63));
410 tcg_gen_shri_tl(r_temp
, r_temp
, 63 - PSR_OVF_SHIFT
);
411 tcg_gen_trunc_tl_i32(cpu_tmp32
, r_temp
);
412 tcg_temp_free(r_temp
);
413 tcg_gen_or_i32(cpu_xcc
, cpu_xcc
, cpu_tmp32
);
417 static inline void gen_add_tv(TCGv dst
, TCGv src1
, TCGv src2
)
419 TCGv r_temp
, r_const
;
422 l1
= gen_new_label();
424 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
425 tcg_gen_xor_tl(r_temp
, src1
, src2
);
426 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
427 tcg_gen_xor_tl(cpu_tmp0
, src1
, dst
);
428 tcg_gen_and_tl(r_temp
, r_temp
, cpu_tmp0
);
429 tcg_gen_andi_tl(r_temp
, r_temp
, (1ULL << 31));
430 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_temp
, 0, l1
);
431 r_const
= tcg_const_i32(TT_TOVF
);
432 tcg_gen_helper_0_1(raise_exception
, r_const
);
433 tcg_temp_free(r_const
);
435 tcg_temp_free(r_temp
);
438 static inline void gen_cc_V_tag(TCGv src1
, TCGv src2
)
442 l1
= gen_new_label();
443 tcg_gen_or_tl(cpu_tmp0
, src1
, src2
);
444 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0x3);
445 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, l1
);
446 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_OVF
);
450 static inline void gen_tag_tv(TCGv src1
, TCGv src2
)
455 l1
= gen_new_label();
456 tcg_gen_or_tl(cpu_tmp0
, src1
, src2
);
457 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0x3);
458 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, l1
);
459 r_const
= tcg_const_i32(TT_TOVF
);
460 tcg_gen_helper_0_1(raise_exception
, r_const
);
461 tcg_temp_free(r_const
);
465 static inline void gen_op_add_cc(TCGv dst
, TCGv src1
, TCGv src2
)
467 tcg_gen_mov_tl(cpu_cc_src
, src1
);
468 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
469 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
471 gen_cc_NZ_icc(cpu_cc_dst
);
472 gen_cc_C_add_icc(cpu_cc_dst
, cpu_cc_src
);
473 gen_cc_V_add_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
474 #ifdef TARGET_SPARC64
476 gen_cc_NZ_xcc(cpu_cc_dst
);
477 gen_cc_C_add_xcc(cpu_cc_dst
, cpu_cc_src
);
478 gen_cc_V_add_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
480 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
483 static inline void gen_op_addx_cc(TCGv dst
, TCGv src1
, TCGv src2
)
485 tcg_gen_mov_tl(cpu_cc_src
, src1
);
486 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
487 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
488 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_tmp0
);
490 gen_cc_C_add_icc(cpu_cc_dst
, cpu_cc_src
);
491 #ifdef TARGET_SPARC64
493 gen_cc_C_add_xcc(cpu_cc_dst
, cpu_cc_src
);
495 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_dst
, cpu_cc_src2
);
496 gen_cc_NZ_icc(cpu_cc_dst
);
497 gen_cc_C_add_icc(cpu_cc_dst
, cpu_cc_src
);
498 gen_cc_V_add_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
499 #ifdef TARGET_SPARC64
500 gen_cc_NZ_xcc(cpu_cc_dst
);
501 gen_cc_C_add_xcc(cpu_cc_dst
, cpu_cc_src
);
502 gen_cc_V_add_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
504 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
507 static inline void gen_op_tadd_cc(TCGv dst
, TCGv src1
, TCGv src2
)
509 tcg_gen_mov_tl(cpu_cc_src
, src1
);
510 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
511 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
513 gen_cc_NZ_icc(cpu_cc_dst
);
514 gen_cc_C_add_icc(cpu_cc_dst
, cpu_cc_src
);
515 gen_cc_V_add_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
516 gen_cc_V_tag(cpu_cc_src
, cpu_cc_src2
);
517 #ifdef TARGET_SPARC64
519 gen_cc_NZ_xcc(cpu_cc_dst
);
520 gen_cc_C_add_xcc(cpu_cc_dst
, cpu_cc_src
);
521 gen_cc_V_add_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
523 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
526 static inline void gen_op_tadd_ccTV(TCGv dst
, TCGv src1
, TCGv src2
)
528 tcg_gen_mov_tl(cpu_cc_src
, src1
);
529 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
530 gen_tag_tv(cpu_cc_src
, cpu_cc_src2
);
531 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
532 gen_add_tv(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
534 gen_cc_NZ_icc(cpu_cc_dst
);
535 gen_cc_C_add_icc(cpu_cc_dst
, cpu_cc_src
);
536 #ifdef TARGET_SPARC64
538 gen_cc_NZ_xcc(cpu_cc_dst
);
539 gen_cc_C_add_xcc(cpu_cc_dst
, cpu_cc_src
);
540 gen_cc_V_add_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
542 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
547 env->psr |= PSR_CARRY;
549 static inline void gen_cc_C_sub_icc(TCGv src1
, TCGv src2
)
551 TCGv r_temp1
, r_temp2
;
554 l1
= gen_new_label();
555 r_temp1
= tcg_temp_new(TCG_TYPE_TL
);
556 r_temp2
= tcg_temp_new(TCG_TYPE_TL
);
557 tcg_gen_andi_tl(r_temp1
, src1
, 0xffffffffULL
);
558 tcg_gen_andi_tl(r_temp2
, src2
, 0xffffffffULL
);
559 tcg_gen_brcond_tl(TCG_COND_GEU
, r_temp1
, r_temp2
, l1
);
560 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_CARRY
);
562 tcg_temp_free(r_temp1
);
563 tcg_temp_free(r_temp2
);
566 #ifdef TARGET_SPARC64
567 static inline void gen_cc_C_sub_xcc(TCGv src1
, TCGv src2
)
571 l1
= gen_new_label();
572 tcg_gen_brcond_tl(TCG_COND_GEU
, src1
, src2
, l1
);
573 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_CARRY
);
579 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
582 static inline void gen_cc_V_sub_icc(TCGv dst
, TCGv src1
, TCGv src2
)
586 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
587 tcg_gen_xor_tl(r_temp
, src1
, src2
);
588 tcg_gen_xor_tl(cpu_tmp0
, src1
, dst
);
589 tcg_gen_and_tl(r_temp
, r_temp
, cpu_tmp0
);
590 tcg_gen_andi_tl(r_temp
, r_temp
, (1ULL << 31));
591 tcg_gen_shri_tl(r_temp
, r_temp
, 31 - PSR_OVF_SHIFT
);
592 tcg_gen_trunc_tl_i32(cpu_tmp32
, r_temp
);
593 tcg_gen_or_i32(cpu_psr
, cpu_psr
, cpu_tmp32
);
594 tcg_temp_free(r_temp
);
597 #ifdef TARGET_SPARC64
598 static inline void gen_cc_V_sub_xcc(TCGv dst
, TCGv src1
, TCGv src2
)
602 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
603 tcg_gen_xor_tl(r_temp
, src1
, src2
);
604 tcg_gen_xor_tl(cpu_tmp0
, src1
, dst
);
605 tcg_gen_and_tl(r_temp
, r_temp
, cpu_tmp0
);
606 tcg_gen_andi_tl(r_temp
, r_temp
, (1ULL << 63));
607 tcg_gen_shri_tl(r_temp
, r_temp
, 63 - PSR_OVF_SHIFT
);
608 tcg_gen_trunc_tl_i32(cpu_tmp32
, r_temp
);
609 tcg_gen_or_i32(cpu_xcc
, cpu_xcc
, cpu_tmp32
);
610 tcg_temp_free(r_temp
);
614 static inline void gen_sub_tv(TCGv dst
, TCGv src1
, TCGv src2
)
616 TCGv r_temp
, r_const
;
619 l1
= gen_new_label();
621 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
622 tcg_gen_xor_tl(r_temp
, src1
, src2
);
623 tcg_gen_xor_tl(cpu_tmp0
, src1
, dst
);
624 tcg_gen_and_tl(r_temp
, r_temp
, cpu_tmp0
);
625 tcg_gen_andi_tl(r_temp
, r_temp
, (1ULL << 31));
626 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_temp
, 0, l1
);
627 r_const
= tcg_const_i32(TT_TOVF
);
628 tcg_gen_helper_0_1(raise_exception
, r_const
);
629 tcg_temp_free(r_const
);
631 tcg_temp_free(r_temp
);
634 static inline void gen_op_sub_cc(TCGv dst
, TCGv src1
, TCGv src2
)
636 tcg_gen_mov_tl(cpu_cc_src
, src1
);
637 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
638 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
640 gen_cc_NZ_icc(cpu_cc_dst
);
641 gen_cc_C_sub_icc(cpu_cc_src
, cpu_cc_src2
);
642 gen_cc_V_sub_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
643 #ifdef TARGET_SPARC64
645 gen_cc_NZ_xcc(cpu_cc_dst
);
646 gen_cc_C_sub_xcc(cpu_cc_src
, cpu_cc_src2
);
647 gen_cc_V_sub_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
649 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
652 static inline void gen_op_subx_cc(TCGv dst
, TCGv src1
, TCGv src2
)
654 tcg_gen_mov_tl(cpu_cc_src
, src1
);
655 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
656 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
657 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_tmp0
);
659 gen_cc_C_sub_icc(cpu_cc_dst
, cpu_cc_src
);
660 #ifdef TARGET_SPARC64
662 gen_cc_C_sub_xcc(cpu_cc_dst
, cpu_cc_src
);
664 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_dst
, cpu_cc_src2
);
665 gen_cc_NZ_icc(cpu_cc_dst
);
666 gen_cc_C_sub_icc(cpu_cc_dst
, cpu_cc_src
);
667 gen_cc_V_sub_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
668 #ifdef TARGET_SPARC64
669 gen_cc_NZ_xcc(cpu_cc_dst
);
670 gen_cc_C_sub_xcc(cpu_cc_dst
, cpu_cc_src
);
671 gen_cc_V_sub_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
673 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
676 static inline void gen_op_tsub_cc(TCGv dst
, TCGv src1
, TCGv src2
)
678 tcg_gen_mov_tl(cpu_cc_src
, src1
);
679 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
680 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
682 gen_cc_NZ_icc(cpu_cc_dst
);
683 gen_cc_C_sub_icc(cpu_cc_src
, cpu_cc_src2
);
684 gen_cc_V_sub_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
685 gen_cc_V_tag(cpu_cc_src
, cpu_cc_src2
);
686 #ifdef TARGET_SPARC64
688 gen_cc_NZ_xcc(cpu_cc_dst
);
689 gen_cc_C_sub_xcc(cpu_cc_src
, cpu_cc_src2
);
690 gen_cc_V_sub_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
692 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
695 static inline void gen_op_tsub_ccTV(TCGv dst
, TCGv src1
, TCGv src2
)
697 tcg_gen_mov_tl(cpu_cc_src
, src1
);
698 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
699 gen_tag_tv(cpu_cc_src
, cpu_cc_src2
);
700 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
701 gen_sub_tv(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
703 gen_cc_NZ_icc(cpu_cc_dst
);
704 gen_cc_C_sub_icc(cpu_cc_src
, cpu_cc_src2
);
705 #ifdef TARGET_SPARC64
707 gen_cc_NZ_xcc(cpu_cc_dst
);
708 gen_cc_C_sub_xcc(cpu_cc_src
, cpu_cc_src2
);
709 gen_cc_V_sub_xcc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
711 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
714 static inline void gen_op_mulscc(TCGv dst
, TCGv src1
, TCGv src2
)
716 TCGv r_temp
, r_temp2
;
719 l1
= gen_new_label();
720 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
721 r_temp2
= tcg_temp_new(TCG_TYPE_I32
);
727 tcg_gen_mov_tl(cpu_cc_src
, src1
);
728 tcg_gen_ld32u_tl(r_temp
, cpu_env
, offsetof(CPUSPARCState
, y
));
729 tcg_gen_trunc_tl_i32(r_temp2
, r_temp
);
730 tcg_gen_andi_i32(r_temp2
, r_temp2
, 0x1);
731 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
732 tcg_gen_brcondi_i32(TCG_COND_NE
, r_temp2
, 0, l1
);
733 tcg_gen_movi_tl(cpu_cc_src2
, 0);
737 // env->y = (b2 << 31) | (env->y >> 1);
738 tcg_gen_trunc_tl_i32(r_temp2
, cpu_cc_src
);
739 tcg_gen_andi_i32(r_temp2
, r_temp2
, 0x1);
740 tcg_gen_shli_i32(r_temp2
, r_temp2
, 31);
741 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, y
));
742 tcg_gen_shri_i32(cpu_tmp32
, cpu_tmp32
, 1);
743 tcg_gen_or_i32(cpu_tmp32
, cpu_tmp32
, r_temp2
);
744 tcg_temp_free(r_temp2
);
745 tcg_gen_st_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, y
));
748 gen_mov_reg_N(cpu_tmp0
, cpu_psr
);
749 gen_mov_reg_V(r_temp
, cpu_psr
);
750 tcg_gen_xor_tl(cpu_tmp0
, cpu_tmp0
, r_temp
);
751 tcg_temp_free(r_temp
);
753 // T0 = (b1 << 31) | (T0 >> 1);
755 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, 31);
756 tcg_gen_shri_tl(cpu_cc_src
, cpu_cc_src
, 1);
757 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
759 /* do addition and update flags */
760 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
763 gen_cc_NZ_icc(cpu_cc_dst
);
764 gen_cc_V_add_icc(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
765 gen_cc_C_add_icc(cpu_cc_dst
, cpu_cc_src
);
766 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
769 static inline void gen_op_umul(TCGv dst
, TCGv src1
, TCGv src2
)
771 TCGv r_temp
, r_temp2
;
773 r_temp
= tcg_temp_new(TCG_TYPE_I64
);
774 r_temp2
= tcg_temp_new(TCG_TYPE_I64
);
776 tcg_gen_extu_tl_i64(r_temp
, src2
);
777 tcg_gen_extu_tl_i64(r_temp2
, src1
);
778 tcg_gen_mul_i64(r_temp2
, r_temp
, r_temp2
);
780 tcg_gen_shri_i64(r_temp
, r_temp2
, 32);
781 tcg_gen_trunc_i64_i32(r_temp
, r_temp
);
782 tcg_gen_st_i32(r_temp
, cpu_env
, offsetof(CPUSPARCState
, y
));
783 tcg_temp_free(r_temp
);
784 #ifdef TARGET_SPARC64
785 tcg_gen_mov_i64(dst
, r_temp2
);
787 tcg_gen_trunc_i64_tl(dst
, r_temp2
);
789 tcg_temp_free(r_temp2
);
792 static inline void gen_op_smul(TCGv dst
, TCGv src1
, TCGv src2
)
794 TCGv r_temp
, r_temp2
;
796 r_temp
= tcg_temp_new(TCG_TYPE_I64
);
797 r_temp2
= tcg_temp_new(TCG_TYPE_I64
);
799 tcg_gen_ext_tl_i64(r_temp
, src2
);
800 tcg_gen_ext_tl_i64(r_temp2
, src1
);
801 tcg_gen_mul_i64(r_temp2
, r_temp
, r_temp2
);
803 tcg_gen_shri_i64(r_temp
, r_temp2
, 32);
804 tcg_gen_trunc_i64_i32(r_temp
, r_temp
);
805 tcg_gen_st_i32(r_temp
, cpu_env
, offsetof(CPUSPARCState
, y
));
806 tcg_temp_free(r_temp
);
807 #ifdef TARGET_SPARC64
808 tcg_gen_mov_i64(dst
, r_temp2
);
810 tcg_gen_trunc_i64_tl(dst
, r_temp2
);
812 tcg_temp_free(r_temp2
);
815 #ifdef TARGET_SPARC64
816 static inline void gen_trap_ifdivzero_tl(TCGv divisor
)
821 l1
= gen_new_label();
822 tcg_gen_brcondi_tl(TCG_COND_NE
, divisor
, 0, l1
);
823 r_const
= tcg_const_i32(TT_DIV_ZERO
);
824 tcg_gen_helper_0_1(raise_exception
, r_const
);
825 tcg_temp_free(r_const
);
829 static inline void gen_op_sdivx(TCGv dst
, TCGv src1
, TCGv src2
)
833 l1
= gen_new_label();
834 l2
= gen_new_label();
835 tcg_gen_mov_tl(cpu_cc_src
, src1
);
836 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
837 gen_trap_ifdivzero_tl(cpu_cc_src2
);
838 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_cc_src
, INT64_MIN
, l1
);
839 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_cc_src2
, -1, l1
);
840 tcg_gen_movi_i64(dst
, INT64_MIN
);
843 tcg_gen_div_i64(dst
, cpu_cc_src
, cpu_cc_src2
);
848 static inline void gen_op_div_cc(TCGv dst
)
852 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
854 gen_cc_NZ_icc(cpu_cc_dst
);
855 l1
= gen_new_label();
856 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_cc_src2
, 0, l1
);
857 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_OVF
);
861 static inline void gen_op_logic_cc(TCGv dst
)
863 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
866 gen_cc_NZ_icc(cpu_cc_dst
);
867 #ifdef TARGET_SPARC64
869 gen_cc_NZ_xcc(cpu_cc_dst
);
874 static inline void gen_op_eval_ba(TCGv dst
)
876 tcg_gen_movi_tl(dst
, 1);
880 static inline void gen_op_eval_be(TCGv dst
, TCGv src
)
882 gen_mov_reg_Z(dst
, src
);
886 static inline void gen_op_eval_ble(TCGv dst
, TCGv src
)
888 gen_mov_reg_N(cpu_tmp0
, src
);
889 gen_mov_reg_V(dst
, src
);
890 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
891 gen_mov_reg_Z(cpu_tmp0
, src
);
892 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
896 static inline void gen_op_eval_bl(TCGv dst
, TCGv src
)
898 gen_mov_reg_V(cpu_tmp0
, src
);
899 gen_mov_reg_N(dst
, src
);
900 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
904 static inline void gen_op_eval_bleu(TCGv dst
, TCGv src
)
906 gen_mov_reg_Z(cpu_tmp0
, src
);
907 gen_mov_reg_C(dst
, src
);
908 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
912 static inline void gen_op_eval_bcs(TCGv dst
, TCGv src
)
914 gen_mov_reg_C(dst
, src
);
918 static inline void gen_op_eval_bvs(TCGv dst
, TCGv src
)
920 gen_mov_reg_V(dst
, src
);
924 static inline void gen_op_eval_bn(TCGv dst
)
926 tcg_gen_movi_tl(dst
, 0);
930 static inline void gen_op_eval_bneg(TCGv dst
, TCGv src
)
932 gen_mov_reg_N(dst
, src
);
936 static inline void gen_op_eval_bne(TCGv dst
, TCGv src
)
938 gen_mov_reg_Z(dst
, src
);
939 tcg_gen_xori_tl(dst
, dst
, 0x1);
943 static inline void gen_op_eval_bg(TCGv dst
, TCGv src
)
945 gen_mov_reg_N(cpu_tmp0
, src
);
946 gen_mov_reg_V(dst
, src
);
947 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
948 gen_mov_reg_Z(cpu_tmp0
, src
);
949 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
950 tcg_gen_xori_tl(dst
, dst
, 0x1);
954 static inline void gen_op_eval_bge(TCGv dst
, TCGv src
)
956 gen_mov_reg_V(cpu_tmp0
, src
);
957 gen_mov_reg_N(dst
, src
);
958 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
959 tcg_gen_xori_tl(dst
, dst
, 0x1);
963 static inline void gen_op_eval_bgu(TCGv dst
, TCGv src
)
965 gen_mov_reg_Z(cpu_tmp0
, src
);
966 gen_mov_reg_C(dst
, src
);
967 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
968 tcg_gen_xori_tl(dst
, dst
, 0x1);
972 static inline void gen_op_eval_bcc(TCGv dst
, TCGv src
)
974 gen_mov_reg_C(dst
, src
);
975 tcg_gen_xori_tl(dst
, dst
, 0x1);
979 static inline void gen_op_eval_bpos(TCGv dst
, TCGv src
)
981 gen_mov_reg_N(dst
, src
);
982 tcg_gen_xori_tl(dst
, dst
, 0x1);
986 static inline void gen_op_eval_bvc(TCGv dst
, TCGv src
)
988 gen_mov_reg_V(dst
, src
);
989 tcg_gen_xori_tl(dst
, dst
, 0x1);
993 FPSR bit field FCC1 | FCC0:
999 static inline void gen_mov_reg_FCC0(TCGv reg
, TCGv src
,
1000 unsigned int fcc_offset
)
1002 tcg_gen_extu_i32_tl(reg
, src
);
1003 tcg_gen_shri_tl(reg
, reg
, FSR_FCC0_SHIFT
+ fcc_offset
);
1004 tcg_gen_andi_tl(reg
, reg
, 0x1);
1007 static inline void gen_mov_reg_FCC1(TCGv reg
, TCGv src
,
1008 unsigned int fcc_offset
)
1010 tcg_gen_extu_i32_tl(reg
, src
);
1011 tcg_gen_shri_tl(reg
, reg
, FSR_FCC1_SHIFT
+ fcc_offset
);
1012 tcg_gen_andi_tl(reg
, reg
, 0x1);
1016 static inline void gen_op_eval_fbne(TCGv dst
, TCGv src
,
1017 unsigned int fcc_offset
)
1019 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1020 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1021 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
1024 // 1 or 2: FCC0 ^ FCC1
1025 static inline void gen_op_eval_fblg(TCGv dst
, TCGv src
,
1026 unsigned int fcc_offset
)
1028 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1029 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1030 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
1034 static inline void gen_op_eval_fbul(TCGv dst
, TCGv src
,
1035 unsigned int fcc_offset
)
1037 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1041 static inline void gen_op_eval_fbl(TCGv dst
, TCGv src
,
1042 unsigned int fcc_offset
)
1044 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1045 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1046 tcg_gen_xori_tl(cpu_tmp0
, cpu_tmp0
, 0x1);
1047 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
1051 static inline void gen_op_eval_fbug(TCGv dst
, TCGv src
,
1052 unsigned int fcc_offset
)
1054 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
1058 static inline void gen_op_eval_fbg(TCGv dst
, TCGv src
,
1059 unsigned int fcc_offset
)
1061 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1062 tcg_gen_xori_tl(dst
, dst
, 0x1);
1063 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1064 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
1068 static inline void gen_op_eval_fbu(TCGv dst
, TCGv src
,
1069 unsigned int fcc_offset
)
1071 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1072 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1073 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
1076 // 0: !(FCC0 | FCC1)
1077 static inline void gen_op_eval_fbe(TCGv dst
, TCGv src
,
1078 unsigned int fcc_offset
)
1080 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1081 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1082 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
1083 tcg_gen_xori_tl(dst
, dst
, 0x1);
1086 // 0 or 3: !(FCC0 ^ FCC1)
1087 static inline void gen_op_eval_fbue(TCGv dst
, TCGv src
,
1088 unsigned int fcc_offset
)
1090 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1091 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1092 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
1093 tcg_gen_xori_tl(dst
, dst
, 0x1);
1097 static inline void gen_op_eval_fbge(TCGv dst
, TCGv src
,
1098 unsigned int fcc_offset
)
1100 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1101 tcg_gen_xori_tl(dst
, dst
, 0x1);
1104 // !1: !(FCC0 & !FCC1)
1105 static inline void gen_op_eval_fbuge(TCGv dst
, TCGv src
,
1106 unsigned int fcc_offset
)
1108 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1109 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1110 tcg_gen_xori_tl(cpu_tmp0
, cpu_tmp0
, 0x1);
1111 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
1112 tcg_gen_xori_tl(dst
, dst
, 0x1);
1116 static inline void gen_op_eval_fble(TCGv dst
, TCGv src
,
1117 unsigned int fcc_offset
)
1119 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
1120 tcg_gen_xori_tl(dst
, dst
, 0x1);
1123 // !2: !(!FCC0 & FCC1)
1124 static inline void gen_op_eval_fbule(TCGv dst
, TCGv src
,
1125 unsigned int fcc_offset
)
1127 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1128 tcg_gen_xori_tl(dst
, dst
, 0x1);
1129 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1130 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
1131 tcg_gen_xori_tl(dst
, dst
, 0x1);
1134 // !3: !(FCC0 & FCC1)
1135 static inline void gen_op_eval_fbo(TCGv dst
, TCGv src
,
1136 unsigned int fcc_offset
)
1138 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1139 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
1140 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
1141 tcg_gen_xori_tl(dst
, dst
, 0x1);
1144 static inline void gen_branch2(DisasContext
*dc
, target_ulong pc1
,
1145 target_ulong pc2
, TCGv r_cond
)
1149 l1
= gen_new_label();
1151 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
1153 gen_goto_tb(dc
, 0, pc1
, pc1
+ 4);
1156 gen_goto_tb(dc
, 1, pc2
, pc2
+ 4);
1159 static inline void gen_branch_a(DisasContext
*dc
, target_ulong pc1
,
1160 target_ulong pc2
, TCGv r_cond
)
1164 l1
= gen_new_label();
1166 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
1168 gen_goto_tb(dc
, 0, pc2
, pc1
);
1171 gen_goto_tb(dc
, 1, pc2
+ 4, pc2
+ 8);
1174 static inline void gen_generic_branch(target_ulong npc1
, target_ulong npc2
,
1179 l1
= gen_new_label();
1180 l2
= gen_new_label();
1182 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
1184 tcg_gen_movi_tl(cpu_npc
, npc1
);
1188 tcg_gen_movi_tl(cpu_npc
, npc2
);
1192 /* call this function before using the condition register as it may
1193 have been set for a jump */
1194 static inline void flush_cond(DisasContext
*dc
, TCGv cond
)
1196 if (dc
->npc
== JUMP_PC
) {
1197 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1], cond
);
1198 dc
->npc
= DYNAMIC_PC
;
1202 static inline void save_npc(DisasContext
*dc
, TCGv cond
)
1204 if (dc
->npc
== JUMP_PC
) {
1205 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1], cond
);
1206 dc
->npc
= DYNAMIC_PC
;
1207 } else if (dc
->npc
!= DYNAMIC_PC
) {
1208 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
1212 static inline void save_state(DisasContext
*dc
, TCGv cond
)
1214 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1218 static inline void gen_mov_pc_npc(DisasContext
*dc
, TCGv cond
)
1220 if (dc
->npc
== JUMP_PC
) {
1221 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1], cond
);
1222 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1223 dc
->pc
= DYNAMIC_PC
;
1224 } else if (dc
->npc
== DYNAMIC_PC
) {
1225 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1226 dc
->pc
= DYNAMIC_PC
;
1232 static inline void gen_op_next_insn(void)
1234 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1235 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
1238 static inline void gen_cond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1242 #ifdef TARGET_SPARC64
1252 gen_op_eval_bn(r_dst
);
1255 gen_op_eval_be(r_dst
, r_src
);
1258 gen_op_eval_ble(r_dst
, r_src
);
1261 gen_op_eval_bl(r_dst
, r_src
);
1264 gen_op_eval_bleu(r_dst
, r_src
);
1267 gen_op_eval_bcs(r_dst
, r_src
);
1270 gen_op_eval_bneg(r_dst
, r_src
);
1273 gen_op_eval_bvs(r_dst
, r_src
);
1276 gen_op_eval_ba(r_dst
);
1279 gen_op_eval_bne(r_dst
, r_src
);
1282 gen_op_eval_bg(r_dst
, r_src
);
1285 gen_op_eval_bge(r_dst
, r_src
);
1288 gen_op_eval_bgu(r_dst
, r_src
);
1291 gen_op_eval_bcc(r_dst
, r_src
);
1294 gen_op_eval_bpos(r_dst
, r_src
);
1297 gen_op_eval_bvc(r_dst
, r_src
);
1302 static inline void gen_fcond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1304 unsigned int offset
;
1324 gen_op_eval_bn(r_dst
);
1327 gen_op_eval_fbne(r_dst
, cpu_fsr
, offset
);
1330 gen_op_eval_fblg(r_dst
, cpu_fsr
, offset
);
1333 gen_op_eval_fbul(r_dst
, cpu_fsr
, offset
);
1336 gen_op_eval_fbl(r_dst
, cpu_fsr
, offset
);
1339 gen_op_eval_fbug(r_dst
, cpu_fsr
, offset
);
1342 gen_op_eval_fbg(r_dst
, cpu_fsr
, offset
);
1345 gen_op_eval_fbu(r_dst
, cpu_fsr
, offset
);
1348 gen_op_eval_ba(r_dst
);
1351 gen_op_eval_fbe(r_dst
, cpu_fsr
, offset
);
1354 gen_op_eval_fbue(r_dst
, cpu_fsr
, offset
);
1357 gen_op_eval_fbge(r_dst
, cpu_fsr
, offset
);
1360 gen_op_eval_fbuge(r_dst
, cpu_fsr
, offset
);
1363 gen_op_eval_fble(r_dst
, cpu_fsr
, offset
);
1366 gen_op_eval_fbule(r_dst
, cpu_fsr
, offset
);
1369 gen_op_eval_fbo(r_dst
, cpu_fsr
, offset
);
1374 #ifdef TARGET_SPARC64
1376 static const int gen_tcg_cond_reg
[8] = {
1387 static inline void gen_cond_reg(TCGv r_dst
, int cond
, TCGv r_src
)
1391 l1
= gen_new_label();
1392 tcg_gen_movi_tl(r_dst
, 0);
1393 tcg_gen_brcondi_tl(gen_tcg_cond_reg
[cond
], r_src
, 0, l1
);
1394 tcg_gen_movi_tl(r_dst
, 1);
1399 /* XXX: potentially incorrect if dynamic npc */
1400 static void do_branch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
,
1403 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1404 target_ulong target
= dc
->pc
+ offset
;
1407 /* unconditional not taken */
1409 dc
->pc
= dc
->npc
+ 4;
1410 dc
->npc
= dc
->pc
+ 4;
1413 dc
->npc
= dc
->pc
+ 4;
1415 } else if (cond
== 0x8) {
1416 /* unconditional taken */
1419 dc
->npc
= dc
->pc
+ 4;
1425 flush_cond(dc
, r_cond
);
1426 gen_cond(r_cond
, cc
, cond
);
1428 gen_branch_a(dc
, target
, dc
->npc
, r_cond
);
1432 dc
->jump_pc
[0] = target
;
1433 dc
->jump_pc
[1] = dc
->npc
+ 4;
1439 /* XXX: potentially incorrect if dynamic npc */
1440 static void do_fbranch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
,
1443 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1444 target_ulong target
= dc
->pc
+ offset
;
1447 /* unconditional not taken */
1449 dc
->pc
= dc
->npc
+ 4;
1450 dc
->npc
= dc
->pc
+ 4;
1453 dc
->npc
= dc
->pc
+ 4;
1455 } else if (cond
== 0x8) {
1456 /* unconditional taken */
1459 dc
->npc
= dc
->pc
+ 4;
1465 flush_cond(dc
, r_cond
);
1466 gen_fcond(r_cond
, cc
, cond
);
1468 gen_branch_a(dc
, target
, dc
->npc
, r_cond
);
1472 dc
->jump_pc
[0] = target
;
1473 dc
->jump_pc
[1] = dc
->npc
+ 4;
1479 #ifdef TARGET_SPARC64
1480 /* XXX: potentially incorrect if dynamic npc */
1481 static void do_branch_reg(DisasContext
*dc
, int32_t offset
, uint32_t insn
,
1482 TCGv r_cond
, TCGv r_reg
)
1484 unsigned int cond
= GET_FIELD_SP(insn
, 25, 27), a
= (insn
& (1 << 29));
1485 target_ulong target
= dc
->pc
+ offset
;
1487 flush_cond(dc
, r_cond
);
1488 gen_cond_reg(r_cond
, cond
, r_reg
);
1490 gen_branch_a(dc
, target
, dc
->npc
, r_cond
);
1494 dc
->jump_pc
[0] = target
;
1495 dc
->jump_pc
[1] = dc
->npc
+ 4;
1500 static GenOpFunc
* const gen_fcmps
[4] = {
1507 static GenOpFunc
* const gen_fcmpd
[4] = {
1514 static GenOpFunc
* const gen_fcmpq
[4] = {
1521 static GenOpFunc
* const gen_fcmpes
[4] = {
1528 static GenOpFunc
* const gen_fcmped
[4] = {
1535 static GenOpFunc
* const gen_fcmpeq
[4] = {
1542 static inline void gen_op_fcmps(int fccno
)
1544 tcg_gen_helper_0_0(gen_fcmps
[fccno
]);
1547 static inline void gen_op_fcmpd(int fccno
)
1549 tcg_gen_helper_0_0(gen_fcmpd
[fccno
]);
1552 static inline void gen_op_fcmpq(int fccno
)
1554 tcg_gen_helper_0_0(gen_fcmpq
[fccno
]);
1557 static inline void gen_op_fcmpes(int fccno
)
1559 tcg_gen_helper_0_0(gen_fcmpes
[fccno
]);
1562 static inline void gen_op_fcmped(int fccno
)
1564 tcg_gen_helper_0_0(gen_fcmped
[fccno
]);
1567 static inline void gen_op_fcmpeq(int fccno
)
1569 tcg_gen_helper_0_0(gen_fcmpeq
[fccno
]);
1574 static inline void gen_op_fcmps(int fccno
)
1576 tcg_gen_helper_0_0(helper_fcmps
);
1579 static inline void gen_op_fcmpd(int fccno
)
1581 tcg_gen_helper_0_0(helper_fcmpd
);
1584 static inline void gen_op_fcmpq(int fccno
)
1586 tcg_gen_helper_0_0(helper_fcmpq
);
1589 static inline void gen_op_fcmpes(int fccno
)
1591 tcg_gen_helper_0_0(helper_fcmpes
);
1594 static inline void gen_op_fcmped(int fccno
)
1596 tcg_gen_helper_0_0(helper_fcmped
);
1599 static inline void gen_op_fcmpeq(int fccno
)
1601 tcg_gen_helper_0_0(helper_fcmpeq
);
1605 static inline void gen_op_fpexception_im(int fsr_flags
)
1609 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, ~FSR_FTT_MASK
);
1610 tcg_gen_ori_tl(cpu_fsr
, cpu_fsr
, fsr_flags
);
1611 r_const
= tcg_const_i32(TT_FP_EXCP
);
1612 tcg_gen_helper_0_1(raise_exception
, r_const
);
1613 tcg_temp_free(r_const
);
1616 static int gen_trap_ifnofpu(DisasContext
*dc
, TCGv r_cond
)
1618 #if !defined(CONFIG_USER_ONLY)
1619 if (!dc
->fpu_enabled
) {
1622 save_state(dc
, r_cond
);
1623 r_const
= tcg_const_i32(TT_NFPU_INSN
);
1624 tcg_gen_helper_0_1(raise_exception
, r_const
);
1625 tcg_temp_free(r_const
);
1633 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1635 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, ~(FSR_FTT_MASK
| FSR_CEXC_MASK
));
1638 static inline void gen_clear_float_exceptions(void)
1640 tcg_gen_helper_0_0(helper_clear_float_exceptions
);
1644 #ifdef TARGET_SPARC64
1645 static inline TCGv
gen_get_asi(int insn
, TCGv r_addr
)
1651 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1652 tcg_gen_ld_i32(r_asi
, cpu_env
, offsetof(CPUSPARCState
, asi
));
1654 asi
= GET_FIELD(insn
, 19, 26);
1655 r_asi
= tcg_const_i32(asi
);
1660 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
1663 TCGv r_asi
, r_size
, r_sign
;
1665 r_asi
= gen_get_asi(insn
, addr
);
1666 r_size
= tcg_const_i32(size
);
1667 r_sign
= tcg_const_i32(sign
);
1668 tcg_gen_helper_1_4(helper_ld_asi
, dst
, addr
, r_asi
, r_size
, r_sign
);
1669 tcg_temp_free(r_sign
);
1670 tcg_temp_free(r_size
);
1671 tcg_temp_free(r_asi
);
1674 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
1678 r_asi
= gen_get_asi(insn
, addr
);
1679 r_size
= tcg_const_i32(size
);
1680 tcg_gen_helper_0_4(helper_st_asi
, addr
, src
, r_asi
, r_size
);
1681 tcg_temp_free(r_size
);
1682 tcg_temp_free(r_asi
);
1685 static inline void gen_ldf_asi(TCGv addr
, int insn
, int size
, int rd
)
1687 TCGv r_asi
, r_size
, r_rd
;
1689 r_asi
= gen_get_asi(insn
, addr
);
1690 r_size
= tcg_const_i32(size
);
1691 r_rd
= tcg_const_i32(rd
);
1692 tcg_gen_helper_0_4(helper_ldf_asi
, addr
, r_asi
, r_size
, r_rd
);
1693 tcg_temp_free(r_rd
);
1694 tcg_temp_free(r_size
);
1695 tcg_temp_free(r_asi
);
1698 static inline void gen_stf_asi(TCGv addr
, int insn
, int size
, int rd
)
1700 TCGv r_asi
, r_size
, r_rd
;
1702 r_asi
= gen_get_asi(insn
, addr
);
1703 r_size
= tcg_const_i32(size
);
1704 r_rd
= tcg_const_i32(rd
);
1705 tcg_gen_helper_0_4(helper_stf_asi
, addr
, r_asi
, r_size
, r_rd
);
1706 tcg_temp_free(r_rd
);
1707 tcg_temp_free(r_size
);
1708 tcg_temp_free(r_asi
);
1711 static inline void gen_swap_asi(TCGv dst
, TCGv addr
, int insn
)
1713 TCGv r_asi
, r_size
, r_sign
;
1715 r_asi
= gen_get_asi(insn
, addr
);
1716 r_size
= tcg_const_i32(4);
1717 r_sign
= tcg_const_i32(0);
1718 tcg_gen_helper_1_4(helper_ld_asi
, cpu_tmp64
, addr
, r_asi
, r_size
, r_sign
);
1719 tcg_temp_free(r_sign
);
1720 tcg_gen_helper_0_4(helper_st_asi
, addr
, dst
, r_asi
, r_size
);
1721 tcg_temp_free(r_size
);
1722 tcg_temp_free(r_asi
);
1723 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
1726 static inline void gen_ldda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
1730 r_asi
= gen_get_asi(insn
, addr
);
1731 r_rd
= tcg_const_i32(rd
);
1732 tcg_gen_helper_0_3(helper_ldda_asi
, addr
, r_asi
, r_rd
);
1733 tcg_temp_free(r_rd
);
1734 tcg_temp_free(r_asi
);
1737 static inline void gen_stda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
1739 TCGv r_temp
, r_asi
, r_size
;
1741 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
1742 gen_movl_reg_TN(rd
+ 1, r_temp
);
1743 tcg_gen_helper_1_2(helper_pack64
, cpu_tmp64
, hi
,
1745 tcg_temp_free(r_temp
);
1746 r_asi
= gen_get_asi(insn
, addr
);
1747 r_size
= tcg_const_i32(8);
1748 tcg_gen_helper_0_4(helper_st_asi
, addr
, cpu_tmp64
, r_asi
, r_size
);
1749 tcg_temp_free(r_size
);
1750 tcg_temp_free(r_asi
);
1753 static inline void gen_cas_asi(TCGv dst
, TCGv addr
, TCGv val2
, int insn
,
1758 r_val1
= tcg_temp_new(TCG_TYPE_TL
);
1759 gen_movl_reg_TN(rd
, r_val1
);
1760 r_asi
= gen_get_asi(insn
, addr
);
1761 tcg_gen_helper_1_4(helper_cas_asi
, dst
, addr
, r_val1
, val2
, r_asi
);
1762 tcg_temp_free(r_asi
);
1763 tcg_temp_free(r_val1
);
1766 static inline void gen_casx_asi(TCGv dst
, TCGv addr
, TCGv val2
, int insn
,
1771 gen_movl_reg_TN(rd
, cpu_tmp64
);
1772 r_asi
= gen_get_asi(insn
, addr
);
1773 tcg_gen_helper_1_4(helper_casx_asi
, dst
, addr
, cpu_tmp64
, val2
, r_asi
);
1774 tcg_temp_free(r_asi
);
1777 #elif !defined(CONFIG_USER_ONLY)
1779 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
1782 TCGv r_asi
, r_size
, r_sign
;
1784 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
1785 r_size
= tcg_const_i32(size
);
1786 r_sign
= tcg_const_i32(sign
);
1787 tcg_gen_helper_1_4(helper_ld_asi
, cpu_tmp64
, addr
, r_asi
, r_size
, r_sign
);
1788 tcg_temp_free(r_sign
);
1789 tcg_temp_free(r_size
);
1790 tcg_temp_free(r_asi
);
1791 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
1794 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
1798 tcg_gen_extu_tl_i64(cpu_tmp64
, src
);
1799 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
1800 r_size
= tcg_const_i32(size
);
1801 tcg_gen_helper_0_4(helper_st_asi
, addr
, cpu_tmp64
, r_asi
, r_size
);
1802 tcg_temp_free(r_size
);
1803 tcg_temp_free(r_asi
);
1806 static inline void gen_swap_asi(TCGv dst
, TCGv addr
, int insn
)
1808 TCGv r_asi
, r_size
, r_sign
;
1810 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
1811 r_size
= tcg_const_i32(4);
1812 r_sign
= tcg_const_i32(0);
1813 tcg_gen_helper_1_4(helper_ld_asi
, cpu_tmp64
, addr
, r_asi
, r_size
, r_sign
);
1814 tcg_temp_free(r_sign
);
1815 tcg_gen_helper_0_4(helper_st_asi
, addr
, dst
, r_asi
, r_size
);
1816 tcg_temp_free(r_size
);
1817 tcg_temp_free(r_asi
);
1818 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
1821 static inline void gen_ldda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
1823 TCGv r_asi
, r_size
, r_sign
;
1825 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
1826 r_size
= tcg_const_i32(8);
1827 r_sign
= tcg_const_i32(0);
1828 tcg_gen_helper_1_4(helper_ld_asi
, cpu_tmp64
, addr
, r_asi
, r_size
, r_sign
);
1829 tcg_temp_free(r_sign
);
1830 tcg_temp_free(r_size
);
1831 tcg_temp_free(r_asi
);
1832 tcg_gen_trunc_i64_tl(cpu_tmp0
, cpu_tmp64
);
1833 gen_movl_TN_reg(rd
+ 1, cpu_tmp0
);
1834 tcg_gen_shri_i64(cpu_tmp64
, cpu_tmp64
, 32);
1835 tcg_gen_trunc_i64_tl(hi
, cpu_tmp64
);
1836 gen_movl_TN_reg(rd
, hi
);
1839 static inline void gen_stda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
1841 TCGv r_temp
, r_asi
, r_size
;
1843 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
1844 gen_movl_reg_TN(rd
+ 1, r_temp
);
1845 tcg_gen_helper_1_2(helper_pack64
, cpu_tmp64
, hi
, r_temp
);
1846 tcg_temp_free(r_temp
);
1847 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
1848 r_size
= tcg_const_i32(8);
1849 tcg_gen_helper_0_4(helper_st_asi
, addr
, cpu_tmp64
, r_asi
, r_size
);
1850 tcg_temp_free(r_size
);
1851 tcg_temp_free(r_asi
);
1855 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1856 static inline void gen_ldstub_asi(TCGv dst
, TCGv addr
, int insn
)
1858 TCGv r_val
, r_asi
, r_size
;
1860 gen_ld_asi(dst
, addr
, insn
, 1, 0);
1862 r_val
= tcg_const_i64(0xffULL
);
1863 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
1864 r_size
= tcg_const_i32(1);
1865 tcg_gen_helper_0_4(helper_st_asi
, addr
, r_val
, r_asi
, r_size
);
1866 tcg_temp_free(r_size
);
1867 tcg_temp_free(r_asi
);
1868 tcg_temp_free(r_val
);
1872 static inline TCGv
get_src1(unsigned int insn
, TCGv def
)
1877 rs1
= GET_FIELD(insn
, 13, 17);
1879 r_rs1
= tcg_const_tl(0); // XXX how to free?
1881 r_rs1
= cpu_gregs
[rs1
];
1883 tcg_gen_ld_tl(def
, cpu_regwptr
, (rs1
- 8) * sizeof(target_ulong
));
1887 static inline TCGv
get_src2(unsigned int insn
, TCGv def
)
1892 if (IS_IMM
) { /* immediate */
1893 rs2
= GET_FIELDs(insn
, 19, 31);
1894 r_rs2
= tcg_const_tl((int)rs2
); // XXX how to free?
1895 } else { /* register */
1896 rs2
= GET_FIELD(insn
, 27, 31);
1898 r_rs2
= tcg_const_tl(0); // XXX how to free?
1900 r_rs2
= cpu_gregs
[rs2
];
1902 tcg_gen_ld_tl(def
, cpu_regwptr
, (rs2
- 8) * sizeof(target_ulong
));
1907 #define CHECK_IU_FEATURE(dc, FEATURE) \
1908 if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1910 #define CHECK_FPU_FEATURE(dc, FEATURE) \
1911 if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1914 /* before an instruction, dc->pc must be static */
1915 static void disas_sparc_insn(DisasContext
* dc
)
1917 unsigned int insn
, opc
, rs1
, rs2
, rd
;
1919 if (unlikely(loglevel
& CPU_LOG_TB_OP
))
1920 tcg_gen_debug_insn_start(dc
->pc
);
1921 insn
= ldl_code(dc
->pc
);
1922 opc
= GET_FIELD(insn
, 0, 1);
1924 rd
= GET_FIELD(insn
, 2, 6);
1926 cpu_src1
= tcg_temp_new(TCG_TYPE_TL
); // const
1927 cpu_src2
= tcg_temp_new(TCG_TYPE_TL
); // const
1930 case 0: /* branches/sethi */
1932 unsigned int xop
= GET_FIELD(insn
, 7, 9);
1935 #ifdef TARGET_SPARC64
1936 case 0x1: /* V9 BPcc */
1940 target
= GET_FIELD_SP(insn
, 0, 18);
1941 target
= sign_extend(target
, 18);
1943 cc
= GET_FIELD_SP(insn
, 20, 21);
1945 do_branch(dc
, target
, insn
, 0, cpu_cond
);
1947 do_branch(dc
, target
, insn
, 1, cpu_cond
);
1952 case 0x3: /* V9 BPr */
1954 target
= GET_FIELD_SP(insn
, 0, 13) |
1955 (GET_FIELD_SP(insn
, 20, 21) << 14);
1956 target
= sign_extend(target
, 16);
1958 cpu_src1
= get_src1(insn
, cpu_src1
);
1959 do_branch_reg(dc
, target
, insn
, cpu_cond
, cpu_src1
);
1962 case 0x5: /* V9 FBPcc */
1964 int cc
= GET_FIELD_SP(insn
, 20, 21);
1965 if (gen_trap_ifnofpu(dc
, cpu_cond
))
1967 target
= GET_FIELD_SP(insn
, 0, 18);
1968 target
= sign_extend(target
, 19);
1970 do_fbranch(dc
, target
, insn
, cc
, cpu_cond
);
1974 case 0x7: /* CBN+x */
1979 case 0x2: /* BN+x */
1981 target
= GET_FIELD(insn
, 10, 31);
1982 target
= sign_extend(target
, 22);
1984 do_branch(dc
, target
, insn
, 0, cpu_cond
);
1987 case 0x6: /* FBN+x */
1989 if (gen_trap_ifnofpu(dc
, cpu_cond
))
1991 target
= GET_FIELD(insn
, 10, 31);
1992 target
= sign_extend(target
, 22);
1994 do_fbranch(dc
, target
, insn
, 0, cpu_cond
);
1997 case 0x4: /* SETHI */
1999 uint32_t value
= GET_FIELD(insn
, 10, 31);
2002 r_const
= tcg_const_tl(value
<< 10);
2003 gen_movl_TN_reg(rd
, r_const
);
2004 tcg_temp_free(r_const
);
2007 case 0x0: /* UNIMPL */
2016 target_long target
= GET_FIELDs(insn
, 2, 31) << 2;
2019 r_const
= tcg_const_tl(dc
->pc
);
2020 gen_movl_TN_reg(15, r_const
);
2021 tcg_temp_free(r_const
);
2023 gen_mov_pc_npc(dc
, cpu_cond
);
2027 case 2: /* FPU & Logical Operations */
2029 unsigned int xop
= GET_FIELD(insn
, 7, 12);
2030 if (xop
== 0x3a) { /* generate trap */
2033 cpu_src1
= get_src1(insn
, cpu_src1
);
2035 rs2
= GET_FIELD(insn
, 25, 31);
2036 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, rs2
);
2038 rs2
= GET_FIELD(insn
, 27, 31);
2040 gen_movl_reg_TN(rs2
, cpu_src2
);
2041 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
2043 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
2045 cond
= GET_FIELD(insn
, 3, 6);
2047 save_state(dc
, cpu_cond
);
2048 tcg_gen_helper_0_1(helper_trap
, cpu_dst
);
2049 } else if (cond
!= 0) {
2050 TCGv r_cond
= tcg_temp_new(TCG_TYPE_TL
);
2051 #ifdef TARGET_SPARC64
2053 int cc
= GET_FIELD_SP(insn
, 11, 12);
2055 save_state(dc
, cpu_cond
);
2057 gen_cond(r_cond
, 0, cond
);
2059 gen_cond(r_cond
, 1, cond
);
2063 save_state(dc
, cpu_cond
);
2064 gen_cond(r_cond
, 0, cond
);
2066 tcg_gen_helper_0_2(helper_trapcc
, cpu_dst
, r_cond
);
2067 tcg_temp_free(r_cond
);
2073 } else if (xop
== 0x28) {
2074 rs1
= GET_FIELD(insn
, 13, 17);
2077 #ifndef TARGET_SPARC64
2078 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2079 manual, rdy on the microSPARC
2081 case 0x0f: /* stbar in the SPARCv8 manual,
2082 rdy on the microSPARC II */
2083 case 0x10 ... 0x1f: /* implementation-dependent in the
2084 SPARCv8 manual, rdy on the
2087 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2088 offsetof(CPUSPARCState
, y
));
2089 gen_movl_TN_reg(rd
, cpu_tmp0
);
2091 #ifdef TARGET_SPARC64
2092 case 0x2: /* V9 rdccr */
2093 tcg_gen_helper_1_0(helper_rdccr
, cpu_dst
);
2094 gen_movl_TN_reg(rd
, cpu_dst
);
2096 case 0x3: /* V9 rdasi */
2097 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2098 offsetof(CPUSPARCState
, asi
));
2099 tcg_gen_ext_i32_tl(cpu_dst
, cpu_tmp32
);
2100 gen_movl_TN_reg(rd
, cpu_dst
);
2102 case 0x4: /* V9 rdtick */
2106 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
2107 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2108 offsetof(CPUState
, tick
));
2109 tcg_gen_helper_1_1(helper_tick_get_count
, cpu_dst
,
2111 tcg_temp_free(r_tickptr
);
2112 gen_movl_TN_reg(rd
, cpu_dst
);
2115 case 0x5: /* V9 rdpc */
2119 r_const
= tcg_const_tl(dc
->pc
);
2120 gen_movl_TN_reg(rd
, r_const
);
2121 tcg_temp_free(r_const
);
2124 case 0x6: /* V9 rdfprs */
2125 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2126 offsetof(CPUSPARCState
, fprs
));
2127 tcg_gen_ext_i32_tl(cpu_dst
, cpu_tmp32
);
2128 gen_movl_TN_reg(rd
, cpu_dst
);
2130 case 0xf: /* V9 membar */
2131 break; /* no effect */
2132 case 0x13: /* Graphics Status */
2133 if (gen_trap_ifnofpu(dc
, cpu_cond
))
2135 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2136 offsetof(CPUSPARCState
, gsr
));
2137 gen_movl_TN_reg(rd
, cpu_tmp0
);
2139 case 0x17: /* Tick compare */
2140 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2141 offsetof(CPUSPARCState
, tick_cmpr
));
2142 gen_movl_TN_reg(rd
, cpu_tmp0
);
2144 case 0x18: /* System tick */
2148 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
2149 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2150 offsetof(CPUState
, stick
));
2151 tcg_gen_helper_1_1(helper_tick_get_count
, cpu_dst
,
2153 tcg_temp_free(r_tickptr
);
2154 gen_movl_TN_reg(rd
, cpu_dst
);
2157 case 0x19: /* System tick compare */
2158 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2159 offsetof(CPUSPARCState
, stick_cmpr
));
2160 gen_movl_TN_reg(rd
, cpu_tmp0
);
2162 case 0x10: /* Performance Control */
2163 case 0x11: /* Performance Instrumentation Counter */
2164 case 0x12: /* Dispatch Control */
2165 case 0x14: /* Softint set, WO */
2166 case 0x15: /* Softint clear, WO */
2167 case 0x16: /* Softint write */
2172 #if !defined(CONFIG_USER_ONLY)
2173 } else if (xop
== 0x29) { /* rdpsr / UA2005 rdhpr */
2174 #ifndef TARGET_SPARC64
2175 if (!supervisor(dc
))
2177 tcg_gen_helper_1_0(helper_rdpsr
, cpu_dst
);
2179 CHECK_IU_FEATURE(dc
, HYPV
);
2180 if (!hypervisor(dc
))
2182 rs1
= GET_FIELD(insn
, 13, 17);
2185 // gen_op_rdhpstate();
2188 // gen_op_rdhtstate();
2191 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2192 offsetof(CPUSPARCState
, hintp
));
2193 tcg_gen_ext_i32_tl(cpu_dst
, cpu_tmp32
);
2196 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2197 offsetof(CPUSPARCState
, htba
));
2198 tcg_gen_ext_i32_tl(cpu_dst
, cpu_tmp32
);
2201 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2202 offsetof(CPUSPARCState
, hver
));
2203 tcg_gen_ext_i32_tl(cpu_dst
, cpu_tmp32
);
2205 case 31: // hstick_cmpr
2206 tcg_gen_ld_tl(cpu_dst
, cpu_env
,
2207 offsetof(CPUSPARCState
, hstick_cmpr
));
2213 gen_movl_TN_reg(rd
, cpu_dst
);
2215 } else if (xop
== 0x2a) { /* rdwim / V9 rdpr */
2216 if (!supervisor(dc
))
2218 #ifdef TARGET_SPARC64
2219 rs1
= GET_FIELD(insn
, 13, 17);
2225 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2226 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2227 offsetof(CPUState
, tsptr
));
2228 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2229 offsetof(trap_state
, tpc
));
2230 tcg_temp_free(r_tsptr
);
2237 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2238 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2239 offsetof(CPUState
, tsptr
));
2240 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2241 offsetof(trap_state
, tnpc
));
2242 tcg_temp_free(r_tsptr
);
2249 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2250 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2251 offsetof(CPUState
, tsptr
));
2252 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2253 offsetof(trap_state
, tstate
));
2254 tcg_temp_free(r_tsptr
);
2261 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2262 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2263 offsetof(CPUState
, tsptr
));
2264 tcg_gen_ld_i32(cpu_tmp0
, r_tsptr
,
2265 offsetof(trap_state
, tt
));
2266 tcg_temp_free(r_tsptr
);
2273 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
2274 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2275 offsetof(CPUState
, tick
));
2276 tcg_gen_helper_1_1(helper_tick_get_count
, cpu_tmp0
,
2278 gen_movl_TN_reg(rd
, cpu_tmp0
);
2279 tcg_temp_free(r_tickptr
);
2283 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2284 offsetof(CPUSPARCState
, tbr
));
2287 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2288 offsetof(CPUSPARCState
, pstate
));
2289 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2292 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2293 offsetof(CPUSPARCState
, tl
));
2294 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2297 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2298 offsetof(CPUSPARCState
, psrpil
));
2299 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2302 tcg_gen_helper_1_0(helper_rdcwp
, cpu_tmp0
);
2305 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2306 offsetof(CPUSPARCState
, cansave
));
2307 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2309 case 11: // canrestore
2310 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2311 offsetof(CPUSPARCState
, canrestore
));
2312 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2314 case 12: // cleanwin
2315 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2316 offsetof(CPUSPARCState
, cleanwin
));
2317 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2319 case 13: // otherwin
2320 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2321 offsetof(CPUSPARCState
, otherwin
));
2322 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2325 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2326 offsetof(CPUSPARCState
, wstate
));
2327 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2329 case 16: // UA2005 gl
2330 CHECK_IU_FEATURE(dc
, GL
);
2331 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2332 offsetof(CPUSPARCState
, gl
));
2333 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2335 case 26: // UA2005 strand status
2336 CHECK_IU_FEATURE(dc
, HYPV
);
2337 if (!hypervisor(dc
))
2339 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2340 offsetof(CPUSPARCState
, ssr
));
2341 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2344 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2345 offsetof(CPUSPARCState
, version
));
2352 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2353 offsetof(CPUSPARCState
, wim
));
2354 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2356 gen_movl_TN_reg(rd
, cpu_tmp0
);
2358 } else if (xop
== 0x2b) { /* rdtbr / V9 flushw */
2359 #ifdef TARGET_SPARC64
2360 save_state(dc
, cpu_cond
);
2361 tcg_gen_helper_0_0(helper_flushw
);
2363 if (!supervisor(dc
))
2365 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, tbr
));
2366 gen_movl_TN_reg(rd
, cpu_tmp0
);
2370 } else if (xop
== 0x34) { /* FPU Operations */
2371 if (gen_trap_ifnofpu(dc
, cpu_cond
))
2373 gen_op_clear_ieee_excp_and_FTT();
2374 rs1
= GET_FIELD(insn
, 13, 17);
2375 rs2
= GET_FIELD(insn
, 27, 31);
2376 xop
= GET_FIELD(insn
, 18, 26);
2378 case 0x1: /* fmovs */
2379 gen_op_load_fpr_FT0(rs2
);
2380 gen_op_store_FT0_fpr(rd
);
2382 case 0x5: /* fnegs */
2383 gen_op_load_fpr_FT1(rs2
);
2384 tcg_gen_helper_0_0(helper_fnegs
);
2385 gen_op_store_FT0_fpr(rd
);
2387 case 0x9: /* fabss */
2388 gen_op_load_fpr_FT1(rs2
);
2389 tcg_gen_helper_0_0(helper_fabss
);
2390 gen_op_store_FT0_fpr(rd
);
2392 case 0x29: /* fsqrts */
2393 CHECK_FPU_FEATURE(dc
, FSQRT
);
2394 gen_op_load_fpr_FT1(rs2
);
2395 gen_clear_float_exceptions();
2396 tcg_gen_helper_0_0(helper_fsqrts
);
2397 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2398 gen_op_store_FT0_fpr(rd
);
2400 case 0x2a: /* fsqrtd */
2401 CHECK_FPU_FEATURE(dc
, FSQRT
);
2402 gen_op_load_fpr_DT1(DFPREG(rs2
));
2403 gen_clear_float_exceptions();
2404 tcg_gen_helper_0_0(helper_fsqrtd
);
2405 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2406 gen_op_store_DT0_fpr(DFPREG(rd
));
2408 case 0x2b: /* fsqrtq */
2409 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2410 gen_op_load_fpr_QT1(QFPREG(rs2
));
2411 gen_clear_float_exceptions();
2412 tcg_gen_helper_0_0(helper_fsqrtq
);
2413 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2414 gen_op_store_QT0_fpr(QFPREG(rd
));
2417 gen_op_load_fpr_FT0(rs1
);
2418 gen_op_load_fpr_FT1(rs2
);
2419 gen_clear_float_exceptions();
2420 tcg_gen_helper_0_0(helper_fadds
);
2421 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2422 gen_op_store_FT0_fpr(rd
);
2425 gen_op_load_fpr_DT0(DFPREG(rs1
));
2426 gen_op_load_fpr_DT1(DFPREG(rs2
));
2427 gen_clear_float_exceptions();
2428 tcg_gen_helper_0_0(helper_faddd
);
2429 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2430 gen_op_store_DT0_fpr(DFPREG(rd
));
2432 case 0x43: /* faddq */
2433 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2434 gen_op_load_fpr_QT0(QFPREG(rs1
));
2435 gen_op_load_fpr_QT1(QFPREG(rs2
));
2436 gen_clear_float_exceptions();
2437 tcg_gen_helper_0_0(helper_faddq
);
2438 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2439 gen_op_store_QT0_fpr(QFPREG(rd
));
2442 gen_op_load_fpr_FT0(rs1
);
2443 gen_op_load_fpr_FT1(rs2
);
2444 gen_clear_float_exceptions();
2445 tcg_gen_helper_0_0(helper_fsubs
);
2446 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2447 gen_op_store_FT0_fpr(rd
);
2450 gen_op_load_fpr_DT0(DFPREG(rs1
));
2451 gen_op_load_fpr_DT1(DFPREG(rs2
));
2452 gen_clear_float_exceptions();
2453 tcg_gen_helper_0_0(helper_fsubd
);
2454 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2455 gen_op_store_DT0_fpr(DFPREG(rd
));
2457 case 0x47: /* fsubq */
2458 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2459 gen_op_load_fpr_QT0(QFPREG(rs1
));
2460 gen_op_load_fpr_QT1(QFPREG(rs2
));
2461 gen_clear_float_exceptions();
2462 tcg_gen_helper_0_0(helper_fsubq
);
2463 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2464 gen_op_store_QT0_fpr(QFPREG(rd
));
2466 case 0x49: /* fmuls */
2467 CHECK_FPU_FEATURE(dc
, FMUL
);
2468 gen_op_load_fpr_FT0(rs1
);
2469 gen_op_load_fpr_FT1(rs2
);
2470 gen_clear_float_exceptions();
2471 tcg_gen_helper_0_0(helper_fmuls
);
2472 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2473 gen_op_store_FT0_fpr(rd
);
2475 case 0x4a: /* fmuld */
2476 CHECK_FPU_FEATURE(dc
, FMUL
);
2477 gen_op_load_fpr_DT0(DFPREG(rs1
));
2478 gen_op_load_fpr_DT1(DFPREG(rs2
));
2479 gen_clear_float_exceptions();
2480 tcg_gen_helper_0_0(helper_fmuld
);
2481 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2482 gen_op_store_DT0_fpr(DFPREG(rd
));
2484 case 0x4b: /* fmulq */
2485 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2486 CHECK_FPU_FEATURE(dc
, FMUL
);
2487 gen_op_load_fpr_QT0(QFPREG(rs1
));
2488 gen_op_load_fpr_QT1(QFPREG(rs2
));
2489 gen_clear_float_exceptions();
2490 tcg_gen_helper_0_0(helper_fmulq
);
2491 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2492 gen_op_store_QT0_fpr(QFPREG(rd
));
2495 gen_op_load_fpr_FT0(rs1
);
2496 gen_op_load_fpr_FT1(rs2
);
2497 gen_clear_float_exceptions();
2498 tcg_gen_helper_0_0(helper_fdivs
);
2499 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2500 gen_op_store_FT0_fpr(rd
);
2503 gen_op_load_fpr_DT0(DFPREG(rs1
));
2504 gen_op_load_fpr_DT1(DFPREG(rs2
));
2505 gen_clear_float_exceptions();
2506 tcg_gen_helper_0_0(helper_fdivd
);
2507 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2508 gen_op_store_DT0_fpr(DFPREG(rd
));
2510 case 0x4f: /* fdivq */
2511 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2512 gen_op_load_fpr_QT0(QFPREG(rs1
));
2513 gen_op_load_fpr_QT1(QFPREG(rs2
));
2514 gen_clear_float_exceptions();
2515 tcg_gen_helper_0_0(helper_fdivq
);
2516 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2517 gen_op_store_QT0_fpr(QFPREG(rd
));
2520 CHECK_FPU_FEATURE(dc
, FSMULD
);
2521 gen_op_load_fpr_FT0(rs1
);
2522 gen_op_load_fpr_FT1(rs2
);
2523 gen_clear_float_exceptions();
2524 tcg_gen_helper_0_0(helper_fsmuld
);
2525 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2526 gen_op_store_DT0_fpr(DFPREG(rd
));
2528 case 0x6e: /* fdmulq */
2529 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2530 gen_op_load_fpr_DT0(DFPREG(rs1
));
2531 gen_op_load_fpr_DT1(DFPREG(rs2
));
2532 gen_clear_float_exceptions();
2533 tcg_gen_helper_0_0(helper_fdmulq
);
2534 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2535 gen_op_store_QT0_fpr(QFPREG(rd
));
2538 gen_op_load_fpr_FT1(rs2
);
2539 gen_clear_float_exceptions();
2540 tcg_gen_helper_0_0(helper_fitos
);
2541 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2542 gen_op_store_FT0_fpr(rd
);
2545 gen_op_load_fpr_DT1(DFPREG(rs2
));
2546 gen_clear_float_exceptions();
2547 tcg_gen_helper_0_0(helper_fdtos
);
2548 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2549 gen_op_store_FT0_fpr(rd
);
2551 case 0xc7: /* fqtos */
2552 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2553 gen_op_load_fpr_QT1(QFPREG(rs2
));
2554 gen_clear_float_exceptions();
2555 tcg_gen_helper_0_0(helper_fqtos
);
2556 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2557 gen_op_store_FT0_fpr(rd
);
2560 gen_op_load_fpr_FT1(rs2
);
2561 tcg_gen_helper_0_0(helper_fitod
);
2562 gen_op_store_DT0_fpr(DFPREG(rd
));
2565 gen_op_load_fpr_FT1(rs2
);
2566 tcg_gen_helper_0_0(helper_fstod
);
2567 gen_op_store_DT0_fpr(DFPREG(rd
));
2569 case 0xcb: /* fqtod */
2570 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2571 gen_op_load_fpr_QT1(QFPREG(rs2
));
2572 gen_clear_float_exceptions();
2573 tcg_gen_helper_0_0(helper_fqtod
);
2574 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2575 gen_op_store_DT0_fpr(DFPREG(rd
));
2577 case 0xcc: /* fitoq */
2578 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2579 gen_op_load_fpr_FT1(rs2
);
2580 tcg_gen_helper_0_0(helper_fitoq
);
2581 gen_op_store_QT0_fpr(QFPREG(rd
));
2583 case 0xcd: /* fstoq */
2584 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2585 gen_op_load_fpr_FT1(rs2
);
2586 tcg_gen_helper_0_0(helper_fstoq
);
2587 gen_op_store_QT0_fpr(QFPREG(rd
));
2589 case 0xce: /* fdtoq */
2590 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2591 gen_op_load_fpr_DT1(DFPREG(rs2
));
2592 tcg_gen_helper_0_0(helper_fdtoq
);
2593 gen_op_store_QT0_fpr(QFPREG(rd
));
2596 gen_op_load_fpr_FT1(rs2
);
2597 gen_clear_float_exceptions();
2598 tcg_gen_helper_0_0(helper_fstoi
);
2599 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2600 gen_op_store_FT0_fpr(rd
);
2603 gen_op_load_fpr_DT1(DFPREG(rs2
));
2604 gen_clear_float_exceptions();
2605 tcg_gen_helper_0_0(helper_fdtoi
);
2606 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2607 gen_op_store_FT0_fpr(rd
);
2609 case 0xd3: /* fqtoi */
2610 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2611 gen_op_load_fpr_QT1(QFPREG(rs2
));
2612 gen_clear_float_exceptions();
2613 tcg_gen_helper_0_0(helper_fqtoi
);
2614 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2615 gen_op_store_FT0_fpr(rd
);
2617 #ifdef TARGET_SPARC64
2618 case 0x2: /* V9 fmovd */
2619 gen_op_load_fpr_DT0(DFPREG(rs2
));
2620 gen_op_store_DT0_fpr(DFPREG(rd
));
2622 case 0x3: /* V9 fmovq */
2623 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2624 gen_op_load_fpr_QT0(QFPREG(rs2
));
2625 gen_op_store_QT0_fpr(QFPREG(rd
));
2627 case 0x6: /* V9 fnegd */
2628 gen_op_load_fpr_DT1(DFPREG(rs2
));
2629 tcg_gen_helper_0_0(helper_fnegd
);
2630 gen_op_store_DT0_fpr(DFPREG(rd
));
2632 case 0x7: /* V9 fnegq */
2633 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2634 gen_op_load_fpr_QT1(QFPREG(rs2
));
2635 tcg_gen_helper_0_0(helper_fnegq
);
2636 gen_op_store_QT0_fpr(QFPREG(rd
));
2638 case 0xa: /* V9 fabsd */
2639 gen_op_load_fpr_DT1(DFPREG(rs2
));
2640 tcg_gen_helper_0_0(helper_fabsd
);
2641 gen_op_store_DT0_fpr(DFPREG(rd
));
2643 case 0xb: /* V9 fabsq */
2644 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2645 gen_op_load_fpr_QT1(QFPREG(rs2
));
2646 tcg_gen_helper_0_0(helper_fabsq
);
2647 gen_op_store_QT0_fpr(QFPREG(rd
));
2649 case 0x81: /* V9 fstox */
2650 gen_op_load_fpr_FT1(rs2
);
2651 gen_clear_float_exceptions();
2652 tcg_gen_helper_0_0(helper_fstox
);
2653 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2654 gen_op_store_DT0_fpr(DFPREG(rd
));
2656 case 0x82: /* V9 fdtox */
2657 gen_op_load_fpr_DT1(DFPREG(rs2
));
2658 gen_clear_float_exceptions();
2659 tcg_gen_helper_0_0(helper_fdtox
);
2660 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2661 gen_op_store_DT0_fpr(DFPREG(rd
));
2663 case 0x83: /* V9 fqtox */
2664 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2665 gen_op_load_fpr_QT1(QFPREG(rs2
));
2666 gen_clear_float_exceptions();
2667 tcg_gen_helper_0_0(helper_fqtox
);
2668 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2669 gen_op_store_DT0_fpr(DFPREG(rd
));
2671 case 0x84: /* V9 fxtos */
2672 gen_op_load_fpr_DT1(DFPREG(rs2
));
2673 gen_clear_float_exceptions();
2674 tcg_gen_helper_0_0(helper_fxtos
);
2675 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2676 gen_op_store_FT0_fpr(rd
);
2678 case 0x88: /* V9 fxtod */
2679 gen_op_load_fpr_DT1(DFPREG(rs2
));
2680 gen_clear_float_exceptions();
2681 tcg_gen_helper_0_0(helper_fxtod
);
2682 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2683 gen_op_store_DT0_fpr(DFPREG(rd
));
2685 case 0x8c: /* V9 fxtoq */
2686 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2687 gen_op_load_fpr_DT1(DFPREG(rs2
));
2688 gen_clear_float_exceptions();
2689 tcg_gen_helper_0_0(helper_fxtoq
);
2690 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2691 gen_op_store_QT0_fpr(QFPREG(rd
));
2697 } else if (xop
== 0x35) { /* FPU Operations */
2698 #ifdef TARGET_SPARC64
2701 if (gen_trap_ifnofpu(dc
, cpu_cond
))
2703 gen_op_clear_ieee_excp_and_FTT();
2704 rs1
= GET_FIELD(insn
, 13, 17);
2705 rs2
= GET_FIELD(insn
, 27, 31);
2706 xop
= GET_FIELD(insn
, 18, 26);
2707 #ifdef TARGET_SPARC64
2708 if ((xop
& 0x11f) == 0x005) { // V9 fmovsr
2711 l1
= gen_new_label();
2712 cond
= GET_FIELD_SP(insn
, 14, 17);
2713 cpu_src1
= get_src1(insn
, cpu_src1
);
2714 tcg_gen_brcondi_tl(gen_tcg_cond_reg
[cond
], cpu_src1
,
2716 gen_op_load_fpr_FT0(rs2
);
2717 gen_op_store_FT0_fpr(rd
);
2720 } else if ((xop
& 0x11f) == 0x006) { // V9 fmovdr
2723 l1
= gen_new_label();
2724 cond
= GET_FIELD_SP(insn
, 14, 17);
2725 cpu_src1
= get_src1(insn
, cpu_src1
);
2726 tcg_gen_brcondi_tl(gen_tcg_cond_reg
[cond
], cpu_src1
,
2728 gen_op_load_fpr_DT0(DFPREG(rs2
));
2729 gen_op_store_DT0_fpr(DFPREG(rd
));
2732 } else if ((xop
& 0x11f) == 0x007) { // V9 fmovqr
2735 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2736 l1
= gen_new_label();
2737 cond
= GET_FIELD_SP(insn
, 14, 17);
2738 cpu_src1
= get_src1(insn
, cpu_src1
);
2739 tcg_gen_brcondi_tl(gen_tcg_cond_reg
[cond
], cpu_src1
,
2741 gen_op_load_fpr_QT0(QFPREG(rs2
));
2742 gen_op_store_QT0_fpr(QFPREG(rd
));
2748 #ifdef TARGET_SPARC64
2749 #define FMOVCC(size_FDQ, fcc) \
2754 l1 = gen_new_label(); \
2755 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2756 cond = GET_FIELD_SP(insn, 14, 17); \
2757 gen_fcond(r_cond, fcc, cond); \
2758 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2760 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2761 (glue(size_FDQ, FPREG(rs2))); \
2762 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2763 (glue(size_FDQ, FPREG(rd))); \
2764 gen_set_label(l1); \
2765 tcg_temp_free(r_cond); \
2767 case 0x001: /* V9 fmovscc %fcc0 */
2770 case 0x002: /* V9 fmovdcc %fcc0 */
2773 case 0x003: /* V9 fmovqcc %fcc0 */
2774 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2777 case 0x041: /* V9 fmovscc %fcc1 */
2780 case 0x042: /* V9 fmovdcc %fcc1 */
2783 case 0x043: /* V9 fmovqcc %fcc1 */
2784 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2787 case 0x081: /* V9 fmovscc %fcc2 */
2790 case 0x082: /* V9 fmovdcc %fcc2 */
2793 case 0x083: /* V9 fmovqcc %fcc2 */
2794 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2797 case 0x0c1: /* V9 fmovscc %fcc3 */
2800 case 0x0c2: /* V9 fmovdcc %fcc3 */
2803 case 0x0c3: /* V9 fmovqcc %fcc3 */
2804 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2808 #define FMOVCC(size_FDQ, icc) \
2813 l1 = gen_new_label(); \
2814 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2815 cond = GET_FIELD_SP(insn, 14, 17); \
2816 gen_cond(r_cond, icc, cond); \
2817 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2819 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2820 (glue(size_FDQ, FPREG(rs2))); \
2821 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2822 (glue(size_FDQ, FPREG(rd))); \
2823 gen_set_label(l1); \
2824 tcg_temp_free(r_cond); \
2827 case 0x101: /* V9 fmovscc %icc */
2830 case 0x102: /* V9 fmovdcc %icc */
2832 case 0x103: /* V9 fmovqcc %icc */
2833 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2836 case 0x181: /* V9 fmovscc %xcc */
2839 case 0x182: /* V9 fmovdcc %xcc */
2842 case 0x183: /* V9 fmovqcc %xcc */
2843 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2848 case 0x51: /* fcmps, V9 %fcc */
2849 gen_op_load_fpr_FT0(rs1
);
2850 gen_op_load_fpr_FT1(rs2
);
2851 gen_op_fcmps(rd
& 3);
2853 case 0x52: /* fcmpd, V9 %fcc */
2854 gen_op_load_fpr_DT0(DFPREG(rs1
));
2855 gen_op_load_fpr_DT1(DFPREG(rs2
));
2856 gen_op_fcmpd(rd
& 3);
2858 case 0x53: /* fcmpq, V9 %fcc */
2859 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2860 gen_op_load_fpr_QT0(QFPREG(rs1
));
2861 gen_op_load_fpr_QT1(QFPREG(rs2
));
2862 gen_op_fcmpq(rd
& 3);
2864 case 0x55: /* fcmpes, V9 %fcc */
2865 gen_op_load_fpr_FT0(rs1
);
2866 gen_op_load_fpr_FT1(rs2
);
2867 gen_op_fcmpes(rd
& 3);
2869 case 0x56: /* fcmped, V9 %fcc */
2870 gen_op_load_fpr_DT0(DFPREG(rs1
));
2871 gen_op_load_fpr_DT1(DFPREG(rs2
));
2872 gen_op_fcmped(rd
& 3);
2874 case 0x57: /* fcmpeq, V9 %fcc */
2875 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2876 gen_op_load_fpr_QT0(QFPREG(rs1
));
2877 gen_op_load_fpr_QT1(QFPREG(rs2
));
2878 gen_op_fcmpeq(rd
& 3);
2883 } else if (xop
== 0x2) {
2886 rs1
= GET_FIELD(insn
, 13, 17);
2888 // or %g0, x, y -> mov T0, x; mov y, T0
2889 if (IS_IMM
) { /* immediate */
2892 rs2
= GET_FIELDs(insn
, 19, 31);
2893 r_const
= tcg_const_tl((int)rs2
);
2894 gen_movl_TN_reg(rd
, r_const
);
2895 tcg_temp_free(r_const
);
2896 } else { /* register */
2897 rs2
= GET_FIELD(insn
, 27, 31);
2898 gen_movl_reg_TN(rs2
, cpu_dst
);
2899 gen_movl_TN_reg(rd
, cpu_dst
);
2902 cpu_src1
= get_src1(insn
, cpu_src1
);
2903 if (IS_IMM
) { /* immediate */
2904 rs2
= GET_FIELDs(insn
, 19, 31);
2905 tcg_gen_ori_tl(cpu_dst
, cpu_src1
, (int)rs2
);
2906 gen_movl_TN_reg(rd
, cpu_dst
);
2907 } else { /* register */
2908 // or x, %g0, y -> mov T1, x; mov y, T1
2909 rs2
= GET_FIELD(insn
, 27, 31);
2911 gen_movl_reg_TN(rs2
, cpu_src2
);
2912 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_src2
);
2913 gen_movl_TN_reg(rd
, cpu_dst
);
2915 gen_movl_TN_reg(rd
, cpu_src1
);
2918 #ifdef TARGET_SPARC64
2919 } else if (xop
== 0x25) { /* sll, V9 sllx */
2920 cpu_src1
= get_src1(insn
, cpu_src1
);
2921 if (IS_IMM
) { /* immediate */
2922 rs2
= GET_FIELDs(insn
, 20, 31);
2923 if (insn
& (1 << 12)) {
2924 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, rs2
& 0x3f);
2926 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, rs2
& 0x1f);
2928 } else { /* register */
2929 rs2
= GET_FIELD(insn
, 27, 31);
2930 gen_movl_reg_TN(rs2
, cpu_src2
);
2931 if (insn
& (1 << 12)) {
2932 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
2934 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
2936 tcg_gen_shl_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
2938 gen_movl_TN_reg(rd
, cpu_dst
);
2939 } else if (xop
== 0x26) { /* srl, V9 srlx */
2940 cpu_src1
= get_src1(insn
, cpu_src1
);
2941 if (IS_IMM
) { /* immediate */
2942 rs2
= GET_FIELDs(insn
, 20, 31);
2943 if (insn
& (1 << 12)) {
2944 tcg_gen_shri_i64(cpu_dst
, cpu_src1
, rs2
& 0x3f);
2946 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
2947 tcg_gen_shri_i64(cpu_dst
, cpu_dst
, rs2
& 0x1f);
2949 } else { /* register */
2950 rs2
= GET_FIELD(insn
, 27, 31);
2951 gen_movl_reg_TN(rs2
, cpu_src2
);
2952 if (insn
& (1 << 12)) {
2953 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
2954 tcg_gen_shr_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
2956 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
2957 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
2958 tcg_gen_shr_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
2961 gen_movl_TN_reg(rd
, cpu_dst
);
2962 } else if (xop
== 0x27) { /* sra, V9 srax */
2963 cpu_src1
= get_src1(insn
, cpu_src1
);
2964 if (IS_IMM
) { /* immediate */
2965 rs2
= GET_FIELDs(insn
, 20, 31);
2966 if (insn
& (1 << 12)) {
2967 tcg_gen_sari_i64(cpu_dst
, cpu_src1
, rs2
& 0x3f);
2969 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
2970 tcg_gen_ext_i32_i64(cpu_dst
, cpu_dst
);
2971 tcg_gen_sari_i64(cpu_dst
, cpu_dst
, rs2
& 0x1f);
2973 } else { /* register */
2974 rs2
= GET_FIELD(insn
, 27, 31);
2975 gen_movl_reg_TN(rs2
, cpu_src2
);
2976 if (insn
& (1 << 12)) {
2977 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
2978 tcg_gen_sar_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
2980 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
2981 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
2982 tcg_gen_ext_i32_i64(cpu_dst
, cpu_dst
);
2983 tcg_gen_sar_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
2986 gen_movl_TN_reg(rd
, cpu_dst
);
2988 } else if (xop
< 0x36) {
2989 cpu_src1
= get_src1(insn
, cpu_src1
);
2990 cpu_src2
= get_src2(insn
, cpu_src2
);
2992 switch (xop
& ~0x10) {
2995 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
2997 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3000 tcg_gen_and_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3002 gen_op_logic_cc(cpu_dst
);
3005 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3007 gen_op_logic_cc(cpu_dst
);
3010 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3012 gen_op_logic_cc(cpu_dst
);
3016 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3018 tcg_gen_sub_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3021 tcg_gen_xori_tl(cpu_tmp0
, cpu_src2
, -1);
3022 tcg_gen_and_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3024 gen_op_logic_cc(cpu_dst
);
3027 tcg_gen_xori_tl(cpu_tmp0
, cpu_src2
, -1);
3028 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3030 gen_op_logic_cc(cpu_dst
);
3033 tcg_gen_xori_tl(cpu_tmp0
, cpu_src2
, -1);
3034 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3036 gen_op_logic_cc(cpu_dst
);
3040 gen_op_addx_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3042 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
3043 tcg_gen_add_tl(cpu_tmp0
, cpu_src2
, cpu_tmp0
);
3044 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3047 #ifdef TARGET_SPARC64
3048 case 0x9: /* V9 mulx */
3049 tcg_gen_mul_i64(cpu_dst
, cpu_src1
, cpu_src2
);
3053 CHECK_IU_FEATURE(dc
, MUL
);
3054 gen_op_umul(cpu_dst
, cpu_src1
, cpu_src2
);
3056 gen_op_logic_cc(cpu_dst
);
3059 CHECK_IU_FEATURE(dc
, MUL
);
3060 gen_op_smul(cpu_dst
, cpu_src1
, cpu_src2
);
3062 gen_op_logic_cc(cpu_dst
);
3066 gen_op_subx_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3068 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
3069 tcg_gen_add_tl(cpu_tmp0
, cpu_src2
, cpu_tmp0
);
3070 tcg_gen_sub_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3073 #ifdef TARGET_SPARC64
3074 case 0xd: /* V9 udivx */
3075 tcg_gen_mov_tl(cpu_cc_src
, cpu_src1
);
3076 tcg_gen_mov_tl(cpu_cc_src2
, cpu_src2
);
3077 gen_trap_ifdivzero_tl(cpu_cc_src2
);
3078 tcg_gen_divu_i64(cpu_dst
, cpu_cc_src
, cpu_cc_src2
);
3082 CHECK_IU_FEATURE(dc
, DIV
);
3083 tcg_gen_helper_1_2(helper_udiv
, cpu_dst
, cpu_src1
,
3086 gen_op_div_cc(cpu_dst
);
3089 CHECK_IU_FEATURE(dc
, DIV
);
3090 tcg_gen_helper_1_2(helper_sdiv
, cpu_dst
, cpu_src1
,
3093 gen_op_div_cc(cpu_dst
);
3098 gen_movl_TN_reg(rd
, cpu_dst
);
3101 case 0x20: /* taddcc */
3102 gen_op_tadd_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3103 gen_movl_TN_reg(rd
, cpu_dst
);
3105 case 0x21: /* tsubcc */
3106 gen_op_tsub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3107 gen_movl_TN_reg(rd
, cpu_dst
);
3109 case 0x22: /* taddcctv */
3110 save_state(dc
, cpu_cond
);
3111 gen_op_tadd_ccTV(cpu_dst
, cpu_src1
, cpu_src2
);
3112 gen_movl_TN_reg(rd
, cpu_dst
);
3114 case 0x23: /* tsubcctv */
3115 save_state(dc
, cpu_cond
);
3116 gen_op_tsub_ccTV(cpu_dst
, cpu_src1
, cpu_src2
);
3117 gen_movl_TN_reg(rd
, cpu_dst
);
3119 case 0x24: /* mulscc */
3120 gen_op_mulscc(cpu_dst
, cpu_src1
, cpu_src2
);
3121 gen_movl_TN_reg(rd
, cpu_dst
);
3123 #ifndef TARGET_SPARC64
3124 case 0x25: /* sll */
3125 if (IS_IMM
) { /* immediate */
3126 rs2
= GET_FIELDs(insn
, 20, 31);
3127 tcg_gen_shli_tl(cpu_dst
, cpu_src1
, rs2
& 0x1f);
3128 } else { /* register */
3129 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3130 tcg_gen_shl_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3132 gen_movl_TN_reg(rd
, cpu_dst
);
3134 case 0x26: /* srl */
3135 if (IS_IMM
) { /* immediate */
3136 rs2
= GET_FIELDs(insn
, 20, 31);
3137 tcg_gen_shri_tl(cpu_dst
, cpu_src1
, rs2
& 0x1f);
3138 } else { /* register */
3139 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3140 tcg_gen_shr_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3142 gen_movl_TN_reg(rd
, cpu_dst
);
3144 case 0x27: /* sra */
3145 if (IS_IMM
) { /* immediate */
3146 rs2
= GET_FIELDs(insn
, 20, 31);
3147 tcg_gen_sari_tl(cpu_dst
, cpu_src1
, rs2
& 0x1f);
3148 } else { /* register */
3149 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3150 tcg_gen_sar_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3152 gen_movl_TN_reg(rd
, cpu_dst
);
3159 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3160 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3161 offsetof(CPUSPARCState
, y
));
3163 #ifndef TARGET_SPARC64
3164 case 0x01 ... 0x0f: /* undefined in the
3168 case 0x10 ... 0x1f: /* implementation-dependent
3174 case 0x2: /* V9 wrccr */
3175 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3176 tcg_gen_helper_0_1(helper_wrccr
, cpu_dst
);
3178 case 0x3: /* V9 wrasi */
3179 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3180 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_dst
);
3181 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3182 offsetof(CPUSPARCState
, asi
));
3184 case 0x6: /* V9 wrfprs */
3185 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3186 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_dst
);
3187 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3188 offsetof(CPUSPARCState
, fprs
));
3189 save_state(dc
, cpu_cond
);
3194 case 0xf: /* V9 sir, nop if user */
3195 #if !defined(CONFIG_USER_ONLY)
3200 case 0x13: /* Graphics Status */
3201 if (gen_trap_ifnofpu(dc
, cpu_cond
))
3203 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3204 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3205 offsetof(CPUSPARCState
, gsr
));
3207 case 0x17: /* Tick compare */
3208 #if !defined(CONFIG_USER_ONLY)
3209 if (!supervisor(dc
))
3215 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
,
3217 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3218 offsetof(CPUSPARCState
,
3220 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3221 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3222 offsetof(CPUState
, tick
));
3223 tcg_gen_helper_0_2(helper_tick_set_limit
,
3224 r_tickptr
, cpu_tmp0
);
3225 tcg_temp_free(r_tickptr
);
3228 case 0x18: /* System tick */
3229 #if !defined(CONFIG_USER_ONLY)
3230 if (!supervisor(dc
))
3236 tcg_gen_xor_tl(cpu_dst
, cpu_src1
,
3238 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3239 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3240 offsetof(CPUState
, stick
));
3241 tcg_gen_helper_0_2(helper_tick_set_count
,
3242 r_tickptr
, cpu_dst
);
3243 tcg_temp_free(r_tickptr
);
3246 case 0x19: /* System tick compare */
3247 #if !defined(CONFIG_USER_ONLY)
3248 if (!supervisor(dc
))
3254 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
,
3256 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3257 offsetof(CPUSPARCState
,
3259 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3260 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3261 offsetof(CPUState
, stick
));
3262 tcg_gen_helper_0_2(helper_tick_set_limit
,
3263 r_tickptr
, cpu_tmp0
);
3264 tcg_temp_free(r_tickptr
);
3268 case 0x10: /* Performance Control */
3269 case 0x11: /* Performance Instrumentation
3271 case 0x12: /* Dispatch Control */
3272 case 0x14: /* Softint set */
3273 case 0x15: /* Softint clear */
3274 case 0x16: /* Softint write */
3281 #if !defined(CONFIG_USER_ONLY)
3282 case 0x31: /* wrpsr, V9 saved, restored */
3284 if (!supervisor(dc
))
3286 #ifdef TARGET_SPARC64
3289 tcg_gen_helper_0_0(helper_saved
);
3292 tcg_gen_helper_0_0(helper_restored
);
3294 case 2: /* UA2005 allclean */
3295 case 3: /* UA2005 otherw */
3296 case 4: /* UA2005 normalw */
3297 case 5: /* UA2005 invalw */
3303 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3304 tcg_gen_helper_0_1(helper_wrpsr
, cpu_dst
);
3305 save_state(dc
, cpu_cond
);
3312 case 0x32: /* wrwim, V9 wrpr */
3314 if (!supervisor(dc
))
3316 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3317 #ifdef TARGET_SPARC64
3323 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3324 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3325 offsetof(CPUState
, tsptr
));
3326 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3327 offsetof(trap_state
, tpc
));
3328 tcg_temp_free(r_tsptr
);
3335 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3336 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3337 offsetof(CPUState
, tsptr
));
3338 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3339 offsetof(trap_state
, tnpc
));
3340 tcg_temp_free(r_tsptr
);
3347 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3348 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3349 offsetof(CPUState
, tsptr
));
3350 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3351 offsetof(trap_state
,
3353 tcg_temp_free(r_tsptr
);
3360 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3361 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3362 offsetof(CPUState
, tsptr
));
3363 tcg_gen_st_i32(cpu_tmp0
, r_tsptr
,
3364 offsetof(trap_state
, tt
));
3365 tcg_temp_free(r_tsptr
);
3372 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3373 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3374 offsetof(CPUState
, tick
));
3375 tcg_gen_helper_0_2(helper_tick_set_count
,
3376 r_tickptr
, cpu_tmp0
);
3377 tcg_temp_free(r_tickptr
);
3381 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3382 offsetof(CPUSPARCState
, tbr
));
3385 save_state(dc
, cpu_cond
);
3386 tcg_gen_helper_0_1(helper_wrpstate
, cpu_tmp0
);
3392 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3393 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3394 offsetof(CPUSPARCState
, tl
));
3397 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3398 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3399 offsetof(CPUSPARCState
,
3403 tcg_gen_helper_0_1(helper_wrcwp
, cpu_tmp0
);
3406 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3407 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3408 offsetof(CPUSPARCState
,
3411 case 11: // canrestore
3412 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3413 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3414 offsetof(CPUSPARCState
,
3417 case 12: // cleanwin
3418 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3419 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3420 offsetof(CPUSPARCState
,
3423 case 13: // otherwin
3424 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3425 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3426 offsetof(CPUSPARCState
,
3430 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3431 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3432 offsetof(CPUSPARCState
,
3435 case 16: // UA2005 gl
3436 CHECK_IU_FEATURE(dc
, GL
);
3437 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3438 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3439 offsetof(CPUSPARCState
, gl
));
3441 case 26: // UA2005 strand status
3442 CHECK_IU_FEATURE(dc
, HYPV
);
3443 if (!hypervisor(dc
))
3445 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3446 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3447 offsetof(CPUSPARCState
, ssr
));
3453 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3454 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3455 offsetof(CPUSPARCState
, wim
));
3459 case 0x33: /* wrtbr, UA2005 wrhpr */
3461 #ifndef TARGET_SPARC64
3462 if (!supervisor(dc
))
3464 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3465 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3466 offsetof(CPUSPARCState
, tbr
));
3468 CHECK_IU_FEATURE(dc
, HYPV
);
3469 if (!hypervisor(dc
))
3471 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3474 // XXX gen_op_wrhpstate();
3475 save_state(dc
, cpu_cond
);
3481 // XXX gen_op_wrhtstate();
3484 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3485 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3486 offsetof(CPUSPARCState
, hintp
));
3489 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3490 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3491 offsetof(CPUSPARCState
, htba
));
3493 case 31: // hstick_cmpr
3497 tcg_gen_st_tl(cpu_tmp0
, cpu_env
,
3498 offsetof(CPUSPARCState
,
3500 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3501 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3502 offsetof(CPUState
, hstick
));
3503 tcg_gen_helper_0_2(helper_tick_set_limit
,
3504 r_tickptr
, cpu_tmp0
);
3505 tcg_temp_free(r_tickptr
);
3508 case 6: // hver readonly
3516 #ifdef TARGET_SPARC64
3517 case 0x2c: /* V9 movcc */
3519 int cc
= GET_FIELD_SP(insn
, 11, 12);
3520 int cond
= GET_FIELD_SP(insn
, 14, 17);
3524 r_cond
= tcg_temp_new(TCG_TYPE_TL
);
3525 if (insn
& (1 << 18)) {
3527 gen_cond(r_cond
, 0, cond
);
3529 gen_cond(r_cond
, 1, cond
);
3533 gen_fcond(r_cond
, cc
, cond
);
3536 l1
= gen_new_label();
3538 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
3539 if (IS_IMM
) { /* immediate */
3542 rs2
= GET_FIELD_SPs(insn
, 0, 10);
3543 r_const
= tcg_const_tl((int)rs2
);
3544 gen_movl_TN_reg(rd
, r_const
);
3545 tcg_temp_free(r_const
);
3547 rs2
= GET_FIELD_SP(insn
, 0, 4);
3548 gen_movl_reg_TN(rs2
, cpu_tmp0
);
3549 gen_movl_TN_reg(rd
, cpu_tmp0
);
3552 tcg_temp_free(r_cond
);
3555 case 0x2d: /* V9 sdivx */
3556 gen_op_sdivx(cpu_dst
, cpu_src1
, cpu_src2
);
3557 gen_movl_TN_reg(rd
, cpu_dst
);
3559 case 0x2e: /* V9 popc */
3561 cpu_src2
= get_src2(insn
, cpu_src2
);
3562 tcg_gen_helper_1_1(helper_popc
, cpu_dst
,
3564 gen_movl_TN_reg(rd
, cpu_dst
);
3566 case 0x2f: /* V9 movr */
3568 int cond
= GET_FIELD_SP(insn
, 10, 12);
3571 cpu_src1
= get_src1(insn
, cpu_src1
);
3573 l1
= gen_new_label();
3575 tcg_gen_brcondi_tl(gen_tcg_cond_reg
[cond
],
3577 if (IS_IMM
) { /* immediate */
3580 rs2
= GET_FIELD_SPs(insn
, 0, 9);
3581 r_const
= tcg_const_tl((int)rs2
);
3582 gen_movl_TN_reg(rd
, r_const
);
3583 tcg_temp_free(r_const
);
3585 rs2
= GET_FIELD_SP(insn
, 0, 4);
3586 gen_movl_reg_TN(rs2
, cpu_tmp0
);
3587 gen_movl_TN_reg(rd
, cpu_tmp0
);
3597 } else if (xop
== 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3598 #ifdef TARGET_SPARC64
3599 int opf
= GET_FIELD_SP(insn
, 5, 13);
3600 rs1
= GET_FIELD(insn
, 13, 17);
3601 rs2
= GET_FIELD(insn
, 27, 31);
3602 if (gen_trap_ifnofpu(dc
, cpu_cond
))
3606 case 0x000: /* VIS I edge8cc */
3607 case 0x001: /* VIS II edge8n */
3608 case 0x002: /* VIS I edge8lcc */
3609 case 0x003: /* VIS II edge8ln */
3610 case 0x004: /* VIS I edge16cc */
3611 case 0x005: /* VIS II edge16n */
3612 case 0x006: /* VIS I edge16lcc */
3613 case 0x007: /* VIS II edge16ln */
3614 case 0x008: /* VIS I edge32cc */
3615 case 0x009: /* VIS II edge32n */
3616 case 0x00a: /* VIS I edge32lcc */
3617 case 0x00b: /* VIS II edge32ln */
3620 case 0x010: /* VIS I array8 */
3621 CHECK_FPU_FEATURE(dc
, VIS1
);
3622 cpu_src1
= get_src1(insn
, cpu_src1
);
3623 gen_movl_reg_TN(rs2
, cpu_src2
);
3624 tcg_gen_helper_1_2(helper_array8
, cpu_dst
, cpu_src1
,
3626 gen_movl_TN_reg(rd
, cpu_dst
);
3628 case 0x012: /* VIS I array16 */
3629 CHECK_FPU_FEATURE(dc
, VIS1
);
3630 cpu_src1
= get_src1(insn
, cpu_src1
);
3631 gen_movl_reg_TN(rs2
, cpu_src2
);
3632 tcg_gen_helper_1_2(helper_array8
, cpu_dst
, cpu_src1
,
3634 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 1);
3635 gen_movl_TN_reg(rd
, cpu_dst
);
3637 case 0x014: /* VIS I array32 */
3638 CHECK_FPU_FEATURE(dc
, VIS1
);
3639 cpu_src1
= get_src1(insn
, cpu_src1
);
3640 gen_movl_reg_TN(rs2
, cpu_src2
);
3641 tcg_gen_helper_1_2(helper_array8
, cpu_dst
, cpu_src1
,
3643 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 2);
3644 gen_movl_TN_reg(rd
, cpu_dst
);
3646 case 0x018: /* VIS I alignaddr */
3647 CHECK_FPU_FEATURE(dc
, VIS1
);
3648 cpu_src1
= get_src1(insn
, cpu_src1
);
3649 gen_movl_reg_TN(rs2
, cpu_src2
);
3650 tcg_gen_helper_1_2(helper_alignaddr
, cpu_dst
, cpu_src1
,
3652 gen_movl_TN_reg(rd
, cpu_dst
);
3654 case 0x019: /* VIS II bmask */
3655 case 0x01a: /* VIS I alignaddrl */
3658 case 0x020: /* VIS I fcmple16 */
3659 CHECK_FPU_FEATURE(dc
, VIS1
);
3660 gen_op_load_fpr_DT0(DFPREG(rs1
));
3661 gen_op_load_fpr_DT1(DFPREG(rs2
));
3662 tcg_gen_helper_0_0(helper_fcmple16
);
3663 gen_op_store_DT0_fpr(DFPREG(rd
));
3665 case 0x022: /* VIS I fcmpne16 */
3666 CHECK_FPU_FEATURE(dc
, VIS1
);
3667 gen_op_load_fpr_DT0(DFPREG(rs1
));
3668 gen_op_load_fpr_DT1(DFPREG(rs2
));
3669 tcg_gen_helper_0_0(helper_fcmpne16
);
3670 gen_op_store_DT0_fpr(DFPREG(rd
));
3672 case 0x024: /* VIS I fcmple32 */
3673 CHECK_FPU_FEATURE(dc
, VIS1
);
3674 gen_op_load_fpr_DT0(DFPREG(rs1
));
3675 gen_op_load_fpr_DT1(DFPREG(rs2
));
3676 tcg_gen_helper_0_0(helper_fcmple32
);
3677 gen_op_store_DT0_fpr(DFPREG(rd
));
3679 case 0x026: /* VIS I fcmpne32 */
3680 CHECK_FPU_FEATURE(dc
, VIS1
);
3681 gen_op_load_fpr_DT0(DFPREG(rs1
));
3682 gen_op_load_fpr_DT1(DFPREG(rs2
));
3683 tcg_gen_helper_0_0(helper_fcmpne32
);
3684 gen_op_store_DT0_fpr(DFPREG(rd
));
3686 case 0x028: /* VIS I fcmpgt16 */
3687 CHECK_FPU_FEATURE(dc
, VIS1
);
3688 gen_op_load_fpr_DT0(DFPREG(rs1
));
3689 gen_op_load_fpr_DT1(DFPREG(rs2
));
3690 tcg_gen_helper_0_0(helper_fcmpgt16
);
3691 gen_op_store_DT0_fpr(DFPREG(rd
));
3693 case 0x02a: /* VIS I fcmpeq16 */
3694 CHECK_FPU_FEATURE(dc
, VIS1
);
3695 gen_op_load_fpr_DT0(DFPREG(rs1
));
3696 gen_op_load_fpr_DT1(DFPREG(rs2
));
3697 tcg_gen_helper_0_0(helper_fcmpeq16
);
3698 gen_op_store_DT0_fpr(DFPREG(rd
));
3700 case 0x02c: /* VIS I fcmpgt32 */
3701 CHECK_FPU_FEATURE(dc
, VIS1
);
3702 gen_op_load_fpr_DT0(DFPREG(rs1
));
3703 gen_op_load_fpr_DT1(DFPREG(rs2
));
3704 tcg_gen_helper_0_0(helper_fcmpgt32
);
3705 gen_op_store_DT0_fpr(DFPREG(rd
));
3707 case 0x02e: /* VIS I fcmpeq32 */
3708 CHECK_FPU_FEATURE(dc
, VIS1
);
3709 gen_op_load_fpr_DT0(DFPREG(rs1
));
3710 gen_op_load_fpr_DT1(DFPREG(rs2
));
3711 tcg_gen_helper_0_0(helper_fcmpeq32
);
3712 gen_op_store_DT0_fpr(DFPREG(rd
));
3714 case 0x031: /* VIS I fmul8x16 */
3715 CHECK_FPU_FEATURE(dc
, VIS1
);
3716 gen_op_load_fpr_DT0(DFPREG(rs1
));
3717 gen_op_load_fpr_DT1(DFPREG(rs2
));
3718 tcg_gen_helper_0_0(helper_fmul8x16
);
3719 gen_op_store_DT0_fpr(DFPREG(rd
));
3721 case 0x033: /* VIS I fmul8x16au */
3722 CHECK_FPU_FEATURE(dc
, VIS1
);
3723 gen_op_load_fpr_DT0(DFPREG(rs1
));
3724 gen_op_load_fpr_DT1(DFPREG(rs2
));
3725 tcg_gen_helper_0_0(helper_fmul8x16au
);
3726 gen_op_store_DT0_fpr(DFPREG(rd
));
3728 case 0x035: /* VIS I fmul8x16al */
3729 CHECK_FPU_FEATURE(dc
, VIS1
);
3730 gen_op_load_fpr_DT0(DFPREG(rs1
));
3731 gen_op_load_fpr_DT1(DFPREG(rs2
));
3732 tcg_gen_helper_0_0(helper_fmul8x16al
);
3733 gen_op_store_DT0_fpr(DFPREG(rd
));
3735 case 0x036: /* VIS I fmul8sux16 */
3736 CHECK_FPU_FEATURE(dc
, VIS1
);
3737 gen_op_load_fpr_DT0(DFPREG(rs1
));
3738 gen_op_load_fpr_DT1(DFPREG(rs2
));
3739 tcg_gen_helper_0_0(helper_fmul8sux16
);
3740 gen_op_store_DT0_fpr(DFPREG(rd
));
3742 case 0x037: /* VIS I fmul8ulx16 */
3743 CHECK_FPU_FEATURE(dc
, VIS1
);
3744 gen_op_load_fpr_DT0(DFPREG(rs1
));
3745 gen_op_load_fpr_DT1(DFPREG(rs2
));
3746 tcg_gen_helper_0_0(helper_fmul8ulx16
);
3747 gen_op_store_DT0_fpr(DFPREG(rd
));
3749 case 0x038: /* VIS I fmuld8sux16 */
3750 CHECK_FPU_FEATURE(dc
, VIS1
);
3751 gen_op_load_fpr_DT0(DFPREG(rs1
));
3752 gen_op_load_fpr_DT1(DFPREG(rs2
));
3753 tcg_gen_helper_0_0(helper_fmuld8sux16
);
3754 gen_op_store_DT0_fpr(DFPREG(rd
));
3756 case 0x039: /* VIS I fmuld8ulx16 */
3757 CHECK_FPU_FEATURE(dc
, VIS1
);
3758 gen_op_load_fpr_DT0(DFPREG(rs1
));
3759 gen_op_load_fpr_DT1(DFPREG(rs2
));
3760 tcg_gen_helper_0_0(helper_fmuld8ulx16
);
3761 gen_op_store_DT0_fpr(DFPREG(rd
));
3763 case 0x03a: /* VIS I fpack32 */
3764 case 0x03b: /* VIS I fpack16 */
3765 case 0x03d: /* VIS I fpackfix */
3766 case 0x03e: /* VIS I pdist */
3769 case 0x048: /* VIS I faligndata */
3770 CHECK_FPU_FEATURE(dc
, VIS1
);
3771 gen_op_load_fpr_DT0(DFPREG(rs1
));
3772 gen_op_load_fpr_DT1(DFPREG(rs2
));
3773 tcg_gen_helper_0_0(helper_faligndata
);
3774 gen_op_store_DT0_fpr(DFPREG(rd
));
3776 case 0x04b: /* VIS I fpmerge */
3777 CHECK_FPU_FEATURE(dc
, VIS1
);
3778 gen_op_load_fpr_DT0(DFPREG(rs1
));
3779 gen_op_load_fpr_DT1(DFPREG(rs2
));
3780 tcg_gen_helper_0_0(helper_fpmerge
);
3781 gen_op_store_DT0_fpr(DFPREG(rd
));
3783 case 0x04c: /* VIS II bshuffle */
3786 case 0x04d: /* VIS I fexpand */
3787 CHECK_FPU_FEATURE(dc
, VIS1
);
3788 gen_op_load_fpr_DT0(DFPREG(rs1
));
3789 gen_op_load_fpr_DT1(DFPREG(rs2
));
3790 tcg_gen_helper_0_0(helper_fexpand
);
3791 gen_op_store_DT0_fpr(DFPREG(rd
));
3793 case 0x050: /* VIS I fpadd16 */
3794 CHECK_FPU_FEATURE(dc
, VIS1
);
3795 gen_op_load_fpr_DT0(DFPREG(rs1
));
3796 gen_op_load_fpr_DT1(DFPREG(rs2
));
3797 tcg_gen_helper_0_0(helper_fpadd16
);
3798 gen_op_store_DT0_fpr(DFPREG(rd
));
3800 case 0x051: /* VIS I fpadd16s */
3801 CHECK_FPU_FEATURE(dc
, VIS1
);
3802 gen_op_load_fpr_FT0(rs1
);
3803 gen_op_load_fpr_FT1(rs2
);
3804 tcg_gen_helper_0_0(helper_fpadd16s
);
3805 gen_op_store_FT0_fpr(rd
);
3807 case 0x052: /* VIS I fpadd32 */
3808 CHECK_FPU_FEATURE(dc
, VIS1
);
3809 gen_op_load_fpr_DT0(DFPREG(rs1
));
3810 gen_op_load_fpr_DT1(DFPREG(rs2
));
3811 tcg_gen_helper_0_0(helper_fpadd32
);
3812 gen_op_store_DT0_fpr(DFPREG(rd
));
3814 case 0x053: /* VIS I fpadd32s */
3815 CHECK_FPU_FEATURE(dc
, VIS1
);
3816 gen_op_load_fpr_FT0(rs1
);
3817 gen_op_load_fpr_FT1(rs2
);
3818 tcg_gen_helper_0_0(helper_fpadd32s
);
3819 gen_op_store_FT0_fpr(rd
);
3821 case 0x054: /* VIS I fpsub16 */
3822 CHECK_FPU_FEATURE(dc
, VIS1
);
3823 gen_op_load_fpr_DT0(DFPREG(rs1
));
3824 gen_op_load_fpr_DT1(DFPREG(rs2
));
3825 tcg_gen_helper_0_0(helper_fpsub16
);
3826 gen_op_store_DT0_fpr(DFPREG(rd
));
3828 case 0x055: /* VIS I fpsub16s */
3829 CHECK_FPU_FEATURE(dc
, VIS1
);
3830 gen_op_load_fpr_FT0(rs1
);
3831 gen_op_load_fpr_FT1(rs2
);
3832 tcg_gen_helper_0_0(helper_fpsub16s
);
3833 gen_op_store_FT0_fpr(rd
);
3835 case 0x056: /* VIS I fpsub32 */
3836 CHECK_FPU_FEATURE(dc
, VIS1
);
3837 gen_op_load_fpr_DT0(DFPREG(rs1
));
3838 gen_op_load_fpr_DT1(DFPREG(rs2
));
3839 tcg_gen_helper_0_0(helper_fpadd32
);
3840 gen_op_store_DT0_fpr(DFPREG(rd
));
3842 case 0x057: /* VIS I fpsub32s */
3843 CHECK_FPU_FEATURE(dc
, VIS1
);
3844 gen_op_load_fpr_FT0(rs1
);
3845 gen_op_load_fpr_FT1(rs2
);
3846 tcg_gen_helper_0_0(helper_fpsub32s
);
3847 gen_op_store_FT0_fpr(rd
);
3849 case 0x060: /* VIS I fzero */
3850 CHECK_FPU_FEATURE(dc
, VIS1
);
3851 tcg_gen_helper_0_0(helper_movl_DT0_0
);
3852 gen_op_store_DT0_fpr(DFPREG(rd
));
3854 case 0x061: /* VIS I fzeros */
3855 CHECK_FPU_FEATURE(dc
, VIS1
);
3856 tcg_gen_helper_0_0(helper_movl_FT0_0
);
3857 gen_op_store_FT0_fpr(rd
);
3859 case 0x062: /* VIS I fnor */
3860 CHECK_FPU_FEATURE(dc
, VIS1
);
3861 gen_op_load_fpr_DT0(DFPREG(rs1
));
3862 gen_op_load_fpr_DT1(DFPREG(rs2
));
3863 tcg_gen_helper_0_0(helper_fnor
);
3864 gen_op_store_DT0_fpr(DFPREG(rd
));
3866 case 0x063: /* VIS I fnors */
3867 CHECK_FPU_FEATURE(dc
, VIS1
);
3868 gen_op_load_fpr_FT0(rs1
);
3869 gen_op_load_fpr_FT1(rs2
);
3870 tcg_gen_helper_0_0(helper_fnors
);
3871 gen_op_store_FT0_fpr(rd
);
3873 case 0x064: /* VIS I fandnot2 */
3874 CHECK_FPU_FEATURE(dc
, VIS1
);
3875 gen_op_load_fpr_DT1(DFPREG(rs1
));
3876 gen_op_load_fpr_DT0(DFPREG(rs2
));
3877 tcg_gen_helper_0_0(helper_fandnot
);
3878 gen_op_store_DT0_fpr(DFPREG(rd
));
3880 case 0x065: /* VIS I fandnot2s */
3881 CHECK_FPU_FEATURE(dc
, VIS1
);
3882 gen_op_load_fpr_FT1(rs1
);
3883 gen_op_load_fpr_FT0(rs2
);
3884 tcg_gen_helper_0_0(helper_fandnots
);
3885 gen_op_store_FT0_fpr(rd
);
3887 case 0x066: /* VIS I fnot2 */
3888 CHECK_FPU_FEATURE(dc
, VIS1
);
3889 gen_op_load_fpr_DT1(DFPREG(rs2
));
3890 tcg_gen_helper_0_0(helper_fnot
);
3891 gen_op_store_DT0_fpr(DFPREG(rd
));
3893 case 0x067: /* VIS I fnot2s */
3894 CHECK_FPU_FEATURE(dc
, VIS1
);
3895 gen_op_load_fpr_FT1(rs2
);
3896 tcg_gen_helper_0_0(helper_fnot
);
3897 gen_op_store_FT0_fpr(rd
);
3899 case 0x068: /* VIS I fandnot1 */
3900 CHECK_FPU_FEATURE(dc
, VIS1
);
3901 gen_op_load_fpr_DT0(DFPREG(rs1
));
3902 gen_op_load_fpr_DT1(DFPREG(rs2
));
3903 tcg_gen_helper_0_0(helper_fandnot
);
3904 gen_op_store_DT0_fpr(DFPREG(rd
));
3906 case 0x069: /* VIS I fandnot1s */
3907 CHECK_FPU_FEATURE(dc
, VIS1
);
3908 gen_op_load_fpr_FT0(rs1
);
3909 gen_op_load_fpr_FT1(rs2
);
3910 tcg_gen_helper_0_0(helper_fandnots
);
3911 gen_op_store_FT0_fpr(rd
);
3913 case 0x06a: /* VIS I fnot1 */
3914 CHECK_FPU_FEATURE(dc
, VIS1
);
3915 gen_op_load_fpr_DT1(DFPREG(rs1
));
3916 tcg_gen_helper_0_0(helper_fnot
);
3917 gen_op_store_DT0_fpr(DFPREG(rd
));
3919 case 0x06b: /* VIS I fnot1s */
3920 CHECK_FPU_FEATURE(dc
, VIS1
);
3921 gen_op_load_fpr_FT1(rs1
);
3922 tcg_gen_helper_0_0(helper_fnot
);
3923 gen_op_store_FT0_fpr(rd
);
3925 case 0x06c: /* VIS I fxor */
3926 CHECK_FPU_FEATURE(dc
, VIS1
);
3927 gen_op_load_fpr_DT0(DFPREG(rs1
));
3928 gen_op_load_fpr_DT1(DFPREG(rs2
));
3929 tcg_gen_helper_0_0(helper_fxor
);
3930 gen_op_store_DT0_fpr(DFPREG(rd
));
3932 case 0x06d: /* VIS I fxors */
3933 CHECK_FPU_FEATURE(dc
, VIS1
);
3934 gen_op_load_fpr_FT0(rs1
);
3935 gen_op_load_fpr_FT1(rs2
);
3936 tcg_gen_helper_0_0(helper_fxors
);
3937 gen_op_store_FT0_fpr(rd
);
3939 case 0x06e: /* VIS I fnand */
3940 CHECK_FPU_FEATURE(dc
, VIS1
);
3941 gen_op_load_fpr_DT0(DFPREG(rs1
));
3942 gen_op_load_fpr_DT1(DFPREG(rs2
));
3943 tcg_gen_helper_0_0(helper_fnand
);
3944 gen_op_store_DT0_fpr(DFPREG(rd
));
3946 case 0x06f: /* VIS I fnands */
3947 CHECK_FPU_FEATURE(dc
, VIS1
);
3948 gen_op_load_fpr_FT0(rs1
);
3949 gen_op_load_fpr_FT1(rs2
);
3950 tcg_gen_helper_0_0(helper_fnands
);
3951 gen_op_store_FT0_fpr(rd
);
3953 case 0x070: /* VIS I fand */
3954 CHECK_FPU_FEATURE(dc
, VIS1
);
3955 gen_op_load_fpr_DT0(DFPREG(rs1
));
3956 gen_op_load_fpr_DT1(DFPREG(rs2
));
3957 tcg_gen_helper_0_0(helper_fand
);
3958 gen_op_store_DT0_fpr(DFPREG(rd
));
3960 case 0x071: /* VIS I fands */
3961 CHECK_FPU_FEATURE(dc
, VIS1
);
3962 gen_op_load_fpr_FT0(rs1
);
3963 gen_op_load_fpr_FT1(rs2
);
3964 tcg_gen_helper_0_0(helper_fands
);
3965 gen_op_store_FT0_fpr(rd
);
3967 case 0x072: /* VIS I fxnor */
3968 CHECK_FPU_FEATURE(dc
, VIS1
);
3969 gen_op_load_fpr_DT0(DFPREG(rs1
));
3970 gen_op_load_fpr_DT1(DFPREG(rs2
));
3971 tcg_gen_helper_0_0(helper_fxnor
);
3972 gen_op_store_DT0_fpr(DFPREG(rd
));
3974 case 0x073: /* VIS I fxnors */
3975 CHECK_FPU_FEATURE(dc
, VIS1
);
3976 gen_op_load_fpr_FT0(rs1
);
3977 gen_op_load_fpr_FT1(rs2
);
3978 tcg_gen_helper_0_0(helper_fxnors
);
3979 gen_op_store_FT0_fpr(rd
);
3981 case 0x074: /* VIS I fsrc1 */
3982 CHECK_FPU_FEATURE(dc
, VIS1
);
3983 gen_op_load_fpr_DT0(DFPREG(rs1
));
3984 gen_op_store_DT0_fpr(DFPREG(rd
));
3986 case 0x075: /* VIS I fsrc1s */
3987 CHECK_FPU_FEATURE(dc
, VIS1
);
3988 gen_op_load_fpr_FT0(rs1
);
3989 gen_op_store_FT0_fpr(rd
);
3991 case 0x076: /* VIS I fornot2 */
3992 CHECK_FPU_FEATURE(dc
, VIS1
);
3993 gen_op_load_fpr_DT1(DFPREG(rs1
));
3994 gen_op_load_fpr_DT0(DFPREG(rs2
));
3995 tcg_gen_helper_0_0(helper_fornot
);
3996 gen_op_store_DT0_fpr(DFPREG(rd
));
3998 case 0x077: /* VIS I fornot2s */
3999 CHECK_FPU_FEATURE(dc
, VIS1
);
4000 gen_op_load_fpr_FT1(rs1
);
4001 gen_op_load_fpr_FT0(rs2
);
4002 tcg_gen_helper_0_0(helper_fornots
);
4003 gen_op_store_FT0_fpr(rd
);
4005 case 0x078: /* VIS I fsrc2 */
4006 CHECK_FPU_FEATURE(dc
, VIS1
);
4007 gen_op_load_fpr_DT0(DFPREG(rs2
));
4008 gen_op_store_DT0_fpr(DFPREG(rd
));
4010 case 0x079: /* VIS I fsrc2s */
4011 CHECK_FPU_FEATURE(dc
, VIS1
);
4012 gen_op_load_fpr_FT0(rs2
);
4013 gen_op_store_FT0_fpr(rd
);
4015 case 0x07a: /* VIS I fornot1 */
4016 CHECK_FPU_FEATURE(dc
, VIS1
);
4017 gen_op_load_fpr_DT0(DFPREG(rs1
));
4018 gen_op_load_fpr_DT1(DFPREG(rs2
));
4019 tcg_gen_helper_0_0(helper_fornot
);
4020 gen_op_store_DT0_fpr(DFPREG(rd
));
4022 case 0x07b: /* VIS I fornot1s */
4023 CHECK_FPU_FEATURE(dc
, VIS1
);
4024 gen_op_load_fpr_FT0(rs1
);
4025 gen_op_load_fpr_FT1(rs2
);
4026 tcg_gen_helper_0_0(helper_fornots
);
4027 gen_op_store_FT0_fpr(rd
);
4029 case 0x07c: /* VIS I for */
4030 CHECK_FPU_FEATURE(dc
, VIS1
);
4031 gen_op_load_fpr_DT0(DFPREG(rs1
));
4032 gen_op_load_fpr_DT1(DFPREG(rs2
));
4033 tcg_gen_helper_0_0(helper_for
);
4034 gen_op_store_DT0_fpr(DFPREG(rd
));
4036 case 0x07d: /* VIS I fors */
4037 CHECK_FPU_FEATURE(dc
, VIS1
);
4038 gen_op_load_fpr_FT0(rs1
);
4039 gen_op_load_fpr_FT1(rs2
);
4040 tcg_gen_helper_0_0(helper_fors
);
4041 gen_op_store_FT0_fpr(rd
);
4043 case 0x07e: /* VIS I fone */
4044 CHECK_FPU_FEATURE(dc
, VIS1
);
4045 tcg_gen_helper_0_0(helper_movl_DT0_1
);
4046 gen_op_store_DT0_fpr(DFPREG(rd
));
4048 case 0x07f: /* VIS I fones */
4049 CHECK_FPU_FEATURE(dc
, VIS1
);
4050 tcg_gen_helper_0_0(helper_movl_FT0_1
);
4051 gen_op_store_FT0_fpr(rd
);
4053 case 0x080: /* VIS I shutdown */
4054 case 0x081: /* VIS II siam */
4063 } else if (xop
== 0x37) { /* V8 CPop2, V9 impdep2 */
4064 #ifdef TARGET_SPARC64
4069 #ifdef TARGET_SPARC64
4070 } else if (xop
== 0x39) { /* V9 return */
4073 save_state(dc
, cpu_cond
);
4074 cpu_src1
= get_src1(insn
, cpu_src1
);
4075 if (IS_IMM
) { /* immediate */
4076 rs2
= GET_FIELDs(insn
, 19, 31);
4077 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, (int)rs2
);
4078 } else { /* register */
4079 rs2
= GET_FIELD(insn
, 27, 31);
4081 gen_movl_reg_TN(rs2
, cpu_src2
);
4082 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4084 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
4086 tcg_gen_helper_0_0(helper_restore
);
4087 gen_mov_pc_npc(dc
, cpu_cond
);
4088 r_const
= tcg_const_i32(3);
4089 tcg_gen_helper_0_2(helper_check_align
, cpu_dst
, r_const
);
4090 tcg_temp_free(r_const
);
4091 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4092 dc
->npc
= DYNAMIC_PC
;
4096 cpu_src1
= get_src1(insn
, cpu_src1
);
4097 if (IS_IMM
) { /* immediate */
4098 rs2
= GET_FIELDs(insn
, 19, 31);
4099 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, (int)rs2
);
4100 } else { /* register */
4101 rs2
= GET_FIELD(insn
, 27, 31);
4103 gen_movl_reg_TN(rs2
, cpu_src2
);
4104 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4106 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
4109 case 0x38: /* jmpl */
4113 r_const
= tcg_const_tl(dc
->pc
);
4114 gen_movl_TN_reg(rd
, r_const
);
4115 tcg_temp_free(r_const
);
4116 gen_mov_pc_npc(dc
, cpu_cond
);
4117 r_const
= tcg_const_i32(3);
4118 tcg_gen_helper_0_2(helper_check_align
, cpu_dst
,
4120 tcg_temp_free(r_const
);
4121 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4122 dc
->npc
= DYNAMIC_PC
;
4125 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4126 case 0x39: /* rett, V9 return */
4130 if (!supervisor(dc
))
4132 gen_mov_pc_npc(dc
, cpu_cond
);
4133 r_const
= tcg_const_i32(3);
4134 tcg_gen_helper_0_2(helper_check_align
, cpu_dst
,
4136 tcg_temp_free(r_const
);
4137 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4138 dc
->npc
= DYNAMIC_PC
;
4139 tcg_gen_helper_0_0(helper_rett
);
4143 case 0x3b: /* flush */
4144 if (!((dc
)->features
& CPU_FEATURE_FLUSH
))
4146 tcg_gen_helper_0_1(helper_flush
, cpu_dst
);
4148 case 0x3c: /* save */
4149 save_state(dc
, cpu_cond
);
4150 tcg_gen_helper_0_0(helper_save
);
4151 gen_movl_TN_reg(rd
, cpu_dst
);
4153 case 0x3d: /* restore */
4154 save_state(dc
, cpu_cond
);
4155 tcg_gen_helper_0_0(helper_restore
);
4156 gen_movl_TN_reg(rd
, cpu_dst
);
4158 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4159 case 0x3e: /* V9 done/retry */
4163 if (!supervisor(dc
))
4165 dc
->npc
= DYNAMIC_PC
;
4166 dc
->pc
= DYNAMIC_PC
;
4167 tcg_gen_helper_0_0(helper_done
);
4170 if (!supervisor(dc
))
4172 dc
->npc
= DYNAMIC_PC
;
4173 dc
->pc
= DYNAMIC_PC
;
4174 tcg_gen_helper_0_0(helper_retry
);
4189 case 3: /* load/store instructions */
4191 unsigned int xop
= GET_FIELD(insn
, 7, 12);
4193 cpu_src1
= get_src1(insn
, cpu_src1
);
4194 if (xop
== 0x3c || xop
== 0x3e) { // V9 casa/casxa
4195 rs2
= GET_FIELD(insn
, 27, 31);
4196 gen_movl_reg_TN(rs2
, cpu_src2
);
4197 tcg_gen_mov_tl(cpu_addr
, cpu_src1
);
4198 } else if (IS_IMM
) { /* immediate */
4199 rs2
= GET_FIELDs(insn
, 19, 31);
4200 tcg_gen_addi_tl(cpu_addr
, cpu_src1
, (int)rs2
);
4201 } else { /* register */
4202 rs2
= GET_FIELD(insn
, 27, 31);
4204 gen_movl_reg_TN(rs2
, cpu_src2
);
4205 tcg_gen_add_tl(cpu_addr
, cpu_src1
, cpu_src2
);
4207 tcg_gen_mov_tl(cpu_addr
, cpu_src1
);
4209 if (xop
< 4 || (xop
> 7 && xop
< 0x14 && xop
!= 0x0e) ||
4210 (xop
> 0x17 && xop
<= 0x1d ) ||
4211 (xop
> 0x2c && xop
<= 0x33) || xop
== 0x1f || xop
== 0x3d) {
4213 case 0x0: /* load unsigned word */
4214 gen_address_mask(dc
, cpu_addr
);
4215 tcg_gen_qemu_ld32u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4217 case 0x1: /* load unsigned byte */
4218 gen_address_mask(dc
, cpu_addr
);
4219 tcg_gen_qemu_ld8u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4221 case 0x2: /* load unsigned halfword */
4222 gen_address_mask(dc
, cpu_addr
);
4223 tcg_gen_qemu_ld16u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4225 case 0x3: /* load double word */
4231 save_state(dc
, cpu_cond
);
4232 r_const
= tcg_const_i32(7);
4233 tcg_gen_helper_0_2(helper_check_align
, cpu_addr
,
4234 r_const
); // XXX remove
4235 tcg_temp_free(r_const
);
4236 gen_address_mask(dc
, cpu_addr
);
4237 tcg_gen_qemu_ld64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4238 tcg_gen_trunc_i64_tl(cpu_tmp0
, cpu_tmp64
);
4239 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffffULL
);
4240 gen_movl_TN_reg(rd
+ 1, cpu_tmp0
);
4241 tcg_gen_shri_i64(cpu_tmp64
, cpu_tmp64
, 32);
4242 tcg_gen_trunc_i64_tl(cpu_val
, cpu_tmp64
);
4243 tcg_gen_andi_tl(cpu_val
, cpu_val
, 0xffffffffULL
);
4246 case 0x9: /* load signed byte */
4247 gen_address_mask(dc
, cpu_addr
);
4248 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4250 case 0xa: /* load signed halfword */
4251 gen_address_mask(dc
, cpu_addr
);
4252 tcg_gen_qemu_ld16s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4254 case 0xd: /* ldstub -- XXX: should be atomically */
4258 gen_address_mask(dc
, cpu_addr
);
4259 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4260 r_const
= tcg_const_tl(0xff);
4261 tcg_gen_qemu_st8(r_const
, cpu_addr
, dc
->mem_idx
);
4262 tcg_temp_free(r_const
);
4265 case 0x0f: /* swap register with memory. Also
4267 CHECK_IU_FEATURE(dc
, SWAP
);
4268 gen_movl_reg_TN(rd
, cpu_val
);
4269 gen_address_mask(dc
, cpu_addr
);
4270 tcg_gen_qemu_ld32u(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4271 tcg_gen_qemu_st32(cpu_val
, cpu_addr
, dc
->mem_idx
);
4272 tcg_gen_extu_i32_tl(cpu_val
, cpu_tmp32
);
4274 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4275 case 0x10: /* load word alternate */
4276 #ifndef TARGET_SPARC64
4279 if (!supervisor(dc
))
4282 save_state(dc
, cpu_cond
);
4283 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 0);
4285 case 0x11: /* load unsigned byte alternate */
4286 #ifndef TARGET_SPARC64
4289 if (!supervisor(dc
))
4292 save_state(dc
, cpu_cond
);
4293 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 0);
4295 case 0x12: /* load unsigned halfword alternate */
4296 #ifndef TARGET_SPARC64
4299 if (!supervisor(dc
))
4302 save_state(dc
, cpu_cond
);
4303 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 0);
4305 case 0x13: /* load double word alternate */
4306 #ifndef TARGET_SPARC64
4309 if (!supervisor(dc
))
4314 save_state(dc
, cpu_cond
);
4315 gen_ldda_asi(cpu_val
, cpu_addr
, insn
, rd
);
4317 case 0x19: /* load signed byte alternate */
4318 #ifndef TARGET_SPARC64
4321 if (!supervisor(dc
))
4324 save_state(dc
, cpu_cond
);
4325 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 1);
4327 case 0x1a: /* load signed halfword alternate */
4328 #ifndef TARGET_SPARC64
4331 if (!supervisor(dc
))
4334 save_state(dc
, cpu_cond
);
4335 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 1);
4337 case 0x1d: /* ldstuba -- XXX: should be atomically */
4338 #ifndef TARGET_SPARC64
4341 if (!supervisor(dc
))
4344 save_state(dc
, cpu_cond
);
4345 gen_ldstub_asi(cpu_val
, cpu_addr
, insn
);
4347 case 0x1f: /* swap reg with alt. memory. Also
4349 CHECK_IU_FEATURE(dc
, SWAP
);
4350 #ifndef TARGET_SPARC64
4353 if (!supervisor(dc
))
4356 save_state(dc
, cpu_cond
);
4357 gen_movl_reg_TN(rd
, cpu_val
);
4358 gen_swap_asi(cpu_val
, cpu_addr
, insn
);
4361 #ifndef TARGET_SPARC64
4362 case 0x30: /* ldc */
4363 case 0x31: /* ldcsr */
4364 case 0x33: /* lddc */
4368 #ifdef TARGET_SPARC64
4369 case 0x08: /* V9 ldsw */
4370 gen_address_mask(dc
, cpu_addr
);
4371 tcg_gen_qemu_ld32s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4373 case 0x0b: /* V9 ldx */
4374 gen_address_mask(dc
, cpu_addr
);
4375 tcg_gen_qemu_ld64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4377 case 0x18: /* V9 ldswa */
4378 save_state(dc
, cpu_cond
);
4379 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 1);
4381 case 0x1b: /* V9 ldxa */
4382 save_state(dc
, cpu_cond
);
4383 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 8, 0);
4385 case 0x2d: /* V9 prefetch, no effect */
4387 case 0x30: /* V9 ldfa */
4388 save_state(dc
, cpu_cond
);
4389 gen_ldf_asi(cpu_addr
, insn
, 4, rd
);
4391 case 0x33: /* V9 lddfa */
4392 save_state(dc
, cpu_cond
);
4393 gen_ldf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
4395 case 0x3d: /* V9 prefetcha, no effect */
4397 case 0x32: /* V9 ldqfa */
4398 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4399 save_state(dc
, cpu_cond
);
4400 gen_ldf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
4406 gen_movl_TN_reg(rd
, cpu_val
);
4407 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4410 } else if (xop
>= 0x20 && xop
< 0x24) {
4411 if (gen_trap_ifnofpu(dc
, cpu_cond
))
4413 save_state(dc
, cpu_cond
);
4415 case 0x20: /* load fpreg */
4416 gen_address_mask(dc
, cpu_addr
);
4417 tcg_gen_qemu_ld32u(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4418 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
4419 offsetof(CPUState
, fpr
[rd
]));
4421 case 0x21: /* load fsr */
4422 gen_address_mask(dc
, cpu_addr
);
4423 tcg_gen_qemu_ld32u(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4424 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
4425 offsetof(CPUState
, ft0
));
4426 tcg_gen_helper_0_0(helper_ldfsr
);
4428 case 0x22: /* load quad fpreg */
4432 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4433 r_const
= tcg_const_i32(dc
->mem_idx
);
4434 tcg_gen_helper_0_2(helper_ldqf
, cpu_addr
, r_const
);
4435 tcg_temp_free(r_const
);
4436 gen_op_store_QT0_fpr(QFPREG(rd
));
4439 case 0x23: /* load double fpreg */
4443 r_const
= tcg_const_i32(dc
->mem_idx
);
4444 tcg_gen_helper_0_2(helper_lddf
, cpu_addr
, r_const
);
4445 tcg_temp_free(r_const
);
4446 gen_op_store_DT0_fpr(DFPREG(rd
));
4452 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18) || \
4453 xop
== 0xe || xop
== 0x1e) {
4454 gen_movl_reg_TN(rd
, cpu_val
);
4456 case 0x4: /* store word */
4457 gen_address_mask(dc
, cpu_addr
);
4458 tcg_gen_qemu_st32(cpu_val
, cpu_addr
, dc
->mem_idx
);
4460 case 0x5: /* store byte */
4461 gen_address_mask(dc
, cpu_addr
);
4462 tcg_gen_qemu_st8(cpu_val
, cpu_addr
, dc
->mem_idx
);
4464 case 0x6: /* store halfword */
4465 gen_address_mask(dc
, cpu_addr
);
4466 tcg_gen_qemu_st16(cpu_val
, cpu_addr
, dc
->mem_idx
);
4468 case 0x7: /* store double word */
4472 TCGv r_low
, r_const
;
4474 save_state(dc
, cpu_cond
);
4475 gen_address_mask(dc
, cpu_addr
);
4476 r_const
= tcg_const_i32(7);
4477 tcg_gen_helper_0_2(helper_check_align
, cpu_addr
,
4478 r_const
); // XXX remove
4479 tcg_temp_free(r_const
);
4480 r_low
= tcg_temp_new(TCG_TYPE_TL
);
4481 gen_movl_reg_TN(rd
+ 1, r_low
);
4482 tcg_gen_helper_1_2(helper_pack64
, cpu_tmp64
, cpu_val
,
4484 tcg_temp_free(r_low
);
4485 tcg_gen_qemu_st64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4488 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4489 case 0x14: /* store word alternate */
4490 #ifndef TARGET_SPARC64
4493 if (!supervisor(dc
))
4496 save_state(dc
, cpu_cond
);
4497 gen_st_asi(cpu_val
, cpu_addr
, insn
, 4);
4499 case 0x15: /* store byte alternate */
4500 #ifndef TARGET_SPARC64
4503 if (!supervisor(dc
))
4506 save_state(dc
, cpu_cond
);
4507 gen_st_asi(cpu_val
, cpu_addr
, insn
, 1);
4509 case 0x16: /* store halfword alternate */
4510 #ifndef TARGET_SPARC64
4513 if (!supervisor(dc
))
4516 save_state(dc
, cpu_cond
);
4517 gen_st_asi(cpu_val
, cpu_addr
, insn
, 2);
4519 case 0x17: /* store double word alternate */
4520 #ifndef TARGET_SPARC64
4523 if (!supervisor(dc
))
4529 save_state(dc
, cpu_cond
);
4530 gen_stda_asi(cpu_val
, cpu_addr
, insn
, rd
);
4534 #ifdef TARGET_SPARC64
4535 case 0x0e: /* V9 stx */
4536 gen_address_mask(dc
, cpu_addr
);
4537 tcg_gen_qemu_st64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4539 case 0x1e: /* V9 stxa */
4540 save_state(dc
, cpu_cond
);
4541 gen_st_asi(cpu_val
, cpu_addr
, insn
, 8);
4547 } else if (xop
> 0x23 && xop
< 0x28) {
4548 if (gen_trap_ifnofpu(dc
, cpu_cond
))
4550 save_state(dc
, cpu_cond
);
4552 case 0x24: /* store fpreg */
4553 gen_address_mask(dc
, cpu_addr
);
4554 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
4555 offsetof(CPUState
, fpr
[rd
]));
4556 tcg_gen_qemu_st32(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4558 case 0x25: /* stfsr, V9 stxfsr */
4559 gen_address_mask(dc
, cpu_addr
);
4560 tcg_gen_helper_0_0(helper_stfsr
);
4561 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
4562 offsetof(CPUState
, ft0
));
4563 tcg_gen_qemu_st32(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4566 #ifdef TARGET_SPARC64
4567 /* V9 stqf, store quad fpreg */
4571 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4572 gen_op_load_fpr_QT0(QFPREG(rd
));
4573 r_const
= tcg_const_i32(dc
->mem_idx
);
4574 tcg_gen_helper_0_2(helper_stqf
, cpu_addr
, r_const
);
4575 tcg_temp_free(r_const
);
4578 #else /* !TARGET_SPARC64 */
4579 /* stdfq, store floating point queue */
4580 #if defined(CONFIG_USER_ONLY)
4583 if (!supervisor(dc
))
4585 if (gen_trap_ifnofpu(dc
, cpu_cond
))
4590 case 0x27: /* store double fpreg */
4594 gen_op_load_fpr_DT0(DFPREG(rd
));
4595 r_const
= tcg_const_i32(dc
->mem_idx
);
4596 tcg_gen_helper_0_2(helper_stdf
, cpu_addr
, r_const
);
4597 tcg_temp_free(r_const
);
4603 } else if (xop
> 0x33 && xop
< 0x3f) {
4604 save_state(dc
, cpu_cond
);
4606 #ifdef TARGET_SPARC64
4607 case 0x34: /* V9 stfa */
4608 gen_op_load_fpr_FT0(rd
);
4609 gen_stf_asi(cpu_addr
, insn
, 4, rd
);
4611 case 0x36: /* V9 stqfa */
4615 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4616 r_const
= tcg_const_i32(7);
4617 tcg_gen_helper_0_2(helper_check_align
, cpu_addr
,
4619 tcg_temp_free(r_const
);
4620 gen_op_load_fpr_QT0(QFPREG(rd
));
4621 gen_stf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
4624 case 0x37: /* V9 stdfa */
4625 gen_op_load_fpr_DT0(DFPREG(rd
));
4626 gen_stf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
4628 case 0x3c: /* V9 casa */
4629 gen_cas_asi(cpu_val
, cpu_addr
, cpu_src2
, insn
, rd
);
4630 gen_movl_TN_reg(rd
, cpu_val
);
4632 case 0x3e: /* V9 casxa */
4633 gen_casx_asi(cpu_val
, cpu_addr
, cpu_src2
, insn
, rd
);
4634 gen_movl_TN_reg(rd
, cpu_val
);
4637 case 0x34: /* stc */
4638 case 0x35: /* stcsr */
4639 case 0x36: /* stdcq */
4640 case 0x37: /* stdc */
4652 /* default case for non jump instructions */
4653 if (dc
->npc
== DYNAMIC_PC
) {
4654 dc
->pc
= DYNAMIC_PC
;
4656 } else if (dc
->npc
== JUMP_PC
) {
4657 /* we can do a static jump */
4658 gen_branch2(dc
, dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_cond
);
4662 dc
->npc
= dc
->npc
+ 4;
4670 save_state(dc
, cpu_cond
);
4671 r_const
= tcg_const_i32(TT_ILL_INSN
);
4672 tcg_gen_helper_0_1(raise_exception
, r_const
);
4673 tcg_temp_free(r_const
);
4681 save_state(dc
, cpu_cond
);
4682 r_const
= tcg_const_i32(TT_UNIMP_FLUSH
);
4683 tcg_gen_helper_0_1(raise_exception
, r_const
);
4684 tcg_temp_free(r_const
);
4688 #if !defined(CONFIG_USER_ONLY)
4693 save_state(dc
, cpu_cond
);
4694 r_const
= tcg_const_i32(TT_PRIV_INSN
);
4695 tcg_gen_helper_0_1(raise_exception
, r_const
);
4696 tcg_temp_free(r_const
);
4702 save_state(dc
, cpu_cond
);
4703 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP
);
4706 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4708 save_state(dc
, cpu_cond
);
4709 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR
);
4713 #ifndef TARGET_SPARC64
4718 save_state(dc
, cpu_cond
);
4719 r_const
= tcg_const_i32(TT_NCP_INSN
);
4720 tcg_gen_helper_0_1(raise_exception
, r_const
);
4721 tcg_temp_free(r_const
);
4728 static inline void gen_intermediate_code_internal(TranslationBlock
* tb
,
4729 int spc
, CPUSPARCState
*env
)
4731 target_ulong pc_start
, last_pc
;
4732 uint16_t *gen_opc_end
;
4733 DisasContext dc1
, *dc
= &dc1
;
4738 memset(dc
, 0, sizeof(DisasContext
));
4743 dc
->npc
= (target_ulong
) tb
->cs_base
;
4744 dc
->mem_idx
= cpu_mmu_index(env
);
4745 dc
->features
= env
->features
;
4746 if ((dc
->features
& CPU_FEATURE_FLOAT
)) {
4747 dc
->fpu_enabled
= cpu_fpu_enabled(env
);
4748 #if defined(CONFIG_USER_ONLY)
4749 dc
->features
|= CPU_FEATURE_FLOAT128
;
4752 dc
->fpu_enabled
= 0;
4753 #ifdef TARGET_SPARC64
4754 dc
->address_mask_32bit
= env
->pstate
& PS_AM
;
4756 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
4758 cpu_tmp0
= tcg_temp_new(TCG_TYPE_TL
);
4759 cpu_tmp32
= tcg_temp_new(TCG_TYPE_I32
);
4760 cpu_tmp64
= tcg_temp_new(TCG_TYPE_I64
);
4762 cpu_dst
= tcg_temp_local_new(TCG_TYPE_TL
);
4765 cpu_val
= tcg_temp_local_new(TCG_TYPE_TL
);
4766 cpu_addr
= tcg_temp_local_new(TCG_TYPE_TL
);
4769 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
4771 max_insns
= CF_COUNT_MASK
;
4774 if (env
->nb_breakpoints
> 0) {
4775 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
4776 if (env
->breakpoints
[j
] == dc
->pc
) {
4777 if (dc
->pc
!= pc_start
)
4778 save_state(dc
, cpu_cond
);
4779 tcg_gen_helper_0_0(helper_debug
);
4788 fprintf(logfile
, "Search PC...\n");
4789 j
= gen_opc_ptr
- gen_opc_buf
;
4793 gen_opc_instr_start
[lj
++] = 0;
4794 gen_opc_pc
[lj
] = dc
->pc
;
4795 gen_opc_npc
[lj
] = dc
->npc
;
4796 gen_opc_instr_start
[lj
] = 1;
4797 gen_opc_icount
[lj
] = num_insns
;
4800 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
4803 disas_sparc_insn(dc
);
4808 /* if the next PC is different, we abort now */
4809 if (dc
->pc
!= (last_pc
+ 4))
4811 /* if we reach a page boundary, we stop generation so that the
4812 PC of a TT_TFAULT exception is always in the right page */
4813 if ((dc
->pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
4815 /* if single step mode, we generate only one instruction and
4816 generate an exception */
4817 if (env
->singlestep_enabled
) {
4818 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
4822 } while ((gen_opc_ptr
< gen_opc_end
) &&
4823 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32) &&
4824 num_insns
< max_insns
);
4827 tcg_temp_free(cpu_addr
);
4828 tcg_temp_free(cpu_val
);
4829 tcg_temp_free(cpu_dst
);
4830 tcg_temp_free(cpu_tmp64
);
4831 tcg_temp_free(cpu_tmp32
);
4832 tcg_temp_free(cpu_tmp0
);
4833 if (tb
->cflags
& CF_LAST_IO
)
4836 if (dc
->pc
!= DYNAMIC_PC
&&
4837 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
4838 /* static PC and NPC: we can use direct chaining */
4839 gen_goto_tb(dc
, 0, dc
->pc
, dc
->npc
);
4841 if (dc
->pc
!= DYNAMIC_PC
)
4842 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
4843 save_npc(dc
, cpu_cond
);
4847 gen_icount_end(tb
, num_insns
);
4848 *gen_opc_ptr
= INDEX_op_end
;
4850 j
= gen_opc_ptr
- gen_opc_buf
;
4853 gen_opc_instr_start
[lj
++] = 0;
4859 gen_opc_jump_pc
[0] = dc
->jump_pc
[0];
4860 gen_opc_jump_pc
[1] = dc
->jump_pc
[1];
4862 tb
->size
= last_pc
+ 4 - pc_start
;
4863 tb
->icount
= num_insns
;
4866 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4867 fprintf(logfile
, "--------------\n");
4868 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
4869 target_disas(logfile
, pc_start
, last_pc
+ 4 - pc_start
, 0);
4870 fprintf(logfile
, "\n");
4875 void gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
4877 gen_intermediate_code_internal(tb
, 0, env
);
4880 void gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
4882 gen_intermediate_code_internal(tb
, 1, env
);
4885 void gen_intermediate_code_init(CPUSPARCState
*env
)
4889 static const char * const gregnames
[8] = {
4890 NULL
, // g0 not used
4900 /* init various static tables */
4904 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
4905 cpu_regwptr
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
4906 offsetof(CPUState
, regwptr
),
4908 #ifdef TARGET_SPARC64
4909 cpu_xcc
= tcg_global_mem_new(TCG_TYPE_I32
,
4910 TCG_AREG0
, offsetof(CPUState
, xcc
),
4913 cpu_cond
= tcg_global_mem_new(TCG_TYPE_TL
,
4914 TCG_AREG0
, offsetof(CPUState
, cond
),
4916 cpu_cc_src
= tcg_global_mem_new(TCG_TYPE_TL
,
4917 TCG_AREG0
, offsetof(CPUState
, cc_src
),
4919 cpu_cc_src2
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
4920 offsetof(CPUState
, cc_src2
),
4922 cpu_cc_dst
= tcg_global_mem_new(TCG_TYPE_TL
,
4923 TCG_AREG0
, offsetof(CPUState
, cc_dst
),
4925 cpu_psr
= tcg_global_mem_new(TCG_TYPE_I32
,
4926 TCG_AREG0
, offsetof(CPUState
, psr
),
4928 cpu_fsr
= tcg_global_mem_new(TCG_TYPE_TL
,
4929 TCG_AREG0
, offsetof(CPUState
, fsr
),
4931 cpu_pc
= tcg_global_mem_new(TCG_TYPE_TL
,
4932 TCG_AREG0
, offsetof(CPUState
, pc
),
4934 cpu_npc
= tcg_global_mem_new(TCG_TYPE_TL
,
4935 TCG_AREG0
, offsetof(CPUState
, npc
),
4937 for (i
= 1; i
< 8; i
++)
4938 cpu_gregs
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
4939 offsetof(CPUState
, gregs
[i
]),
4941 /* register helpers */
4944 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4949 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
4950 unsigned long searched_pc
, int pc_pos
, void *puc
)
4953 env
->pc
= gen_opc_pc
[pc_pos
];
4954 npc
= gen_opc_npc
[pc_pos
];
4956 /* dynamic NPC: already stored */
4957 } else if (npc
== 2) {
4958 target_ulong t2
= (target_ulong
)(unsigned long)puc
;
4959 /* jump PC: use T2 and the jump targets of the translation */
4961 env
->npc
= gen_opc_jump_pc
[0];
4963 env
->npc
= gen_opc_jump_pc
[1];