4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 #define DYNAMIC_PC 1 /* dynamic pc value */
38 #define JUMP_PC 2 /* dynamic pc value which takes only two values
39 according to jump_pc[T2] */
41 /* global register indexes */
42 static TCGv_ptr cpu_env
, cpu_regwptr
;
43 static TCGv cpu_cc_src
, cpu_cc_src2
, cpu_cc_dst
;
44 static TCGv_i32 cpu_cc_op
;
45 static TCGv_i32 cpu_psr
;
46 static TCGv cpu_fsr
, cpu_pc
, cpu_npc
, cpu_gregs
[8];
48 #ifndef CONFIG_USER_ONLY
51 static TCGv cpu_cond
, cpu_dst
, cpu_addr
, cpu_val
;
53 static TCGv_i32 cpu_xcc
, cpu_asi
, cpu_fprs
;
55 static TCGv cpu_tick_cmpr
, cpu_stick_cmpr
, cpu_hstick_cmpr
;
56 static TCGv cpu_hintp
, cpu_htba
, cpu_hver
, cpu_ssr
, cpu_ver
;
57 static TCGv_i32 cpu_softint
;
61 /* local register indexes (only used inside old micro ops) */
63 static TCGv_i32 cpu_tmp32
;
64 static TCGv_i64 cpu_tmp64
;
65 /* Floating point registers */
66 static TCGv_i64 cpu_fpr
[TARGET_DPREGS
];
68 static target_ulong gen_opc_npc
[OPC_BUF_SIZE
];
69 static target_ulong gen_opc_jump_pc
[2];
71 #include "gen-icount.h"
73 typedef struct DisasContext
{
74 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
75 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
76 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
80 int address_mask_32bit
;
82 uint32_t cc_op
; /* current CC operation */
83 struct TranslationBlock
*tb
;
96 // This function uses non-native bit order
97 #define GET_FIELD(X, FROM, TO) \
98 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
100 // This function uses the order in the manuals, i.e. bit 0 is 2^0
101 #define GET_FIELD_SP(X, FROM, TO) \
102 GET_FIELD(X, 31 - (TO), 31 - (FROM))
104 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
105 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
107 #ifdef TARGET_SPARC64
108 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
109 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
111 #define DFPREG(r) (r & 0x1e)
112 #define QFPREG(r) (r & 0x1c)
115 #define UA2005_HTRAP_MASK 0xff
116 #define V8_TRAP_MASK 0x7f
118 static int sign_extend(int x
, int len
)
121 return (x
<< len
) >> len
;
124 #define IS_IMM (insn & (1<<13))
126 static inline void gen_update_fprs_dirty(int rd
)
128 #if defined(TARGET_SPARC64)
129 tcg_gen_ori_i32(cpu_fprs
, cpu_fprs
, (rd
< 32) ? 1 : 2);
133 /* floating point registers moves */
134 static TCGv_i32
gen_load_fpr_F(DisasContext
*dc
, unsigned int src
)
136 #if TCG_TARGET_REG_BITS == 32
138 return TCGV_LOW(cpu_fpr
[src
/ 2]);
140 return TCGV_HIGH(cpu_fpr
[src
/ 2]);
144 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr
[src
/ 2]));
146 TCGv_i32 ret
= tcg_temp_local_new_i32();
147 TCGv_i64 t
= tcg_temp_new_i64();
149 tcg_gen_shri_i64(t
, cpu_fpr
[src
/ 2], 32);
150 tcg_gen_trunc_i64_i32(ret
, t
);
151 tcg_temp_free_i64(t
);
153 dc
->t32
[dc
->n_t32
++] = ret
;
154 assert(dc
->n_t32
<= ARRAY_SIZE(dc
->t32
));
161 static void gen_store_fpr_F(DisasContext
*dc
, unsigned int dst
, TCGv_i32 v
)
163 #if TCG_TARGET_REG_BITS == 32
165 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr
[dst
/ 2]), v
);
167 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr
[dst
/ 2]), v
);
170 TCGv_i64 t
= MAKE_TCGV_I64(GET_TCGV_I32(v
));
171 tcg_gen_deposit_i64(cpu_fpr
[dst
/ 2], cpu_fpr
[dst
/ 2], t
,
172 (dst
& 1 ? 0 : 32), 32);
174 gen_update_fprs_dirty(dst
);
177 static TCGv_i32
gen_dest_fpr_F(void)
182 static TCGv_i64
gen_load_fpr_D(DisasContext
*dc
, unsigned int src
)
185 return cpu_fpr
[src
/ 2];
188 static void gen_store_fpr_D(DisasContext
*dc
, unsigned int dst
, TCGv_i64 v
)
191 tcg_gen_mov_i64(cpu_fpr
[dst
/ 2], v
);
192 gen_update_fprs_dirty(dst
);
195 static TCGv_i64
gen_dest_fpr_D(void)
200 static void gen_op_load_fpr_QT0(unsigned int src
)
202 tcg_gen_st_i64(cpu_fpr
[src
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
203 offsetof(CPU_QuadU
, ll
.upper
));
204 tcg_gen_st_i64(cpu_fpr
[src
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
205 offsetof(CPU_QuadU
, ll
.lower
));
208 static void gen_op_load_fpr_QT1(unsigned int src
)
210 tcg_gen_st_i64(cpu_fpr
[src
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt1
) +
211 offsetof(CPU_QuadU
, ll
.upper
));
212 tcg_gen_st_i64(cpu_fpr
[src
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt1
) +
213 offsetof(CPU_QuadU
, ll
.lower
));
216 static void gen_op_store_QT0_fpr(unsigned int dst
)
218 tcg_gen_ld_i64(cpu_fpr
[dst
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
219 offsetof(CPU_QuadU
, ll
.upper
));
220 tcg_gen_ld_i64(cpu_fpr
[dst
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
221 offsetof(CPU_QuadU
, ll
.lower
));
224 #ifdef TARGET_SPARC64
225 static void gen_move_Q(unsigned int rd
, unsigned int rs
)
230 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2], cpu_fpr
[rs
/ 2]);
231 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2 + 1], cpu_fpr
[rs
/ 2 + 1]);
232 gen_update_fprs_dirty(rd
);
237 #ifdef CONFIG_USER_ONLY
238 #define supervisor(dc) 0
239 #ifdef TARGET_SPARC64
240 #define hypervisor(dc) 0
243 #define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
244 #ifdef TARGET_SPARC64
245 #define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
250 #ifdef TARGET_SPARC64
252 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
254 #define AM_CHECK(dc) (1)
258 static inline void gen_address_mask(DisasContext
*dc
, TCGv addr
)
260 #ifdef TARGET_SPARC64
262 tcg_gen_andi_tl(addr
, addr
, 0xffffffffULL
);
266 static inline void gen_movl_reg_TN(int reg
, TCGv tn
)
269 tcg_gen_movi_tl(tn
, 0);
271 tcg_gen_mov_tl(tn
, cpu_gregs
[reg
]);
273 tcg_gen_ld_tl(tn
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
277 static inline void gen_movl_TN_reg(int reg
, TCGv tn
)
282 tcg_gen_mov_tl(cpu_gregs
[reg
], tn
);
284 tcg_gen_st_tl(tn
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
288 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
,
289 target_ulong pc
, target_ulong npc
)
291 TranslationBlock
*tb
;
294 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
295 (npc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
297 /* jump to same page: we can use a direct jump */
298 tcg_gen_goto_tb(tb_num
);
299 tcg_gen_movi_tl(cpu_pc
, pc
);
300 tcg_gen_movi_tl(cpu_npc
, npc
);
301 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
303 /* jump to another page: currently not optimized */
304 tcg_gen_movi_tl(cpu_pc
, pc
);
305 tcg_gen_movi_tl(cpu_npc
, npc
);
311 static inline void gen_mov_reg_N(TCGv reg
, TCGv_i32 src
)
313 tcg_gen_extu_i32_tl(reg
, src
);
314 tcg_gen_shri_tl(reg
, reg
, PSR_NEG_SHIFT
);
315 tcg_gen_andi_tl(reg
, reg
, 0x1);
318 static inline void gen_mov_reg_Z(TCGv reg
, TCGv_i32 src
)
320 tcg_gen_extu_i32_tl(reg
, src
);
321 tcg_gen_shri_tl(reg
, reg
, PSR_ZERO_SHIFT
);
322 tcg_gen_andi_tl(reg
, reg
, 0x1);
325 static inline void gen_mov_reg_V(TCGv reg
, TCGv_i32 src
)
327 tcg_gen_extu_i32_tl(reg
, src
);
328 tcg_gen_shri_tl(reg
, reg
, PSR_OVF_SHIFT
);
329 tcg_gen_andi_tl(reg
, reg
, 0x1);
332 static inline void gen_mov_reg_C(TCGv reg
, TCGv_i32 src
)
334 tcg_gen_extu_i32_tl(reg
, src
);
335 tcg_gen_shri_tl(reg
, reg
, PSR_CARRY_SHIFT
);
336 tcg_gen_andi_tl(reg
, reg
, 0x1);
339 static inline void gen_op_addi_cc(TCGv dst
, TCGv src1
, target_long src2
)
341 tcg_gen_mov_tl(cpu_cc_src
, src1
);
342 tcg_gen_movi_tl(cpu_cc_src2
, src2
);
343 tcg_gen_addi_tl(cpu_cc_dst
, cpu_cc_src
, src2
);
344 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
347 static inline void gen_op_add_cc(TCGv dst
, TCGv src1
, TCGv src2
)
349 tcg_gen_mov_tl(cpu_cc_src
, src1
);
350 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
351 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
352 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
355 static TCGv_i32
gen_add32_carry32(void)
357 TCGv_i32 carry_32
, cc_src1_32
, cc_src2_32
;
359 /* Carry is computed from a previous add: (dst < src) */
360 #if TARGET_LONG_BITS == 64
361 cc_src1_32
= tcg_temp_new_i32();
362 cc_src2_32
= tcg_temp_new_i32();
363 tcg_gen_trunc_i64_i32(cc_src1_32
, cpu_cc_dst
);
364 tcg_gen_trunc_i64_i32(cc_src2_32
, cpu_cc_src
);
366 cc_src1_32
= cpu_cc_dst
;
367 cc_src2_32
= cpu_cc_src
;
370 carry_32
= tcg_temp_new_i32();
371 tcg_gen_setcond_i32(TCG_COND_LTU
, carry_32
, cc_src1_32
, cc_src2_32
);
373 #if TARGET_LONG_BITS == 64
374 tcg_temp_free_i32(cc_src1_32
);
375 tcg_temp_free_i32(cc_src2_32
);
381 static TCGv_i32
gen_sub32_carry32(void)
383 TCGv_i32 carry_32
, cc_src1_32
, cc_src2_32
;
385 /* Carry is computed from a previous borrow: (src1 < src2) */
386 #if TARGET_LONG_BITS == 64
387 cc_src1_32
= tcg_temp_new_i32();
388 cc_src2_32
= tcg_temp_new_i32();
389 tcg_gen_trunc_i64_i32(cc_src1_32
, cpu_cc_src
);
390 tcg_gen_trunc_i64_i32(cc_src2_32
, cpu_cc_src2
);
392 cc_src1_32
= cpu_cc_src
;
393 cc_src2_32
= cpu_cc_src2
;
396 carry_32
= tcg_temp_new_i32();
397 tcg_gen_setcond_i32(TCG_COND_LTU
, carry_32
, cc_src1_32
, cc_src2_32
);
399 #if TARGET_LONG_BITS == 64
400 tcg_temp_free_i32(cc_src1_32
);
401 tcg_temp_free_i32(cc_src2_32
);
407 static void gen_op_addx_int(DisasContext
*dc
, TCGv dst
, TCGv src1
,
408 TCGv src2
, int update_cc
)
416 /* Carry is known to be zero. Fall back to plain ADD. */
418 gen_op_add_cc(dst
, src1
, src2
);
420 tcg_gen_add_tl(dst
, src1
, src2
);
427 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
429 /* For 32-bit hosts, we can re-use the host's hardware carry
430 generation by using an ADD2 opcode. We discard the low
431 part of the output. Ideally we'd combine this operation
432 with the add that generated the carry in the first place. */
433 TCGv dst_low
= tcg_temp_new();
434 tcg_gen_op6_i32(INDEX_op_add2_i32
, dst_low
, dst
,
435 cpu_cc_src
, src1
, cpu_cc_src2
, src2
);
436 tcg_temp_free(dst_low
);
440 carry_32
= gen_add32_carry32();
446 carry_32
= gen_sub32_carry32();
450 /* We need external help to produce the carry. */
451 carry_32
= tcg_temp_new_i32();
452 gen_helper_compute_C_icc(carry_32
, cpu_env
);
456 #if TARGET_LONG_BITS == 64
457 carry
= tcg_temp_new();
458 tcg_gen_extu_i32_i64(carry
, carry_32
);
463 tcg_gen_add_tl(dst
, src1
, src2
);
464 tcg_gen_add_tl(dst
, dst
, carry
);
466 tcg_temp_free_i32(carry_32
);
467 #if TARGET_LONG_BITS == 64
468 tcg_temp_free(carry
);
471 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
475 tcg_gen_mov_tl(cpu_cc_src
, src1
);
476 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
477 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
478 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADDX
);
479 dc
->cc_op
= CC_OP_ADDX
;
483 static inline void gen_op_subi_cc(TCGv dst
, TCGv src1
, target_long src2
, DisasContext
*dc
)
485 tcg_gen_mov_tl(cpu_cc_src
, src1
);
486 tcg_gen_movi_tl(cpu_cc_src2
, src2
);
488 tcg_gen_mov_tl(cpu_cc_dst
, src1
);
489 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
490 dc
->cc_op
= CC_OP_LOGIC
;
492 tcg_gen_subi_tl(cpu_cc_dst
, cpu_cc_src
, src2
);
493 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
494 dc
->cc_op
= CC_OP_SUB
;
496 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
499 static inline void gen_op_sub_cc(TCGv dst
, TCGv src1
, TCGv src2
)
501 tcg_gen_mov_tl(cpu_cc_src
, src1
);
502 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
503 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
504 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
507 static void gen_op_subx_int(DisasContext
*dc
, TCGv dst
, TCGv src1
,
508 TCGv src2
, int update_cc
)
516 /* Carry is known to be zero. Fall back to plain SUB. */
518 gen_op_sub_cc(dst
, src1
, src2
);
520 tcg_gen_sub_tl(dst
, src1
, src2
);
527 carry_32
= gen_add32_carry32();
533 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
535 /* For 32-bit hosts, we can re-use the host's hardware carry
536 generation by using a SUB2 opcode. We discard the low
537 part of the output. Ideally we'd combine this operation
538 with the add that generated the carry in the first place. */
539 TCGv dst_low
= tcg_temp_new();
540 tcg_gen_op6_i32(INDEX_op_sub2_i32
, dst_low
, dst
,
541 cpu_cc_src
, src1
, cpu_cc_src2
, src2
);
542 tcg_temp_free(dst_low
);
546 carry_32
= gen_sub32_carry32();
550 /* We need external help to produce the carry. */
551 carry_32
= tcg_temp_new_i32();
552 gen_helper_compute_C_icc(carry_32
, cpu_env
);
556 #if TARGET_LONG_BITS == 64
557 carry
= tcg_temp_new();
558 tcg_gen_extu_i32_i64(carry
, carry_32
);
563 tcg_gen_sub_tl(dst
, src1
, src2
);
564 tcg_gen_sub_tl(dst
, dst
, carry
);
566 tcg_temp_free_i32(carry_32
);
567 #if TARGET_LONG_BITS == 64
568 tcg_temp_free(carry
);
571 #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
575 tcg_gen_mov_tl(cpu_cc_src
, src1
);
576 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
577 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
578 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUBX
);
579 dc
->cc_op
= CC_OP_SUBX
;
583 static inline void gen_op_mulscc(TCGv dst
, TCGv src1
, TCGv src2
)
587 r_temp
= tcg_temp_new();
593 zero
= tcg_const_tl(0);
594 tcg_gen_andi_tl(cpu_cc_src
, src1
, 0xffffffff);
595 tcg_gen_andi_tl(r_temp
, cpu_y
, 0x1);
596 tcg_gen_andi_tl(cpu_cc_src2
, src2
, 0xffffffff);
597 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_cc_src2
, r_temp
, zero
,
602 // env->y = (b2 << 31) | (env->y >> 1);
603 tcg_gen_andi_tl(r_temp
, cpu_cc_src
, 0x1);
604 tcg_gen_shli_tl(r_temp
, r_temp
, 31);
605 tcg_gen_shri_tl(cpu_tmp0
, cpu_y
, 1);
606 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0x7fffffff);
607 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, r_temp
);
608 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
611 gen_mov_reg_N(cpu_tmp0
, cpu_psr
);
612 gen_mov_reg_V(r_temp
, cpu_psr
);
613 tcg_gen_xor_tl(cpu_tmp0
, cpu_tmp0
, r_temp
);
614 tcg_temp_free(r_temp
);
616 // T0 = (b1 << 31) | (T0 >> 1);
618 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, 31);
619 tcg_gen_shri_tl(cpu_cc_src
, cpu_cc_src
, 1);
620 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
622 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
624 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
627 static inline void gen_op_multiply(TCGv dst
, TCGv src1
, TCGv src2
, int sign_ext
)
629 TCGv_i32 r_src1
, r_src2
;
630 TCGv_i64 r_temp
, r_temp2
;
632 r_src1
= tcg_temp_new_i32();
633 r_src2
= tcg_temp_new_i32();
635 tcg_gen_trunc_tl_i32(r_src1
, src1
);
636 tcg_gen_trunc_tl_i32(r_src2
, src2
);
638 r_temp
= tcg_temp_new_i64();
639 r_temp2
= tcg_temp_new_i64();
642 tcg_gen_ext_i32_i64(r_temp
, r_src2
);
643 tcg_gen_ext_i32_i64(r_temp2
, r_src1
);
645 tcg_gen_extu_i32_i64(r_temp
, r_src2
);
646 tcg_gen_extu_i32_i64(r_temp2
, r_src1
);
649 tcg_gen_mul_i64(r_temp2
, r_temp
, r_temp2
);
651 tcg_gen_shri_i64(r_temp
, r_temp2
, 32);
652 tcg_gen_trunc_i64_tl(cpu_tmp0
, r_temp
);
653 tcg_temp_free_i64(r_temp
);
654 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
656 tcg_gen_trunc_i64_tl(dst
, r_temp2
);
658 tcg_temp_free_i64(r_temp2
);
660 tcg_temp_free_i32(r_src1
);
661 tcg_temp_free_i32(r_src2
);
664 static inline void gen_op_umul(TCGv dst
, TCGv src1
, TCGv src2
)
666 /* zero-extend truncated operands before multiplication */
667 gen_op_multiply(dst
, src1
, src2
, 0);
670 static inline void gen_op_smul(TCGv dst
, TCGv src1
, TCGv src2
)
672 /* sign-extend truncated operands before multiplication */
673 gen_op_multiply(dst
, src1
, src2
, 1);
677 static inline void gen_op_eval_ba(TCGv dst
)
679 tcg_gen_movi_tl(dst
, 1);
683 static inline void gen_op_eval_be(TCGv dst
, TCGv_i32 src
)
685 gen_mov_reg_Z(dst
, src
);
689 static inline void gen_op_eval_ble(TCGv dst
, TCGv_i32 src
)
691 gen_mov_reg_N(cpu_tmp0
, src
);
692 gen_mov_reg_V(dst
, src
);
693 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
694 gen_mov_reg_Z(cpu_tmp0
, src
);
695 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
699 static inline void gen_op_eval_bl(TCGv dst
, TCGv_i32 src
)
701 gen_mov_reg_V(cpu_tmp0
, src
);
702 gen_mov_reg_N(dst
, src
);
703 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
707 static inline void gen_op_eval_bleu(TCGv dst
, TCGv_i32 src
)
709 gen_mov_reg_Z(cpu_tmp0
, src
);
710 gen_mov_reg_C(dst
, src
);
711 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
715 static inline void gen_op_eval_bcs(TCGv dst
, TCGv_i32 src
)
717 gen_mov_reg_C(dst
, src
);
721 static inline void gen_op_eval_bvs(TCGv dst
, TCGv_i32 src
)
723 gen_mov_reg_V(dst
, src
);
727 static inline void gen_op_eval_bn(TCGv dst
)
729 tcg_gen_movi_tl(dst
, 0);
733 static inline void gen_op_eval_bneg(TCGv dst
, TCGv_i32 src
)
735 gen_mov_reg_N(dst
, src
);
739 static inline void gen_op_eval_bne(TCGv dst
, TCGv_i32 src
)
741 gen_mov_reg_Z(dst
, src
);
742 tcg_gen_xori_tl(dst
, dst
, 0x1);
746 static inline void gen_op_eval_bg(TCGv dst
, TCGv_i32 src
)
748 gen_mov_reg_N(cpu_tmp0
, src
);
749 gen_mov_reg_V(dst
, src
);
750 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
751 gen_mov_reg_Z(cpu_tmp0
, src
);
752 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
753 tcg_gen_xori_tl(dst
, dst
, 0x1);
757 static inline void gen_op_eval_bge(TCGv dst
, TCGv_i32 src
)
759 gen_mov_reg_V(cpu_tmp0
, src
);
760 gen_mov_reg_N(dst
, src
);
761 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
762 tcg_gen_xori_tl(dst
, dst
, 0x1);
766 static inline void gen_op_eval_bgu(TCGv dst
, TCGv_i32 src
)
768 gen_mov_reg_Z(cpu_tmp0
, src
);
769 gen_mov_reg_C(dst
, src
);
770 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
771 tcg_gen_xori_tl(dst
, dst
, 0x1);
775 static inline void gen_op_eval_bcc(TCGv dst
, TCGv_i32 src
)
777 gen_mov_reg_C(dst
, src
);
778 tcg_gen_xori_tl(dst
, dst
, 0x1);
782 static inline void gen_op_eval_bpos(TCGv dst
, TCGv_i32 src
)
784 gen_mov_reg_N(dst
, src
);
785 tcg_gen_xori_tl(dst
, dst
, 0x1);
789 static inline void gen_op_eval_bvc(TCGv dst
, TCGv_i32 src
)
791 gen_mov_reg_V(dst
, src
);
792 tcg_gen_xori_tl(dst
, dst
, 0x1);
796 FPSR bit field FCC1 | FCC0:
802 static inline void gen_mov_reg_FCC0(TCGv reg
, TCGv src
,
803 unsigned int fcc_offset
)
805 tcg_gen_shri_tl(reg
, src
, FSR_FCC0_SHIFT
+ fcc_offset
);
806 tcg_gen_andi_tl(reg
, reg
, 0x1);
809 static inline void gen_mov_reg_FCC1(TCGv reg
, TCGv src
,
810 unsigned int fcc_offset
)
812 tcg_gen_shri_tl(reg
, src
, FSR_FCC1_SHIFT
+ fcc_offset
);
813 tcg_gen_andi_tl(reg
, reg
, 0x1);
817 static inline void gen_op_eval_fbne(TCGv dst
, TCGv src
,
818 unsigned int fcc_offset
)
820 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
821 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
822 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
825 // 1 or 2: FCC0 ^ FCC1
826 static inline void gen_op_eval_fblg(TCGv dst
, TCGv src
,
827 unsigned int fcc_offset
)
829 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
830 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
831 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
835 static inline void gen_op_eval_fbul(TCGv dst
, TCGv src
,
836 unsigned int fcc_offset
)
838 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
842 static inline void gen_op_eval_fbl(TCGv dst
, TCGv src
,
843 unsigned int fcc_offset
)
845 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
846 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
847 tcg_gen_xori_tl(cpu_tmp0
, cpu_tmp0
, 0x1);
848 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
852 static inline void gen_op_eval_fbug(TCGv dst
, TCGv src
,
853 unsigned int fcc_offset
)
855 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
859 static inline void gen_op_eval_fbg(TCGv dst
, TCGv src
,
860 unsigned int fcc_offset
)
862 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
863 tcg_gen_xori_tl(dst
, dst
, 0x1);
864 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
865 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
869 static inline void gen_op_eval_fbu(TCGv dst
, TCGv src
,
870 unsigned int fcc_offset
)
872 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
873 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
874 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
878 static inline void gen_op_eval_fbe(TCGv dst
, TCGv src
,
879 unsigned int fcc_offset
)
881 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
882 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
883 tcg_gen_or_tl(dst
, dst
, cpu_tmp0
);
884 tcg_gen_xori_tl(dst
, dst
, 0x1);
887 // 0 or 3: !(FCC0 ^ FCC1)
888 static inline void gen_op_eval_fbue(TCGv dst
, TCGv src
,
889 unsigned int fcc_offset
)
891 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
892 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
893 tcg_gen_xor_tl(dst
, dst
, cpu_tmp0
);
894 tcg_gen_xori_tl(dst
, dst
, 0x1);
898 static inline void gen_op_eval_fbge(TCGv dst
, TCGv src
,
899 unsigned int fcc_offset
)
901 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
902 tcg_gen_xori_tl(dst
, dst
, 0x1);
905 // !1: !(FCC0 & !FCC1)
906 static inline void gen_op_eval_fbuge(TCGv dst
, TCGv src
,
907 unsigned int fcc_offset
)
909 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
910 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
911 tcg_gen_xori_tl(cpu_tmp0
, cpu_tmp0
, 0x1);
912 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
913 tcg_gen_xori_tl(dst
, dst
, 0x1);
917 static inline void gen_op_eval_fble(TCGv dst
, TCGv src
,
918 unsigned int fcc_offset
)
920 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
921 tcg_gen_xori_tl(dst
, dst
, 0x1);
924 // !2: !(!FCC0 & FCC1)
925 static inline void gen_op_eval_fbule(TCGv dst
, TCGv src
,
926 unsigned int fcc_offset
)
928 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
929 tcg_gen_xori_tl(dst
, dst
, 0x1);
930 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
931 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
932 tcg_gen_xori_tl(dst
, dst
, 0x1);
935 // !3: !(FCC0 & FCC1)
936 static inline void gen_op_eval_fbo(TCGv dst
, TCGv src
,
937 unsigned int fcc_offset
)
939 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
940 gen_mov_reg_FCC1(cpu_tmp0
, src
, fcc_offset
);
941 tcg_gen_and_tl(dst
, dst
, cpu_tmp0
);
942 tcg_gen_xori_tl(dst
, dst
, 0x1);
945 static inline void gen_branch2(DisasContext
*dc
, target_ulong pc1
,
946 target_ulong pc2
, TCGv r_cond
)
950 l1
= gen_new_label();
952 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
954 gen_goto_tb(dc
, 0, pc1
, pc1
+ 4);
957 gen_goto_tb(dc
, 1, pc2
, pc2
+ 4);
960 static inline void gen_branch_a(DisasContext
*dc
, target_ulong pc1
,
961 target_ulong pc2
, TCGv r_cond
)
965 l1
= gen_new_label();
967 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
969 gen_goto_tb(dc
, 0, pc2
, pc1
);
972 gen_goto_tb(dc
, 1, pc2
+ 4, pc2
+ 8);
975 static inline void gen_generic_branch(DisasContext
*dc
)
977 TCGv npc0
= tcg_const_tl(dc
->jump_pc
[0]);
978 TCGv npc1
= tcg_const_tl(dc
->jump_pc
[1]);
979 TCGv zero
= tcg_const_tl(0);
981 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_npc
, cpu_cond
, zero
, npc0
, npc1
);
988 /* call this function before using the condition register as it may
989 have been set for a jump */
990 static inline void flush_cond(DisasContext
*dc
)
992 if (dc
->npc
== JUMP_PC
) {
993 gen_generic_branch(dc
);
994 dc
->npc
= DYNAMIC_PC
;
998 static inline void save_npc(DisasContext
*dc
)
1000 if (dc
->npc
== JUMP_PC
) {
1001 gen_generic_branch(dc
);
1002 dc
->npc
= DYNAMIC_PC
;
1003 } else if (dc
->npc
!= DYNAMIC_PC
) {
1004 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
1008 static inline void save_state(DisasContext
*dc
)
1010 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1011 /* flush pending conditional evaluations before exposing cpu state */
1012 if (dc
->cc_op
!= CC_OP_FLAGS
) {
1013 dc
->cc_op
= CC_OP_FLAGS
;
1014 gen_helper_compute_psr(cpu_env
);
1019 static inline void gen_mov_pc_npc(DisasContext
*dc
)
1021 if (dc
->npc
== JUMP_PC
) {
1022 gen_generic_branch(dc
);
1023 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1024 dc
->pc
= DYNAMIC_PC
;
1025 } else if (dc
->npc
== DYNAMIC_PC
) {
1026 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1027 dc
->pc
= DYNAMIC_PC
;
1033 static inline void gen_op_next_insn(void)
1035 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1036 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
1039 static void free_compare(DisasCompare
*cmp
)
1042 tcg_temp_free(cmp
->c1
);
1045 tcg_temp_free(cmp
->c2
);
1049 static void gen_compare(DisasCompare
*cmp
, bool xcc
, unsigned int cond
,
1052 static int subcc_cond
[16] = {
1068 -1, /* no overflow */
1071 static int logic_cond
[16] = {
1073 TCG_COND_EQ
, /* eq: Z */
1074 TCG_COND_LE
, /* le: Z | (N ^ V) -> Z | N */
1075 TCG_COND_LT
, /* lt: N ^ V -> N */
1076 TCG_COND_EQ
, /* leu: C | Z -> Z */
1077 TCG_COND_NEVER
, /* ltu: C -> 0 */
1078 TCG_COND_LT
, /* neg: N */
1079 TCG_COND_NEVER
, /* vs: V -> 0 */
1081 TCG_COND_NE
, /* ne: !Z */
1082 TCG_COND_GT
, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1083 TCG_COND_GE
, /* ge: !(N ^ V) -> !N */
1084 TCG_COND_NE
, /* gtu: !(C | Z) -> !Z */
1085 TCG_COND_ALWAYS
, /* geu: !C -> 1 */
1086 TCG_COND_GE
, /* pos: !N */
1087 TCG_COND_ALWAYS
, /* vc: !V -> 1 */
1093 #ifdef TARGET_SPARC64
1103 switch (dc
->cc_op
) {
1105 cmp
->cond
= logic_cond
[cond
];
1107 cmp
->is_bool
= false;
1109 cmp
->c2
= tcg_const_tl(0);
1110 #ifdef TARGET_SPARC64
1113 cmp
->c1
= tcg_temp_new();
1114 tcg_gen_ext32s_tl(cmp
->c1
, cpu_cc_dst
);
1119 cmp
->c1
= cpu_cc_dst
;
1126 cmp
->cond
= (cond
== 6 ? TCG_COND_LT
: TCG_COND_GE
);
1127 goto do_compare_dst_0
;
1129 case 7: /* overflow */
1130 case 15: /* !overflow */
1134 cmp
->cond
= subcc_cond
[cond
];
1135 cmp
->is_bool
= false;
1136 #ifdef TARGET_SPARC64
1138 /* Note that sign-extension works for unsigned compares as
1139 long as both operands are sign-extended. */
1140 cmp
->g1
= cmp
->g2
= false;
1141 cmp
->c1
= tcg_temp_new();
1142 cmp
->c2
= tcg_temp_new();
1143 tcg_gen_ext32s_tl(cmp
->c1
, cpu_cc_src
);
1144 tcg_gen_ext32s_tl(cmp
->c2
, cpu_cc_src2
);
1148 cmp
->g1
= cmp
->g2
= true;
1149 cmp
->c1
= cpu_cc_src
;
1150 cmp
->c2
= cpu_cc_src2
;
1157 gen_helper_compute_psr(cpu_env
);
1158 dc
->cc_op
= CC_OP_FLAGS
;
1162 /* We're going to generate a boolean result. */
1163 cmp
->cond
= TCG_COND_NE
;
1164 cmp
->is_bool
= true;
1165 cmp
->g1
= cmp
->g2
= false;
1166 cmp
->c1
= r_dst
= tcg_temp_new();
1167 cmp
->c2
= tcg_const_tl(0);
1171 gen_op_eval_bn(r_dst
);
1174 gen_op_eval_be(r_dst
, r_src
);
1177 gen_op_eval_ble(r_dst
, r_src
);
1180 gen_op_eval_bl(r_dst
, r_src
);
1183 gen_op_eval_bleu(r_dst
, r_src
);
1186 gen_op_eval_bcs(r_dst
, r_src
);
1189 gen_op_eval_bneg(r_dst
, r_src
);
1192 gen_op_eval_bvs(r_dst
, r_src
);
1195 gen_op_eval_ba(r_dst
);
1198 gen_op_eval_bne(r_dst
, r_src
);
1201 gen_op_eval_bg(r_dst
, r_src
);
1204 gen_op_eval_bge(r_dst
, r_src
);
1207 gen_op_eval_bgu(r_dst
, r_src
);
1210 gen_op_eval_bcc(r_dst
, r_src
);
1213 gen_op_eval_bpos(r_dst
, r_src
);
1216 gen_op_eval_bvc(r_dst
, r_src
);
1223 static void gen_fcompare(DisasCompare
*cmp
, unsigned int cc
, unsigned int cond
)
1225 unsigned int offset
;
1228 /* For now we still generate a straight boolean result. */
1229 cmp
->cond
= TCG_COND_NE
;
1230 cmp
->is_bool
= true;
1231 cmp
->g1
= cmp
->g2
= false;
1232 cmp
->c1
= r_dst
= tcg_temp_new();
1233 cmp
->c2
= tcg_const_tl(0);
1253 gen_op_eval_bn(r_dst
);
1256 gen_op_eval_fbne(r_dst
, cpu_fsr
, offset
);
1259 gen_op_eval_fblg(r_dst
, cpu_fsr
, offset
);
1262 gen_op_eval_fbul(r_dst
, cpu_fsr
, offset
);
1265 gen_op_eval_fbl(r_dst
, cpu_fsr
, offset
);
1268 gen_op_eval_fbug(r_dst
, cpu_fsr
, offset
);
1271 gen_op_eval_fbg(r_dst
, cpu_fsr
, offset
);
1274 gen_op_eval_fbu(r_dst
, cpu_fsr
, offset
);
1277 gen_op_eval_ba(r_dst
);
1280 gen_op_eval_fbe(r_dst
, cpu_fsr
, offset
);
1283 gen_op_eval_fbue(r_dst
, cpu_fsr
, offset
);
1286 gen_op_eval_fbge(r_dst
, cpu_fsr
, offset
);
1289 gen_op_eval_fbuge(r_dst
, cpu_fsr
, offset
);
1292 gen_op_eval_fble(r_dst
, cpu_fsr
, offset
);
1295 gen_op_eval_fbule(r_dst
, cpu_fsr
, offset
);
1298 gen_op_eval_fbo(r_dst
, cpu_fsr
, offset
);
1303 static void gen_cond(TCGv r_dst
, unsigned int cc
, unsigned int cond
,
1307 gen_compare(&cmp
, cc
, cond
, dc
);
1309 /* The interface is to return a boolean in r_dst. */
1311 tcg_gen_mov_tl(r_dst
, cmp
.c1
);
1313 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1319 static void gen_fcond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1322 gen_fcompare(&cmp
, cc
, cond
);
1324 /* The interface is to return a boolean in r_dst. */
1326 tcg_gen_mov_tl(r_dst
, cmp
.c1
);
1328 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1334 #ifdef TARGET_SPARC64
1336 static const int gen_tcg_cond_reg
[8] = {
1347 static void gen_compare_reg(DisasCompare
*cmp
, int cond
, TCGv r_src
)
1349 cmp
->cond
= tcg_invert_cond(gen_tcg_cond_reg
[cond
]);
1350 cmp
->is_bool
= false;
1354 cmp
->c2
= tcg_const_tl(0);
1357 static inline void gen_cond_reg(TCGv r_dst
, int cond
, TCGv r_src
)
1360 gen_compare_reg(&cmp
, cond
, r_src
);
1362 /* The interface is to return a boolean in r_dst. */
1363 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1369 static void do_branch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
)
1371 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1372 target_ulong target
= dc
->pc
+ offset
;
1374 #ifdef TARGET_SPARC64
1375 if (unlikely(AM_CHECK(dc
))) {
1376 target
&= 0xffffffffULL
;
1380 /* unconditional not taken */
1382 dc
->pc
= dc
->npc
+ 4;
1383 dc
->npc
= dc
->pc
+ 4;
1386 dc
->npc
= dc
->pc
+ 4;
1388 } else if (cond
== 0x8) {
1389 /* unconditional taken */
1392 dc
->npc
= dc
->pc
+ 4;
1396 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1400 gen_cond(cpu_cond
, cc
, cond
, dc
);
1402 gen_branch_a(dc
, target
, dc
->npc
, cpu_cond
);
1406 dc
->jump_pc
[0] = target
;
1407 if (unlikely(dc
->npc
== DYNAMIC_PC
)) {
1408 dc
->jump_pc
[1] = DYNAMIC_PC
;
1409 tcg_gen_addi_tl(cpu_pc
, cpu_npc
, 4);
1411 dc
->jump_pc
[1] = dc
->npc
+ 4;
1418 static void do_fbranch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
)
1420 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1421 target_ulong target
= dc
->pc
+ offset
;
1423 #ifdef TARGET_SPARC64
1424 if (unlikely(AM_CHECK(dc
))) {
1425 target
&= 0xffffffffULL
;
1429 /* unconditional not taken */
1431 dc
->pc
= dc
->npc
+ 4;
1432 dc
->npc
= dc
->pc
+ 4;
1435 dc
->npc
= dc
->pc
+ 4;
1437 } else if (cond
== 0x8) {
1438 /* unconditional taken */
1441 dc
->npc
= dc
->pc
+ 4;
1445 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1449 gen_fcond(cpu_cond
, cc
, cond
);
1451 gen_branch_a(dc
, target
, dc
->npc
, cpu_cond
);
1455 dc
->jump_pc
[0] = target
;
1456 if (unlikely(dc
->npc
== DYNAMIC_PC
)) {
1457 dc
->jump_pc
[1] = DYNAMIC_PC
;
1458 tcg_gen_addi_tl(cpu_pc
, cpu_npc
, 4);
1460 dc
->jump_pc
[1] = dc
->npc
+ 4;
1467 #ifdef TARGET_SPARC64
1468 static void do_branch_reg(DisasContext
*dc
, int32_t offset
, uint32_t insn
,
1471 unsigned int cond
= GET_FIELD_SP(insn
, 25, 27), a
= (insn
& (1 << 29));
1472 target_ulong target
= dc
->pc
+ offset
;
1474 if (unlikely(AM_CHECK(dc
))) {
1475 target
&= 0xffffffffULL
;
1478 gen_cond_reg(cpu_cond
, cond
, r_reg
);
1480 gen_branch_a(dc
, target
, dc
->npc
, cpu_cond
);
1484 dc
->jump_pc
[0] = target
;
1485 if (unlikely(dc
->npc
== DYNAMIC_PC
)) {
1486 dc
->jump_pc
[1] = DYNAMIC_PC
;
1487 tcg_gen_addi_tl(cpu_pc
, cpu_npc
, 4);
1489 dc
->jump_pc
[1] = dc
->npc
+ 4;
1495 static inline void gen_op_fcmps(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1499 gen_helper_fcmps(cpu_env
, r_rs1
, r_rs2
);
1502 gen_helper_fcmps_fcc1(cpu_env
, r_rs1
, r_rs2
);
1505 gen_helper_fcmps_fcc2(cpu_env
, r_rs1
, r_rs2
);
1508 gen_helper_fcmps_fcc3(cpu_env
, r_rs1
, r_rs2
);
1513 static inline void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1517 gen_helper_fcmpd(cpu_env
, r_rs1
, r_rs2
);
1520 gen_helper_fcmpd_fcc1(cpu_env
, r_rs1
, r_rs2
);
1523 gen_helper_fcmpd_fcc2(cpu_env
, r_rs1
, r_rs2
);
1526 gen_helper_fcmpd_fcc3(cpu_env
, r_rs1
, r_rs2
);
1531 static inline void gen_op_fcmpq(int fccno
)
1535 gen_helper_fcmpq(cpu_env
);
1538 gen_helper_fcmpq_fcc1(cpu_env
);
1541 gen_helper_fcmpq_fcc2(cpu_env
);
1544 gen_helper_fcmpq_fcc3(cpu_env
);
1549 static inline void gen_op_fcmpes(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1553 gen_helper_fcmpes(cpu_env
, r_rs1
, r_rs2
);
1556 gen_helper_fcmpes_fcc1(cpu_env
, r_rs1
, r_rs2
);
1559 gen_helper_fcmpes_fcc2(cpu_env
, r_rs1
, r_rs2
);
1562 gen_helper_fcmpes_fcc3(cpu_env
, r_rs1
, r_rs2
);
1567 static inline void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1571 gen_helper_fcmped(cpu_env
, r_rs1
, r_rs2
);
1574 gen_helper_fcmped_fcc1(cpu_env
, r_rs1
, r_rs2
);
1577 gen_helper_fcmped_fcc2(cpu_env
, r_rs1
, r_rs2
);
1580 gen_helper_fcmped_fcc3(cpu_env
, r_rs1
, r_rs2
);
1585 static inline void gen_op_fcmpeq(int fccno
)
1589 gen_helper_fcmpeq(cpu_env
);
1592 gen_helper_fcmpeq_fcc1(cpu_env
);
1595 gen_helper_fcmpeq_fcc2(cpu_env
);
1598 gen_helper_fcmpeq_fcc3(cpu_env
);
1605 static inline void gen_op_fcmps(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1607 gen_helper_fcmps(cpu_env
, r_rs1
, r_rs2
);
1610 static inline void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1612 gen_helper_fcmpd(cpu_env
, r_rs1
, r_rs2
);
1615 static inline void gen_op_fcmpq(int fccno
)
1617 gen_helper_fcmpq(cpu_env
);
1620 static inline void gen_op_fcmpes(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1622 gen_helper_fcmpes(cpu_env
, r_rs1
, r_rs2
);
1625 static inline void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1627 gen_helper_fcmped(cpu_env
, r_rs1
, r_rs2
);
1630 static inline void gen_op_fcmpeq(int fccno
)
1632 gen_helper_fcmpeq(cpu_env
);
1636 static inline void gen_op_fpexception_im(int fsr_flags
)
1640 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_NMASK
);
1641 tcg_gen_ori_tl(cpu_fsr
, cpu_fsr
, fsr_flags
);
1642 r_const
= tcg_const_i32(TT_FP_EXCP
);
1643 gen_helper_raise_exception(cpu_env
, r_const
);
1644 tcg_temp_free_i32(r_const
);
1647 static int gen_trap_ifnofpu(DisasContext
*dc
)
1649 #if !defined(CONFIG_USER_ONLY)
1650 if (!dc
->fpu_enabled
) {
1654 r_const
= tcg_const_i32(TT_NFPU_INSN
);
1655 gen_helper_raise_exception(cpu_env
, r_const
);
1656 tcg_temp_free_i32(r_const
);
1664 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1666 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_CEXC_NMASK
);
1669 static inline void gen_fop_FF(DisasContext
*dc
, int rd
, int rs
,
1670 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i32
))
1674 src
= gen_load_fpr_F(dc
, rs
);
1675 dst
= gen_dest_fpr_F();
1677 gen(dst
, cpu_env
, src
);
1679 gen_store_fpr_F(dc
, rd
, dst
);
1682 static inline void gen_ne_fop_FF(DisasContext
*dc
, int rd
, int rs
,
1683 void (*gen
)(TCGv_i32
, TCGv_i32
))
1687 src
= gen_load_fpr_F(dc
, rs
);
1688 dst
= gen_dest_fpr_F();
1692 gen_store_fpr_F(dc
, rd
, dst
);
1695 static inline void gen_fop_FFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1696 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
))
1698 TCGv_i32 dst
, src1
, src2
;
1700 src1
= gen_load_fpr_F(dc
, rs1
);
1701 src2
= gen_load_fpr_F(dc
, rs2
);
1702 dst
= gen_dest_fpr_F();
1704 gen(dst
, cpu_env
, src1
, src2
);
1706 gen_store_fpr_F(dc
, rd
, dst
);
1709 #ifdef TARGET_SPARC64
1710 static inline void gen_ne_fop_FFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1711 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
1713 TCGv_i32 dst
, src1
, src2
;
1715 src1
= gen_load_fpr_F(dc
, rs1
);
1716 src2
= gen_load_fpr_F(dc
, rs2
);
1717 dst
= gen_dest_fpr_F();
1719 gen(dst
, src1
, src2
);
1721 gen_store_fpr_F(dc
, rd
, dst
);
1725 static inline void gen_fop_DD(DisasContext
*dc
, int rd
, int rs
,
1726 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i64
))
1730 src
= gen_load_fpr_D(dc
, rs
);
1731 dst
= gen_dest_fpr_D();
1733 gen(dst
, cpu_env
, src
);
1735 gen_store_fpr_D(dc
, rd
, dst
);
1738 #ifdef TARGET_SPARC64
1739 static inline void gen_ne_fop_DD(DisasContext
*dc
, int rd
, int rs
,
1740 void (*gen
)(TCGv_i64
, TCGv_i64
))
1744 src
= gen_load_fpr_D(dc
, rs
);
1745 dst
= gen_dest_fpr_D();
1749 gen_store_fpr_D(dc
, rd
, dst
);
1753 static inline void gen_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1754 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
))
1756 TCGv_i64 dst
, src1
, src2
;
1758 src1
= gen_load_fpr_D(dc
, rs1
);
1759 src2
= gen_load_fpr_D(dc
, rs2
);
1760 dst
= gen_dest_fpr_D();
1762 gen(dst
, cpu_env
, src1
, src2
);
1764 gen_store_fpr_D(dc
, rd
, dst
);
1767 #ifdef TARGET_SPARC64
1768 static inline void gen_ne_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1769 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
))
1771 TCGv_i64 dst
, src1
, src2
;
1773 src1
= gen_load_fpr_D(dc
, rs1
);
1774 src2
= gen_load_fpr_D(dc
, rs2
);
1775 dst
= gen_dest_fpr_D();
1777 gen(dst
, src1
, src2
);
1779 gen_store_fpr_D(dc
, rd
, dst
);
1782 static inline void gen_gsr_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1783 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
1785 TCGv_i64 dst
, src1
, src2
;
1787 src1
= gen_load_fpr_D(dc
, rs1
);
1788 src2
= gen_load_fpr_D(dc
, rs2
);
1789 dst
= gen_dest_fpr_D();
1791 gen(dst
, cpu_gsr
, src1
, src2
);
1793 gen_store_fpr_D(dc
, rd
, dst
);
1796 static inline void gen_ne_fop_DDDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1797 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
1799 TCGv_i64 dst
, src0
, src1
, src2
;
1801 src1
= gen_load_fpr_D(dc
, rs1
);
1802 src2
= gen_load_fpr_D(dc
, rs2
);
1803 src0
= gen_load_fpr_D(dc
, rd
);
1804 dst
= gen_dest_fpr_D();
1806 gen(dst
, src0
, src1
, src2
);
1808 gen_store_fpr_D(dc
, rd
, dst
);
1812 static inline void gen_fop_QQ(DisasContext
*dc
, int rd
, int rs
,
1813 void (*gen
)(TCGv_ptr
))
1815 gen_op_load_fpr_QT1(QFPREG(rs
));
1819 gen_op_store_QT0_fpr(QFPREG(rd
));
1820 gen_update_fprs_dirty(QFPREG(rd
));
1823 #ifdef TARGET_SPARC64
1824 static inline void gen_ne_fop_QQ(DisasContext
*dc
, int rd
, int rs
,
1825 void (*gen
)(TCGv_ptr
))
1827 gen_op_load_fpr_QT1(QFPREG(rs
));
1831 gen_op_store_QT0_fpr(QFPREG(rd
));
1832 gen_update_fprs_dirty(QFPREG(rd
));
1836 static inline void gen_fop_QQQ(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1837 void (*gen
)(TCGv_ptr
))
1839 gen_op_load_fpr_QT0(QFPREG(rs1
));
1840 gen_op_load_fpr_QT1(QFPREG(rs2
));
1844 gen_op_store_QT0_fpr(QFPREG(rd
));
1845 gen_update_fprs_dirty(QFPREG(rd
));
1848 static inline void gen_fop_DFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1849 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
, TCGv_i32
))
1852 TCGv_i32 src1
, src2
;
1854 src1
= gen_load_fpr_F(dc
, rs1
);
1855 src2
= gen_load_fpr_F(dc
, rs2
);
1856 dst
= gen_dest_fpr_D();
1858 gen(dst
, cpu_env
, src1
, src2
);
1860 gen_store_fpr_D(dc
, rd
, dst
);
1863 static inline void gen_fop_QDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1864 void (*gen
)(TCGv_ptr
, TCGv_i64
, TCGv_i64
))
1866 TCGv_i64 src1
, src2
;
1868 src1
= gen_load_fpr_D(dc
, rs1
);
1869 src2
= gen_load_fpr_D(dc
, rs2
);
1871 gen(cpu_env
, src1
, src2
);
1873 gen_op_store_QT0_fpr(QFPREG(rd
));
1874 gen_update_fprs_dirty(QFPREG(rd
));
1877 #ifdef TARGET_SPARC64
1878 static inline void gen_fop_DF(DisasContext
*dc
, int rd
, int rs
,
1879 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
))
1884 src
= gen_load_fpr_F(dc
, rs
);
1885 dst
= gen_dest_fpr_D();
1887 gen(dst
, cpu_env
, src
);
1889 gen_store_fpr_D(dc
, rd
, dst
);
1893 static inline void gen_ne_fop_DF(DisasContext
*dc
, int rd
, int rs
,
1894 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
))
1899 src
= gen_load_fpr_F(dc
, rs
);
1900 dst
= gen_dest_fpr_D();
1902 gen(dst
, cpu_env
, src
);
1904 gen_store_fpr_D(dc
, rd
, dst
);
1907 static inline void gen_fop_FD(DisasContext
*dc
, int rd
, int rs
,
1908 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i64
))
1913 src
= gen_load_fpr_D(dc
, rs
);
1914 dst
= gen_dest_fpr_F();
1916 gen(dst
, cpu_env
, src
);
1918 gen_store_fpr_F(dc
, rd
, dst
);
1921 static inline void gen_fop_FQ(DisasContext
*dc
, int rd
, int rs
,
1922 void (*gen
)(TCGv_i32
, TCGv_ptr
))
1926 gen_op_load_fpr_QT1(QFPREG(rs
));
1927 dst
= gen_dest_fpr_F();
1931 gen_store_fpr_F(dc
, rd
, dst
);
1934 static inline void gen_fop_DQ(DisasContext
*dc
, int rd
, int rs
,
1935 void (*gen
)(TCGv_i64
, TCGv_ptr
))
1939 gen_op_load_fpr_QT1(QFPREG(rs
));
1940 dst
= gen_dest_fpr_D();
1944 gen_store_fpr_D(dc
, rd
, dst
);
1947 static inline void gen_ne_fop_QF(DisasContext
*dc
, int rd
, int rs
,
1948 void (*gen
)(TCGv_ptr
, TCGv_i32
))
1952 src
= gen_load_fpr_F(dc
, rs
);
1956 gen_op_store_QT0_fpr(QFPREG(rd
));
1957 gen_update_fprs_dirty(QFPREG(rd
));
1960 static inline void gen_ne_fop_QD(DisasContext
*dc
, int rd
, int rs
,
1961 void (*gen
)(TCGv_ptr
, TCGv_i64
))
1965 src
= gen_load_fpr_D(dc
, rs
);
1969 gen_op_store_QT0_fpr(QFPREG(rd
));
1970 gen_update_fprs_dirty(QFPREG(rd
));
1974 #ifdef TARGET_SPARC64
1975 static inline TCGv_i32
gen_get_asi(int insn
, TCGv r_addr
)
1981 r_asi
= tcg_temp_new_i32();
1982 tcg_gen_mov_i32(r_asi
, cpu_asi
);
1984 asi
= GET_FIELD(insn
, 19, 26);
1985 r_asi
= tcg_const_i32(asi
);
1990 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
1993 TCGv_i32 r_asi
, r_size
, r_sign
;
1995 r_asi
= gen_get_asi(insn
, addr
);
1996 r_size
= tcg_const_i32(size
);
1997 r_sign
= tcg_const_i32(sign
);
1998 gen_helper_ld_asi(dst
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
1999 tcg_temp_free_i32(r_sign
);
2000 tcg_temp_free_i32(r_size
);
2001 tcg_temp_free_i32(r_asi
);
2004 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
2006 TCGv_i32 r_asi
, r_size
;
2008 r_asi
= gen_get_asi(insn
, addr
);
2009 r_size
= tcg_const_i32(size
);
2010 gen_helper_st_asi(cpu_env
, addr
, src
, r_asi
, r_size
);
2011 tcg_temp_free_i32(r_size
);
2012 tcg_temp_free_i32(r_asi
);
2015 static inline void gen_ldf_asi(TCGv addr
, int insn
, int size
, int rd
)
2017 TCGv_i32 r_asi
, r_size
, r_rd
;
2019 r_asi
= gen_get_asi(insn
, addr
);
2020 r_size
= tcg_const_i32(size
);
2021 r_rd
= tcg_const_i32(rd
);
2022 gen_helper_ldf_asi(cpu_env
, addr
, r_asi
, r_size
, r_rd
);
2023 tcg_temp_free_i32(r_rd
);
2024 tcg_temp_free_i32(r_size
);
2025 tcg_temp_free_i32(r_asi
);
2028 static inline void gen_stf_asi(TCGv addr
, int insn
, int size
, int rd
)
2030 TCGv_i32 r_asi
, r_size
, r_rd
;
2032 r_asi
= gen_get_asi(insn
, addr
);
2033 r_size
= tcg_const_i32(size
);
2034 r_rd
= tcg_const_i32(rd
);
2035 gen_helper_stf_asi(cpu_env
, addr
, r_asi
, r_size
, r_rd
);
2036 tcg_temp_free_i32(r_rd
);
2037 tcg_temp_free_i32(r_size
);
2038 tcg_temp_free_i32(r_asi
);
2041 static inline void gen_swap_asi(TCGv dst
, TCGv addr
, int insn
)
2043 TCGv_i32 r_asi
, r_size
, r_sign
;
2045 r_asi
= gen_get_asi(insn
, addr
);
2046 r_size
= tcg_const_i32(4);
2047 r_sign
= tcg_const_i32(0);
2048 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2049 tcg_temp_free_i32(r_sign
);
2050 gen_helper_st_asi(cpu_env
, addr
, dst
, r_asi
, r_size
);
2051 tcg_temp_free_i32(r_size
);
2052 tcg_temp_free_i32(r_asi
);
2053 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
2056 static inline void gen_ldda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
2058 TCGv_i32 r_asi
, r_rd
;
2060 r_asi
= gen_get_asi(insn
, addr
);
2061 r_rd
= tcg_const_i32(rd
);
2062 gen_helper_ldda_asi(cpu_env
, addr
, r_asi
, r_rd
);
2063 tcg_temp_free_i32(r_rd
);
2064 tcg_temp_free_i32(r_asi
);
2067 static inline void gen_stda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
2069 TCGv_i32 r_asi
, r_size
;
2071 gen_movl_reg_TN(rd
+ 1, cpu_tmp0
);
2072 tcg_gen_concat_tl_i64(cpu_tmp64
, cpu_tmp0
, hi
);
2073 r_asi
= gen_get_asi(insn
, addr
);
2074 r_size
= tcg_const_i32(8);
2075 gen_helper_st_asi(cpu_env
, addr
, cpu_tmp64
, r_asi
, r_size
);
2076 tcg_temp_free_i32(r_size
);
2077 tcg_temp_free_i32(r_asi
);
2080 static inline void gen_cas_asi(TCGv dst
, TCGv addr
, TCGv val2
, int insn
,
2086 r_val1
= tcg_temp_new();
2087 gen_movl_reg_TN(rd
, r_val1
);
2088 r_asi
= gen_get_asi(insn
, addr
);
2089 gen_helper_cas_asi(dst
, cpu_env
, addr
, r_val1
, val2
, r_asi
);
2090 tcg_temp_free_i32(r_asi
);
2091 tcg_temp_free(r_val1
);
2094 static inline void gen_casx_asi(TCGv dst
, TCGv addr
, TCGv val2
, int insn
,
2099 gen_movl_reg_TN(rd
, cpu_tmp64
);
2100 r_asi
= gen_get_asi(insn
, addr
);
2101 gen_helper_casx_asi(dst
, cpu_env
, addr
, cpu_tmp64
, val2
, r_asi
);
2102 tcg_temp_free_i32(r_asi
);
2105 #elif !defined(CONFIG_USER_ONLY)
2107 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
2110 TCGv_i32 r_asi
, r_size
, r_sign
;
2112 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2113 r_size
= tcg_const_i32(size
);
2114 r_sign
= tcg_const_i32(sign
);
2115 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2116 tcg_temp_free(r_sign
);
2117 tcg_temp_free(r_size
);
2118 tcg_temp_free(r_asi
);
2119 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
2122 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
2124 TCGv_i32 r_asi
, r_size
;
2126 tcg_gen_extu_tl_i64(cpu_tmp64
, src
);
2127 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2128 r_size
= tcg_const_i32(size
);
2129 gen_helper_st_asi(cpu_env
, addr
, cpu_tmp64
, r_asi
, r_size
);
2130 tcg_temp_free(r_size
);
2131 tcg_temp_free(r_asi
);
2134 static inline void gen_swap_asi(TCGv dst
, TCGv addr
, int insn
)
2136 TCGv_i32 r_asi
, r_size
, r_sign
;
2139 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2140 r_size
= tcg_const_i32(4);
2141 r_sign
= tcg_const_i32(0);
2142 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2143 tcg_temp_free(r_sign
);
2144 r_val
= tcg_temp_new_i64();
2145 tcg_gen_extu_tl_i64(r_val
, dst
);
2146 gen_helper_st_asi(cpu_env
, addr
, r_val
, r_asi
, r_size
);
2147 tcg_temp_free_i64(r_val
);
2148 tcg_temp_free(r_size
);
2149 tcg_temp_free(r_asi
);
2150 tcg_gen_trunc_i64_tl(dst
, cpu_tmp64
);
2153 static inline void gen_ldda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
2155 TCGv_i32 r_asi
, r_size
, r_sign
;
2157 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2158 r_size
= tcg_const_i32(8);
2159 r_sign
= tcg_const_i32(0);
2160 gen_helper_ld_asi(cpu_tmp64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2161 tcg_temp_free(r_sign
);
2162 tcg_temp_free(r_size
);
2163 tcg_temp_free(r_asi
);
2164 tcg_gen_trunc_i64_tl(cpu_tmp0
, cpu_tmp64
);
2165 gen_movl_TN_reg(rd
+ 1, cpu_tmp0
);
2166 tcg_gen_shri_i64(cpu_tmp64
, cpu_tmp64
, 32);
2167 tcg_gen_trunc_i64_tl(hi
, cpu_tmp64
);
2168 gen_movl_TN_reg(rd
, hi
);
2171 static inline void gen_stda_asi(TCGv hi
, TCGv addr
, int insn
, int rd
)
2173 TCGv_i32 r_asi
, r_size
;
2175 gen_movl_reg_TN(rd
+ 1, cpu_tmp0
);
2176 tcg_gen_concat_tl_i64(cpu_tmp64
, cpu_tmp0
, hi
);
2177 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2178 r_size
= tcg_const_i32(8);
2179 gen_helper_st_asi(cpu_env
, addr
, cpu_tmp64
, r_asi
, r_size
);
2180 tcg_temp_free(r_size
);
2181 tcg_temp_free(r_asi
);
2185 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2186 static inline void gen_ldstub_asi(TCGv dst
, TCGv addr
, int insn
)
2189 TCGv_i32 r_asi
, r_size
;
2191 gen_ld_asi(dst
, addr
, insn
, 1, 0);
2193 r_val
= tcg_const_i64(0xffULL
);
2194 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2195 r_size
= tcg_const_i32(1);
2196 gen_helper_st_asi(cpu_env
, addr
, r_val
, r_asi
, r_size
);
2197 tcg_temp_free_i32(r_size
);
2198 tcg_temp_free_i32(r_asi
);
2199 tcg_temp_free_i64(r_val
);
2203 static inline TCGv
get_src1(unsigned int insn
, TCGv def
)
2208 rs1
= GET_FIELD(insn
, 13, 17);
2210 tcg_gen_movi_tl(def
, 0);
2211 } else if (rs1
< 8) {
2212 r_rs1
= cpu_gregs
[rs1
];
2214 tcg_gen_ld_tl(def
, cpu_regwptr
, (rs1
- 8) * sizeof(target_ulong
));
2219 static inline TCGv
get_src2(unsigned int insn
, TCGv def
)
2223 if (IS_IMM
) { /* immediate */
2224 target_long simm
= GET_FIELDs(insn
, 19, 31);
2225 tcg_gen_movi_tl(def
, simm
);
2226 } else { /* register */
2227 unsigned int rs2
= GET_FIELD(insn
, 27, 31);
2229 tcg_gen_movi_tl(def
, 0);
2230 } else if (rs2
< 8) {
2231 r_rs2
= cpu_gregs
[rs2
];
2233 tcg_gen_ld_tl(def
, cpu_regwptr
, (rs2
- 8) * sizeof(target_ulong
));
2239 #ifdef TARGET_SPARC64
2240 static void gen_fmovs(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2242 TCGv_i32 c32
, zero
, dst
, s1
, s2
;
2244 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2245 or fold the comparison down to 32 bits and use movcond_i32. Choose
2247 c32
= tcg_temp_new_i32();
2249 tcg_gen_trunc_i64_i32(c32
, cmp
->c1
);
2251 TCGv_i64 c64
= tcg_temp_new_i64();
2252 tcg_gen_setcond_i64(cmp
->cond
, c64
, cmp
->c1
, cmp
->c2
);
2253 tcg_gen_trunc_i64_i32(c32
, c64
);
2254 tcg_temp_free_i64(c64
);
2257 s1
= gen_load_fpr_F(dc
, rs
);
2258 s2
= gen_load_fpr_F(dc
, rd
);
2259 dst
= gen_dest_fpr_F();
2260 zero
= tcg_const_i32(0);
2262 tcg_gen_movcond_i32(TCG_COND_NE
, dst
, c32
, zero
, s1
, s2
);
2264 tcg_temp_free_i32(c32
);
2265 tcg_temp_free_i32(zero
);
2266 gen_store_fpr_F(dc
, rd
, dst
);
2269 static void gen_fmovd(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2271 TCGv_i64 dst
= gen_dest_fpr_D();
2272 tcg_gen_movcond_i64(cmp
->cond
, dst
, cmp
->c1
, cmp
->c2
,
2273 gen_load_fpr_D(dc
, rs
),
2274 gen_load_fpr_D(dc
, rd
));
2275 gen_store_fpr_D(dc
, rd
, dst
);
2278 static void gen_fmovq(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2280 int qd
= QFPREG(rd
);
2281 int qs
= QFPREG(rs
);
2283 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2], cmp
->c1
, cmp
->c2
,
2284 cpu_fpr
[qs
/ 2], cpu_fpr
[qd
/ 2]);
2285 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2 + 1], cmp
->c1
, cmp
->c2
,
2286 cpu_fpr
[qs
/ 2 + 1], cpu_fpr
[qd
/ 2 + 1]);
2288 gen_update_fprs_dirty(qd
);
2291 static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr
, TCGv_ptr cpu_env
)
2293 TCGv_i32 r_tl
= tcg_temp_new_i32();
2295 /* load env->tl into r_tl */
2296 tcg_gen_ld_i32(r_tl
, cpu_env
, offsetof(CPUSPARCState
, tl
));
2298 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2299 tcg_gen_andi_i32(r_tl
, r_tl
, MAXTL_MASK
);
2301 /* calculate offset to current trap state from env->ts, reuse r_tl */
2302 tcg_gen_muli_i32(r_tl
, r_tl
, sizeof (trap_state
));
2303 tcg_gen_addi_ptr(r_tsptr
, cpu_env
, offsetof(CPUSPARCState
, ts
));
2305 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2307 TCGv_ptr r_tl_tmp
= tcg_temp_new_ptr();
2308 tcg_gen_ext_i32_ptr(r_tl_tmp
, r_tl
);
2309 tcg_gen_add_ptr(r_tsptr
, r_tsptr
, r_tl_tmp
);
2310 tcg_temp_free_ptr(r_tl_tmp
);
2313 tcg_temp_free_i32(r_tl
);
2316 static void gen_edge(DisasContext
*dc
, TCGv dst
, TCGv s1
, TCGv s2
,
2317 int width
, bool cc
, bool left
)
2319 TCGv lo1
, lo2
, t1
, t2
;
2320 uint64_t amask
, tabl
, tabr
;
2321 int shift
, imask
, omask
;
2324 tcg_gen_mov_tl(cpu_cc_src
, s1
);
2325 tcg_gen_mov_tl(cpu_cc_src2
, s2
);
2326 tcg_gen_sub_tl(cpu_cc_dst
, s1
, s2
);
2327 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
2328 dc
->cc_op
= CC_OP_SUB
;
2331 /* Theory of operation: there are two tables, left and right (not to
2332 be confused with the left and right versions of the opcode). These
2333 are indexed by the low 3 bits of the inputs. To make things "easy",
2334 these tables are loaded into two constants, TABL and TABR below.
2335 The operation index = (input & imask) << shift calculates the index
2336 into the constant, while val = (table >> index) & omask calculates
2337 the value we're looking for. */
2344 tabl
= 0x80c0e0f0f8fcfeffULL
;
2345 tabr
= 0xff7f3f1f0f070301ULL
;
2347 tabl
= 0x0103070f1f3f7fffULL
;
2348 tabr
= 0xfffefcf8f0e0c080ULL
;
2368 tabl
= (2 << 2) | 3;
2369 tabr
= (3 << 2) | 1;
2371 tabl
= (1 << 2) | 3;
2372 tabr
= (3 << 2) | 2;
2379 lo1
= tcg_temp_new();
2380 lo2
= tcg_temp_new();
2381 tcg_gen_andi_tl(lo1
, s1
, imask
);
2382 tcg_gen_andi_tl(lo2
, s2
, imask
);
2383 tcg_gen_shli_tl(lo1
, lo1
, shift
);
2384 tcg_gen_shli_tl(lo2
, lo2
, shift
);
2386 t1
= tcg_const_tl(tabl
);
2387 t2
= tcg_const_tl(tabr
);
2388 tcg_gen_shr_tl(lo1
, t1
, lo1
);
2389 tcg_gen_shr_tl(lo2
, t2
, lo2
);
2390 tcg_gen_andi_tl(dst
, lo1
, omask
);
2391 tcg_gen_andi_tl(lo2
, lo2
, omask
);
2395 amask
&= 0xffffffffULL
;
2397 tcg_gen_andi_tl(s1
, s1
, amask
);
2398 tcg_gen_andi_tl(s2
, s2
, amask
);
2400 /* We want to compute
2401 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2402 We've already done dst = lo1, so this reduces to
2403 dst &= (s1 == s2 ? -1 : lo2)
2408 tcg_gen_setcond_tl(TCG_COND_EQ
, t1
, s1
, s2
);
2409 tcg_gen_neg_tl(t1
, t1
);
2410 tcg_gen_or_tl(lo2
, lo2
, t1
);
2411 tcg_gen_and_tl(dst
, dst
, lo2
);
2419 static void gen_alignaddr(TCGv dst
, TCGv s1
, TCGv s2
, bool left
)
2421 TCGv tmp
= tcg_temp_new();
2423 tcg_gen_add_tl(tmp
, s1
, s2
);
2424 tcg_gen_andi_tl(dst
, tmp
, -8);
2426 tcg_gen_neg_tl(tmp
, tmp
);
2428 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, tmp
, 0, 3);
2433 static void gen_faligndata(TCGv dst
, TCGv gsr
, TCGv s1
, TCGv s2
)
2437 t1
= tcg_temp_new();
2438 t2
= tcg_temp_new();
2439 shift
= tcg_temp_new();
2441 tcg_gen_andi_tl(shift
, gsr
, 7);
2442 tcg_gen_shli_tl(shift
, shift
, 3);
2443 tcg_gen_shl_tl(t1
, s1
, shift
);
2445 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2446 shift of (up to 63) followed by a constant shift of 1. */
2447 tcg_gen_xori_tl(shift
, shift
, 63);
2448 tcg_gen_shr_tl(t2
, s2
, shift
);
2449 tcg_gen_shri_tl(t2
, t2
, 1);
2451 tcg_gen_or_tl(dst
, t1
, t2
);
2455 tcg_temp_free(shift
);
2459 #define CHECK_IU_FEATURE(dc, FEATURE) \
2460 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2462 #define CHECK_FPU_FEATURE(dc, FEATURE) \
2463 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2466 /* before an instruction, dc->pc must be static */
2467 static void disas_sparc_insn(DisasContext
* dc
, unsigned int insn
)
2469 unsigned int opc
, rs1
, rs2
, rd
;
2470 TCGv cpu_src1
, cpu_src2
, cpu_tmp1
, cpu_tmp2
;
2471 TCGv_i32 cpu_src1_32
, cpu_src2_32
, cpu_dst_32
;
2472 TCGv_i64 cpu_src1_64
, cpu_src2_64
, cpu_dst_64
;
2475 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2476 tcg_gen_debug_insn_start(dc
->pc
);
2479 opc
= GET_FIELD(insn
, 0, 1);
2481 rd
= GET_FIELD(insn
, 2, 6);
2483 cpu_tmp1
= cpu_src1
= tcg_temp_new();
2484 cpu_tmp2
= cpu_src2
= tcg_temp_new();
2487 case 0: /* branches/sethi */
2489 unsigned int xop
= GET_FIELD(insn
, 7, 9);
2492 #ifdef TARGET_SPARC64
2493 case 0x1: /* V9 BPcc */
2497 target
= GET_FIELD_SP(insn
, 0, 18);
2498 target
= sign_extend(target
, 19);
2500 cc
= GET_FIELD_SP(insn
, 20, 21);
2502 do_branch(dc
, target
, insn
, 0);
2504 do_branch(dc
, target
, insn
, 1);
2509 case 0x3: /* V9 BPr */
2511 target
= GET_FIELD_SP(insn
, 0, 13) |
2512 (GET_FIELD_SP(insn
, 20, 21) << 14);
2513 target
= sign_extend(target
, 16);
2515 cpu_src1
= get_src1(insn
, cpu_src1
);
2516 do_branch_reg(dc
, target
, insn
, cpu_src1
);
2519 case 0x5: /* V9 FBPcc */
2521 int cc
= GET_FIELD_SP(insn
, 20, 21);
2522 if (gen_trap_ifnofpu(dc
)) {
2525 target
= GET_FIELD_SP(insn
, 0, 18);
2526 target
= sign_extend(target
, 19);
2528 do_fbranch(dc
, target
, insn
, cc
);
2532 case 0x7: /* CBN+x */
2537 case 0x2: /* BN+x */
2539 target
= GET_FIELD(insn
, 10, 31);
2540 target
= sign_extend(target
, 22);
2542 do_branch(dc
, target
, insn
, 0);
2545 case 0x6: /* FBN+x */
2547 if (gen_trap_ifnofpu(dc
)) {
2550 target
= GET_FIELD(insn
, 10, 31);
2551 target
= sign_extend(target
, 22);
2553 do_fbranch(dc
, target
, insn
, 0);
2556 case 0x4: /* SETHI */
2558 uint32_t value
= GET_FIELD(insn
, 10, 31);
2561 r_const
= tcg_const_tl(value
<< 10);
2562 gen_movl_TN_reg(rd
, r_const
);
2563 tcg_temp_free(r_const
);
2566 case 0x0: /* UNIMPL */
2575 target_long target
= GET_FIELDs(insn
, 2, 31) << 2;
2578 r_const
= tcg_const_tl(dc
->pc
);
2579 gen_movl_TN_reg(15, r_const
);
2580 tcg_temp_free(r_const
);
2583 #ifdef TARGET_SPARC64
2584 if (unlikely(AM_CHECK(dc
))) {
2585 target
&= 0xffffffffULL
;
2591 case 2: /* FPU & Logical Operations */
2593 unsigned int xop
= GET_FIELD(insn
, 7, 12);
2594 if (xop
== 0x3a) { /* generate trap */
2595 int cond
= GET_FIELD(insn
, 3, 6);
2607 /* Conditional trap. */
2609 #ifdef TARGET_SPARC64
2611 int cc
= GET_FIELD_SP(insn
, 11, 12);
2613 gen_compare(&cmp
, 0, cond
, dc
);
2614 } else if (cc
== 2) {
2615 gen_compare(&cmp
, 1, cond
, dc
);
2620 gen_compare(&cmp
, 0, cond
, dc
);
2622 l1
= gen_new_label();
2623 tcg_gen_brcond_tl(tcg_invert_cond(cmp
.cond
),
2624 cmp
.c1
, cmp
.c2
, l1
);
2628 mask
= ((dc
->def
->features
& CPU_FEATURE_HYPV
) && supervisor(dc
)
2629 ? UA2005_HTRAP_MASK
: V8_TRAP_MASK
);
2631 /* Don't use the normal temporaries, as they may well have
2632 gone out of scope with the branch above. While we're
2633 doing that we might as well pre-truncate to 32-bit. */
2634 trap
= tcg_temp_new_i32();
2636 rs1
= GET_FIELD_SP(insn
, 14, 18);
2638 rs2
= GET_FIELD_SP(insn
, 0, 6);
2640 tcg_gen_movi_i32(trap
, (rs2
& mask
) + TT_TRAP
);
2641 /* Signal that the trap value is fully constant. */
2644 TCGv t1
= tcg_temp_new();
2645 gen_movl_reg_TN(rs1
, t1
);
2646 tcg_gen_trunc_tl_i32(trap
, t1
);
2648 tcg_gen_addi_i32(trap
, trap
, rs2
);
2651 TCGv t1
= tcg_temp_new();
2652 TCGv t2
= tcg_temp_new();
2653 rs2
= GET_FIELD_SP(insn
, 0, 4);
2654 gen_movl_reg_TN(rs1
, t1
);
2655 gen_movl_reg_TN(rs2
, t2
);
2656 tcg_gen_add_tl(t1
, t1
, t2
);
2657 tcg_gen_trunc_tl_i32(trap
, t1
);
2662 tcg_gen_andi_i32(trap
, trap
, mask
);
2663 tcg_gen_addi_i32(trap
, trap
, TT_TRAP
);
2666 gen_helper_raise_exception(cpu_env
, trap
);
2667 tcg_temp_free_i32(trap
);
2670 /* An unconditional trap ends the TB. */
2674 /* A conditional trap falls through to the next insn. */
2678 } else if (xop
== 0x28) {
2679 rs1
= GET_FIELD(insn
, 13, 17);
2682 #ifndef TARGET_SPARC64
2683 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2684 manual, rdy on the microSPARC
2686 case 0x0f: /* stbar in the SPARCv8 manual,
2687 rdy on the microSPARC II */
2688 case 0x10 ... 0x1f: /* implementation-dependent in the
2689 SPARCv8 manual, rdy on the
2692 if (rs1
== 0x11 && dc
->def
->features
& CPU_FEATURE_ASR17
) {
2695 /* Read Asr17 for a Leon3 monoprocessor */
2696 r_const
= tcg_const_tl((1 << 8)
2697 | (dc
->def
->nwindows
- 1));
2698 gen_movl_TN_reg(rd
, r_const
);
2699 tcg_temp_free(r_const
);
2703 gen_movl_TN_reg(rd
, cpu_y
);
2705 #ifdef TARGET_SPARC64
2706 case 0x2: /* V9 rdccr */
2707 gen_helper_compute_psr(cpu_env
);
2708 gen_helper_rdccr(cpu_dst
, cpu_env
);
2709 gen_movl_TN_reg(rd
, cpu_dst
);
2711 case 0x3: /* V9 rdasi */
2712 tcg_gen_ext_i32_tl(cpu_dst
, cpu_asi
);
2713 gen_movl_TN_reg(rd
, cpu_dst
);
2715 case 0x4: /* V9 rdtick */
2719 r_tickptr
= tcg_temp_new_ptr();
2720 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2721 offsetof(CPUSPARCState
, tick
));
2722 gen_helper_tick_get_count(cpu_dst
, r_tickptr
);
2723 tcg_temp_free_ptr(r_tickptr
);
2724 gen_movl_TN_reg(rd
, cpu_dst
);
2727 case 0x5: /* V9 rdpc */
2731 if (unlikely(AM_CHECK(dc
))) {
2732 r_const
= tcg_const_tl(dc
->pc
& 0xffffffffULL
);
2734 r_const
= tcg_const_tl(dc
->pc
);
2736 gen_movl_TN_reg(rd
, r_const
);
2737 tcg_temp_free(r_const
);
2740 case 0x6: /* V9 rdfprs */
2741 tcg_gen_ext_i32_tl(cpu_dst
, cpu_fprs
);
2742 gen_movl_TN_reg(rd
, cpu_dst
);
2744 case 0xf: /* V9 membar */
2745 break; /* no effect */
2746 case 0x13: /* Graphics Status */
2747 if (gen_trap_ifnofpu(dc
)) {
2750 gen_movl_TN_reg(rd
, cpu_gsr
);
2752 case 0x16: /* Softint */
2753 tcg_gen_ext_i32_tl(cpu_dst
, cpu_softint
);
2754 gen_movl_TN_reg(rd
, cpu_dst
);
2756 case 0x17: /* Tick compare */
2757 gen_movl_TN_reg(rd
, cpu_tick_cmpr
);
2759 case 0x18: /* System tick */
2763 r_tickptr
= tcg_temp_new_ptr();
2764 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2765 offsetof(CPUSPARCState
, stick
));
2766 gen_helper_tick_get_count(cpu_dst
, r_tickptr
);
2767 tcg_temp_free_ptr(r_tickptr
);
2768 gen_movl_TN_reg(rd
, cpu_dst
);
2771 case 0x19: /* System tick compare */
2772 gen_movl_TN_reg(rd
, cpu_stick_cmpr
);
2774 case 0x10: /* Performance Control */
2775 case 0x11: /* Performance Instrumentation Counter */
2776 case 0x12: /* Dispatch Control */
2777 case 0x14: /* Softint set, WO */
2778 case 0x15: /* Softint clear, WO */
2783 #if !defined(CONFIG_USER_ONLY)
2784 } else if (xop
== 0x29) { /* rdpsr / UA2005 rdhpr */
2785 #ifndef TARGET_SPARC64
2786 if (!supervisor(dc
))
2788 gen_helper_compute_psr(cpu_env
);
2789 dc
->cc_op
= CC_OP_FLAGS
;
2790 gen_helper_rdpsr(cpu_dst
, cpu_env
);
2792 CHECK_IU_FEATURE(dc
, HYPV
);
2793 if (!hypervisor(dc
))
2795 rs1
= GET_FIELD(insn
, 13, 17);
2798 // gen_op_rdhpstate();
2801 // gen_op_rdhtstate();
2804 tcg_gen_mov_tl(cpu_dst
, cpu_hintp
);
2807 tcg_gen_mov_tl(cpu_dst
, cpu_htba
);
2810 tcg_gen_mov_tl(cpu_dst
, cpu_hver
);
2812 case 31: // hstick_cmpr
2813 tcg_gen_mov_tl(cpu_dst
, cpu_hstick_cmpr
);
2819 gen_movl_TN_reg(rd
, cpu_dst
);
2821 } else if (xop
== 0x2a) { /* rdwim / V9 rdpr */
2822 if (!supervisor(dc
))
2824 #ifdef TARGET_SPARC64
2825 rs1
= GET_FIELD(insn
, 13, 17);
2831 r_tsptr
= tcg_temp_new_ptr();
2832 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2833 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2834 offsetof(trap_state
, tpc
));
2835 tcg_temp_free_ptr(r_tsptr
);
2842 r_tsptr
= tcg_temp_new_ptr();
2843 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2844 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2845 offsetof(trap_state
, tnpc
));
2846 tcg_temp_free_ptr(r_tsptr
);
2853 r_tsptr
= tcg_temp_new_ptr();
2854 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2855 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2856 offsetof(trap_state
, tstate
));
2857 tcg_temp_free_ptr(r_tsptr
);
2864 r_tsptr
= tcg_temp_new_ptr();
2865 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2866 tcg_gen_ld_i32(cpu_tmp32
, r_tsptr
,
2867 offsetof(trap_state
, tt
));
2868 tcg_temp_free_ptr(r_tsptr
);
2869 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2876 r_tickptr
= tcg_temp_new_ptr();
2877 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2878 offsetof(CPUSPARCState
, tick
));
2879 gen_helper_tick_get_count(cpu_tmp0
, r_tickptr
);
2880 gen_movl_TN_reg(rd
, cpu_tmp0
);
2881 tcg_temp_free_ptr(r_tickptr
);
2885 tcg_gen_mov_tl(cpu_tmp0
, cpu_tbr
);
2888 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2889 offsetof(CPUSPARCState
, pstate
));
2890 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2893 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2894 offsetof(CPUSPARCState
, tl
));
2895 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2898 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2899 offsetof(CPUSPARCState
, psrpil
));
2900 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2903 gen_helper_rdcwp(cpu_tmp0
, cpu_env
);
2906 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2907 offsetof(CPUSPARCState
, cansave
));
2908 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2910 case 11: // canrestore
2911 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2912 offsetof(CPUSPARCState
, canrestore
));
2913 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2915 case 12: // cleanwin
2916 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2917 offsetof(CPUSPARCState
, cleanwin
));
2918 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2920 case 13: // otherwin
2921 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2922 offsetof(CPUSPARCState
, otherwin
));
2923 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2926 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2927 offsetof(CPUSPARCState
, wstate
));
2928 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2930 case 16: // UA2005 gl
2931 CHECK_IU_FEATURE(dc
, GL
);
2932 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
,
2933 offsetof(CPUSPARCState
, gl
));
2934 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_tmp32
);
2936 case 26: // UA2005 strand status
2937 CHECK_IU_FEATURE(dc
, HYPV
);
2938 if (!hypervisor(dc
))
2940 tcg_gen_mov_tl(cpu_tmp0
, cpu_ssr
);
2943 tcg_gen_mov_tl(cpu_tmp0
, cpu_ver
);
2950 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_wim
);
2952 gen_movl_TN_reg(rd
, cpu_tmp0
);
2954 } else if (xop
== 0x2b) { /* rdtbr / V9 flushw */
2955 #ifdef TARGET_SPARC64
2957 gen_helper_flushw(cpu_env
);
2959 if (!supervisor(dc
))
2961 gen_movl_TN_reg(rd
, cpu_tbr
);
2965 } else if (xop
== 0x34) { /* FPU Operations */
2966 if (gen_trap_ifnofpu(dc
)) {
2969 gen_op_clear_ieee_excp_and_FTT();
2970 rs1
= GET_FIELD(insn
, 13, 17);
2971 rs2
= GET_FIELD(insn
, 27, 31);
2972 xop
= GET_FIELD(insn
, 18, 26);
2975 case 0x1: /* fmovs */
2976 cpu_src1_32
= gen_load_fpr_F(dc
, rs2
);
2977 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
2979 case 0x5: /* fnegs */
2980 gen_ne_fop_FF(dc
, rd
, rs2
, gen_helper_fnegs
);
2982 case 0x9: /* fabss */
2983 gen_ne_fop_FF(dc
, rd
, rs2
, gen_helper_fabss
);
2985 case 0x29: /* fsqrts */
2986 CHECK_FPU_FEATURE(dc
, FSQRT
);
2987 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fsqrts
);
2989 case 0x2a: /* fsqrtd */
2990 CHECK_FPU_FEATURE(dc
, FSQRT
);
2991 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fsqrtd
);
2993 case 0x2b: /* fsqrtq */
2994 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2995 gen_fop_QQ(dc
, rd
, rs2
, gen_helper_fsqrtq
);
2997 case 0x41: /* fadds */
2998 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fadds
);
3000 case 0x42: /* faddd */
3001 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_faddd
);
3003 case 0x43: /* faddq */
3004 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3005 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_faddq
);
3007 case 0x45: /* fsubs */
3008 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fsubs
);
3010 case 0x46: /* fsubd */
3011 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fsubd
);
3013 case 0x47: /* fsubq */
3014 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3015 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fsubq
);
3017 case 0x49: /* fmuls */
3018 CHECK_FPU_FEATURE(dc
, FMUL
);
3019 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fmuls
);
3021 case 0x4a: /* fmuld */
3022 CHECK_FPU_FEATURE(dc
, FMUL
);
3023 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld
);
3025 case 0x4b: /* fmulq */
3026 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3027 CHECK_FPU_FEATURE(dc
, FMUL
);
3028 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fmulq
);
3030 case 0x4d: /* fdivs */
3031 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fdivs
);
3033 case 0x4e: /* fdivd */
3034 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fdivd
);
3036 case 0x4f: /* fdivq */
3037 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3038 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fdivq
);
3040 case 0x69: /* fsmuld */
3041 CHECK_FPU_FEATURE(dc
, FSMULD
);
3042 gen_fop_DFF(dc
, rd
, rs1
, rs2
, gen_helper_fsmuld
);
3044 case 0x6e: /* fdmulq */
3045 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3046 gen_fop_QDD(dc
, rd
, rs1
, rs2
, gen_helper_fdmulq
);
3048 case 0xc4: /* fitos */
3049 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fitos
);
3051 case 0xc6: /* fdtos */
3052 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fdtos
);
3054 case 0xc7: /* fqtos */
3055 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3056 gen_fop_FQ(dc
, rd
, rs2
, gen_helper_fqtos
);
3058 case 0xc8: /* fitod */
3059 gen_ne_fop_DF(dc
, rd
, rs2
, gen_helper_fitod
);
3061 case 0xc9: /* fstod */
3062 gen_ne_fop_DF(dc
, rd
, rs2
, gen_helper_fstod
);
3064 case 0xcb: /* fqtod */
3065 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3066 gen_fop_DQ(dc
, rd
, rs2
, gen_helper_fqtod
);
3068 case 0xcc: /* fitoq */
3069 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3070 gen_ne_fop_QF(dc
, rd
, rs2
, gen_helper_fitoq
);
3072 case 0xcd: /* fstoq */
3073 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3074 gen_ne_fop_QF(dc
, rd
, rs2
, gen_helper_fstoq
);
3076 case 0xce: /* fdtoq */
3077 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3078 gen_ne_fop_QD(dc
, rd
, rs2
, gen_helper_fdtoq
);
3080 case 0xd1: /* fstoi */
3081 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fstoi
);
3083 case 0xd2: /* fdtoi */
3084 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fdtoi
);
3086 case 0xd3: /* fqtoi */
3087 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3088 gen_fop_FQ(dc
, rd
, rs2
, gen_helper_fqtoi
);
3090 #ifdef TARGET_SPARC64
3091 case 0x2: /* V9 fmovd */
3092 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
3093 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
3095 case 0x3: /* V9 fmovq */
3096 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3097 gen_move_Q(rd
, rs2
);
3099 case 0x6: /* V9 fnegd */
3100 gen_ne_fop_DD(dc
, rd
, rs2
, gen_helper_fnegd
);
3102 case 0x7: /* V9 fnegq */
3103 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3104 gen_ne_fop_QQ(dc
, rd
, rs2
, gen_helper_fnegq
);
3106 case 0xa: /* V9 fabsd */
3107 gen_ne_fop_DD(dc
, rd
, rs2
, gen_helper_fabsd
);
3109 case 0xb: /* V9 fabsq */
3110 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3111 gen_ne_fop_QQ(dc
, rd
, rs2
, gen_helper_fabsq
);
3113 case 0x81: /* V9 fstox */
3114 gen_fop_DF(dc
, rd
, rs2
, gen_helper_fstox
);
3116 case 0x82: /* V9 fdtox */
3117 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fdtox
);
3119 case 0x83: /* V9 fqtox */
3120 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3121 gen_fop_DQ(dc
, rd
, rs2
, gen_helper_fqtox
);
3123 case 0x84: /* V9 fxtos */
3124 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fxtos
);
3126 case 0x88: /* V9 fxtod */
3127 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fxtod
);
3129 case 0x8c: /* V9 fxtoq */
3130 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3131 gen_ne_fop_QD(dc
, rd
, rs2
, gen_helper_fxtoq
);
3137 } else if (xop
== 0x35) { /* FPU Operations */
3138 #ifdef TARGET_SPARC64
3141 if (gen_trap_ifnofpu(dc
)) {
3144 gen_op_clear_ieee_excp_and_FTT();
3145 rs1
= GET_FIELD(insn
, 13, 17);
3146 rs2
= GET_FIELD(insn
, 27, 31);
3147 xop
= GET_FIELD(insn
, 18, 26);
3150 #ifdef TARGET_SPARC64
3154 cond = GET_FIELD_SP(insn, 14, 17); \
3155 cpu_src1 = get_src1(insn, cpu_src1); \
3156 gen_compare_reg(&cmp, cond, cpu_src1); \
3157 gen_fmov##sz(dc, &cmp, rd, rs2); \
3158 free_compare(&cmp); \
3161 if ((xop
& 0x11f) == 0x005) { /* V9 fmovsr */
3164 } else if ((xop
& 0x11f) == 0x006) { // V9 fmovdr
3167 } else if ((xop
& 0x11f) == 0x007) { // V9 fmovqr
3168 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3175 #ifdef TARGET_SPARC64
3176 #define FMOVCC(fcc, sz) \
3179 cond = GET_FIELD_SP(insn, 14, 17); \
3180 gen_fcompare(&cmp, fcc, cond); \
3181 gen_fmov##sz(dc, &cmp, rd, rs2); \
3182 free_compare(&cmp); \
3185 case 0x001: /* V9 fmovscc %fcc0 */
3188 case 0x002: /* V9 fmovdcc %fcc0 */
3191 case 0x003: /* V9 fmovqcc %fcc0 */
3192 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3195 case 0x041: /* V9 fmovscc %fcc1 */
3198 case 0x042: /* V9 fmovdcc %fcc1 */
3201 case 0x043: /* V9 fmovqcc %fcc1 */
3202 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3205 case 0x081: /* V9 fmovscc %fcc2 */
3208 case 0x082: /* V9 fmovdcc %fcc2 */
3211 case 0x083: /* V9 fmovqcc %fcc2 */
3212 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3215 case 0x0c1: /* V9 fmovscc %fcc3 */
3218 case 0x0c2: /* V9 fmovdcc %fcc3 */
3221 case 0x0c3: /* V9 fmovqcc %fcc3 */
3222 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3226 #define FMOVCC(xcc, sz) \
3229 cond = GET_FIELD_SP(insn, 14, 17); \
3230 gen_compare(&cmp, xcc, cond, dc); \
3231 gen_fmov##sz(dc, &cmp, rd, rs2); \
3232 free_compare(&cmp); \
3235 case 0x101: /* V9 fmovscc %icc */
3238 case 0x102: /* V9 fmovdcc %icc */
3241 case 0x103: /* V9 fmovqcc %icc */
3242 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3245 case 0x181: /* V9 fmovscc %xcc */
3248 case 0x182: /* V9 fmovdcc %xcc */
3251 case 0x183: /* V9 fmovqcc %xcc */
3252 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3257 case 0x51: /* fcmps, V9 %fcc */
3258 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
3259 cpu_src2_32
= gen_load_fpr_F(dc
, rs2
);
3260 gen_op_fcmps(rd
& 3, cpu_src1_32
, cpu_src2_32
);
3262 case 0x52: /* fcmpd, V9 %fcc */
3263 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
3264 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
3265 gen_op_fcmpd(rd
& 3, cpu_src1_64
, cpu_src2_64
);
3267 case 0x53: /* fcmpq, V9 %fcc */
3268 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3269 gen_op_load_fpr_QT0(QFPREG(rs1
));
3270 gen_op_load_fpr_QT1(QFPREG(rs2
));
3271 gen_op_fcmpq(rd
& 3);
3273 case 0x55: /* fcmpes, V9 %fcc */
3274 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
3275 cpu_src2_32
= gen_load_fpr_F(dc
, rs2
);
3276 gen_op_fcmpes(rd
& 3, cpu_src1_32
, cpu_src2_32
);
3278 case 0x56: /* fcmped, V9 %fcc */
3279 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
3280 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
3281 gen_op_fcmped(rd
& 3, cpu_src1_64
, cpu_src2_64
);
3283 case 0x57: /* fcmpeq, V9 %fcc */
3284 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3285 gen_op_load_fpr_QT0(QFPREG(rs1
));
3286 gen_op_load_fpr_QT1(QFPREG(rs2
));
3287 gen_op_fcmpeq(rd
& 3);
3292 } else if (xop
== 0x2) {
3295 rs1
= GET_FIELD(insn
, 13, 17);
3297 // or %g0, x, y -> mov T0, x; mov y, T0
3298 if (IS_IMM
) { /* immediate */
3301 simm
= GET_FIELDs(insn
, 19, 31);
3302 r_const
= tcg_const_tl(simm
);
3303 gen_movl_TN_reg(rd
, r_const
);
3304 tcg_temp_free(r_const
);
3305 } else { /* register */
3306 rs2
= GET_FIELD(insn
, 27, 31);
3307 gen_movl_reg_TN(rs2
, cpu_dst
);
3308 gen_movl_TN_reg(rd
, cpu_dst
);
3311 cpu_src1
= get_src1(insn
, cpu_src1
);
3312 if (IS_IMM
) { /* immediate */
3313 simm
= GET_FIELDs(insn
, 19, 31);
3314 tcg_gen_ori_tl(cpu_dst
, cpu_src1
, simm
);
3315 gen_movl_TN_reg(rd
, cpu_dst
);
3316 } else { /* register */
3317 // or x, %g0, y -> mov T1, x; mov y, T1
3318 rs2
= GET_FIELD(insn
, 27, 31);
3320 gen_movl_reg_TN(rs2
, cpu_src2
);
3321 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3322 gen_movl_TN_reg(rd
, cpu_dst
);
3324 gen_movl_TN_reg(rd
, cpu_src1
);
3327 #ifdef TARGET_SPARC64
3328 } else if (xop
== 0x25) { /* sll, V9 sllx */
3329 cpu_src1
= get_src1(insn
, cpu_src1
);
3330 if (IS_IMM
) { /* immediate */
3331 simm
= GET_FIELDs(insn
, 20, 31);
3332 if (insn
& (1 << 12)) {
3333 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3335 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, simm
& 0x1f);
3337 } else { /* register */
3338 rs2
= GET_FIELD(insn
, 27, 31);
3339 gen_movl_reg_TN(rs2
, cpu_src2
);
3340 if (insn
& (1 << 12)) {
3341 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3343 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3345 tcg_gen_shl_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3347 gen_movl_TN_reg(rd
, cpu_dst
);
3348 } else if (xop
== 0x26) { /* srl, V9 srlx */
3349 cpu_src1
= get_src1(insn
, cpu_src1
);
3350 if (IS_IMM
) { /* immediate */
3351 simm
= GET_FIELDs(insn
, 20, 31);
3352 if (insn
& (1 << 12)) {
3353 tcg_gen_shri_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3355 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3356 tcg_gen_shri_i64(cpu_dst
, cpu_dst
, simm
& 0x1f);
3358 } else { /* register */
3359 rs2
= GET_FIELD(insn
, 27, 31);
3360 gen_movl_reg_TN(rs2
, cpu_src2
);
3361 if (insn
& (1 << 12)) {
3362 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3363 tcg_gen_shr_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3365 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3366 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3367 tcg_gen_shr_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
3370 gen_movl_TN_reg(rd
, cpu_dst
);
3371 } else if (xop
== 0x27) { /* sra, V9 srax */
3372 cpu_src1
= get_src1(insn
, cpu_src1
);
3373 if (IS_IMM
) { /* immediate */
3374 simm
= GET_FIELDs(insn
, 20, 31);
3375 if (insn
& (1 << 12)) {
3376 tcg_gen_sari_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3378 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3379 tcg_gen_ext32s_i64(cpu_dst
, cpu_dst
);
3380 tcg_gen_sari_i64(cpu_dst
, cpu_dst
, simm
& 0x1f);
3382 } else { /* register */
3383 rs2
= GET_FIELD(insn
, 27, 31);
3384 gen_movl_reg_TN(rs2
, cpu_src2
);
3385 if (insn
& (1 << 12)) {
3386 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3387 tcg_gen_sar_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3389 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3390 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3391 tcg_gen_ext32s_i64(cpu_dst
, cpu_dst
);
3392 tcg_gen_sar_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
3395 gen_movl_TN_reg(rd
, cpu_dst
);
3397 } else if (xop
< 0x36) {
3399 cpu_src1
= get_src1(insn
, cpu_src1
);
3400 cpu_src2
= get_src2(insn
, cpu_src2
);
3401 switch (xop
& ~0x10) {
3404 simm
= GET_FIELDs(insn
, 19, 31);
3406 gen_op_addi_cc(cpu_dst
, cpu_src1
, simm
);
3407 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3408 dc
->cc_op
= CC_OP_ADD
;
3410 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, simm
);
3414 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3415 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3416 dc
->cc_op
= CC_OP_ADD
;
3418 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3424 simm
= GET_FIELDs(insn
, 19, 31);
3425 tcg_gen_andi_tl(cpu_dst
, cpu_src1
, simm
);
3427 tcg_gen_and_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3430 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3431 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3432 dc
->cc_op
= CC_OP_LOGIC
;
3437 simm
= GET_FIELDs(insn
, 19, 31);
3438 tcg_gen_ori_tl(cpu_dst
, cpu_src1
, simm
);
3440 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3443 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3444 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3445 dc
->cc_op
= CC_OP_LOGIC
;
3450 simm
= GET_FIELDs(insn
, 19, 31);
3451 tcg_gen_xori_tl(cpu_dst
, cpu_src1
, simm
);
3453 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3456 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3457 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3458 dc
->cc_op
= CC_OP_LOGIC
;
3463 simm
= GET_FIELDs(insn
, 19, 31);
3465 gen_op_subi_cc(cpu_dst
, cpu_src1
, simm
, dc
);
3467 tcg_gen_subi_tl(cpu_dst
, cpu_src1
, simm
);
3471 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3472 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
3473 dc
->cc_op
= CC_OP_SUB
;
3475 tcg_gen_sub_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3479 case 0x5: /* andn */
3481 simm
= GET_FIELDs(insn
, 19, 31);
3482 tcg_gen_andi_tl(cpu_dst
, cpu_src1
, ~simm
);
3484 tcg_gen_andc_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3487 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3488 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3489 dc
->cc_op
= CC_OP_LOGIC
;
3494 simm
= GET_FIELDs(insn
, 19, 31);
3495 tcg_gen_ori_tl(cpu_dst
, cpu_src1
, ~simm
);
3497 tcg_gen_orc_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3500 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3501 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3502 dc
->cc_op
= CC_OP_LOGIC
;
3505 case 0x7: /* xorn */
3507 simm
= GET_FIELDs(insn
, 19, 31);
3508 tcg_gen_xori_tl(cpu_dst
, cpu_src1
, ~simm
);
3510 tcg_gen_not_tl(cpu_tmp0
, cpu_src2
);
3511 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3514 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3515 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3516 dc
->cc_op
= CC_OP_LOGIC
;
3519 case 0x8: /* addx, V9 addc */
3520 gen_op_addx_int(dc
, cpu_dst
, cpu_src1
, cpu_src2
,
3523 #ifdef TARGET_SPARC64
3524 case 0x9: /* V9 mulx */
3526 simm
= GET_FIELDs(insn
, 19, 31);
3527 tcg_gen_muli_i64(cpu_dst
, cpu_src1
, simm
);
3529 tcg_gen_mul_i64(cpu_dst
, cpu_src1
, cpu_src2
);
3533 case 0xa: /* umul */
3534 CHECK_IU_FEATURE(dc
, MUL
);
3535 gen_op_umul(cpu_dst
, cpu_src1
, cpu_src2
);
3537 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3538 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3539 dc
->cc_op
= CC_OP_LOGIC
;
3542 case 0xb: /* smul */
3543 CHECK_IU_FEATURE(dc
, MUL
);
3544 gen_op_smul(cpu_dst
, cpu_src1
, cpu_src2
);
3546 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3547 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3548 dc
->cc_op
= CC_OP_LOGIC
;
3551 case 0xc: /* subx, V9 subc */
3552 gen_op_subx_int(dc
, cpu_dst
, cpu_src1
, cpu_src2
,
3555 #ifdef TARGET_SPARC64
3556 case 0xd: /* V9 udivx */
3557 gen_helper_udivx(cpu_dst
, cpu_env
, cpu_src1
, cpu_src2
);
3560 case 0xe: /* udiv */
3561 CHECK_IU_FEATURE(dc
, DIV
);
3563 gen_helper_udiv_cc(cpu_dst
, cpu_env
, cpu_src1
,
3565 dc
->cc_op
= CC_OP_DIV
;
3567 gen_helper_udiv(cpu_dst
, cpu_env
, cpu_src1
,
3571 case 0xf: /* sdiv */
3572 CHECK_IU_FEATURE(dc
, DIV
);
3574 gen_helper_sdiv_cc(cpu_dst
, cpu_env
, cpu_src1
,
3576 dc
->cc_op
= CC_OP_DIV
;
3578 gen_helper_sdiv(cpu_dst
, cpu_env
, cpu_src1
,
3585 gen_movl_TN_reg(rd
, cpu_dst
);
3587 cpu_src1
= get_src1(insn
, cpu_src1
);
3588 cpu_src2
= get_src2(insn
, cpu_src2
);
3590 case 0x20: /* taddcc */
3591 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3592 gen_movl_TN_reg(rd
, cpu_dst
);
3593 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_TADD
);
3594 dc
->cc_op
= CC_OP_TADD
;
3596 case 0x21: /* tsubcc */
3597 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3598 gen_movl_TN_reg(rd
, cpu_dst
);
3599 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_TSUB
);
3600 dc
->cc_op
= CC_OP_TSUB
;
3602 case 0x22: /* taddcctv */
3603 gen_helper_taddcctv(cpu_dst
, cpu_env
,
3604 cpu_src1
, cpu_src2
);
3605 gen_movl_TN_reg(rd
, cpu_dst
);
3606 dc
->cc_op
= CC_OP_TADDTV
;
3608 case 0x23: /* tsubcctv */
3609 gen_helper_tsubcctv(cpu_dst
, cpu_env
,
3610 cpu_src1
, cpu_src2
);
3611 gen_movl_TN_reg(rd
, cpu_dst
);
3612 dc
->cc_op
= CC_OP_TSUBTV
;
3614 case 0x24: /* mulscc */
3615 gen_helper_compute_psr(cpu_env
);
3616 gen_op_mulscc(cpu_dst
, cpu_src1
, cpu_src2
);
3617 gen_movl_TN_reg(rd
, cpu_dst
);
3618 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3619 dc
->cc_op
= CC_OP_ADD
;
3621 #ifndef TARGET_SPARC64
3622 case 0x25: /* sll */
3623 if (IS_IMM
) { /* immediate */
3624 simm
= GET_FIELDs(insn
, 20, 31);
3625 tcg_gen_shli_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3626 } else { /* register */
3627 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3628 tcg_gen_shl_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3630 gen_movl_TN_reg(rd
, cpu_dst
);
3632 case 0x26: /* srl */
3633 if (IS_IMM
) { /* immediate */
3634 simm
= GET_FIELDs(insn
, 20, 31);
3635 tcg_gen_shri_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3636 } else { /* register */
3637 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3638 tcg_gen_shr_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3640 gen_movl_TN_reg(rd
, cpu_dst
);
3642 case 0x27: /* sra */
3643 if (IS_IMM
) { /* immediate */
3644 simm
= GET_FIELDs(insn
, 20, 31);
3645 tcg_gen_sari_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3646 } else { /* register */
3647 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3648 tcg_gen_sar_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3650 gen_movl_TN_reg(rd
, cpu_dst
);
3657 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3658 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
3660 #ifndef TARGET_SPARC64
3661 case 0x01 ... 0x0f: /* undefined in the
3665 case 0x10 ... 0x1f: /* implementation-dependent
3671 case 0x2: /* V9 wrccr */
3672 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3673 gen_helper_wrccr(cpu_env
, cpu_dst
);
3674 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_FLAGS
);
3675 dc
->cc_op
= CC_OP_FLAGS
;
3677 case 0x3: /* V9 wrasi */
3678 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3679 tcg_gen_andi_tl(cpu_dst
, cpu_dst
, 0xff);
3680 tcg_gen_trunc_tl_i32(cpu_asi
, cpu_dst
);
3682 case 0x6: /* V9 wrfprs */
3683 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3684 tcg_gen_trunc_tl_i32(cpu_fprs
, cpu_dst
);
3690 case 0xf: /* V9 sir, nop if user */
3691 #if !defined(CONFIG_USER_ONLY)
3692 if (supervisor(dc
)) {
3697 case 0x13: /* Graphics Status */
3698 if (gen_trap_ifnofpu(dc
)) {
3701 tcg_gen_xor_tl(cpu_gsr
, cpu_src1
, cpu_src2
);
3703 case 0x14: /* Softint set */
3704 if (!supervisor(dc
))
3706 tcg_gen_xor_tl(cpu_tmp64
, cpu_src1
, cpu_src2
);
3707 gen_helper_set_softint(cpu_env
, cpu_tmp64
);
3709 case 0x15: /* Softint clear */
3710 if (!supervisor(dc
))
3712 tcg_gen_xor_tl(cpu_tmp64
, cpu_src1
, cpu_src2
);
3713 gen_helper_clear_softint(cpu_env
, cpu_tmp64
);
3715 case 0x16: /* Softint write */
3716 if (!supervisor(dc
))
3718 tcg_gen_xor_tl(cpu_tmp64
, cpu_src1
, cpu_src2
);
3719 gen_helper_write_softint(cpu_env
, cpu_tmp64
);
3721 case 0x17: /* Tick compare */
3722 #if !defined(CONFIG_USER_ONLY)
3723 if (!supervisor(dc
))
3729 tcg_gen_xor_tl(cpu_tick_cmpr
, cpu_src1
,
3731 r_tickptr
= tcg_temp_new_ptr();
3732 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3733 offsetof(CPUSPARCState
, tick
));
3734 gen_helper_tick_set_limit(r_tickptr
,
3736 tcg_temp_free_ptr(r_tickptr
);
3739 case 0x18: /* System tick */
3740 #if !defined(CONFIG_USER_ONLY)
3741 if (!supervisor(dc
))
3747 tcg_gen_xor_tl(cpu_dst
, cpu_src1
,
3749 r_tickptr
= tcg_temp_new_ptr();
3750 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3751 offsetof(CPUSPARCState
, stick
));
3752 gen_helper_tick_set_count(r_tickptr
,
3754 tcg_temp_free_ptr(r_tickptr
);
3757 case 0x19: /* System tick compare */
3758 #if !defined(CONFIG_USER_ONLY)
3759 if (!supervisor(dc
))
3765 tcg_gen_xor_tl(cpu_stick_cmpr
, cpu_src1
,
3767 r_tickptr
= tcg_temp_new_ptr();
3768 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3769 offsetof(CPUSPARCState
, stick
));
3770 gen_helper_tick_set_limit(r_tickptr
,
3772 tcg_temp_free_ptr(r_tickptr
);
3776 case 0x10: /* Performance Control */
3777 case 0x11: /* Performance Instrumentation
3779 case 0x12: /* Dispatch Control */
3786 #if !defined(CONFIG_USER_ONLY)
3787 case 0x31: /* wrpsr, V9 saved, restored */
3789 if (!supervisor(dc
))
3791 #ifdef TARGET_SPARC64
3794 gen_helper_saved(cpu_env
);
3797 gen_helper_restored(cpu_env
);
3799 case 2: /* UA2005 allclean */
3800 case 3: /* UA2005 otherw */
3801 case 4: /* UA2005 normalw */
3802 case 5: /* UA2005 invalw */
3808 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3809 gen_helper_wrpsr(cpu_env
, cpu_dst
);
3810 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_FLAGS
);
3811 dc
->cc_op
= CC_OP_FLAGS
;
3819 case 0x32: /* wrwim, V9 wrpr */
3821 if (!supervisor(dc
))
3823 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3824 #ifdef TARGET_SPARC64
3830 r_tsptr
= tcg_temp_new_ptr();
3831 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3832 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3833 offsetof(trap_state
, tpc
));
3834 tcg_temp_free_ptr(r_tsptr
);
3841 r_tsptr
= tcg_temp_new_ptr();
3842 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3843 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3844 offsetof(trap_state
, tnpc
));
3845 tcg_temp_free_ptr(r_tsptr
);
3852 r_tsptr
= tcg_temp_new_ptr();
3853 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3854 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3855 offsetof(trap_state
,
3857 tcg_temp_free_ptr(r_tsptr
);
3864 r_tsptr
= tcg_temp_new_ptr();
3865 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3866 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3867 tcg_gen_st_i32(cpu_tmp32
, r_tsptr
,
3868 offsetof(trap_state
, tt
));
3869 tcg_temp_free_ptr(r_tsptr
);
3876 r_tickptr
= tcg_temp_new_ptr();
3877 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3878 offsetof(CPUSPARCState
, tick
));
3879 gen_helper_tick_set_count(r_tickptr
,
3881 tcg_temp_free_ptr(r_tickptr
);
3885 tcg_gen_mov_tl(cpu_tbr
, cpu_tmp0
);
3889 TCGv r_tmp
= tcg_temp_local_new();
3891 tcg_gen_mov_tl(r_tmp
, cpu_tmp0
);
3893 gen_helper_wrpstate(cpu_env
, r_tmp
);
3894 tcg_temp_free(r_tmp
);
3895 dc
->npc
= DYNAMIC_PC
;
3900 TCGv r_tmp
= tcg_temp_local_new();
3902 tcg_gen_mov_tl(r_tmp
, cpu_tmp0
);
3904 tcg_gen_trunc_tl_i32(cpu_tmp32
, r_tmp
);
3905 tcg_temp_free(r_tmp
);
3906 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3907 offsetof(CPUSPARCState
, tl
));
3908 dc
->npc
= DYNAMIC_PC
;
3912 gen_helper_wrpil(cpu_env
, cpu_tmp0
);
3915 gen_helper_wrcwp(cpu_env
, cpu_tmp0
);
3918 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3919 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3920 offsetof(CPUSPARCState
,
3923 case 11: // canrestore
3924 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3925 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3926 offsetof(CPUSPARCState
,
3929 case 12: // cleanwin
3930 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3931 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3932 offsetof(CPUSPARCState
,
3935 case 13: // otherwin
3936 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3937 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3938 offsetof(CPUSPARCState
,
3942 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3943 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3944 offsetof(CPUSPARCState
,
3947 case 16: // UA2005 gl
3948 CHECK_IU_FEATURE(dc
, GL
);
3949 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3950 tcg_gen_st_i32(cpu_tmp32
, cpu_env
,
3951 offsetof(CPUSPARCState
, gl
));
3953 case 26: // UA2005 strand status
3954 CHECK_IU_FEATURE(dc
, HYPV
);
3955 if (!hypervisor(dc
))
3957 tcg_gen_mov_tl(cpu_ssr
, cpu_tmp0
);
3963 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
3964 if (dc
->def
->nwindows
!= 32)
3965 tcg_gen_andi_tl(cpu_tmp32
, cpu_tmp32
,
3966 (1 << dc
->def
->nwindows
) - 1);
3967 tcg_gen_mov_i32(cpu_wim
, cpu_tmp32
);
3971 case 0x33: /* wrtbr, UA2005 wrhpr */
3973 #ifndef TARGET_SPARC64
3974 if (!supervisor(dc
))
3976 tcg_gen_xor_tl(cpu_tbr
, cpu_src1
, cpu_src2
);
3978 CHECK_IU_FEATURE(dc
, HYPV
);
3979 if (!hypervisor(dc
))
3981 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3984 // XXX gen_op_wrhpstate();
3991 // XXX gen_op_wrhtstate();
3994 tcg_gen_mov_tl(cpu_hintp
, cpu_tmp0
);
3997 tcg_gen_mov_tl(cpu_htba
, cpu_tmp0
);
3999 case 31: // hstick_cmpr
4003 tcg_gen_mov_tl(cpu_hstick_cmpr
, cpu_tmp0
);
4004 r_tickptr
= tcg_temp_new_ptr();
4005 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
4006 offsetof(CPUSPARCState
, hstick
));
4007 gen_helper_tick_set_limit(r_tickptr
,
4009 tcg_temp_free_ptr(r_tickptr
);
4012 case 6: // hver readonly
4020 #ifdef TARGET_SPARC64
4021 case 0x2c: /* V9 movcc */
4023 int cc
= GET_FIELD_SP(insn
, 11, 12);
4024 int cond
= GET_FIELD_SP(insn
, 14, 17);
4027 if (insn
& (1 << 18)) {
4029 gen_compare(&cmp
, 0, cond
, dc
);
4030 } else if (cc
== 2) {
4031 gen_compare(&cmp
, 1, cond
, dc
);
4036 gen_fcompare(&cmp
, cc
, cond
);
4039 /* The get_src2 above loaded the normal 13-bit
4040 immediate field, not the 11-bit field we have
4041 in movcc. But it did handle the reg case. */
4043 simm
= GET_FIELD_SPs(insn
, 0, 10);
4044 tcg_gen_movi_tl(cpu_src2
, simm
);
4047 gen_movl_reg_TN(rd
, cpu_dst
);
4048 tcg_gen_movcond_tl(cmp
.cond
, cpu_dst
,
4052 gen_movl_TN_reg(rd
, cpu_dst
);
4055 case 0x2d: /* V9 sdivx */
4056 gen_helper_sdivx(cpu_dst
, cpu_env
, cpu_src1
, cpu_src2
);
4057 gen_movl_TN_reg(rd
, cpu_dst
);
4059 case 0x2e: /* V9 popc */
4061 cpu_src2
= get_src2(insn
, cpu_src2
);
4062 gen_helper_popc(cpu_dst
, cpu_src2
);
4063 gen_movl_TN_reg(rd
, cpu_dst
);
4065 case 0x2f: /* V9 movr */
4067 int cond
= GET_FIELD_SP(insn
, 10, 12);
4070 gen_compare_reg(&cmp
, cond
, cpu_src1
);
4072 /* The get_src2 above loaded the normal 13-bit
4073 immediate field, not the 10-bit field we have
4074 in movr. But it did handle the reg case. */
4076 simm
= GET_FIELD_SPs(insn
, 0, 9);
4077 tcg_gen_movi_tl(cpu_src2
, simm
);
4080 gen_movl_reg_TN(rd
, cpu_dst
);
4081 tcg_gen_movcond_tl(cmp
.cond
, cpu_dst
,
4085 gen_movl_TN_reg(rd
, cpu_dst
);
4093 } else if (xop
== 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4094 #ifdef TARGET_SPARC64
4095 int opf
= GET_FIELD_SP(insn
, 5, 13);
4096 rs1
= GET_FIELD(insn
, 13, 17);
4097 rs2
= GET_FIELD(insn
, 27, 31);
4098 if (gen_trap_ifnofpu(dc
)) {
4103 case 0x000: /* VIS I edge8cc */
4104 CHECK_FPU_FEATURE(dc
, VIS1
);
4105 gen_movl_reg_TN(rs1
, cpu_src1
);
4106 gen_movl_reg_TN(rs2
, cpu_src2
);
4107 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 1, 0);
4108 gen_movl_TN_reg(rd
, cpu_dst
);
4110 case 0x001: /* VIS II edge8n */
4111 CHECK_FPU_FEATURE(dc
, VIS2
);
4112 gen_movl_reg_TN(rs1
, cpu_src1
);
4113 gen_movl_reg_TN(rs2
, cpu_src2
);
4114 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 0, 0);
4115 gen_movl_TN_reg(rd
, cpu_dst
);
4117 case 0x002: /* VIS I edge8lcc */
4118 CHECK_FPU_FEATURE(dc
, VIS1
);
4119 gen_movl_reg_TN(rs1
, cpu_src1
);
4120 gen_movl_reg_TN(rs2
, cpu_src2
);
4121 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 1, 1);
4122 gen_movl_TN_reg(rd
, cpu_dst
);
4124 case 0x003: /* VIS II edge8ln */
4125 CHECK_FPU_FEATURE(dc
, VIS2
);
4126 gen_movl_reg_TN(rs1
, cpu_src1
);
4127 gen_movl_reg_TN(rs2
, cpu_src2
);
4128 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 0, 1);
4129 gen_movl_TN_reg(rd
, cpu_dst
);
4131 case 0x004: /* VIS I edge16cc */
4132 CHECK_FPU_FEATURE(dc
, VIS1
);
4133 gen_movl_reg_TN(rs1
, cpu_src1
);
4134 gen_movl_reg_TN(rs2
, cpu_src2
);
4135 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 1, 0);
4136 gen_movl_TN_reg(rd
, cpu_dst
);
4138 case 0x005: /* VIS II edge16n */
4139 CHECK_FPU_FEATURE(dc
, VIS2
);
4140 gen_movl_reg_TN(rs1
, cpu_src1
);
4141 gen_movl_reg_TN(rs2
, cpu_src2
);
4142 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 0, 0);
4143 gen_movl_TN_reg(rd
, cpu_dst
);
4145 case 0x006: /* VIS I edge16lcc */
4146 CHECK_FPU_FEATURE(dc
, VIS1
);
4147 gen_movl_reg_TN(rs1
, cpu_src1
);
4148 gen_movl_reg_TN(rs2
, cpu_src2
);
4149 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 1, 1);
4150 gen_movl_TN_reg(rd
, cpu_dst
);
4152 case 0x007: /* VIS II edge16ln */
4153 CHECK_FPU_FEATURE(dc
, VIS2
);
4154 gen_movl_reg_TN(rs1
, cpu_src1
);
4155 gen_movl_reg_TN(rs2
, cpu_src2
);
4156 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 0, 1);
4157 gen_movl_TN_reg(rd
, cpu_dst
);
4159 case 0x008: /* VIS I edge32cc */
4160 CHECK_FPU_FEATURE(dc
, VIS1
);
4161 gen_movl_reg_TN(rs1
, cpu_src1
);
4162 gen_movl_reg_TN(rs2
, cpu_src2
);
4163 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 1, 0);
4164 gen_movl_TN_reg(rd
, cpu_dst
);
4166 case 0x009: /* VIS II edge32n */
4167 CHECK_FPU_FEATURE(dc
, VIS2
);
4168 gen_movl_reg_TN(rs1
, cpu_src1
);
4169 gen_movl_reg_TN(rs2
, cpu_src2
);
4170 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 0, 0);
4171 gen_movl_TN_reg(rd
, cpu_dst
);
4173 case 0x00a: /* VIS I edge32lcc */
4174 CHECK_FPU_FEATURE(dc
, VIS1
);
4175 gen_movl_reg_TN(rs1
, cpu_src1
);
4176 gen_movl_reg_TN(rs2
, cpu_src2
);
4177 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 1, 1);
4178 gen_movl_TN_reg(rd
, cpu_dst
);
4180 case 0x00b: /* VIS II edge32ln */
4181 CHECK_FPU_FEATURE(dc
, VIS2
);
4182 gen_movl_reg_TN(rs1
, cpu_src1
);
4183 gen_movl_reg_TN(rs2
, cpu_src2
);
4184 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 0, 1);
4185 gen_movl_TN_reg(rd
, cpu_dst
);
4187 case 0x010: /* VIS I array8 */
4188 CHECK_FPU_FEATURE(dc
, VIS1
);
4189 cpu_src1
= get_src1(insn
, cpu_src1
);
4190 gen_movl_reg_TN(rs2
, cpu_src2
);
4191 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4192 gen_movl_TN_reg(rd
, cpu_dst
);
4194 case 0x012: /* VIS I array16 */
4195 CHECK_FPU_FEATURE(dc
, VIS1
);
4196 cpu_src1
= get_src1(insn
, cpu_src1
);
4197 gen_movl_reg_TN(rs2
, cpu_src2
);
4198 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4199 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 1);
4200 gen_movl_TN_reg(rd
, cpu_dst
);
4202 case 0x014: /* VIS I array32 */
4203 CHECK_FPU_FEATURE(dc
, VIS1
);
4204 cpu_src1
= get_src1(insn
, cpu_src1
);
4205 gen_movl_reg_TN(rs2
, cpu_src2
);
4206 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4207 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 2);
4208 gen_movl_TN_reg(rd
, cpu_dst
);
4210 case 0x018: /* VIS I alignaddr */
4211 CHECK_FPU_FEATURE(dc
, VIS1
);
4212 cpu_src1
= get_src1(insn
, cpu_src1
);
4213 gen_movl_reg_TN(rs2
, cpu_src2
);
4214 gen_alignaddr(cpu_dst
, cpu_src1
, cpu_src2
, 0);
4215 gen_movl_TN_reg(rd
, cpu_dst
);
4217 case 0x01a: /* VIS I alignaddrl */
4218 CHECK_FPU_FEATURE(dc
, VIS1
);
4219 cpu_src1
= get_src1(insn
, cpu_src1
);
4220 gen_movl_reg_TN(rs2
, cpu_src2
);
4221 gen_alignaddr(cpu_dst
, cpu_src1
, cpu_src2
, 1);
4222 gen_movl_TN_reg(rd
, cpu_dst
);
4224 case 0x019: /* VIS II bmask */
4225 CHECK_FPU_FEATURE(dc
, VIS2
);
4226 cpu_src1
= get_src1(insn
, cpu_src1
);
4227 cpu_src2
= get_src1(insn
, cpu_src2
);
4228 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4229 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, cpu_dst
, 32, 32);
4230 gen_movl_TN_reg(rd
, cpu_dst
);
4232 case 0x020: /* VIS I fcmple16 */
4233 CHECK_FPU_FEATURE(dc
, VIS1
);
4234 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4235 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4236 gen_helper_fcmple16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4237 gen_movl_TN_reg(rd
, cpu_dst
);
4239 case 0x022: /* VIS I fcmpne16 */
4240 CHECK_FPU_FEATURE(dc
, VIS1
);
4241 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4242 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4243 gen_helper_fcmpne16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4244 gen_movl_TN_reg(rd
, cpu_dst
);
4246 case 0x024: /* VIS I fcmple32 */
4247 CHECK_FPU_FEATURE(dc
, VIS1
);
4248 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4249 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4250 gen_helper_fcmple32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4251 gen_movl_TN_reg(rd
, cpu_dst
);
4253 case 0x026: /* VIS I fcmpne32 */
4254 CHECK_FPU_FEATURE(dc
, VIS1
);
4255 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4256 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4257 gen_helper_fcmpne32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4258 gen_movl_TN_reg(rd
, cpu_dst
);
4260 case 0x028: /* VIS I fcmpgt16 */
4261 CHECK_FPU_FEATURE(dc
, VIS1
);
4262 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4263 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4264 gen_helper_fcmpgt16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4265 gen_movl_TN_reg(rd
, cpu_dst
);
4267 case 0x02a: /* VIS I fcmpeq16 */
4268 CHECK_FPU_FEATURE(dc
, VIS1
);
4269 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4270 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4271 gen_helper_fcmpeq16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4272 gen_movl_TN_reg(rd
, cpu_dst
);
4274 case 0x02c: /* VIS I fcmpgt32 */
4275 CHECK_FPU_FEATURE(dc
, VIS1
);
4276 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4277 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4278 gen_helper_fcmpgt32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4279 gen_movl_TN_reg(rd
, cpu_dst
);
4281 case 0x02e: /* VIS I fcmpeq32 */
4282 CHECK_FPU_FEATURE(dc
, VIS1
);
4283 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4284 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4285 gen_helper_fcmpeq32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4286 gen_movl_TN_reg(rd
, cpu_dst
);
4288 case 0x031: /* VIS I fmul8x16 */
4289 CHECK_FPU_FEATURE(dc
, VIS1
);
4290 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16
);
4292 case 0x033: /* VIS I fmul8x16au */
4293 CHECK_FPU_FEATURE(dc
, VIS1
);
4294 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16au
);
4296 case 0x035: /* VIS I fmul8x16al */
4297 CHECK_FPU_FEATURE(dc
, VIS1
);
4298 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16al
);
4300 case 0x036: /* VIS I fmul8sux16 */
4301 CHECK_FPU_FEATURE(dc
, VIS1
);
4302 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8sux16
);
4304 case 0x037: /* VIS I fmul8ulx16 */
4305 CHECK_FPU_FEATURE(dc
, VIS1
);
4306 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8ulx16
);
4308 case 0x038: /* VIS I fmuld8sux16 */
4309 CHECK_FPU_FEATURE(dc
, VIS1
);
4310 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld8sux16
);
4312 case 0x039: /* VIS I fmuld8ulx16 */
4313 CHECK_FPU_FEATURE(dc
, VIS1
);
4314 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld8ulx16
);
4316 case 0x03a: /* VIS I fpack32 */
4317 CHECK_FPU_FEATURE(dc
, VIS1
);
4318 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpack32
);
4320 case 0x03b: /* VIS I fpack16 */
4321 CHECK_FPU_FEATURE(dc
, VIS1
);
4322 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4323 cpu_dst_32
= gen_dest_fpr_F();
4324 gen_helper_fpack16(cpu_dst_32
, cpu_gsr
, cpu_src1_64
);
4325 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4327 case 0x03d: /* VIS I fpackfix */
4328 CHECK_FPU_FEATURE(dc
, VIS1
);
4329 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4330 cpu_dst_32
= gen_dest_fpr_F();
4331 gen_helper_fpackfix(cpu_dst_32
, cpu_gsr
, cpu_src1_64
);
4332 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4334 case 0x03e: /* VIS I pdist */
4335 CHECK_FPU_FEATURE(dc
, VIS1
);
4336 gen_ne_fop_DDDD(dc
, rd
, rs1
, rs2
, gen_helper_pdist
);
4338 case 0x048: /* VIS I faligndata */
4339 CHECK_FPU_FEATURE(dc
, VIS1
);
4340 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_faligndata
);
4342 case 0x04b: /* VIS I fpmerge */
4343 CHECK_FPU_FEATURE(dc
, VIS1
);
4344 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpmerge
);
4346 case 0x04c: /* VIS II bshuffle */
4347 CHECK_FPU_FEATURE(dc
, VIS2
);
4348 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_bshuffle
);
4350 case 0x04d: /* VIS I fexpand */
4351 CHECK_FPU_FEATURE(dc
, VIS1
);
4352 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fexpand
);
4354 case 0x050: /* VIS I fpadd16 */
4355 CHECK_FPU_FEATURE(dc
, VIS1
);
4356 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpadd16
);
4358 case 0x051: /* VIS I fpadd16s */
4359 CHECK_FPU_FEATURE(dc
, VIS1
);
4360 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fpadd16s
);
4362 case 0x052: /* VIS I fpadd32 */
4363 CHECK_FPU_FEATURE(dc
, VIS1
);
4364 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpadd32
);
4366 case 0x053: /* VIS I fpadd32s */
4367 CHECK_FPU_FEATURE(dc
, VIS1
);
4368 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_add_i32
);
4370 case 0x054: /* VIS I fpsub16 */
4371 CHECK_FPU_FEATURE(dc
, VIS1
);
4372 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpsub16
);
4374 case 0x055: /* VIS I fpsub16s */
4375 CHECK_FPU_FEATURE(dc
, VIS1
);
4376 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fpsub16s
);
4378 case 0x056: /* VIS I fpsub32 */
4379 CHECK_FPU_FEATURE(dc
, VIS1
);
4380 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpsub32
);
4382 case 0x057: /* VIS I fpsub32s */
4383 CHECK_FPU_FEATURE(dc
, VIS1
);
4384 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_sub_i32
);
4386 case 0x060: /* VIS I fzero */
4387 CHECK_FPU_FEATURE(dc
, VIS1
);
4388 cpu_dst_64
= gen_dest_fpr_D();
4389 tcg_gen_movi_i64(cpu_dst_64
, 0);
4390 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4392 case 0x061: /* VIS I fzeros */
4393 CHECK_FPU_FEATURE(dc
, VIS1
);
4394 cpu_dst_32
= gen_dest_fpr_F();
4395 tcg_gen_movi_i32(cpu_dst_32
, 0);
4396 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4398 case 0x062: /* VIS I fnor */
4399 CHECK_FPU_FEATURE(dc
, VIS1
);
4400 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_nor_i64
);
4402 case 0x063: /* VIS I fnors */
4403 CHECK_FPU_FEATURE(dc
, VIS1
);
4404 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_nor_i32
);
4406 case 0x064: /* VIS I fandnot2 */
4407 CHECK_FPU_FEATURE(dc
, VIS1
);
4408 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_andc_i64
);
4410 case 0x065: /* VIS I fandnot2s */
4411 CHECK_FPU_FEATURE(dc
, VIS1
);
4412 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_andc_i32
);
4414 case 0x066: /* VIS I fnot2 */
4415 CHECK_FPU_FEATURE(dc
, VIS1
);
4416 gen_ne_fop_DD(dc
, rd
, rs2
, tcg_gen_not_i64
);
4418 case 0x067: /* VIS I fnot2s */
4419 CHECK_FPU_FEATURE(dc
, VIS1
);
4420 gen_ne_fop_FF(dc
, rd
, rs2
, tcg_gen_not_i32
);
4422 case 0x068: /* VIS I fandnot1 */
4423 CHECK_FPU_FEATURE(dc
, VIS1
);
4424 gen_ne_fop_DDD(dc
, rd
, rs2
, rs1
, tcg_gen_andc_i64
);
4426 case 0x069: /* VIS I fandnot1s */
4427 CHECK_FPU_FEATURE(dc
, VIS1
);
4428 gen_ne_fop_FFF(dc
, rd
, rs2
, rs1
, tcg_gen_andc_i32
);
4430 case 0x06a: /* VIS I fnot1 */
4431 CHECK_FPU_FEATURE(dc
, VIS1
);
4432 gen_ne_fop_DD(dc
, rd
, rs1
, tcg_gen_not_i64
);
4434 case 0x06b: /* VIS I fnot1s */
4435 CHECK_FPU_FEATURE(dc
, VIS1
);
4436 gen_ne_fop_FF(dc
, rd
, rs1
, tcg_gen_not_i32
);
4438 case 0x06c: /* VIS I fxor */
4439 CHECK_FPU_FEATURE(dc
, VIS1
);
4440 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_xor_i64
);
4442 case 0x06d: /* VIS I fxors */
4443 CHECK_FPU_FEATURE(dc
, VIS1
);
4444 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_xor_i32
);
4446 case 0x06e: /* VIS I fnand */
4447 CHECK_FPU_FEATURE(dc
, VIS1
);
4448 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_nand_i64
);
4450 case 0x06f: /* VIS I fnands */
4451 CHECK_FPU_FEATURE(dc
, VIS1
);
4452 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_nand_i32
);
4454 case 0x070: /* VIS I fand */
4455 CHECK_FPU_FEATURE(dc
, VIS1
);
4456 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_and_i64
);
4458 case 0x071: /* VIS I fands */
4459 CHECK_FPU_FEATURE(dc
, VIS1
);
4460 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_and_i32
);
4462 case 0x072: /* VIS I fxnor */
4463 CHECK_FPU_FEATURE(dc
, VIS1
);
4464 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_eqv_i64
);
4466 case 0x073: /* VIS I fxnors */
4467 CHECK_FPU_FEATURE(dc
, VIS1
);
4468 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_eqv_i32
);
4470 case 0x074: /* VIS I fsrc1 */
4471 CHECK_FPU_FEATURE(dc
, VIS1
);
4472 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4473 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
4475 case 0x075: /* VIS I fsrc1s */
4476 CHECK_FPU_FEATURE(dc
, VIS1
);
4477 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
4478 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
4480 case 0x076: /* VIS I fornot2 */
4481 CHECK_FPU_FEATURE(dc
, VIS1
);
4482 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_orc_i64
);
4484 case 0x077: /* VIS I fornot2s */
4485 CHECK_FPU_FEATURE(dc
, VIS1
);
4486 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_orc_i32
);
4488 case 0x078: /* VIS I fsrc2 */
4489 CHECK_FPU_FEATURE(dc
, VIS1
);
4490 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4491 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
4493 case 0x079: /* VIS I fsrc2s */
4494 CHECK_FPU_FEATURE(dc
, VIS1
);
4495 cpu_src1_32
= gen_load_fpr_F(dc
, rs2
);
4496 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
4498 case 0x07a: /* VIS I fornot1 */
4499 CHECK_FPU_FEATURE(dc
, VIS1
);
4500 gen_ne_fop_DDD(dc
, rd
, rs2
, rs1
, tcg_gen_orc_i64
);
4502 case 0x07b: /* VIS I fornot1s */
4503 CHECK_FPU_FEATURE(dc
, VIS1
);
4504 gen_ne_fop_FFF(dc
, rd
, rs2
, rs1
, tcg_gen_orc_i32
);
4506 case 0x07c: /* VIS I for */
4507 CHECK_FPU_FEATURE(dc
, VIS1
);
4508 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_or_i64
);
4510 case 0x07d: /* VIS I fors */
4511 CHECK_FPU_FEATURE(dc
, VIS1
);
4512 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_or_i32
);
4514 case 0x07e: /* VIS I fone */
4515 CHECK_FPU_FEATURE(dc
, VIS1
);
4516 cpu_dst_64
= gen_dest_fpr_D();
4517 tcg_gen_movi_i64(cpu_dst_64
, -1);
4518 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4520 case 0x07f: /* VIS I fones */
4521 CHECK_FPU_FEATURE(dc
, VIS1
);
4522 cpu_dst_32
= gen_dest_fpr_F();
4523 tcg_gen_movi_i32(cpu_dst_32
, -1);
4524 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4526 case 0x080: /* VIS I shutdown */
4527 case 0x081: /* VIS II siam */
4536 } else if (xop
== 0x37) { /* V8 CPop2, V9 impdep2 */
4537 #ifdef TARGET_SPARC64
4542 #ifdef TARGET_SPARC64
4543 } else if (xop
== 0x39) { /* V9 return */
4547 cpu_src1
= get_src1(insn
, cpu_src1
);
4548 if (IS_IMM
) { /* immediate */
4549 simm
= GET_FIELDs(insn
, 19, 31);
4550 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, simm
);
4551 } else { /* register */
4552 rs2
= GET_FIELD(insn
, 27, 31);
4554 gen_movl_reg_TN(rs2
, cpu_src2
);
4555 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4557 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
4559 gen_helper_restore(cpu_env
);
4561 r_const
= tcg_const_i32(3);
4562 gen_helper_check_align(cpu_env
, cpu_dst
, r_const
);
4563 tcg_temp_free_i32(r_const
);
4564 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4565 dc
->npc
= DYNAMIC_PC
;
4569 cpu_src1
= get_src1(insn
, cpu_src1
);
4570 if (IS_IMM
) { /* immediate */
4571 simm
= GET_FIELDs(insn
, 19, 31);
4572 tcg_gen_addi_tl(cpu_dst
, cpu_src1
, simm
);
4573 } else { /* register */
4574 rs2
= GET_FIELD(insn
, 27, 31);
4576 gen_movl_reg_TN(rs2
, cpu_src2
);
4577 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4579 tcg_gen_mov_tl(cpu_dst
, cpu_src1
);
4582 case 0x38: /* jmpl */
4587 r_pc
= tcg_const_tl(dc
->pc
);
4588 gen_movl_TN_reg(rd
, r_pc
);
4589 tcg_temp_free(r_pc
);
4591 r_const
= tcg_const_i32(3);
4592 gen_helper_check_align(cpu_env
, cpu_dst
, r_const
);
4593 tcg_temp_free_i32(r_const
);
4594 gen_address_mask(dc
, cpu_dst
);
4595 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4596 dc
->npc
= DYNAMIC_PC
;
4599 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4600 case 0x39: /* rett, V9 return */
4604 if (!supervisor(dc
))
4607 r_const
= tcg_const_i32(3);
4608 gen_helper_check_align(cpu_env
, cpu_dst
, r_const
);
4609 tcg_temp_free_i32(r_const
);
4610 tcg_gen_mov_tl(cpu_npc
, cpu_dst
);
4611 dc
->npc
= DYNAMIC_PC
;
4612 gen_helper_rett(cpu_env
);
4616 case 0x3b: /* flush */
4617 if (!((dc
)->def
->features
& CPU_FEATURE_FLUSH
))
4621 case 0x3c: /* save */
4623 gen_helper_save(cpu_env
);
4624 gen_movl_TN_reg(rd
, cpu_dst
);
4626 case 0x3d: /* restore */
4628 gen_helper_restore(cpu_env
);
4629 gen_movl_TN_reg(rd
, cpu_dst
);
4631 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4632 case 0x3e: /* V9 done/retry */
4636 if (!supervisor(dc
))
4638 dc
->npc
= DYNAMIC_PC
;
4639 dc
->pc
= DYNAMIC_PC
;
4640 gen_helper_done(cpu_env
);
4643 if (!supervisor(dc
))
4645 dc
->npc
= DYNAMIC_PC
;
4646 dc
->pc
= DYNAMIC_PC
;
4647 gen_helper_retry(cpu_env
);
4662 case 3: /* load/store instructions */
4664 unsigned int xop
= GET_FIELD(insn
, 7, 12);
4666 /* flush pending conditional evaluations before exposing
4668 if (dc
->cc_op
!= CC_OP_FLAGS
) {
4669 dc
->cc_op
= CC_OP_FLAGS
;
4670 gen_helper_compute_psr(cpu_env
);
4672 cpu_src1
= get_src1(insn
, cpu_src1
);
4673 if (xop
== 0x3c || xop
== 0x3e) { // V9 casa/casxa
4674 rs2
= GET_FIELD(insn
, 27, 31);
4675 gen_movl_reg_TN(rs2
, cpu_src2
);
4676 tcg_gen_mov_tl(cpu_addr
, cpu_src1
);
4677 } else if (IS_IMM
) { /* immediate */
4678 simm
= GET_FIELDs(insn
, 19, 31);
4679 tcg_gen_addi_tl(cpu_addr
, cpu_src1
, simm
);
4680 } else { /* register */
4681 rs2
= GET_FIELD(insn
, 27, 31);
4683 gen_movl_reg_TN(rs2
, cpu_src2
);
4684 tcg_gen_add_tl(cpu_addr
, cpu_src1
, cpu_src2
);
4686 tcg_gen_mov_tl(cpu_addr
, cpu_src1
);
4688 if (xop
< 4 || (xop
> 7 && xop
< 0x14 && xop
!= 0x0e) ||
4689 (xop
> 0x17 && xop
<= 0x1d ) ||
4690 (xop
> 0x2c && xop
<= 0x33) || xop
== 0x1f || xop
== 0x3d) {
4692 case 0x0: /* ld, V9 lduw, load unsigned word */
4693 gen_address_mask(dc
, cpu_addr
);
4694 tcg_gen_qemu_ld32u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4696 case 0x1: /* ldub, load unsigned byte */
4697 gen_address_mask(dc
, cpu_addr
);
4698 tcg_gen_qemu_ld8u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4700 case 0x2: /* lduh, load unsigned halfword */
4701 gen_address_mask(dc
, cpu_addr
);
4702 tcg_gen_qemu_ld16u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4704 case 0x3: /* ldd, load double word */
4711 r_const
= tcg_const_i32(7);
4712 /* XXX remove alignment check */
4713 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
4714 tcg_temp_free_i32(r_const
);
4715 gen_address_mask(dc
, cpu_addr
);
4716 tcg_gen_qemu_ld64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4717 tcg_gen_trunc_i64_tl(cpu_tmp0
, cpu_tmp64
);
4718 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffffULL
);
4719 gen_movl_TN_reg(rd
+ 1, cpu_tmp0
);
4720 tcg_gen_shri_i64(cpu_tmp64
, cpu_tmp64
, 32);
4721 tcg_gen_trunc_i64_tl(cpu_val
, cpu_tmp64
);
4722 tcg_gen_andi_tl(cpu_val
, cpu_val
, 0xffffffffULL
);
4725 case 0x9: /* ldsb, load signed byte */
4726 gen_address_mask(dc
, cpu_addr
);
4727 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4729 case 0xa: /* ldsh, load signed halfword */
4730 gen_address_mask(dc
, cpu_addr
);
4731 tcg_gen_qemu_ld16s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4733 case 0xd: /* ldstub -- XXX: should be atomically */
4737 gen_address_mask(dc
, cpu_addr
);
4738 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4739 r_const
= tcg_const_tl(0xff);
4740 tcg_gen_qemu_st8(r_const
, cpu_addr
, dc
->mem_idx
);
4741 tcg_temp_free(r_const
);
4744 case 0x0f: /* swap, swap register with memory. Also
4746 CHECK_IU_FEATURE(dc
, SWAP
);
4747 gen_movl_reg_TN(rd
, cpu_val
);
4748 gen_address_mask(dc
, cpu_addr
);
4749 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4750 tcg_gen_qemu_st32(cpu_val
, cpu_addr
, dc
->mem_idx
);
4751 tcg_gen_mov_tl(cpu_val
, cpu_tmp0
);
4753 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4754 case 0x10: /* lda, V9 lduwa, load word alternate */
4755 #ifndef TARGET_SPARC64
4758 if (!supervisor(dc
))
4762 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 0);
4764 case 0x11: /* lduba, load unsigned byte alternate */
4765 #ifndef TARGET_SPARC64
4768 if (!supervisor(dc
))
4772 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 0);
4774 case 0x12: /* lduha, load unsigned halfword alternate */
4775 #ifndef TARGET_SPARC64
4778 if (!supervisor(dc
))
4782 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 0);
4784 case 0x13: /* ldda, load double word alternate */
4785 #ifndef TARGET_SPARC64
4788 if (!supervisor(dc
))
4794 gen_ldda_asi(cpu_val
, cpu_addr
, insn
, rd
);
4796 case 0x19: /* ldsba, load signed byte alternate */
4797 #ifndef TARGET_SPARC64
4800 if (!supervisor(dc
))
4804 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 1);
4806 case 0x1a: /* ldsha, load signed halfword alternate */
4807 #ifndef TARGET_SPARC64
4810 if (!supervisor(dc
))
4814 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 1);
4816 case 0x1d: /* ldstuba -- XXX: should be atomically */
4817 #ifndef TARGET_SPARC64
4820 if (!supervisor(dc
))
4824 gen_ldstub_asi(cpu_val
, cpu_addr
, insn
);
4826 case 0x1f: /* swapa, swap reg with alt. memory. Also
4828 CHECK_IU_FEATURE(dc
, SWAP
);
4829 #ifndef TARGET_SPARC64
4832 if (!supervisor(dc
))
4836 gen_movl_reg_TN(rd
, cpu_val
);
4837 gen_swap_asi(cpu_val
, cpu_addr
, insn
);
4840 #ifndef TARGET_SPARC64
4841 case 0x30: /* ldc */
4842 case 0x31: /* ldcsr */
4843 case 0x33: /* lddc */
4847 #ifdef TARGET_SPARC64
4848 case 0x08: /* V9 ldsw */
4849 gen_address_mask(dc
, cpu_addr
);
4850 tcg_gen_qemu_ld32s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4852 case 0x0b: /* V9 ldx */
4853 gen_address_mask(dc
, cpu_addr
);
4854 tcg_gen_qemu_ld64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4856 case 0x18: /* V9 ldswa */
4858 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 1);
4860 case 0x1b: /* V9 ldxa */
4862 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 8, 0);
4864 case 0x2d: /* V9 prefetch, no effect */
4866 case 0x30: /* V9 ldfa */
4867 if (gen_trap_ifnofpu(dc
)) {
4871 gen_ldf_asi(cpu_addr
, insn
, 4, rd
);
4872 gen_update_fprs_dirty(rd
);
4874 case 0x33: /* V9 lddfa */
4875 if (gen_trap_ifnofpu(dc
)) {
4879 gen_ldf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
4880 gen_update_fprs_dirty(DFPREG(rd
));
4882 case 0x3d: /* V9 prefetcha, no effect */
4884 case 0x32: /* V9 ldqfa */
4885 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4886 if (gen_trap_ifnofpu(dc
)) {
4890 gen_ldf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
4891 gen_update_fprs_dirty(QFPREG(rd
));
4897 gen_movl_TN_reg(rd
, cpu_val
);
4898 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4901 } else if (xop
>= 0x20 && xop
< 0x24) {
4902 if (gen_trap_ifnofpu(dc
)) {
4907 case 0x20: /* ldf, load fpreg */
4908 gen_address_mask(dc
, cpu_addr
);
4909 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4910 cpu_dst_32
= gen_dest_fpr_F();
4911 tcg_gen_trunc_tl_i32(cpu_dst_32
, cpu_tmp0
);
4912 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4914 case 0x21: /* ldfsr, V9 ldxfsr */
4915 #ifdef TARGET_SPARC64
4916 gen_address_mask(dc
, cpu_addr
);
4918 tcg_gen_qemu_ld64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4919 gen_helper_ldxfsr(cpu_env
, cpu_tmp64
);
4921 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
4922 tcg_gen_trunc_tl_i32(cpu_tmp32
, cpu_tmp0
);
4923 gen_helper_ldfsr(cpu_env
, cpu_tmp32
);
4927 tcg_gen_qemu_ld32u(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
4928 gen_helper_ldfsr(cpu_env
, cpu_tmp32
);
4932 case 0x22: /* ldqf, load quad fpreg */
4936 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4937 r_const
= tcg_const_i32(dc
->mem_idx
);
4938 gen_address_mask(dc
, cpu_addr
);
4939 gen_helper_ldqf(cpu_env
, cpu_addr
, r_const
);
4940 tcg_temp_free_i32(r_const
);
4941 gen_op_store_QT0_fpr(QFPREG(rd
));
4942 gen_update_fprs_dirty(QFPREG(rd
));
4945 case 0x23: /* lddf, load double fpreg */
4946 gen_address_mask(dc
, cpu_addr
);
4947 cpu_dst_64
= gen_dest_fpr_D();
4948 tcg_gen_qemu_ld64(cpu_dst_64
, cpu_addr
, dc
->mem_idx
);
4949 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4954 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18) ||
4955 xop
== 0xe || xop
== 0x1e) {
4956 gen_movl_reg_TN(rd
, cpu_val
);
4958 case 0x4: /* st, store word */
4959 gen_address_mask(dc
, cpu_addr
);
4960 tcg_gen_qemu_st32(cpu_val
, cpu_addr
, dc
->mem_idx
);
4962 case 0x5: /* stb, store byte */
4963 gen_address_mask(dc
, cpu_addr
);
4964 tcg_gen_qemu_st8(cpu_val
, cpu_addr
, dc
->mem_idx
);
4966 case 0x6: /* sth, store halfword */
4967 gen_address_mask(dc
, cpu_addr
);
4968 tcg_gen_qemu_st16(cpu_val
, cpu_addr
, dc
->mem_idx
);
4970 case 0x7: /* std, store double word */
4977 gen_address_mask(dc
, cpu_addr
);
4978 r_const
= tcg_const_i32(7);
4979 /* XXX remove alignment check */
4980 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
4981 tcg_temp_free_i32(r_const
);
4982 gen_movl_reg_TN(rd
+ 1, cpu_tmp0
);
4983 tcg_gen_concat_tl_i64(cpu_tmp64
, cpu_tmp0
, cpu_val
);
4984 tcg_gen_qemu_st64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
4987 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4988 case 0x14: /* sta, V9 stwa, store word alternate */
4989 #ifndef TARGET_SPARC64
4992 if (!supervisor(dc
))
4996 gen_st_asi(cpu_val
, cpu_addr
, insn
, 4);
4997 dc
->npc
= DYNAMIC_PC
;
4999 case 0x15: /* stba, store byte alternate */
5000 #ifndef TARGET_SPARC64
5003 if (!supervisor(dc
))
5007 gen_st_asi(cpu_val
, cpu_addr
, insn
, 1);
5008 dc
->npc
= DYNAMIC_PC
;
5010 case 0x16: /* stha, store halfword alternate */
5011 #ifndef TARGET_SPARC64
5014 if (!supervisor(dc
))
5018 gen_st_asi(cpu_val
, cpu_addr
, insn
, 2);
5019 dc
->npc
= DYNAMIC_PC
;
5021 case 0x17: /* stda, store double word alternate */
5022 #ifndef TARGET_SPARC64
5025 if (!supervisor(dc
))
5032 gen_stda_asi(cpu_val
, cpu_addr
, insn
, rd
);
5036 #ifdef TARGET_SPARC64
5037 case 0x0e: /* V9 stx */
5038 gen_address_mask(dc
, cpu_addr
);
5039 tcg_gen_qemu_st64(cpu_val
, cpu_addr
, dc
->mem_idx
);
5041 case 0x1e: /* V9 stxa */
5043 gen_st_asi(cpu_val
, cpu_addr
, insn
, 8);
5044 dc
->npc
= DYNAMIC_PC
;
5050 } else if (xop
> 0x23 && xop
< 0x28) {
5051 if (gen_trap_ifnofpu(dc
)) {
5056 case 0x24: /* stf, store fpreg */
5057 gen_address_mask(dc
, cpu_addr
);
5058 cpu_src1_32
= gen_load_fpr_F(dc
, rd
);
5059 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_src1_32
);
5060 tcg_gen_qemu_st32(cpu_tmp0
, cpu_addr
, dc
->mem_idx
);
5062 case 0x25: /* stfsr, V9 stxfsr */
5063 #ifdef TARGET_SPARC64
5064 gen_address_mask(dc
, cpu_addr
);
5065 tcg_gen_ld_i64(cpu_tmp64
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
5067 tcg_gen_qemu_st64(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
5069 tcg_gen_qemu_st32(cpu_tmp64
, cpu_addr
, dc
->mem_idx
);
5071 tcg_gen_ld_i32(cpu_tmp32
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
5072 tcg_gen_qemu_st32(cpu_tmp32
, cpu_addr
, dc
->mem_idx
);
5076 #ifdef TARGET_SPARC64
5077 /* V9 stqf, store quad fpreg */
5081 CHECK_FPU_FEATURE(dc
, FLOAT128
);
5082 gen_op_load_fpr_QT0(QFPREG(rd
));
5083 r_const
= tcg_const_i32(dc
->mem_idx
);
5084 gen_address_mask(dc
, cpu_addr
);
5085 gen_helper_stqf(cpu_env
, cpu_addr
, r_const
);
5086 tcg_temp_free_i32(r_const
);
5089 #else /* !TARGET_SPARC64 */
5090 /* stdfq, store floating point queue */
5091 #if defined(CONFIG_USER_ONLY)
5094 if (!supervisor(dc
))
5096 if (gen_trap_ifnofpu(dc
)) {
5102 case 0x27: /* stdf, store double fpreg */
5103 gen_address_mask(dc
, cpu_addr
);
5104 cpu_src1_64
= gen_load_fpr_D(dc
, rd
);
5105 tcg_gen_qemu_st64(cpu_src1_64
, cpu_addr
, dc
->mem_idx
);
5110 } else if (xop
> 0x33 && xop
< 0x3f) {
5113 #ifdef TARGET_SPARC64
5114 case 0x34: /* V9 stfa */
5115 if (gen_trap_ifnofpu(dc
)) {
5118 gen_stf_asi(cpu_addr
, insn
, 4, rd
);
5120 case 0x36: /* V9 stqfa */
5124 CHECK_FPU_FEATURE(dc
, FLOAT128
);
5125 if (gen_trap_ifnofpu(dc
)) {
5128 r_const
= tcg_const_i32(7);
5129 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
5130 tcg_temp_free_i32(r_const
);
5131 gen_stf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
5134 case 0x37: /* V9 stdfa */
5135 if (gen_trap_ifnofpu(dc
)) {
5138 gen_stf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
5140 case 0x3c: /* V9 casa */
5141 gen_cas_asi(cpu_val
, cpu_addr
, cpu_src2
, insn
, rd
);
5142 gen_movl_TN_reg(rd
, cpu_val
);
5144 case 0x3e: /* V9 casxa */
5145 gen_casx_asi(cpu_val
, cpu_addr
, cpu_src2
, insn
, rd
);
5146 gen_movl_TN_reg(rd
, cpu_val
);
5149 case 0x34: /* stc */
5150 case 0x35: /* stcsr */
5151 case 0x36: /* stdcq */
5152 case 0x37: /* stdc */
5163 /* default case for non jump instructions */
5164 if (dc
->npc
== DYNAMIC_PC
) {
5165 dc
->pc
= DYNAMIC_PC
;
5167 } else if (dc
->npc
== JUMP_PC
) {
5168 /* we can do a static jump */
5169 gen_branch2(dc
, dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_cond
);
5173 dc
->npc
= dc
->npc
+ 4;
5182 r_const
= tcg_const_i32(TT_ILL_INSN
);
5183 gen_helper_raise_exception(cpu_env
, r_const
);
5184 tcg_temp_free_i32(r_const
);
5193 r_const
= tcg_const_i32(TT_UNIMP_FLUSH
);
5194 gen_helper_raise_exception(cpu_env
, r_const
);
5195 tcg_temp_free_i32(r_const
);
5199 #if !defined(CONFIG_USER_ONLY)
5205 r_const
= tcg_const_i32(TT_PRIV_INSN
);
5206 gen_helper_raise_exception(cpu_env
, r_const
);
5207 tcg_temp_free_i32(r_const
);
5214 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP
);
5217 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
5220 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR
);
5224 #ifndef TARGET_SPARC64
5230 r_const
= tcg_const_i32(TT_NCP_INSN
);
5231 gen_helper_raise_exception(cpu_env
, r_const
);
5232 tcg_temp_free(r_const
);
5238 tcg_temp_free(cpu_tmp1
);
5239 tcg_temp_free(cpu_tmp2
);
5240 if (dc
->n_t32
!= 0) {
5242 for (i
= dc
->n_t32
- 1; i
>= 0; --i
) {
5243 tcg_temp_free_i32(dc
->t32
[i
]);
5249 static inline void gen_intermediate_code_internal(TranslationBlock
* tb
,
5250 int spc
, CPUSPARCState
*env
)
5252 target_ulong pc_start
, last_pc
;
5253 uint16_t *gen_opc_end
;
5254 DisasContext dc1
, *dc
= &dc1
;
5261 memset(dc
, 0, sizeof(DisasContext
));
5266 dc
->npc
= (target_ulong
) tb
->cs_base
;
5267 dc
->cc_op
= CC_OP_DYNAMIC
;
5268 dc
->mem_idx
= cpu_mmu_index(env
);
5270 dc
->fpu_enabled
= tb_fpu_enabled(tb
->flags
);
5271 dc
->address_mask_32bit
= tb_am_enabled(tb
->flags
);
5272 dc
->singlestep
= (env
->singlestep_enabled
|| singlestep
);
5273 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
5276 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
5278 max_insns
= CF_COUNT_MASK
;
5281 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
5282 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
5283 if (bp
->pc
== dc
->pc
) {
5284 if (dc
->pc
!= pc_start
)
5286 gen_helper_debug(cpu_env
);
5294 qemu_log("Search PC...\n");
5295 j
= gen_opc_ptr
- gen_opc_buf
;
5299 gen_opc_instr_start
[lj
++] = 0;
5300 gen_opc_pc
[lj
] = dc
->pc
;
5301 gen_opc_npc
[lj
] = dc
->npc
;
5302 gen_opc_instr_start
[lj
] = 1;
5303 gen_opc_icount
[lj
] = num_insns
;
5306 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
5309 insn
= cpu_ldl_code(env
, dc
->pc
);
5311 cpu_tmp0
= tcg_temp_new();
5312 cpu_tmp32
= tcg_temp_new_i32();
5313 cpu_tmp64
= tcg_temp_new_i64();
5314 cpu_dst
= tcg_temp_new();
5315 cpu_val
= tcg_temp_new();
5316 cpu_addr
= tcg_temp_new();
5318 disas_sparc_insn(dc
, insn
);
5321 tcg_temp_free(cpu_addr
);
5322 tcg_temp_free(cpu_val
);
5323 tcg_temp_free(cpu_dst
);
5324 tcg_temp_free_i64(cpu_tmp64
);
5325 tcg_temp_free_i32(cpu_tmp32
);
5326 tcg_temp_free(cpu_tmp0
);
5330 /* if the next PC is different, we abort now */
5331 if (dc
->pc
!= (last_pc
+ 4))
5333 /* if we reach a page boundary, we stop generation so that the
5334 PC of a TT_TFAULT exception is always in the right page */
5335 if ((dc
->pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
5337 /* if single step mode, we generate only one instruction and
5338 generate an exception */
5339 if (dc
->singlestep
) {
5342 } while ((gen_opc_ptr
< gen_opc_end
) &&
5343 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32) &&
5344 num_insns
< max_insns
);
5347 if (tb
->cflags
& CF_LAST_IO
) {
5351 if (dc
->pc
!= DYNAMIC_PC
&&
5352 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
5353 /* static PC and NPC: we can use direct chaining */
5354 gen_goto_tb(dc
, 0, dc
->pc
, dc
->npc
);
5356 if (dc
->pc
!= DYNAMIC_PC
) {
5357 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
5363 gen_icount_end(tb
, num_insns
);
5364 *gen_opc_ptr
= INDEX_op_end
;
5366 j
= gen_opc_ptr
- gen_opc_buf
;
5369 gen_opc_instr_start
[lj
++] = 0;
5373 gen_opc_jump_pc
[0] = dc
->jump_pc
[0];
5374 gen_opc_jump_pc
[1] = dc
->jump_pc
[1];
5376 tb
->size
= last_pc
+ 4 - pc_start
;
5377 tb
->icount
= num_insns
;
5380 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
5381 qemu_log("--------------\n");
5382 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5383 log_target_disas(pc_start
, last_pc
+ 4 - pc_start
, 0);
5389 void gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
5391 gen_intermediate_code_internal(tb
, 0, env
);
5394 void gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
5396 gen_intermediate_code_internal(tb
, 1, env
);
5399 void gen_intermediate_code_init(CPUSPARCState
*env
)
5403 static const char * const gregnames
[8] = {
5404 NULL
, // g0 not used
5413 static const char * const fregnames
[32] = {
5414 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5415 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5416 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5417 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5420 /* init various static tables */
5424 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
5425 cpu_regwptr
= tcg_global_mem_new_ptr(TCG_AREG0
,
5426 offsetof(CPUSPARCState
, regwptr
),
5428 #ifdef TARGET_SPARC64
5429 cpu_xcc
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, xcc
),
5431 cpu_asi
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, asi
),
5433 cpu_fprs
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, fprs
),
5435 cpu_gsr
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, gsr
),
5437 cpu_tick_cmpr
= tcg_global_mem_new(TCG_AREG0
,
5438 offsetof(CPUSPARCState
, tick_cmpr
),
5440 cpu_stick_cmpr
= tcg_global_mem_new(TCG_AREG0
,
5441 offsetof(CPUSPARCState
, stick_cmpr
),
5443 cpu_hstick_cmpr
= tcg_global_mem_new(TCG_AREG0
,
5444 offsetof(CPUSPARCState
, hstick_cmpr
),
5446 cpu_hintp
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, hintp
),
5448 cpu_htba
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, htba
),
5450 cpu_hver
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, hver
),
5452 cpu_ssr
= tcg_global_mem_new(TCG_AREG0
,
5453 offsetof(CPUSPARCState
, ssr
), "ssr");
5454 cpu_ver
= tcg_global_mem_new(TCG_AREG0
,
5455 offsetof(CPUSPARCState
, version
), "ver");
5456 cpu_softint
= tcg_global_mem_new_i32(TCG_AREG0
,
5457 offsetof(CPUSPARCState
, softint
),
5460 cpu_wim
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, wim
),
5463 cpu_cond
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, cond
),
5465 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, cc_src
),
5467 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
,
5468 offsetof(CPUSPARCState
, cc_src2
),
5470 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, cc_dst
),
5472 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, cc_op
),
5474 cpu_psr
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUSPARCState
, psr
),
5476 cpu_fsr
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, fsr
),
5478 cpu_pc
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, pc
),
5480 cpu_npc
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, npc
),
5482 cpu_y
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, y
), "y");
5483 #ifndef CONFIG_USER_ONLY
5484 cpu_tbr
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUSPARCState
, tbr
),
5487 for (i
= 1; i
< 8; i
++) {
5488 cpu_gregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
5489 offsetof(CPUSPARCState
, gregs
[i
]),
5492 for (i
= 0; i
< TARGET_DPREGS
; i
++) {
5493 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
5494 offsetof(CPUSPARCState
, fpr
[i
]),
5498 /* register helpers */
5500 #define GEN_HELPER 2
5505 void restore_state_to_opc(CPUSPARCState
*env
, TranslationBlock
*tb
, int pc_pos
)
5508 env
->pc
= gen_opc_pc
[pc_pos
];
5509 npc
= gen_opc_npc
[pc_pos
];
5511 /* dynamic NPC: already stored */
5512 } else if (npc
== 2) {
5513 /* jump PC: use 'cond' and the jump targets of the translation */
5515 env
->npc
= gen_opc_jump_pc
[0];
5517 env
->npc
= gen_opc_jump_pc
[1];
5523 /* flush pending conditional evaluations before exposing cpu state */
5524 if (CC_OP
!= CC_OP_FLAGS
) {
5525 helper_compute_psr(env
);