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[mirror_qemu.git] / target-sparc / translate.c
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 TODO-list:
24
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
28 128-bit float
29 */
30
31 #include <stdarg.h>
32 #include <stdlib.h>
33 #include <stdio.h>
34 #include <string.h>
35 #include <inttypes.h>
36
37 #include "cpu.h"
38 #include "exec-all.h"
39 #include "disas.h"
40
41 #define DEBUG_DISAS
42
43 #define DYNAMIC_PC 1 /* dynamic pc value */
44 #define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
46
47 typedef struct DisasContext {
48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
51 int is_br;
52 int mem_idx;
53 int fpu_enabled;
54 struct TranslationBlock *tb;
55 } DisasContext;
56
57 struct sparc_def_t {
58 const unsigned char *name;
59 target_ulong iu_version;
60 uint32_t fpu_version;
61 uint32_t mmu_version;
62 };
63
64 static uint16_t *gen_opc_ptr;
65 static uint32_t *gen_opparam_ptr;
66 extern FILE *logfile;
67 extern int loglevel;
68
69 enum {
70 #define DEF(s,n,copy_size) INDEX_op_ ## s,
71 #include "opc.h"
72 #undef DEF
73 NB_OPS
74 };
75
76 #include "gen-op.h"
77
78 // This function uses non-native bit order
79 #define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
81
82 // This function uses the order in the manuals, i.e. bit 0 is 2^0
83 #define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
85
86 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
87 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
88
89 #ifdef TARGET_SPARC64
90 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
91 #else
92 #define DFPREG(r) (r & 0x1e)
93 #endif
94
95 #ifdef USE_DIRECT_JUMP
96 #define TBPARAM(x)
97 #else
98 #define TBPARAM(x) (long)(x)
99 #endif
100
101 static int sign_extend(int x, int len)
102 {
103 len = 32 - len;
104 return (x << len) >> len;
105 }
106
107 #define IS_IMM (insn & (1<<13))
108
109 static void disas_sparc_insn(DisasContext * dc);
110
111 static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
112 {
113 gen_op_movl_g0_T0,
114 gen_op_movl_g1_T0,
115 gen_op_movl_g2_T0,
116 gen_op_movl_g3_T0,
117 gen_op_movl_g4_T0,
118 gen_op_movl_g5_T0,
119 gen_op_movl_g6_T0,
120 gen_op_movl_g7_T0,
121 gen_op_movl_o0_T0,
122 gen_op_movl_o1_T0,
123 gen_op_movl_o2_T0,
124 gen_op_movl_o3_T0,
125 gen_op_movl_o4_T0,
126 gen_op_movl_o5_T0,
127 gen_op_movl_o6_T0,
128 gen_op_movl_o7_T0,
129 gen_op_movl_l0_T0,
130 gen_op_movl_l1_T0,
131 gen_op_movl_l2_T0,
132 gen_op_movl_l3_T0,
133 gen_op_movl_l4_T0,
134 gen_op_movl_l5_T0,
135 gen_op_movl_l6_T0,
136 gen_op_movl_l7_T0,
137 gen_op_movl_i0_T0,
138 gen_op_movl_i1_T0,
139 gen_op_movl_i2_T0,
140 gen_op_movl_i3_T0,
141 gen_op_movl_i4_T0,
142 gen_op_movl_i5_T0,
143 gen_op_movl_i6_T0,
144 gen_op_movl_i7_T0,
145 },
146 {
147 gen_op_movl_g0_T1,
148 gen_op_movl_g1_T1,
149 gen_op_movl_g2_T1,
150 gen_op_movl_g3_T1,
151 gen_op_movl_g4_T1,
152 gen_op_movl_g5_T1,
153 gen_op_movl_g6_T1,
154 gen_op_movl_g7_T1,
155 gen_op_movl_o0_T1,
156 gen_op_movl_o1_T1,
157 gen_op_movl_o2_T1,
158 gen_op_movl_o3_T1,
159 gen_op_movl_o4_T1,
160 gen_op_movl_o5_T1,
161 gen_op_movl_o6_T1,
162 gen_op_movl_o7_T1,
163 gen_op_movl_l0_T1,
164 gen_op_movl_l1_T1,
165 gen_op_movl_l2_T1,
166 gen_op_movl_l3_T1,
167 gen_op_movl_l4_T1,
168 gen_op_movl_l5_T1,
169 gen_op_movl_l6_T1,
170 gen_op_movl_l7_T1,
171 gen_op_movl_i0_T1,
172 gen_op_movl_i1_T1,
173 gen_op_movl_i2_T1,
174 gen_op_movl_i3_T1,
175 gen_op_movl_i4_T1,
176 gen_op_movl_i5_T1,
177 gen_op_movl_i6_T1,
178 gen_op_movl_i7_T1,
179 }
180 };
181
182 static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
183 {
184 gen_op_movl_T0_g0,
185 gen_op_movl_T0_g1,
186 gen_op_movl_T0_g2,
187 gen_op_movl_T0_g3,
188 gen_op_movl_T0_g4,
189 gen_op_movl_T0_g5,
190 gen_op_movl_T0_g6,
191 gen_op_movl_T0_g7,
192 gen_op_movl_T0_o0,
193 gen_op_movl_T0_o1,
194 gen_op_movl_T0_o2,
195 gen_op_movl_T0_o3,
196 gen_op_movl_T0_o4,
197 gen_op_movl_T0_o5,
198 gen_op_movl_T0_o6,
199 gen_op_movl_T0_o7,
200 gen_op_movl_T0_l0,
201 gen_op_movl_T0_l1,
202 gen_op_movl_T0_l2,
203 gen_op_movl_T0_l3,
204 gen_op_movl_T0_l4,
205 gen_op_movl_T0_l5,
206 gen_op_movl_T0_l6,
207 gen_op_movl_T0_l7,
208 gen_op_movl_T0_i0,
209 gen_op_movl_T0_i1,
210 gen_op_movl_T0_i2,
211 gen_op_movl_T0_i3,
212 gen_op_movl_T0_i4,
213 gen_op_movl_T0_i5,
214 gen_op_movl_T0_i6,
215 gen_op_movl_T0_i7,
216 },
217 {
218 gen_op_movl_T1_g0,
219 gen_op_movl_T1_g1,
220 gen_op_movl_T1_g2,
221 gen_op_movl_T1_g3,
222 gen_op_movl_T1_g4,
223 gen_op_movl_T1_g5,
224 gen_op_movl_T1_g6,
225 gen_op_movl_T1_g7,
226 gen_op_movl_T1_o0,
227 gen_op_movl_T1_o1,
228 gen_op_movl_T1_o2,
229 gen_op_movl_T1_o3,
230 gen_op_movl_T1_o4,
231 gen_op_movl_T1_o5,
232 gen_op_movl_T1_o6,
233 gen_op_movl_T1_o7,
234 gen_op_movl_T1_l0,
235 gen_op_movl_T1_l1,
236 gen_op_movl_T1_l2,
237 gen_op_movl_T1_l3,
238 gen_op_movl_T1_l4,
239 gen_op_movl_T1_l5,
240 gen_op_movl_T1_l6,
241 gen_op_movl_T1_l7,
242 gen_op_movl_T1_i0,
243 gen_op_movl_T1_i1,
244 gen_op_movl_T1_i2,
245 gen_op_movl_T1_i3,
246 gen_op_movl_T1_i4,
247 gen_op_movl_T1_i5,
248 gen_op_movl_T1_i6,
249 gen_op_movl_T1_i7,
250 },
251 {
252 gen_op_movl_T2_g0,
253 gen_op_movl_T2_g1,
254 gen_op_movl_T2_g2,
255 gen_op_movl_T2_g3,
256 gen_op_movl_T2_g4,
257 gen_op_movl_T2_g5,
258 gen_op_movl_T2_g6,
259 gen_op_movl_T2_g7,
260 gen_op_movl_T2_o0,
261 gen_op_movl_T2_o1,
262 gen_op_movl_T2_o2,
263 gen_op_movl_T2_o3,
264 gen_op_movl_T2_o4,
265 gen_op_movl_T2_o5,
266 gen_op_movl_T2_o6,
267 gen_op_movl_T2_o7,
268 gen_op_movl_T2_l0,
269 gen_op_movl_T2_l1,
270 gen_op_movl_T2_l2,
271 gen_op_movl_T2_l3,
272 gen_op_movl_T2_l4,
273 gen_op_movl_T2_l5,
274 gen_op_movl_T2_l6,
275 gen_op_movl_T2_l7,
276 gen_op_movl_T2_i0,
277 gen_op_movl_T2_i1,
278 gen_op_movl_T2_i2,
279 gen_op_movl_T2_i3,
280 gen_op_movl_T2_i4,
281 gen_op_movl_T2_i5,
282 gen_op_movl_T2_i6,
283 gen_op_movl_T2_i7,
284 }
285 };
286
287 static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
288 gen_op_movl_T0_im,
289 gen_op_movl_T1_im,
290 gen_op_movl_T2_im
291 };
292
293 // Sign extending version
294 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
295 gen_op_movl_T0_sim,
296 gen_op_movl_T1_sim,
297 gen_op_movl_T2_sim
298 };
299
300 #ifdef TARGET_SPARC64
301 #define GEN32(func, NAME) \
302 static GenOpFunc * const NAME ## _table [64] = { \
303 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
315 }; \
316 static inline void func(int n) \
317 { \
318 NAME ## _table[n](); \
319 }
320 #else
321 #define GEN32(func, NAME) \
322 static GenOpFunc *const NAME ## _table [32] = { \
323 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
331 }; \
332 static inline void func(int n) \
333 { \
334 NAME ## _table[n](); \
335 }
336 #endif
337
338 /* floating point registers moves */
339 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
341 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
343
344 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
346 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
348
349 #ifdef TARGET_SPARC64
350 // 'a' versions allowed to user depending on asi
351 #if defined(CONFIG_USER_ONLY)
352 #define supervisor(dc) 0
353 #define gen_op_ldst(name) gen_op_##name##_raw()
354 #define OP_LD_TABLE(width) \
355 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
356 { \
357 int asi, offset; \
358 \
359 if (IS_IMM) { \
360 offset = GET_FIELD(insn, 25, 31); \
361 if (is_ld) \
362 gen_op_ld_asi_reg(offset, size, sign); \
363 else \
364 gen_op_st_asi_reg(offset, size, sign); \
365 return; \
366 } \
367 asi = GET_FIELD(insn, 19, 26); \
368 switch (asi) { \
369 case 0x80: /* Primary address space */ \
370 gen_op_##width##_raw(); \
371 break; \
372 case 0x82: /* Primary address space, non-faulting load */ \
373 gen_op_##width##_raw(); \
374 break; \
375 default: \
376 break; \
377 } \
378 }
379
380 #else
381 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
382 #define OP_LD_TABLE(width) \
383 static GenOpFunc * const gen_op_##width[] = { \
384 &gen_op_##width##_user, \
385 &gen_op_##width##_kernel, \
386 }; \
387 \
388 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
389 { \
390 int asi, offset; \
391 \
392 if (IS_IMM) { \
393 offset = GET_FIELD(insn, 25, 31); \
394 if (is_ld) \
395 gen_op_ld_asi_reg(offset, size, sign); \
396 else \
397 gen_op_st_asi_reg(offset, size, sign); \
398 return; \
399 } \
400 asi = GET_FIELD(insn, 19, 26); \
401 if (is_ld) \
402 gen_op_ld_asi(asi, size, sign); \
403 else \
404 gen_op_st_asi(asi, size, sign); \
405 }
406
407 #define supervisor(dc) (dc->mem_idx == 1)
408 #endif
409 #else
410 #if defined(CONFIG_USER_ONLY)
411 #define gen_op_ldst(name) gen_op_##name##_raw()
412 #define OP_LD_TABLE(width)
413 #define supervisor(dc) 0
414 #else
415 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
416 #define OP_LD_TABLE(width) \
417 static GenOpFunc * const gen_op_##width[] = { \
418 &gen_op_##width##_user, \
419 &gen_op_##width##_kernel, \
420 }; \
421 \
422 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
423 { \
424 int asi; \
425 \
426 asi = GET_FIELD(insn, 19, 26); \
427 switch (asi) { \
428 case 10: /* User data access */ \
429 gen_op_##width##_user(); \
430 break; \
431 case 11: /* Supervisor data access */ \
432 gen_op_##width##_kernel(); \
433 break; \
434 case 0x20 ... 0x2f: /* MMU passthrough */ \
435 if (is_ld) \
436 gen_op_ld_asi(asi, size, sign); \
437 else \
438 gen_op_st_asi(asi, size, sign); \
439 break; \
440 default: \
441 if (is_ld) \
442 gen_op_ld_asi(asi, size, sign); \
443 else \
444 gen_op_st_asi(asi, size, sign); \
445 break; \
446 } \
447 }
448
449 #define supervisor(dc) (dc->mem_idx == 1)
450 #endif
451 #endif
452
453 OP_LD_TABLE(ld);
454 OP_LD_TABLE(st);
455 OP_LD_TABLE(ldub);
456 OP_LD_TABLE(lduh);
457 OP_LD_TABLE(ldsb);
458 OP_LD_TABLE(ldsh);
459 OP_LD_TABLE(stb);
460 OP_LD_TABLE(sth);
461 OP_LD_TABLE(std);
462 OP_LD_TABLE(ldstub);
463 OP_LD_TABLE(swap);
464 OP_LD_TABLE(ldd);
465 OP_LD_TABLE(stf);
466 OP_LD_TABLE(stdf);
467 OP_LD_TABLE(ldf);
468 OP_LD_TABLE(lddf);
469
470 #ifdef TARGET_SPARC64
471 OP_LD_TABLE(ldsw);
472 OP_LD_TABLE(ldx);
473 OP_LD_TABLE(stx);
474 OP_LD_TABLE(cas);
475 OP_LD_TABLE(casx);
476 #endif
477
478 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
479 {
480 gen_op_movl_TN_im[reg](imm);
481 }
482
483 static inline void gen_movl_imm_T1(uint32_t val)
484 {
485 gen_movl_imm_TN(1, val);
486 }
487
488 static inline void gen_movl_imm_T0(uint32_t val)
489 {
490 gen_movl_imm_TN(0, val);
491 }
492
493 static inline void gen_movl_simm_TN(int reg, int32_t imm)
494 {
495 gen_op_movl_TN_sim[reg](imm);
496 }
497
498 static inline void gen_movl_simm_T1(int32_t val)
499 {
500 gen_movl_simm_TN(1, val);
501 }
502
503 static inline void gen_movl_simm_T0(int32_t val)
504 {
505 gen_movl_simm_TN(0, val);
506 }
507
508 static inline void gen_movl_reg_TN(int reg, int t)
509 {
510 if (reg)
511 gen_op_movl_reg_TN[t][reg] ();
512 else
513 gen_movl_imm_TN(t, 0);
514 }
515
516 static inline void gen_movl_reg_T0(int reg)
517 {
518 gen_movl_reg_TN(reg, 0);
519 }
520
521 static inline void gen_movl_reg_T1(int reg)
522 {
523 gen_movl_reg_TN(reg, 1);
524 }
525
526 static inline void gen_movl_reg_T2(int reg)
527 {
528 gen_movl_reg_TN(reg, 2);
529 }
530
531 static inline void gen_movl_TN_reg(int reg, int t)
532 {
533 if (reg)
534 gen_op_movl_TN_reg[t][reg] ();
535 }
536
537 static inline void gen_movl_T0_reg(int reg)
538 {
539 gen_movl_TN_reg(reg, 0);
540 }
541
542 static inline void gen_movl_T1_reg(int reg)
543 {
544 gen_movl_TN_reg(reg, 1);
545 }
546
547 static inline void gen_jmp_im(target_ulong pc)
548 {
549 #ifdef TARGET_SPARC64
550 if (pc == (uint32_t)pc) {
551 gen_op_jmp_im(pc);
552 } else {
553 gen_op_jmp_im64(pc >> 32, pc);
554 }
555 #else
556 gen_op_jmp_im(pc);
557 #endif
558 }
559
560 static inline void gen_movl_npc_im(target_ulong npc)
561 {
562 #ifdef TARGET_SPARC64
563 if (npc == (uint32_t)npc) {
564 gen_op_movl_npc_im(npc);
565 } else {
566 gen_op_movq_npc_im64(npc >> 32, npc);
567 }
568 #else
569 gen_op_movl_npc_im(npc);
570 #endif
571 }
572
573 static inline void gen_goto_tb(DisasContext *s, int tb_num,
574 target_ulong pc, target_ulong npc)
575 {
576 TranslationBlock *tb;
577
578 tb = s->tb;
579 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
580 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
581 /* jump to same page: we can use a direct jump */
582 if (tb_num == 0)
583 gen_op_goto_tb0(TBPARAM(tb));
584 else
585 gen_op_goto_tb1(TBPARAM(tb));
586 gen_jmp_im(pc);
587 gen_movl_npc_im(npc);
588 gen_op_movl_T0_im((long)tb + tb_num);
589 gen_op_exit_tb();
590 } else {
591 /* jump to another page: currently not optimized */
592 gen_jmp_im(pc);
593 gen_movl_npc_im(npc);
594 gen_op_movl_T0_0();
595 gen_op_exit_tb();
596 }
597 }
598
599 static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
600 {
601 int l1;
602
603 l1 = gen_new_label();
604
605 gen_op_jz_T2_label(l1);
606
607 gen_goto_tb(dc, 0, pc1, pc1 + 4);
608
609 gen_set_label(l1);
610 gen_goto_tb(dc, 1, pc2, pc2 + 4);
611 }
612
613 static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
614 {
615 int l1;
616
617 l1 = gen_new_label();
618
619 gen_op_jz_T2_label(l1);
620
621 gen_goto_tb(dc, 0, pc2, pc1);
622
623 gen_set_label(l1);
624 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
625 }
626
627 static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
628 {
629 gen_goto_tb(dc, 0, pc, npc);
630 }
631
632 static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
633 {
634 int l1, l2;
635
636 l1 = gen_new_label();
637 l2 = gen_new_label();
638 gen_op_jz_T2_label(l1);
639
640 gen_movl_npc_im(npc1);
641 gen_op_jmp_label(l2);
642
643 gen_set_label(l1);
644 gen_movl_npc_im(npc2);
645 gen_set_label(l2);
646 }
647
648 /* call this function before using T2 as it may have been set for a jump */
649 static inline void flush_T2(DisasContext * dc)
650 {
651 if (dc->npc == JUMP_PC) {
652 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
653 dc->npc = DYNAMIC_PC;
654 }
655 }
656
657 static inline void save_npc(DisasContext * dc)
658 {
659 if (dc->npc == JUMP_PC) {
660 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
661 dc->npc = DYNAMIC_PC;
662 } else if (dc->npc != DYNAMIC_PC) {
663 gen_movl_npc_im(dc->npc);
664 }
665 }
666
667 static inline void save_state(DisasContext * dc)
668 {
669 gen_jmp_im(dc->pc);
670 save_npc(dc);
671 }
672
673 static inline void gen_mov_pc_npc(DisasContext * dc)
674 {
675 if (dc->npc == JUMP_PC) {
676 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
677 gen_op_mov_pc_npc();
678 dc->pc = DYNAMIC_PC;
679 } else if (dc->npc == DYNAMIC_PC) {
680 gen_op_mov_pc_npc();
681 dc->pc = DYNAMIC_PC;
682 } else {
683 dc->pc = dc->npc;
684 }
685 }
686
687 static GenOpFunc * const gen_cond[2][16] = {
688 {
689 gen_op_eval_bn,
690 gen_op_eval_be,
691 gen_op_eval_ble,
692 gen_op_eval_bl,
693 gen_op_eval_bleu,
694 gen_op_eval_bcs,
695 gen_op_eval_bneg,
696 gen_op_eval_bvs,
697 gen_op_eval_ba,
698 gen_op_eval_bne,
699 gen_op_eval_bg,
700 gen_op_eval_bge,
701 gen_op_eval_bgu,
702 gen_op_eval_bcc,
703 gen_op_eval_bpos,
704 gen_op_eval_bvc,
705 },
706 {
707 #ifdef TARGET_SPARC64
708 gen_op_eval_bn,
709 gen_op_eval_xbe,
710 gen_op_eval_xble,
711 gen_op_eval_xbl,
712 gen_op_eval_xbleu,
713 gen_op_eval_xbcs,
714 gen_op_eval_xbneg,
715 gen_op_eval_xbvs,
716 gen_op_eval_ba,
717 gen_op_eval_xbne,
718 gen_op_eval_xbg,
719 gen_op_eval_xbge,
720 gen_op_eval_xbgu,
721 gen_op_eval_xbcc,
722 gen_op_eval_xbpos,
723 gen_op_eval_xbvc,
724 #endif
725 },
726 };
727
728 static GenOpFunc * const gen_fcond[4][16] = {
729 {
730 gen_op_eval_bn,
731 gen_op_eval_fbne,
732 gen_op_eval_fblg,
733 gen_op_eval_fbul,
734 gen_op_eval_fbl,
735 gen_op_eval_fbug,
736 gen_op_eval_fbg,
737 gen_op_eval_fbu,
738 gen_op_eval_ba,
739 gen_op_eval_fbe,
740 gen_op_eval_fbue,
741 gen_op_eval_fbge,
742 gen_op_eval_fbuge,
743 gen_op_eval_fble,
744 gen_op_eval_fbule,
745 gen_op_eval_fbo,
746 },
747 #ifdef TARGET_SPARC64
748 {
749 gen_op_eval_bn,
750 gen_op_eval_fbne_fcc1,
751 gen_op_eval_fblg_fcc1,
752 gen_op_eval_fbul_fcc1,
753 gen_op_eval_fbl_fcc1,
754 gen_op_eval_fbug_fcc1,
755 gen_op_eval_fbg_fcc1,
756 gen_op_eval_fbu_fcc1,
757 gen_op_eval_ba,
758 gen_op_eval_fbe_fcc1,
759 gen_op_eval_fbue_fcc1,
760 gen_op_eval_fbge_fcc1,
761 gen_op_eval_fbuge_fcc1,
762 gen_op_eval_fble_fcc1,
763 gen_op_eval_fbule_fcc1,
764 gen_op_eval_fbo_fcc1,
765 },
766 {
767 gen_op_eval_bn,
768 gen_op_eval_fbne_fcc2,
769 gen_op_eval_fblg_fcc2,
770 gen_op_eval_fbul_fcc2,
771 gen_op_eval_fbl_fcc2,
772 gen_op_eval_fbug_fcc2,
773 gen_op_eval_fbg_fcc2,
774 gen_op_eval_fbu_fcc2,
775 gen_op_eval_ba,
776 gen_op_eval_fbe_fcc2,
777 gen_op_eval_fbue_fcc2,
778 gen_op_eval_fbge_fcc2,
779 gen_op_eval_fbuge_fcc2,
780 gen_op_eval_fble_fcc2,
781 gen_op_eval_fbule_fcc2,
782 gen_op_eval_fbo_fcc2,
783 },
784 {
785 gen_op_eval_bn,
786 gen_op_eval_fbne_fcc3,
787 gen_op_eval_fblg_fcc3,
788 gen_op_eval_fbul_fcc3,
789 gen_op_eval_fbl_fcc3,
790 gen_op_eval_fbug_fcc3,
791 gen_op_eval_fbg_fcc3,
792 gen_op_eval_fbu_fcc3,
793 gen_op_eval_ba,
794 gen_op_eval_fbe_fcc3,
795 gen_op_eval_fbue_fcc3,
796 gen_op_eval_fbge_fcc3,
797 gen_op_eval_fbuge_fcc3,
798 gen_op_eval_fble_fcc3,
799 gen_op_eval_fbule_fcc3,
800 gen_op_eval_fbo_fcc3,
801 },
802 #else
803 {}, {}, {},
804 #endif
805 };
806
807 #ifdef TARGET_SPARC64
808 static void gen_cond_reg(int cond)
809 {
810 switch (cond) {
811 case 0x1:
812 gen_op_eval_brz();
813 break;
814 case 0x2:
815 gen_op_eval_brlez();
816 break;
817 case 0x3:
818 gen_op_eval_brlz();
819 break;
820 case 0x5:
821 gen_op_eval_brnz();
822 break;
823 case 0x6:
824 gen_op_eval_brgz();
825 break;
826 default:
827 case 0x7:
828 gen_op_eval_brgez();
829 break;
830 }
831 }
832 #endif
833
834 /* XXX: potentially incorrect if dynamic npc */
835 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
836 {
837 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
838 target_ulong target = dc->pc + offset;
839
840 if (cond == 0x0) {
841 /* unconditional not taken */
842 if (a) {
843 dc->pc = dc->npc + 4;
844 dc->npc = dc->pc + 4;
845 } else {
846 dc->pc = dc->npc;
847 dc->npc = dc->pc + 4;
848 }
849 } else if (cond == 0x8) {
850 /* unconditional taken */
851 if (a) {
852 dc->pc = target;
853 dc->npc = dc->pc + 4;
854 } else {
855 dc->pc = dc->npc;
856 dc->npc = target;
857 }
858 } else {
859 flush_T2(dc);
860 gen_cond[cc][cond]();
861 if (a) {
862 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
863 dc->is_br = 1;
864 } else {
865 dc->pc = dc->npc;
866 dc->jump_pc[0] = target;
867 dc->jump_pc[1] = dc->npc + 4;
868 dc->npc = JUMP_PC;
869 }
870 }
871 }
872
873 /* XXX: potentially incorrect if dynamic npc */
874 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
875 {
876 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
877 target_ulong target = dc->pc + offset;
878
879 if (cond == 0x0) {
880 /* unconditional not taken */
881 if (a) {
882 dc->pc = dc->npc + 4;
883 dc->npc = dc->pc + 4;
884 } else {
885 dc->pc = dc->npc;
886 dc->npc = dc->pc + 4;
887 }
888 } else if (cond == 0x8) {
889 /* unconditional taken */
890 if (a) {
891 dc->pc = target;
892 dc->npc = dc->pc + 4;
893 } else {
894 dc->pc = dc->npc;
895 dc->npc = target;
896 }
897 } else {
898 flush_T2(dc);
899 gen_fcond[cc][cond]();
900 if (a) {
901 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
902 dc->is_br = 1;
903 } else {
904 dc->pc = dc->npc;
905 dc->jump_pc[0] = target;
906 dc->jump_pc[1] = dc->npc + 4;
907 dc->npc = JUMP_PC;
908 }
909 }
910 }
911
912 #ifdef TARGET_SPARC64
913 /* XXX: potentially incorrect if dynamic npc */
914 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
915 {
916 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
917 target_ulong target = dc->pc + offset;
918
919 flush_T2(dc);
920 gen_cond_reg(cond);
921 if (a) {
922 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
923 dc->is_br = 1;
924 } else {
925 dc->pc = dc->npc;
926 dc->jump_pc[0] = target;
927 dc->jump_pc[1] = dc->npc + 4;
928 dc->npc = JUMP_PC;
929 }
930 }
931
932 static GenOpFunc * const gen_fcmps[4] = {
933 gen_op_fcmps,
934 gen_op_fcmps_fcc1,
935 gen_op_fcmps_fcc2,
936 gen_op_fcmps_fcc3,
937 };
938
939 static GenOpFunc * const gen_fcmpd[4] = {
940 gen_op_fcmpd,
941 gen_op_fcmpd_fcc1,
942 gen_op_fcmpd_fcc2,
943 gen_op_fcmpd_fcc3,
944 };
945
946 static GenOpFunc * const gen_fcmpes[4] = {
947 gen_op_fcmpes,
948 gen_op_fcmpes_fcc1,
949 gen_op_fcmpes_fcc2,
950 gen_op_fcmpes_fcc3,
951 };
952
953 static GenOpFunc * const gen_fcmped[4] = {
954 gen_op_fcmped,
955 gen_op_fcmped_fcc1,
956 gen_op_fcmped_fcc2,
957 gen_op_fcmped_fcc3,
958 };
959
960 #endif
961
962 static int gen_trap_ifnofpu(DisasContext * dc)
963 {
964 #if !defined(CONFIG_USER_ONLY)
965 if (!dc->fpu_enabled) {
966 save_state(dc);
967 gen_op_exception(TT_NFPU_INSN);
968 dc->is_br = 1;
969 return 1;
970 }
971 #endif
972 return 0;
973 }
974
975 /* before an instruction, dc->pc must be static */
976 static void disas_sparc_insn(DisasContext * dc)
977 {
978 unsigned int insn, opc, rs1, rs2, rd;
979
980 insn = ldl_code(dc->pc);
981 opc = GET_FIELD(insn, 0, 1);
982
983 rd = GET_FIELD(insn, 2, 6);
984 switch (opc) {
985 case 0: /* branches/sethi */
986 {
987 unsigned int xop = GET_FIELD(insn, 7, 9);
988 int32_t target;
989 switch (xop) {
990 #ifdef TARGET_SPARC64
991 case 0x1: /* V9 BPcc */
992 {
993 int cc;
994
995 target = GET_FIELD_SP(insn, 0, 18);
996 target = sign_extend(target, 18);
997 target <<= 2;
998 cc = GET_FIELD_SP(insn, 20, 21);
999 if (cc == 0)
1000 do_branch(dc, target, insn, 0);
1001 else if (cc == 2)
1002 do_branch(dc, target, insn, 1);
1003 else
1004 goto illegal_insn;
1005 goto jmp_insn;
1006 }
1007 case 0x3: /* V9 BPr */
1008 {
1009 target = GET_FIELD_SP(insn, 0, 13) |
1010 (GET_FIELD_SP(insn, 20, 21) << 14);
1011 target = sign_extend(target, 16);
1012 target <<= 2;
1013 rs1 = GET_FIELD(insn, 13, 17);
1014 gen_movl_reg_T0(rs1);
1015 do_branch_reg(dc, target, insn);
1016 goto jmp_insn;
1017 }
1018 case 0x5: /* V9 FBPcc */
1019 {
1020 int cc = GET_FIELD_SP(insn, 20, 21);
1021 if (gen_trap_ifnofpu(dc))
1022 goto jmp_insn;
1023 target = GET_FIELD_SP(insn, 0, 18);
1024 target = sign_extend(target, 19);
1025 target <<= 2;
1026 do_fbranch(dc, target, insn, cc);
1027 goto jmp_insn;
1028 }
1029 #else
1030 case 0x7: /* CBN+x */
1031 {
1032 goto ncp_insn;
1033 }
1034 #endif
1035 case 0x2: /* BN+x */
1036 {
1037 target = GET_FIELD(insn, 10, 31);
1038 target = sign_extend(target, 22);
1039 target <<= 2;
1040 do_branch(dc, target, insn, 0);
1041 goto jmp_insn;
1042 }
1043 case 0x6: /* FBN+x */
1044 {
1045 if (gen_trap_ifnofpu(dc))
1046 goto jmp_insn;
1047 target = GET_FIELD(insn, 10, 31);
1048 target = sign_extend(target, 22);
1049 target <<= 2;
1050 do_fbranch(dc, target, insn, 0);
1051 goto jmp_insn;
1052 }
1053 case 0x4: /* SETHI */
1054 #define OPTIM
1055 #if defined(OPTIM)
1056 if (rd) { // nop
1057 #endif
1058 uint32_t value = GET_FIELD(insn, 10, 31);
1059 gen_movl_imm_T0(value << 10);
1060 gen_movl_T0_reg(rd);
1061 #if defined(OPTIM)
1062 }
1063 #endif
1064 break;
1065 case 0x0: /* UNIMPL */
1066 default:
1067 goto illegal_insn;
1068 }
1069 break;
1070 }
1071 break;
1072 case 1:
1073 /*CALL*/ {
1074 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1075
1076 #ifdef TARGET_SPARC64
1077 if (dc->pc == (uint32_t)dc->pc) {
1078 gen_op_movl_T0_im(dc->pc);
1079 } else {
1080 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1081 }
1082 #else
1083 gen_op_movl_T0_im(dc->pc);
1084 #endif
1085 gen_movl_T0_reg(15);
1086 target += dc->pc;
1087 gen_mov_pc_npc(dc);
1088 dc->npc = target;
1089 }
1090 goto jmp_insn;
1091 case 2: /* FPU & Logical Operations */
1092 {
1093 unsigned int xop = GET_FIELD(insn, 7, 12);
1094 if (xop == 0x3a) { /* generate trap */
1095 int cond;
1096
1097 rs1 = GET_FIELD(insn, 13, 17);
1098 gen_movl_reg_T0(rs1);
1099 if (IS_IMM) {
1100 rs2 = GET_FIELD(insn, 25, 31);
1101 #if defined(OPTIM)
1102 if (rs2 != 0) {
1103 #endif
1104 gen_movl_simm_T1(rs2);
1105 gen_op_add_T1_T0();
1106 #if defined(OPTIM)
1107 }
1108 #endif
1109 } else {
1110 rs2 = GET_FIELD(insn, 27, 31);
1111 #if defined(OPTIM)
1112 if (rs2 != 0) {
1113 #endif
1114 gen_movl_reg_T1(rs2);
1115 gen_op_add_T1_T0();
1116 #if defined(OPTIM)
1117 }
1118 #endif
1119 }
1120 cond = GET_FIELD(insn, 3, 6);
1121 if (cond == 0x8) {
1122 save_state(dc);
1123 gen_op_trap_T0();
1124 } else if (cond != 0) {
1125 #ifdef TARGET_SPARC64
1126 /* V9 icc/xcc */
1127 int cc = GET_FIELD_SP(insn, 11, 12);
1128 flush_T2(dc);
1129 save_state(dc);
1130 if (cc == 0)
1131 gen_cond[0][cond]();
1132 else if (cc == 2)
1133 gen_cond[1][cond]();
1134 else
1135 goto illegal_insn;
1136 #else
1137 flush_T2(dc);
1138 save_state(dc);
1139 gen_cond[0][cond]();
1140 #endif
1141 gen_op_trapcc_T0();
1142 }
1143 gen_op_next_insn();
1144 gen_op_movl_T0_0();
1145 gen_op_exit_tb();
1146 dc->is_br = 1;
1147 goto jmp_insn;
1148 } else if (xop == 0x28) {
1149 rs1 = GET_FIELD(insn, 13, 17);
1150 switch(rs1) {
1151 case 0: /* rdy */
1152 #ifndef TARGET_SPARC64
1153 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1154 manual, rdy on the microSPARC
1155 II */
1156 case 0x0f: /* stbar in the SPARCv8 manual,
1157 rdy on the microSPARC II */
1158 case 0x10 ... 0x1f: /* implementation-dependent in the
1159 SPARCv8 manual, rdy on the
1160 microSPARC II */
1161 #endif
1162 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1163 gen_movl_T0_reg(rd);
1164 break;
1165 #ifdef TARGET_SPARC64
1166 case 0x2: /* V9 rdccr */
1167 gen_op_rdccr();
1168 gen_movl_T0_reg(rd);
1169 break;
1170 case 0x3: /* V9 rdasi */
1171 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1172 gen_movl_T0_reg(rd);
1173 break;
1174 case 0x4: /* V9 rdtick */
1175 gen_op_rdtick();
1176 gen_movl_T0_reg(rd);
1177 break;
1178 case 0x5: /* V9 rdpc */
1179 if (dc->pc == (uint32_t)dc->pc) {
1180 gen_op_movl_T0_im(dc->pc);
1181 } else {
1182 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1183 }
1184 gen_movl_T0_reg(rd);
1185 break;
1186 case 0x6: /* V9 rdfprs */
1187 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1188 gen_movl_T0_reg(rd);
1189 break;
1190 case 0xf: /* V9 membar */
1191 break; /* no effect */
1192 case 0x13: /* Graphics Status */
1193 if (gen_trap_ifnofpu(dc))
1194 goto jmp_insn;
1195 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1196 gen_movl_T0_reg(rd);
1197 break;
1198 case 0x17: /* Tick compare */
1199 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1200 gen_movl_T0_reg(rd);
1201 break;
1202 case 0x18: /* System tick */
1203 gen_op_rdtick(); // XXX
1204 gen_movl_T0_reg(rd);
1205 break;
1206 case 0x19: /* System tick compare */
1207 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1208 gen_movl_T0_reg(rd);
1209 break;
1210 case 0x10: /* Performance Control */
1211 case 0x11: /* Performance Instrumentation Counter */
1212 case 0x12: /* Dispatch Control */
1213 case 0x14: /* Softint set, WO */
1214 case 0x15: /* Softint clear, WO */
1215 case 0x16: /* Softint write */
1216 #endif
1217 default:
1218 goto illegal_insn;
1219 }
1220 #if !defined(CONFIG_USER_ONLY)
1221 #ifndef TARGET_SPARC64
1222 } else if (xop == 0x29) { /* rdpsr / V9 unimp */
1223 if (!supervisor(dc))
1224 goto priv_insn;
1225 gen_op_rdpsr();
1226 gen_movl_T0_reg(rd);
1227 break;
1228 #endif
1229 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1230 if (!supervisor(dc))
1231 goto priv_insn;
1232 #ifdef TARGET_SPARC64
1233 rs1 = GET_FIELD(insn, 13, 17);
1234 switch (rs1) {
1235 case 0: // tpc
1236 gen_op_rdtpc();
1237 break;
1238 case 1: // tnpc
1239 gen_op_rdtnpc();
1240 break;
1241 case 2: // tstate
1242 gen_op_rdtstate();
1243 break;
1244 case 3: // tt
1245 gen_op_rdtt();
1246 break;
1247 case 4: // tick
1248 gen_op_rdtick();
1249 break;
1250 case 5: // tba
1251 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1252 break;
1253 case 6: // pstate
1254 gen_op_rdpstate();
1255 break;
1256 case 7: // tl
1257 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1258 break;
1259 case 8: // pil
1260 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1261 break;
1262 case 9: // cwp
1263 gen_op_rdcwp();
1264 break;
1265 case 10: // cansave
1266 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1267 break;
1268 case 11: // canrestore
1269 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1270 break;
1271 case 12: // cleanwin
1272 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1273 break;
1274 case 13: // otherwin
1275 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1276 break;
1277 case 14: // wstate
1278 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1279 break;
1280 case 31: // ver
1281 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1282 break;
1283 case 15: // fq
1284 default:
1285 goto illegal_insn;
1286 }
1287 #else
1288 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1289 #endif
1290 gen_movl_T0_reg(rd);
1291 break;
1292 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1293 #ifdef TARGET_SPARC64
1294 gen_op_flushw();
1295 #else
1296 if (!supervisor(dc))
1297 goto priv_insn;
1298 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1299 gen_movl_T0_reg(rd);
1300 #endif
1301 break;
1302 #endif
1303 } else if (xop == 0x34) { /* FPU Operations */
1304 if (gen_trap_ifnofpu(dc))
1305 goto jmp_insn;
1306 gen_op_clear_ieee_excp_and_FTT();
1307 rs1 = GET_FIELD(insn, 13, 17);
1308 rs2 = GET_FIELD(insn, 27, 31);
1309 xop = GET_FIELD(insn, 18, 26);
1310 switch (xop) {
1311 case 0x1: /* fmovs */
1312 gen_op_load_fpr_FT0(rs2);
1313 gen_op_store_FT0_fpr(rd);
1314 break;
1315 case 0x5: /* fnegs */
1316 gen_op_load_fpr_FT1(rs2);
1317 gen_op_fnegs();
1318 gen_op_store_FT0_fpr(rd);
1319 break;
1320 case 0x9: /* fabss */
1321 gen_op_load_fpr_FT1(rs2);
1322 gen_op_fabss();
1323 gen_op_store_FT0_fpr(rd);
1324 break;
1325 case 0x29: /* fsqrts */
1326 gen_op_load_fpr_FT1(rs2);
1327 gen_op_fsqrts();
1328 gen_op_store_FT0_fpr(rd);
1329 break;
1330 case 0x2a: /* fsqrtd */
1331 gen_op_load_fpr_DT1(DFPREG(rs2));
1332 gen_op_fsqrtd();
1333 gen_op_store_DT0_fpr(DFPREG(rd));
1334 break;
1335 case 0x2b: /* fsqrtq */
1336 goto nfpu_insn;
1337 case 0x41:
1338 gen_op_load_fpr_FT0(rs1);
1339 gen_op_load_fpr_FT1(rs2);
1340 gen_op_fadds();
1341 gen_op_store_FT0_fpr(rd);
1342 break;
1343 case 0x42:
1344 gen_op_load_fpr_DT0(DFPREG(rs1));
1345 gen_op_load_fpr_DT1(DFPREG(rs2));
1346 gen_op_faddd();
1347 gen_op_store_DT0_fpr(DFPREG(rd));
1348 break;
1349 case 0x43: /* faddq */
1350 goto nfpu_insn;
1351 case 0x45:
1352 gen_op_load_fpr_FT0(rs1);
1353 gen_op_load_fpr_FT1(rs2);
1354 gen_op_fsubs();
1355 gen_op_store_FT0_fpr(rd);
1356 break;
1357 case 0x46:
1358 gen_op_load_fpr_DT0(DFPREG(rs1));
1359 gen_op_load_fpr_DT1(DFPREG(rs2));
1360 gen_op_fsubd();
1361 gen_op_store_DT0_fpr(DFPREG(rd));
1362 break;
1363 case 0x47: /* fsubq */
1364 goto nfpu_insn;
1365 case 0x49:
1366 gen_op_load_fpr_FT0(rs1);
1367 gen_op_load_fpr_FT1(rs2);
1368 gen_op_fmuls();
1369 gen_op_store_FT0_fpr(rd);
1370 break;
1371 case 0x4a:
1372 gen_op_load_fpr_DT0(DFPREG(rs1));
1373 gen_op_load_fpr_DT1(DFPREG(rs2));
1374 gen_op_fmuld();
1375 gen_op_store_DT0_fpr(rd);
1376 break;
1377 case 0x4b: /* fmulq */
1378 goto nfpu_insn;
1379 case 0x4d:
1380 gen_op_load_fpr_FT0(rs1);
1381 gen_op_load_fpr_FT1(rs2);
1382 gen_op_fdivs();
1383 gen_op_store_FT0_fpr(rd);
1384 break;
1385 case 0x4e:
1386 gen_op_load_fpr_DT0(DFPREG(rs1));
1387 gen_op_load_fpr_DT1(DFPREG(rs2));
1388 gen_op_fdivd();
1389 gen_op_store_DT0_fpr(DFPREG(rd));
1390 break;
1391 case 0x4f: /* fdivq */
1392 goto nfpu_insn;
1393 case 0x69:
1394 gen_op_load_fpr_FT0(rs1);
1395 gen_op_load_fpr_FT1(rs2);
1396 gen_op_fsmuld();
1397 gen_op_store_DT0_fpr(DFPREG(rd));
1398 break;
1399 case 0x6e: /* fdmulq */
1400 goto nfpu_insn;
1401 case 0xc4:
1402 gen_op_load_fpr_FT1(rs2);
1403 gen_op_fitos();
1404 gen_op_store_FT0_fpr(rd);
1405 break;
1406 case 0xc6:
1407 gen_op_load_fpr_DT1(DFPREG(rs2));
1408 gen_op_fdtos();
1409 gen_op_store_FT0_fpr(rd);
1410 break;
1411 case 0xc7: /* fqtos */
1412 goto nfpu_insn;
1413 case 0xc8:
1414 gen_op_load_fpr_FT1(rs2);
1415 gen_op_fitod();
1416 gen_op_store_DT0_fpr(DFPREG(rd));
1417 break;
1418 case 0xc9:
1419 gen_op_load_fpr_FT1(rs2);
1420 gen_op_fstod();
1421 gen_op_store_DT0_fpr(DFPREG(rd));
1422 break;
1423 case 0xcb: /* fqtod */
1424 goto nfpu_insn;
1425 case 0xcc: /* fitoq */
1426 goto nfpu_insn;
1427 case 0xcd: /* fstoq */
1428 goto nfpu_insn;
1429 case 0xce: /* fdtoq */
1430 goto nfpu_insn;
1431 case 0xd1:
1432 gen_op_load_fpr_FT1(rs2);
1433 gen_op_fstoi();
1434 gen_op_store_FT0_fpr(rd);
1435 break;
1436 case 0xd2:
1437 gen_op_load_fpr_DT1(rs2);
1438 gen_op_fdtoi();
1439 gen_op_store_FT0_fpr(rd);
1440 break;
1441 case 0xd3: /* fqtoi */
1442 goto nfpu_insn;
1443 #ifdef TARGET_SPARC64
1444 case 0x2: /* V9 fmovd */
1445 gen_op_load_fpr_DT0(DFPREG(rs2));
1446 gen_op_store_DT0_fpr(DFPREG(rd));
1447 break;
1448 case 0x6: /* V9 fnegd */
1449 gen_op_load_fpr_DT1(DFPREG(rs2));
1450 gen_op_fnegd();
1451 gen_op_store_DT0_fpr(DFPREG(rd));
1452 break;
1453 case 0xa: /* V9 fabsd */
1454 gen_op_load_fpr_DT1(DFPREG(rs2));
1455 gen_op_fabsd();
1456 gen_op_store_DT0_fpr(DFPREG(rd));
1457 break;
1458 case 0x81: /* V9 fstox */
1459 gen_op_load_fpr_FT1(rs2);
1460 gen_op_fstox();
1461 gen_op_store_DT0_fpr(DFPREG(rd));
1462 break;
1463 case 0x82: /* V9 fdtox */
1464 gen_op_load_fpr_DT1(DFPREG(rs2));
1465 gen_op_fdtox();
1466 gen_op_store_DT0_fpr(DFPREG(rd));
1467 break;
1468 case 0x84: /* V9 fxtos */
1469 gen_op_load_fpr_DT1(DFPREG(rs2));
1470 gen_op_fxtos();
1471 gen_op_store_FT0_fpr(rd);
1472 break;
1473 case 0x88: /* V9 fxtod */
1474 gen_op_load_fpr_DT1(DFPREG(rs2));
1475 gen_op_fxtod();
1476 gen_op_store_DT0_fpr(DFPREG(rd));
1477 break;
1478 case 0x3: /* V9 fmovq */
1479 case 0x7: /* V9 fnegq */
1480 case 0xb: /* V9 fabsq */
1481 case 0x83: /* V9 fqtox */
1482 case 0x8c: /* V9 fxtoq */
1483 goto nfpu_insn;
1484 #endif
1485 default:
1486 goto illegal_insn;
1487 }
1488 } else if (xop == 0x35) { /* FPU Operations */
1489 #ifdef TARGET_SPARC64
1490 int cond;
1491 #endif
1492 if (gen_trap_ifnofpu(dc))
1493 goto jmp_insn;
1494 gen_op_clear_ieee_excp_and_FTT();
1495 rs1 = GET_FIELD(insn, 13, 17);
1496 rs2 = GET_FIELD(insn, 27, 31);
1497 xop = GET_FIELD(insn, 18, 26);
1498 #ifdef TARGET_SPARC64
1499 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1500 cond = GET_FIELD_SP(insn, 14, 17);
1501 gen_op_load_fpr_FT0(rd);
1502 gen_op_load_fpr_FT1(rs2);
1503 rs1 = GET_FIELD(insn, 13, 17);
1504 gen_movl_reg_T0(rs1);
1505 flush_T2(dc);
1506 gen_cond_reg(cond);
1507 gen_op_fmovs_cc();
1508 gen_op_store_FT0_fpr(rd);
1509 break;
1510 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1511 cond = GET_FIELD_SP(insn, 14, 17);
1512 gen_op_load_fpr_DT0(rd);
1513 gen_op_load_fpr_DT1(rs2);
1514 flush_T2(dc);
1515 rs1 = GET_FIELD(insn, 13, 17);
1516 gen_movl_reg_T0(rs1);
1517 gen_cond_reg(cond);
1518 gen_op_fmovs_cc();
1519 gen_op_store_DT0_fpr(rd);
1520 break;
1521 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1522 goto nfpu_insn;
1523 }
1524 #endif
1525 switch (xop) {
1526 #ifdef TARGET_SPARC64
1527 case 0x001: /* V9 fmovscc %fcc0 */
1528 cond = GET_FIELD_SP(insn, 14, 17);
1529 gen_op_load_fpr_FT0(rd);
1530 gen_op_load_fpr_FT1(rs2);
1531 flush_T2(dc);
1532 gen_fcond[0][cond]();
1533 gen_op_fmovs_cc();
1534 gen_op_store_FT0_fpr(rd);
1535 break;
1536 case 0x002: /* V9 fmovdcc %fcc0 */
1537 cond = GET_FIELD_SP(insn, 14, 17);
1538 gen_op_load_fpr_DT0(rd);
1539 gen_op_load_fpr_DT1(rs2);
1540 flush_T2(dc);
1541 gen_fcond[0][cond]();
1542 gen_op_fmovd_cc();
1543 gen_op_store_DT0_fpr(rd);
1544 break;
1545 case 0x003: /* V9 fmovqcc %fcc0 */
1546 goto nfpu_insn;
1547 case 0x041: /* V9 fmovscc %fcc1 */
1548 cond = GET_FIELD_SP(insn, 14, 17);
1549 gen_op_load_fpr_FT0(rd);
1550 gen_op_load_fpr_FT1(rs2);
1551 flush_T2(dc);
1552 gen_fcond[1][cond]();
1553 gen_op_fmovs_cc();
1554 gen_op_store_FT0_fpr(rd);
1555 break;
1556 case 0x042: /* V9 fmovdcc %fcc1 */
1557 cond = GET_FIELD_SP(insn, 14, 17);
1558 gen_op_load_fpr_DT0(rd);
1559 gen_op_load_fpr_DT1(rs2);
1560 flush_T2(dc);
1561 gen_fcond[1][cond]();
1562 gen_op_fmovd_cc();
1563 gen_op_store_DT0_fpr(rd);
1564 break;
1565 case 0x043: /* V9 fmovqcc %fcc1 */
1566 goto nfpu_insn;
1567 case 0x081: /* V9 fmovscc %fcc2 */
1568 cond = GET_FIELD_SP(insn, 14, 17);
1569 gen_op_load_fpr_FT0(rd);
1570 gen_op_load_fpr_FT1(rs2);
1571 flush_T2(dc);
1572 gen_fcond[2][cond]();
1573 gen_op_fmovs_cc();
1574 gen_op_store_FT0_fpr(rd);
1575 break;
1576 case 0x082: /* V9 fmovdcc %fcc2 */
1577 cond = GET_FIELD_SP(insn, 14, 17);
1578 gen_op_load_fpr_DT0(rd);
1579 gen_op_load_fpr_DT1(rs2);
1580 flush_T2(dc);
1581 gen_fcond[2][cond]();
1582 gen_op_fmovd_cc();
1583 gen_op_store_DT0_fpr(rd);
1584 break;
1585 case 0x083: /* V9 fmovqcc %fcc2 */
1586 goto nfpu_insn;
1587 case 0x0c1: /* V9 fmovscc %fcc3 */
1588 cond = GET_FIELD_SP(insn, 14, 17);
1589 gen_op_load_fpr_FT0(rd);
1590 gen_op_load_fpr_FT1(rs2);
1591 flush_T2(dc);
1592 gen_fcond[3][cond]();
1593 gen_op_fmovs_cc();
1594 gen_op_store_FT0_fpr(rd);
1595 break;
1596 case 0x0c2: /* V9 fmovdcc %fcc3 */
1597 cond = GET_FIELD_SP(insn, 14, 17);
1598 gen_op_load_fpr_DT0(rd);
1599 gen_op_load_fpr_DT1(rs2);
1600 flush_T2(dc);
1601 gen_fcond[3][cond]();
1602 gen_op_fmovd_cc();
1603 gen_op_store_DT0_fpr(rd);
1604 break;
1605 case 0x0c3: /* V9 fmovqcc %fcc3 */
1606 goto nfpu_insn;
1607 case 0x101: /* V9 fmovscc %icc */
1608 cond = GET_FIELD_SP(insn, 14, 17);
1609 gen_op_load_fpr_FT0(rd);
1610 gen_op_load_fpr_FT1(rs2);
1611 flush_T2(dc);
1612 gen_cond[0][cond]();
1613 gen_op_fmovs_cc();
1614 gen_op_store_FT0_fpr(rd);
1615 break;
1616 case 0x102: /* V9 fmovdcc %icc */
1617 cond = GET_FIELD_SP(insn, 14, 17);
1618 gen_op_load_fpr_DT0(rd);
1619 gen_op_load_fpr_DT1(rs2);
1620 flush_T2(dc);
1621 gen_cond[0][cond]();
1622 gen_op_fmovd_cc();
1623 gen_op_store_DT0_fpr(rd);
1624 break;
1625 case 0x103: /* V9 fmovqcc %icc */
1626 goto nfpu_insn;
1627 case 0x181: /* V9 fmovscc %xcc */
1628 cond = GET_FIELD_SP(insn, 14, 17);
1629 gen_op_load_fpr_FT0(rd);
1630 gen_op_load_fpr_FT1(rs2);
1631 flush_T2(dc);
1632 gen_cond[1][cond]();
1633 gen_op_fmovs_cc();
1634 gen_op_store_FT0_fpr(rd);
1635 break;
1636 case 0x182: /* V9 fmovdcc %xcc */
1637 cond = GET_FIELD_SP(insn, 14, 17);
1638 gen_op_load_fpr_DT0(rd);
1639 gen_op_load_fpr_DT1(rs2);
1640 flush_T2(dc);
1641 gen_cond[1][cond]();
1642 gen_op_fmovd_cc();
1643 gen_op_store_DT0_fpr(rd);
1644 break;
1645 case 0x183: /* V9 fmovqcc %xcc */
1646 goto nfpu_insn;
1647 #endif
1648 case 0x51: /* V9 %fcc */
1649 gen_op_load_fpr_FT0(rs1);
1650 gen_op_load_fpr_FT1(rs2);
1651 #ifdef TARGET_SPARC64
1652 gen_fcmps[rd & 3]();
1653 #else
1654 gen_op_fcmps();
1655 #endif
1656 break;
1657 case 0x52: /* V9 %fcc */
1658 gen_op_load_fpr_DT0(DFPREG(rs1));
1659 gen_op_load_fpr_DT1(DFPREG(rs2));
1660 #ifdef TARGET_SPARC64
1661 gen_fcmpd[rd & 3]();
1662 #else
1663 gen_op_fcmpd();
1664 #endif
1665 break;
1666 case 0x53: /* fcmpq */
1667 goto nfpu_insn;
1668 case 0x55: /* fcmpes, V9 %fcc */
1669 gen_op_load_fpr_FT0(rs1);
1670 gen_op_load_fpr_FT1(rs2);
1671 #ifdef TARGET_SPARC64
1672 gen_fcmpes[rd & 3]();
1673 #else
1674 gen_op_fcmpes();
1675 #endif
1676 break;
1677 case 0x56: /* fcmped, V9 %fcc */
1678 gen_op_load_fpr_DT0(DFPREG(rs1));
1679 gen_op_load_fpr_DT1(DFPREG(rs2));
1680 #ifdef TARGET_SPARC64
1681 gen_fcmped[rd & 3]();
1682 #else
1683 gen_op_fcmped();
1684 #endif
1685 break;
1686 case 0x57: /* fcmpeq */
1687 goto nfpu_insn;
1688 default:
1689 goto illegal_insn;
1690 }
1691 #if defined(OPTIM)
1692 } else if (xop == 0x2) {
1693 // clr/mov shortcut
1694
1695 rs1 = GET_FIELD(insn, 13, 17);
1696 if (rs1 == 0) {
1697 // or %g0, x, y -> mov T1, x; mov y, T1
1698 if (IS_IMM) { /* immediate */
1699 rs2 = GET_FIELDs(insn, 19, 31);
1700 gen_movl_simm_T1(rs2);
1701 } else { /* register */
1702 rs2 = GET_FIELD(insn, 27, 31);
1703 gen_movl_reg_T1(rs2);
1704 }
1705 gen_movl_T1_reg(rd);
1706 } else {
1707 gen_movl_reg_T0(rs1);
1708 if (IS_IMM) { /* immediate */
1709 // or x, #0, y -> mov T1, x; mov y, T1
1710 rs2 = GET_FIELDs(insn, 19, 31);
1711 if (rs2 != 0) {
1712 gen_movl_simm_T1(rs2);
1713 gen_op_or_T1_T0();
1714 }
1715 } else { /* register */
1716 // or x, %g0, y -> mov T1, x; mov y, T1
1717 rs2 = GET_FIELD(insn, 27, 31);
1718 if (rs2 != 0) {
1719 gen_movl_reg_T1(rs2);
1720 gen_op_or_T1_T0();
1721 }
1722 }
1723 gen_movl_T0_reg(rd);
1724 }
1725 #endif
1726 #ifdef TARGET_SPARC64
1727 } else if (xop == 0x25) { /* sll, V9 sllx */
1728 rs1 = GET_FIELD(insn, 13, 17);
1729 gen_movl_reg_T0(rs1);
1730 if (IS_IMM) { /* immediate */
1731 rs2 = GET_FIELDs(insn, 20, 31);
1732 gen_movl_simm_T1(rs2);
1733 } else { /* register */
1734 rs2 = GET_FIELD(insn, 27, 31);
1735 gen_movl_reg_T1(rs2);
1736 }
1737 if (insn & (1 << 12))
1738 gen_op_sllx();
1739 else
1740 gen_op_sll();
1741 gen_movl_T0_reg(rd);
1742 } else if (xop == 0x26) { /* srl, V9 srlx */
1743 rs1 = GET_FIELD(insn, 13, 17);
1744 gen_movl_reg_T0(rs1);
1745 if (IS_IMM) { /* immediate */
1746 rs2 = GET_FIELDs(insn, 20, 31);
1747 gen_movl_simm_T1(rs2);
1748 } else { /* register */
1749 rs2 = GET_FIELD(insn, 27, 31);
1750 gen_movl_reg_T1(rs2);
1751 }
1752 if (insn & (1 << 12))
1753 gen_op_srlx();
1754 else
1755 gen_op_srl();
1756 gen_movl_T0_reg(rd);
1757 } else if (xop == 0x27) { /* sra, V9 srax */
1758 rs1 = GET_FIELD(insn, 13, 17);
1759 gen_movl_reg_T0(rs1);
1760 if (IS_IMM) { /* immediate */
1761 rs2 = GET_FIELDs(insn, 20, 31);
1762 gen_movl_simm_T1(rs2);
1763 } else { /* register */
1764 rs2 = GET_FIELD(insn, 27, 31);
1765 gen_movl_reg_T1(rs2);
1766 }
1767 if (insn & (1 << 12))
1768 gen_op_srax();
1769 else
1770 gen_op_sra();
1771 gen_movl_T0_reg(rd);
1772 #endif
1773 } else if (xop < 0x36) {
1774 rs1 = GET_FIELD(insn, 13, 17);
1775 gen_movl_reg_T0(rs1);
1776 if (IS_IMM) { /* immediate */
1777 rs2 = GET_FIELDs(insn, 19, 31);
1778 gen_movl_simm_T1(rs2);
1779 } else { /* register */
1780 rs2 = GET_FIELD(insn, 27, 31);
1781 gen_movl_reg_T1(rs2);
1782 }
1783 if (xop < 0x20) {
1784 switch (xop & ~0x10) {
1785 case 0x0:
1786 if (xop & 0x10)
1787 gen_op_add_T1_T0_cc();
1788 else
1789 gen_op_add_T1_T0();
1790 break;
1791 case 0x1:
1792 gen_op_and_T1_T0();
1793 if (xop & 0x10)
1794 gen_op_logic_T0_cc();
1795 break;
1796 case 0x2:
1797 gen_op_or_T1_T0();
1798 if (xop & 0x10)
1799 gen_op_logic_T0_cc();
1800 break;
1801 case 0x3:
1802 gen_op_xor_T1_T0();
1803 if (xop & 0x10)
1804 gen_op_logic_T0_cc();
1805 break;
1806 case 0x4:
1807 if (xop & 0x10)
1808 gen_op_sub_T1_T0_cc();
1809 else
1810 gen_op_sub_T1_T0();
1811 break;
1812 case 0x5:
1813 gen_op_andn_T1_T0();
1814 if (xop & 0x10)
1815 gen_op_logic_T0_cc();
1816 break;
1817 case 0x6:
1818 gen_op_orn_T1_T0();
1819 if (xop & 0x10)
1820 gen_op_logic_T0_cc();
1821 break;
1822 case 0x7:
1823 gen_op_xnor_T1_T0();
1824 if (xop & 0x10)
1825 gen_op_logic_T0_cc();
1826 break;
1827 case 0x8:
1828 if (xop & 0x10)
1829 gen_op_addx_T1_T0_cc();
1830 else
1831 gen_op_addx_T1_T0();
1832 break;
1833 #ifdef TARGET_SPARC64
1834 case 0x9: /* V9 mulx */
1835 gen_op_mulx_T1_T0();
1836 break;
1837 #endif
1838 case 0xa:
1839 gen_op_umul_T1_T0();
1840 if (xop & 0x10)
1841 gen_op_logic_T0_cc();
1842 break;
1843 case 0xb:
1844 gen_op_smul_T1_T0();
1845 if (xop & 0x10)
1846 gen_op_logic_T0_cc();
1847 break;
1848 case 0xc:
1849 if (xop & 0x10)
1850 gen_op_subx_T1_T0_cc();
1851 else
1852 gen_op_subx_T1_T0();
1853 break;
1854 #ifdef TARGET_SPARC64
1855 case 0xd: /* V9 udivx */
1856 gen_op_udivx_T1_T0();
1857 break;
1858 #endif
1859 case 0xe:
1860 gen_op_udiv_T1_T0();
1861 if (xop & 0x10)
1862 gen_op_div_cc();
1863 break;
1864 case 0xf:
1865 gen_op_sdiv_T1_T0();
1866 if (xop & 0x10)
1867 gen_op_div_cc();
1868 break;
1869 default:
1870 goto illegal_insn;
1871 }
1872 gen_movl_T0_reg(rd);
1873 } else {
1874 switch (xop) {
1875 case 0x20: /* taddcc */
1876 gen_op_tadd_T1_T0_cc();
1877 gen_movl_T0_reg(rd);
1878 break;
1879 case 0x21: /* tsubcc */
1880 gen_op_tsub_T1_T0_cc();
1881 gen_movl_T0_reg(rd);
1882 break;
1883 case 0x22: /* taddcctv */
1884 gen_op_tadd_T1_T0_ccTV();
1885 gen_movl_T0_reg(rd);
1886 break;
1887 case 0x23: /* tsubcctv */
1888 gen_op_tsub_T1_T0_ccTV();
1889 gen_movl_T0_reg(rd);
1890 break;
1891 case 0x24: /* mulscc */
1892 gen_op_mulscc_T1_T0();
1893 gen_movl_T0_reg(rd);
1894 break;
1895 #ifndef TARGET_SPARC64
1896 case 0x25: /* sll */
1897 gen_op_sll();
1898 gen_movl_T0_reg(rd);
1899 break;
1900 case 0x26: /* srl */
1901 gen_op_srl();
1902 gen_movl_T0_reg(rd);
1903 break;
1904 case 0x27: /* sra */
1905 gen_op_sra();
1906 gen_movl_T0_reg(rd);
1907 break;
1908 #endif
1909 case 0x30:
1910 {
1911 switch(rd) {
1912 case 0: /* wry */
1913 gen_op_xor_T1_T0();
1914 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1915 break;
1916 #ifndef TARGET_SPARC64
1917 case 0x01 ... 0x0f: /* undefined in the
1918 SPARCv8 manual, nop
1919 on the microSPARC
1920 II */
1921 case 0x10 ... 0x1f: /* implementation-dependent
1922 in the SPARCv8
1923 manual, nop on the
1924 microSPARC II */
1925 break;
1926 #else
1927 case 0x2: /* V9 wrccr */
1928 gen_op_wrccr();
1929 break;
1930 case 0x3: /* V9 wrasi */
1931 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1932 break;
1933 case 0x6: /* V9 wrfprs */
1934 gen_op_xor_T1_T0();
1935 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1936 save_state(dc);
1937 gen_op_next_insn();
1938 gen_op_movl_T0_0();
1939 gen_op_exit_tb();
1940 dc->is_br = 1;
1941 break;
1942 case 0xf: /* V9 sir, nop if user */
1943 #if !defined(CONFIG_USER_ONLY)
1944 if (supervisor(dc))
1945 gen_op_sir();
1946 #endif
1947 break;
1948 case 0x13: /* Graphics Status */
1949 if (gen_trap_ifnofpu(dc))
1950 goto jmp_insn;
1951 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
1952 break;
1953 case 0x17: /* Tick compare */
1954 #if !defined(CONFIG_USER_ONLY)
1955 if (!supervisor(dc))
1956 goto illegal_insn;
1957 #endif
1958 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1959 break;
1960 case 0x18: /* System tick */
1961 #if !defined(CONFIG_USER_ONLY)
1962 if (!supervisor(dc))
1963 goto illegal_insn;
1964 #endif
1965 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1966 break;
1967 case 0x19: /* System tick compare */
1968 #if !defined(CONFIG_USER_ONLY)
1969 if (!supervisor(dc))
1970 goto illegal_insn;
1971 #endif
1972 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1973 break;
1974
1975 case 0x10: /* Performance Control */
1976 case 0x11: /* Performance Instrumentation Counter */
1977 case 0x12: /* Dispatch Control */
1978 case 0x14: /* Softint set */
1979 case 0x15: /* Softint clear */
1980 case 0x16: /* Softint write */
1981 #endif
1982 default:
1983 goto illegal_insn;
1984 }
1985 }
1986 break;
1987 #if !defined(CONFIG_USER_ONLY)
1988 case 0x31: /* wrpsr, V9 saved, restored */
1989 {
1990 if (!supervisor(dc))
1991 goto priv_insn;
1992 #ifdef TARGET_SPARC64
1993 switch (rd) {
1994 case 0:
1995 gen_op_saved();
1996 break;
1997 case 1:
1998 gen_op_restored();
1999 break;
2000 default:
2001 goto illegal_insn;
2002 }
2003 #else
2004 gen_op_xor_T1_T0();
2005 gen_op_wrpsr();
2006 save_state(dc);
2007 gen_op_next_insn();
2008 gen_op_movl_T0_0();
2009 gen_op_exit_tb();
2010 dc->is_br = 1;
2011 #endif
2012 }
2013 break;
2014 case 0x32: /* wrwim, V9 wrpr */
2015 {
2016 if (!supervisor(dc))
2017 goto priv_insn;
2018 gen_op_xor_T1_T0();
2019 #ifdef TARGET_SPARC64
2020 switch (rd) {
2021 case 0: // tpc
2022 gen_op_wrtpc();
2023 break;
2024 case 1: // tnpc
2025 gen_op_wrtnpc();
2026 break;
2027 case 2: // tstate
2028 gen_op_wrtstate();
2029 break;
2030 case 3: // tt
2031 gen_op_wrtt();
2032 break;
2033 case 4: // tick
2034 gen_op_wrtick();
2035 break;
2036 case 5: // tba
2037 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2038 break;
2039 case 6: // pstate
2040 gen_op_wrpstate();
2041 save_state(dc);
2042 gen_op_next_insn();
2043 gen_op_movl_T0_0();
2044 gen_op_exit_tb();
2045 dc->is_br = 1;
2046 break;
2047 case 7: // tl
2048 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2049 break;
2050 case 8: // pil
2051 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2052 break;
2053 case 9: // cwp
2054 gen_op_wrcwp();
2055 break;
2056 case 10: // cansave
2057 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2058 break;
2059 case 11: // canrestore
2060 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2061 break;
2062 case 12: // cleanwin
2063 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2064 break;
2065 case 13: // otherwin
2066 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2067 break;
2068 case 14: // wstate
2069 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2070 break;
2071 default:
2072 goto illegal_insn;
2073 }
2074 #else
2075 gen_op_wrwim();
2076 #endif
2077 }
2078 break;
2079 #ifndef TARGET_SPARC64
2080 case 0x33: /* wrtbr, V9 unimp */
2081 {
2082 if (!supervisor(dc))
2083 goto priv_insn;
2084 gen_op_xor_T1_T0();
2085 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2086 }
2087 break;
2088 #endif
2089 #endif
2090 #ifdef TARGET_SPARC64
2091 case 0x2c: /* V9 movcc */
2092 {
2093 int cc = GET_FIELD_SP(insn, 11, 12);
2094 int cond = GET_FIELD_SP(insn, 14, 17);
2095 if (IS_IMM) { /* immediate */
2096 rs2 = GET_FIELD_SPs(insn, 0, 10);
2097 gen_movl_simm_T1(rs2);
2098 }
2099 else {
2100 rs2 = GET_FIELD_SP(insn, 0, 4);
2101 gen_movl_reg_T1(rs2);
2102 }
2103 gen_movl_reg_T0(rd);
2104 flush_T2(dc);
2105 if (insn & (1 << 18)) {
2106 if (cc == 0)
2107 gen_cond[0][cond]();
2108 else if (cc == 2)
2109 gen_cond[1][cond]();
2110 else
2111 goto illegal_insn;
2112 } else {
2113 gen_fcond[cc][cond]();
2114 }
2115 gen_op_mov_cc();
2116 gen_movl_T0_reg(rd);
2117 break;
2118 }
2119 case 0x2d: /* V9 sdivx */
2120 gen_op_sdivx_T1_T0();
2121 gen_movl_T0_reg(rd);
2122 break;
2123 case 0x2e: /* V9 popc */
2124 {
2125 if (IS_IMM) { /* immediate */
2126 rs2 = GET_FIELD_SPs(insn, 0, 12);
2127 gen_movl_simm_T1(rs2);
2128 // XXX optimize: popc(constant)
2129 }
2130 else {
2131 rs2 = GET_FIELD_SP(insn, 0, 4);
2132 gen_movl_reg_T1(rs2);
2133 }
2134 gen_op_popc();
2135 gen_movl_T0_reg(rd);
2136 }
2137 case 0x2f: /* V9 movr */
2138 {
2139 int cond = GET_FIELD_SP(insn, 10, 12);
2140 rs1 = GET_FIELD(insn, 13, 17);
2141 flush_T2(dc);
2142 gen_movl_reg_T0(rs1);
2143 gen_cond_reg(cond);
2144 if (IS_IMM) { /* immediate */
2145 rs2 = GET_FIELD_SPs(insn, 0, 10);
2146 gen_movl_simm_T1(rs2);
2147 }
2148 else {
2149 rs2 = GET_FIELD_SP(insn, 0, 4);
2150 gen_movl_reg_T1(rs2);
2151 }
2152 gen_movl_reg_T0(rd);
2153 gen_op_mov_cc();
2154 gen_movl_T0_reg(rd);
2155 break;
2156 }
2157 #endif
2158 default:
2159 goto illegal_insn;
2160 }
2161 }
2162 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2163 #ifdef TARGET_SPARC64
2164 int opf = GET_FIELD_SP(insn, 5, 13);
2165 rs1 = GET_FIELD(insn, 13, 17);
2166 rs2 = GET_FIELD(insn, 27, 31);
2167
2168 switch (opf) {
2169 case 0x018: /* VIS I alignaddr */
2170 if (gen_trap_ifnofpu(dc))
2171 goto jmp_insn;
2172 gen_movl_reg_T0(rs1);
2173 gen_movl_reg_T1(rs2);
2174 gen_op_alignaddr();
2175 gen_movl_T0_reg(rd);
2176 break;
2177 case 0x01a: /* VIS I alignaddrl */
2178 if (gen_trap_ifnofpu(dc))
2179 goto jmp_insn;
2180 // XXX
2181 break;
2182 case 0x048: /* VIS I faligndata */
2183 if (gen_trap_ifnofpu(dc))
2184 goto jmp_insn;
2185 gen_op_load_fpr_DT0(rs1);
2186 gen_op_load_fpr_DT1(rs2);
2187 gen_op_faligndata();
2188 gen_op_store_DT0_fpr(rd);
2189 break;
2190 case 0x060: /* VIS I fzero */
2191 if (gen_trap_ifnofpu(dc))
2192 goto jmp_insn;
2193 gen_op_movl_DT0_0();
2194 gen_op_store_DT0_fpr(rd);
2195 break;
2196 case 0x061: /* VIS I fzeros */
2197 if (gen_trap_ifnofpu(dc))
2198 goto jmp_insn;
2199 gen_op_movl_FT0_0();
2200 gen_op_store_FT0_fpr(rd);
2201 break;
2202 case 0x074: /* VIS I fsrc1 */
2203 if (gen_trap_ifnofpu(dc))
2204 goto jmp_insn;
2205 gen_op_load_fpr_DT0(rs1);
2206 gen_op_store_DT0_fpr(rd);
2207 break;
2208 case 0x075: /* VIS I fsrc1s */
2209 if (gen_trap_ifnofpu(dc))
2210 goto jmp_insn;
2211 gen_op_load_fpr_FT0(rs1);
2212 gen_op_store_FT0_fpr(rd);
2213 break;
2214 case 0x078: /* VIS I fsrc2 */
2215 if (gen_trap_ifnofpu(dc))
2216 goto jmp_insn;
2217 gen_op_load_fpr_DT0(rs2);
2218 gen_op_store_DT0_fpr(rd);
2219 break;
2220 case 0x079: /* VIS I fsrc2s */
2221 if (gen_trap_ifnofpu(dc))
2222 goto jmp_insn;
2223 gen_op_load_fpr_FT0(rs2);
2224 gen_op_store_FT0_fpr(rd);
2225 break;
2226 case 0x07e: /* VIS I fone */
2227 if (gen_trap_ifnofpu(dc))
2228 goto jmp_insn;
2229 gen_op_movl_DT0_1();
2230 gen_op_store_DT0_fpr(rd);
2231 break;
2232 case 0x07f: /* VIS I fones */
2233 if (gen_trap_ifnofpu(dc))
2234 goto jmp_insn;
2235 gen_op_movl_FT0_1();
2236 gen_op_store_FT0_fpr(rd);
2237 break;
2238 default:
2239 goto illegal_insn;
2240 }
2241 #else
2242 goto ncp_insn;
2243 #endif
2244 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2245 #ifdef TARGET_SPARC64
2246 goto illegal_insn;
2247 #else
2248 goto ncp_insn;
2249 #endif
2250 #ifdef TARGET_SPARC64
2251 } else if (xop == 0x39) { /* V9 return */
2252 rs1 = GET_FIELD(insn, 13, 17);
2253 gen_movl_reg_T0(rs1);
2254 if (IS_IMM) { /* immediate */
2255 rs2 = GET_FIELDs(insn, 19, 31);
2256 #if defined(OPTIM)
2257 if (rs2) {
2258 #endif
2259 gen_movl_simm_T1(rs2);
2260 gen_op_add_T1_T0();
2261 #if defined(OPTIM)
2262 }
2263 #endif
2264 } else { /* register */
2265 rs2 = GET_FIELD(insn, 27, 31);
2266 #if defined(OPTIM)
2267 if (rs2) {
2268 #endif
2269 gen_movl_reg_T1(rs2);
2270 gen_op_add_T1_T0();
2271 #if defined(OPTIM)
2272 }
2273 #endif
2274 }
2275 gen_op_restore();
2276 gen_mov_pc_npc(dc);
2277 gen_op_movl_npc_T0();
2278 dc->npc = DYNAMIC_PC;
2279 goto jmp_insn;
2280 #endif
2281 } else {
2282 rs1 = GET_FIELD(insn, 13, 17);
2283 gen_movl_reg_T0(rs1);
2284 if (IS_IMM) { /* immediate */
2285 rs2 = GET_FIELDs(insn, 19, 31);
2286 #if defined(OPTIM)
2287 if (rs2) {
2288 #endif
2289 gen_movl_simm_T1(rs2);
2290 gen_op_add_T1_T0();
2291 #if defined(OPTIM)
2292 }
2293 #endif
2294 } else { /* register */
2295 rs2 = GET_FIELD(insn, 27, 31);
2296 #if defined(OPTIM)
2297 if (rs2) {
2298 #endif
2299 gen_movl_reg_T1(rs2);
2300 gen_op_add_T1_T0();
2301 #if defined(OPTIM)
2302 }
2303 #endif
2304 }
2305 switch (xop) {
2306 case 0x38: /* jmpl */
2307 {
2308 if (rd != 0) {
2309 #ifdef TARGET_SPARC64
2310 if (dc->pc == (uint32_t)dc->pc) {
2311 gen_op_movl_T1_im(dc->pc);
2312 } else {
2313 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2314 }
2315 #else
2316 gen_op_movl_T1_im(dc->pc);
2317 #endif
2318 gen_movl_T1_reg(rd);
2319 }
2320 gen_mov_pc_npc(dc);
2321 gen_op_movl_npc_T0();
2322 dc->npc = DYNAMIC_PC;
2323 }
2324 goto jmp_insn;
2325 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2326 case 0x39: /* rett, V9 return */
2327 {
2328 if (!supervisor(dc))
2329 goto priv_insn;
2330 gen_mov_pc_npc(dc);
2331 gen_op_movl_npc_T0();
2332 dc->npc = DYNAMIC_PC;
2333 gen_op_rett();
2334 }
2335 goto jmp_insn;
2336 #endif
2337 case 0x3b: /* flush */
2338 gen_op_flush_T0();
2339 break;
2340 case 0x3c: /* save */
2341 save_state(dc);
2342 gen_op_save();
2343 gen_movl_T0_reg(rd);
2344 break;
2345 case 0x3d: /* restore */
2346 save_state(dc);
2347 gen_op_restore();
2348 gen_movl_T0_reg(rd);
2349 break;
2350 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2351 case 0x3e: /* V9 done/retry */
2352 {
2353 switch (rd) {
2354 case 0:
2355 if (!supervisor(dc))
2356 goto priv_insn;
2357 dc->npc = DYNAMIC_PC;
2358 dc->pc = DYNAMIC_PC;
2359 gen_op_done();
2360 goto jmp_insn;
2361 case 1:
2362 if (!supervisor(dc))
2363 goto priv_insn;
2364 dc->npc = DYNAMIC_PC;
2365 dc->pc = DYNAMIC_PC;
2366 gen_op_retry();
2367 goto jmp_insn;
2368 default:
2369 goto illegal_insn;
2370 }
2371 }
2372 break;
2373 #endif
2374 default:
2375 goto illegal_insn;
2376 }
2377 }
2378 break;
2379 }
2380 break;
2381 case 3: /* load/store instructions */
2382 {
2383 unsigned int xop = GET_FIELD(insn, 7, 12);
2384 rs1 = GET_FIELD(insn, 13, 17);
2385 gen_movl_reg_T0(rs1);
2386 if (IS_IMM) { /* immediate */
2387 rs2 = GET_FIELDs(insn, 19, 31);
2388 #if defined(OPTIM)
2389 if (rs2 != 0) {
2390 #endif
2391 gen_movl_simm_T1(rs2);
2392 gen_op_add_T1_T0();
2393 #if defined(OPTIM)
2394 }
2395 #endif
2396 } else { /* register */
2397 rs2 = GET_FIELD(insn, 27, 31);
2398 #if defined(OPTIM)
2399 if (rs2 != 0) {
2400 #endif
2401 gen_movl_reg_T1(rs2);
2402 gen_op_add_T1_T0();
2403 #if defined(OPTIM)
2404 }
2405 #endif
2406 }
2407 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2408 (xop > 0x17 && xop <= 0x1d ) || \
2409 (xop > 0x2c && xop <= 0x33) || xop == 0x1f) {
2410 switch (xop) {
2411 case 0x0: /* load word */
2412 gen_op_ldst(ld);
2413 break;
2414 case 0x1: /* load unsigned byte */
2415 gen_op_ldst(ldub);
2416 break;
2417 case 0x2: /* load unsigned halfword */
2418 gen_op_ldst(lduh);
2419 break;
2420 case 0x3: /* load double word */
2421 if (rd & 1)
2422 goto illegal_insn;
2423 gen_op_ldst(ldd);
2424 gen_movl_T0_reg(rd + 1);
2425 break;
2426 case 0x9: /* load signed byte */
2427 gen_op_ldst(ldsb);
2428 break;
2429 case 0xa: /* load signed halfword */
2430 gen_op_ldst(ldsh);
2431 break;
2432 case 0xd: /* ldstub -- XXX: should be atomically */
2433 gen_op_ldst(ldstub);
2434 break;
2435 case 0x0f: /* swap register with memory. Also atomically */
2436 gen_movl_reg_T1(rd);
2437 gen_op_ldst(swap);
2438 break;
2439 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2440 case 0x10: /* load word alternate */
2441 #ifndef TARGET_SPARC64
2442 if (IS_IMM)
2443 goto illegal_insn;
2444 if (!supervisor(dc))
2445 goto priv_insn;
2446 #endif
2447 gen_op_lda(insn, 1, 4, 0);
2448 break;
2449 case 0x11: /* load unsigned byte alternate */
2450 #ifndef TARGET_SPARC64
2451 if (IS_IMM)
2452 goto illegal_insn;
2453 if (!supervisor(dc))
2454 goto priv_insn;
2455 #endif
2456 gen_op_lduba(insn, 1, 1, 0);
2457 break;
2458 case 0x12: /* load unsigned halfword alternate */
2459 #ifndef TARGET_SPARC64
2460 if (IS_IMM)
2461 goto illegal_insn;
2462 if (!supervisor(dc))
2463 goto priv_insn;
2464 #endif
2465 gen_op_lduha(insn, 1, 2, 0);
2466 break;
2467 case 0x13: /* load double word alternate */
2468 #ifndef TARGET_SPARC64
2469 if (IS_IMM)
2470 goto illegal_insn;
2471 if (!supervisor(dc))
2472 goto priv_insn;
2473 #endif
2474 if (rd & 1)
2475 goto illegal_insn;
2476 gen_op_ldda(insn, 1, 8, 0);
2477 gen_movl_T0_reg(rd + 1);
2478 break;
2479 case 0x19: /* load signed byte alternate */
2480 #ifndef TARGET_SPARC64
2481 if (IS_IMM)
2482 goto illegal_insn;
2483 if (!supervisor(dc))
2484 goto priv_insn;
2485 #endif
2486 gen_op_ldsba(insn, 1, 1, 1);
2487 break;
2488 case 0x1a: /* load signed halfword alternate */
2489 #ifndef TARGET_SPARC64
2490 if (IS_IMM)
2491 goto illegal_insn;
2492 if (!supervisor(dc))
2493 goto priv_insn;
2494 #endif
2495 gen_op_ldsha(insn, 1, 2 ,1);
2496 break;
2497 case 0x1d: /* ldstuba -- XXX: should be atomically */
2498 #ifndef TARGET_SPARC64
2499 if (IS_IMM)
2500 goto illegal_insn;
2501 if (!supervisor(dc))
2502 goto priv_insn;
2503 #endif
2504 gen_op_ldstuba(insn, 1, 1, 0);
2505 break;
2506 case 0x1f: /* swap reg with alt. memory. Also atomically */
2507 #ifndef TARGET_SPARC64
2508 if (IS_IMM)
2509 goto illegal_insn;
2510 if (!supervisor(dc))
2511 goto priv_insn;
2512 #endif
2513 gen_movl_reg_T1(rd);
2514 gen_op_swapa(insn, 1, 4, 0);
2515 break;
2516
2517 #ifndef TARGET_SPARC64
2518 case 0x30: /* ldc */
2519 case 0x31: /* ldcsr */
2520 case 0x33: /* lddc */
2521 goto ncp_insn;
2522 /* avoid warnings */
2523 (void) &gen_op_stfa;
2524 (void) &gen_op_stdfa;
2525 (void) &gen_op_ldfa;
2526 (void) &gen_op_lddfa;
2527 #else
2528 #if !defined(CONFIG_USER_ONLY)
2529 (void) &gen_op_cas;
2530 (void) &gen_op_casx;
2531 #endif
2532 #endif
2533 #endif
2534 #ifdef TARGET_SPARC64
2535 case 0x08: /* V9 ldsw */
2536 gen_op_ldst(ldsw);
2537 break;
2538 case 0x0b: /* V9 ldx */
2539 gen_op_ldst(ldx);
2540 break;
2541 case 0x18: /* V9 ldswa */
2542 gen_op_ldswa(insn, 1, 4, 1);
2543 break;
2544 case 0x1b: /* V9 ldxa */
2545 gen_op_ldxa(insn, 1, 8, 0);
2546 break;
2547 case 0x2d: /* V9 prefetch, no effect */
2548 goto skip_move;
2549 case 0x30: /* V9 ldfa */
2550 gen_op_ldfa(insn, 1, 8, 0); // XXX
2551 break;
2552 case 0x33: /* V9 lddfa */
2553 gen_op_lddfa(insn, 1, 8, 0); // XXX
2554
2555 break;
2556 case 0x3d: /* V9 prefetcha, no effect */
2557 goto skip_move;
2558 case 0x32: /* V9 ldqfa */
2559 goto nfpu_insn;
2560 #endif
2561 default:
2562 goto illegal_insn;
2563 }
2564 gen_movl_T1_reg(rd);
2565 #ifdef TARGET_SPARC64
2566 skip_move: ;
2567 #endif
2568 } else if (xop >= 0x20 && xop < 0x24) {
2569 if (gen_trap_ifnofpu(dc))
2570 goto jmp_insn;
2571 switch (xop) {
2572 case 0x20: /* load fpreg */
2573 gen_op_ldst(ldf);
2574 gen_op_store_FT0_fpr(rd);
2575 break;
2576 case 0x21: /* load fsr */
2577 gen_op_ldst(ldf);
2578 gen_op_ldfsr();
2579 break;
2580 case 0x22: /* load quad fpreg */
2581 goto nfpu_insn;
2582 case 0x23: /* load double fpreg */
2583 gen_op_ldst(lddf);
2584 gen_op_store_DT0_fpr(DFPREG(rd));
2585 break;
2586 default:
2587 goto illegal_insn;
2588 }
2589 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2590 xop == 0xe || xop == 0x1e) {
2591 gen_movl_reg_T1(rd);
2592 switch (xop) {
2593 case 0x4:
2594 gen_op_ldst(st);
2595 break;
2596 case 0x5:
2597 gen_op_ldst(stb);
2598 break;
2599 case 0x6:
2600 gen_op_ldst(sth);
2601 break;
2602 case 0x7:
2603 if (rd & 1)
2604 goto illegal_insn;
2605 flush_T2(dc);
2606 gen_movl_reg_T2(rd + 1);
2607 gen_op_ldst(std);
2608 break;
2609 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2610 case 0x14:
2611 #ifndef TARGET_SPARC64
2612 if (IS_IMM)
2613 goto illegal_insn;
2614 if (!supervisor(dc))
2615 goto priv_insn;
2616 #endif
2617 gen_op_sta(insn, 0, 4, 0);
2618 break;
2619 case 0x15:
2620 #ifndef TARGET_SPARC64
2621 if (IS_IMM)
2622 goto illegal_insn;
2623 if (!supervisor(dc))
2624 goto priv_insn;
2625 #endif
2626 gen_op_stba(insn, 0, 1, 0);
2627 break;
2628 case 0x16:
2629 #ifndef TARGET_SPARC64
2630 if (IS_IMM)
2631 goto illegal_insn;
2632 if (!supervisor(dc))
2633 goto priv_insn;
2634 #endif
2635 gen_op_stha(insn, 0, 2, 0);
2636 break;
2637 case 0x17:
2638 #ifndef TARGET_SPARC64
2639 if (IS_IMM)
2640 goto illegal_insn;
2641 if (!supervisor(dc))
2642 goto priv_insn;
2643 #endif
2644 if (rd & 1)
2645 goto illegal_insn;
2646 flush_T2(dc);
2647 gen_movl_reg_T2(rd + 1);
2648 gen_op_stda(insn, 0, 8, 0);
2649 break;
2650 #endif
2651 #ifdef TARGET_SPARC64
2652 case 0x0e: /* V9 stx */
2653 gen_op_ldst(stx);
2654 break;
2655 case 0x1e: /* V9 stxa */
2656 gen_op_stxa(insn, 0, 8, 0); // XXX
2657 break;
2658 #endif
2659 default:
2660 goto illegal_insn;
2661 }
2662 } else if (xop > 0x23 && xop < 0x28) {
2663 if (gen_trap_ifnofpu(dc))
2664 goto jmp_insn;
2665 switch (xop) {
2666 case 0x24:
2667 gen_op_load_fpr_FT0(rd);
2668 gen_op_ldst(stf);
2669 break;
2670 case 0x25: /* stfsr, V9 stxfsr */
2671 gen_op_stfsr();
2672 gen_op_ldst(stf);
2673 break;
2674 #if !defined(CONFIG_USER_ONLY)
2675 case 0x26: /* stdfq */
2676 if (!supervisor(dc))
2677 goto priv_insn;
2678 if (gen_trap_ifnofpu(dc))
2679 goto jmp_insn;
2680 goto nfq_insn;
2681 #endif
2682 case 0x27:
2683 gen_op_load_fpr_DT0(DFPREG(rd));
2684 gen_op_ldst(stdf);
2685 break;
2686 default:
2687 goto illegal_insn;
2688 }
2689 } else if (xop > 0x33 && xop < 0x3f) {
2690 switch (xop) {
2691 #ifdef TARGET_SPARC64
2692 case 0x34: /* V9 stfa */
2693 gen_op_stfa(insn, 0, 0, 0); // XXX
2694 break;
2695 case 0x37: /* V9 stdfa */
2696 gen_op_stdfa(insn, 0, 0, 0); // XXX
2697 break;
2698 case 0x3c: /* V9 casa */
2699 gen_op_casa(insn, 0, 4, 0); // XXX
2700 break;
2701 case 0x3e: /* V9 casxa */
2702 gen_op_casxa(insn, 0, 8, 0); // XXX
2703 break;
2704 case 0x36: /* V9 stqfa */
2705 goto nfpu_insn;
2706 #else
2707 case 0x34: /* stc */
2708 case 0x35: /* stcsr */
2709 case 0x36: /* stdcq */
2710 case 0x37: /* stdc */
2711 goto ncp_insn;
2712 #endif
2713 default:
2714 goto illegal_insn;
2715 }
2716 }
2717 else
2718 goto illegal_insn;
2719 }
2720 break;
2721 }
2722 /* default case for non jump instructions */
2723 if (dc->npc == DYNAMIC_PC) {
2724 dc->pc = DYNAMIC_PC;
2725 gen_op_next_insn();
2726 } else if (dc->npc == JUMP_PC) {
2727 /* we can do a static jump */
2728 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
2729 dc->is_br = 1;
2730 } else {
2731 dc->pc = dc->npc;
2732 dc->npc = dc->npc + 4;
2733 }
2734 jmp_insn:
2735 return;
2736 illegal_insn:
2737 save_state(dc);
2738 gen_op_exception(TT_ILL_INSN);
2739 dc->is_br = 1;
2740 return;
2741 #if !defined(CONFIG_USER_ONLY)
2742 priv_insn:
2743 save_state(dc);
2744 gen_op_exception(TT_PRIV_INSN);
2745 dc->is_br = 1;
2746 return;
2747 #endif
2748 nfpu_insn:
2749 save_state(dc);
2750 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2751 dc->is_br = 1;
2752 return;
2753 #if !defined(CONFIG_USER_ONLY)
2754 nfq_insn:
2755 save_state(dc);
2756 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
2757 dc->is_br = 1;
2758 return;
2759 #endif
2760 #ifndef TARGET_SPARC64
2761 ncp_insn:
2762 save_state(dc);
2763 gen_op_exception(TT_NCP_INSN);
2764 dc->is_br = 1;
2765 return;
2766 #endif
2767 }
2768
2769 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
2770 int spc, CPUSPARCState *env)
2771 {
2772 target_ulong pc_start, last_pc;
2773 uint16_t *gen_opc_end;
2774 DisasContext dc1, *dc = &dc1;
2775 int j, lj = -1;
2776
2777 memset(dc, 0, sizeof(DisasContext));
2778 dc->tb = tb;
2779 pc_start = tb->pc;
2780 dc->pc = pc_start;
2781 last_pc = dc->pc;
2782 dc->npc = (target_ulong) tb->cs_base;
2783 #if defined(CONFIG_USER_ONLY)
2784 dc->mem_idx = 0;
2785 dc->fpu_enabled = 1;
2786 #else
2787 dc->mem_idx = ((env->psrs) != 0);
2788 #ifdef TARGET_SPARC64
2789 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
2790 #else
2791 dc->fpu_enabled = ((env->psref) != 0);
2792 #endif
2793 #endif
2794 gen_opc_ptr = gen_opc_buf;
2795 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2796 gen_opparam_ptr = gen_opparam_buf;
2797 nb_gen_labels = 0;
2798
2799 do {
2800 if (env->nb_breakpoints > 0) {
2801 for(j = 0; j < env->nb_breakpoints; j++) {
2802 if (env->breakpoints[j] == dc->pc) {
2803 if (dc->pc != pc_start)
2804 save_state(dc);
2805 gen_op_debug();
2806 gen_op_movl_T0_0();
2807 gen_op_exit_tb();
2808 dc->is_br = 1;
2809 goto exit_gen_loop;
2810 }
2811 }
2812 }
2813 if (spc) {
2814 if (loglevel > 0)
2815 fprintf(logfile, "Search PC...\n");
2816 j = gen_opc_ptr - gen_opc_buf;
2817 if (lj < j) {
2818 lj++;
2819 while (lj < j)
2820 gen_opc_instr_start[lj++] = 0;
2821 gen_opc_pc[lj] = dc->pc;
2822 gen_opc_npc[lj] = dc->npc;
2823 gen_opc_instr_start[lj] = 1;
2824 }
2825 }
2826 last_pc = dc->pc;
2827 disas_sparc_insn(dc);
2828
2829 if (dc->is_br)
2830 break;
2831 /* if the next PC is different, we abort now */
2832 if (dc->pc != (last_pc + 4))
2833 break;
2834 /* if we reach a page boundary, we stop generation so that the
2835 PC of a TT_TFAULT exception is always in the right page */
2836 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2837 break;
2838 /* if single step mode, we generate only one instruction and
2839 generate an exception */
2840 if (env->singlestep_enabled) {
2841 gen_jmp_im(dc->pc);
2842 gen_op_movl_T0_0();
2843 gen_op_exit_tb();
2844 break;
2845 }
2846 } while ((gen_opc_ptr < gen_opc_end) &&
2847 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
2848
2849 exit_gen_loop:
2850 if (!dc->is_br) {
2851 if (dc->pc != DYNAMIC_PC &&
2852 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2853 /* static PC and NPC: we can use direct chaining */
2854 gen_branch(dc, (long)tb, dc->pc, dc->npc);
2855 } else {
2856 if (dc->pc != DYNAMIC_PC)
2857 gen_jmp_im(dc->pc);
2858 save_npc(dc);
2859 gen_op_movl_T0_0();
2860 gen_op_exit_tb();
2861 }
2862 }
2863 *gen_opc_ptr = INDEX_op_end;
2864 if (spc) {
2865 j = gen_opc_ptr - gen_opc_buf;
2866 lj++;
2867 while (lj <= j)
2868 gen_opc_instr_start[lj++] = 0;
2869 tb->size = 0;
2870 #if 0
2871 if (loglevel > 0) {
2872 page_dump(logfile);
2873 }
2874 #endif
2875 gen_opc_jump_pc[0] = dc->jump_pc[0];
2876 gen_opc_jump_pc[1] = dc->jump_pc[1];
2877 } else {
2878 tb->size = last_pc + 4 - pc_start;
2879 }
2880 #ifdef DEBUG_DISAS
2881 if (loglevel & CPU_LOG_TB_IN_ASM) {
2882 fprintf(logfile, "--------------\n");
2883 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2884 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
2885 fprintf(logfile, "\n");
2886 if (loglevel & CPU_LOG_TB_OP) {
2887 fprintf(logfile, "OP:\n");
2888 dump_ops(gen_opc_buf, gen_opparam_buf);
2889 fprintf(logfile, "\n");
2890 }
2891 }
2892 #endif
2893 return 0;
2894 }
2895
2896 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
2897 {
2898 return gen_intermediate_code_internal(tb, 0, env);
2899 }
2900
2901 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
2902 {
2903 return gen_intermediate_code_internal(tb, 1, env);
2904 }
2905
2906 extern int ram_size;
2907
2908 void cpu_reset(CPUSPARCState *env)
2909 {
2910 memset(env, 0, sizeof(*env));
2911 tlb_flush(env, 1);
2912 env->cwp = 0;
2913 env->wim = 1;
2914 env->regwptr = env->regbase + (env->cwp * 16);
2915 #if defined(CONFIG_USER_ONLY)
2916 env->user_mode_only = 1;
2917 #ifdef TARGET_SPARC64
2918 env->cleanwin = NWINDOWS - 1;
2919 env->cansave = NWINDOWS - 1;
2920 #endif
2921 #else
2922 env->psrs = 1;
2923 env->psrps = 1;
2924 env->gregs[1] = ram_size;
2925 #ifdef TARGET_SPARC64
2926 env->pstate = PS_PRIV;
2927 env->pc = 0x1fff0000000ULL;
2928 #else
2929 env->pc = 0xffd00000;
2930 #endif
2931 env->npc = env->pc + 4;
2932 #endif
2933 }
2934
2935 CPUSPARCState *cpu_sparc_init(void)
2936 {
2937 CPUSPARCState *env;
2938
2939 env = qemu_mallocz(sizeof(CPUSPARCState));
2940 if (!env)
2941 return NULL;
2942 cpu_exec_init(env);
2943 cpu_reset(env);
2944 return (env);
2945 }
2946
2947 static const sparc_def_t sparc_defs[] = {
2948 #ifdef TARGET_SPARC64
2949 {
2950 .name = "TI UltraSparc II",
2951 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
2952 | (MAXTL << 8) | (NWINDOWS - 1)),
2953 .fpu_version = 0x00000000,
2954 .mmu_version = 0,
2955 },
2956 #else
2957 {
2958 .name = "Fujitsu MB86904",
2959 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
2960 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
2961 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
2962 },
2963 {
2964 /* XXX: Replace with real values */
2965 .name = "TI SuperSparc II",
2966 .iu_version = 0x40000000,
2967 .fpu_version = 0x00000000,
2968 .mmu_version = 0x00000000,
2969 },
2970 #endif
2971 };
2972
2973 int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
2974 {
2975 int ret;
2976 unsigned int i;
2977
2978 ret = -1;
2979 *def = NULL;
2980 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
2981 if (strcasecmp(name, sparc_defs[i].name) == 0) {
2982 *def = &sparc_defs[i];
2983 ret = 0;
2984 break;
2985 }
2986 }
2987
2988 return ret;
2989 }
2990
2991 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
2992 {
2993 unsigned int i;
2994
2995 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
2996 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
2997 sparc_defs[i].name,
2998 sparc_defs[i].iu_version,
2999 sparc_defs[i].fpu_version,
3000 sparc_defs[i].mmu_version);
3001 }
3002 }
3003
3004 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3005 {
3006 env->version = def->iu_version;
3007 env->fsr = def->fpu_version;
3008 #if !defined(TARGET_SPARC64)
3009 env->mmuregs[0] = def->mmu_version;
3010 #endif
3011 return 0;
3012 }
3013
3014 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3015
3016 void cpu_dump_state(CPUState *env, FILE *f,
3017 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3018 int flags)
3019 {
3020 int i, x;
3021
3022 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3023 cpu_fprintf(f, "General Registers:\n");
3024 for (i = 0; i < 4; i++)
3025 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3026 cpu_fprintf(f, "\n");
3027 for (; i < 8; i++)
3028 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3029 cpu_fprintf(f, "\nCurrent Register Window:\n");
3030 for (x = 0; x < 3; x++) {
3031 for (i = 0; i < 4; i++)
3032 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3033 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3034 env->regwptr[i + x * 8]);
3035 cpu_fprintf(f, "\n");
3036 for (; i < 8; i++)
3037 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3038 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3039 env->regwptr[i + x * 8]);
3040 cpu_fprintf(f, "\n");
3041 }
3042 cpu_fprintf(f, "\nFloating Point Registers:\n");
3043 for (i = 0; i < 32; i++) {
3044 if ((i & 3) == 0)
3045 cpu_fprintf(f, "%%f%02d:", i);
3046 cpu_fprintf(f, " %016lf", env->fpr[i]);
3047 if ((i & 3) == 3)
3048 cpu_fprintf(f, "\n");
3049 }
3050 #ifdef TARGET_SPARC64
3051 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3052 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3053 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3054 env->cansave, env->canrestore, env->otherwin, env->wstate,
3055 env->cleanwin, NWINDOWS - 1 - env->cwp);
3056 #else
3057 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3058 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3059 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3060 env->psrs?'S':'-', env->psrps?'P':'-',
3061 env->psret?'E':'-', env->wim);
3062 #endif
3063 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3064 }
3065
3066 #if defined(CONFIG_USER_ONLY)
3067 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3068 {
3069 return addr;
3070 }
3071
3072 #else
3073 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3074 int *access_index, target_ulong address, int rw,
3075 int is_user);
3076
3077 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3078 {
3079 target_phys_addr_t phys_addr;
3080 int prot, access_index;
3081
3082 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
3083 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3084 return -1;
3085 return phys_addr;
3086 }
3087 #endif
3088
3089 void helper_flush(target_ulong addr)
3090 {
3091 addr &= ~7;
3092 tb_invalidate_page_range(addr, addr + 8);
3093 }
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