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git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/translate.c
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 NPC/PC static optimisations (use JUMP_TB when possible)
27 Privileged instructions
28 Coprocessor-Instructions
29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
45 typedef struct DisasContext
{
46 uint8_t *pc
; /* NULL means dynamic value */
47 uint8_t *npc
; /* NULL means dynamic value */
49 struct TranslationBlock
*tb
;
52 static uint16_t *gen_opc_ptr
;
53 static uint32_t *gen_opparam_ptr
;
58 #define DEF(s,n,copy_size) INDEX_op_ ## s,
66 #define GET_FIELD(X, FROM, TO) \
67 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
69 #define IS_IMM (insn & (1<<13))
71 static void disas_sparc_insn(DisasContext
* dc
);
73 static GenOpFunc
*gen_op_movl_TN_reg
[2][32] = {
144 static GenOpFunc
*gen_op_movl_reg_TN
[3][32] = {
249 static GenOpFunc1
*gen_op_movl_TN_im
[3] = {
255 static inline void gen_movl_imm_TN(int reg
, int imm
)
257 gen_op_movl_TN_im
[reg
] (imm
);
260 static inline void gen_movl_imm_T1(int val
)
262 gen_movl_imm_TN(1, val
);
265 static inline void gen_movl_imm_T0(int val
)
267 gen_movl_imm_TN(0, val
);
270 static inline void gen_movl_reg_TN(int reg
, int t
)
273 gen_op_movl_reg_TN
[t
][reg
] ();
275 gen_movl_imm_TN(t
, 0);
278 static inline void gen_movl_reg_T0(int reg
)
280 gen_movl_reg_TN(reg
, 0);
283 static inline void gen_movl_reg_T1(int reg
)
285 gen_movl_reg_TN(reg
, 1);
288 static inline void gen_movl_reg_T2(int reg
)
290 gen_movl_reg_TN(reg
, 2);
293 static inline void gen_movl_TN_reg(int reg
, int t
)
296 gen_op_movl_TN_reg
[t
][reg
] ();
299 static inline void gen_movl_T0_reg(int reg
)
301 gen_movl_TN_reg(reg
, 0);
304 static inline void gen_movl_T1_reg(int reg
)
306 gen_movl_TN_reg(reg
, 1);
309 static void gen_cond(int cond
)
365 static void do_branch(DisasContext
* dc
, uint32_t target
, uint32_t insn
)
367 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
368 target
+= (uint32_t) dc
->pc
;
370 /* unconditional not taken */
372 dc
->pc
= dc
->npc
+ 4;
373 dc
->npc
= dc
->pc
+ 4;
376 dc
->npc
= dc
->pc
+ 4;
378 } else if (cond
== 0x8) {
379 /* unconditional taken */
381 dc
->pc
= (uint8_t *) target
;
382 dc
->npc
= dc
->pc
+ 4;
385 dc
->npc
= (uint8_t *) target
;
390 gen_op_generic_branch_a((uint32_t) target
,
391 (uint32_t) (dc
->npc
));
397 gen_op_generic_branch((uint32_t) target
,
398 (uint32_t) (dc
->npc
+ 4));
404 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
406 static int sign_extend(int x
, int len
)
409 return (x
<< len
) >> len
;
412 static inline void save_state(DisasContext
* dc
)
414 gen_op_jmp_im((uint32_t)dc
->pc
);
416 gen_op_movl_npc_im((long) dc
->npc
);
419 static void disas_sparc_insn(DisasContext
* dc
)
421 unsigned int insn
, opc
, rs1
, rs2
, rd
;
423 insn
= ldl_code(dc
->pc
);
424 opc
= GET_FIELD(insn
, 0, 1);
426 rd
= GET_FIELD(insn
, 2, 6);
428 case 0: /* branches/sethi */
430 unsigned int xop
= GET_FIELD(insn
, 7, 9);
432 target
= GET_FIELD(insn
, 10, 31);
435 case 0x1: /* UNIMPL */
440 target
= sign_extend(target
, 22);
441 do_branch(dc
, target
, insn
);
444 case 0x3: /* FBN+x */
446 case 0x4: /* SETHI */
447 gen_movl_imm_T0(target
<< 10);
457 unsigned int target
= GET_FIELDs(insn
, 2, 31) << 2;
459 gen_op_movl_T0_im((long) (dc
->pc
));
461 target
= (long) dc
->pc
+ target
;
463 dc
->npc
= (uint8_t *) target
;
466 case 2: /* FPU & Logical Operations */
468 unsigned int xop
= GET_FIELD(insn
, 7, 12);
469 if (xop
== 0x3a) { /* generate trap */
471 rs1
= GET_FIELD(insn
, 13, 17);
472 gen_movl_reg_T0(rs1
);
474 gen_movl_imm_T1(GET_FIELD(insn
, 25, 31));
476 rs2
= GET_FIELD(insn
, 27, 31);
477 gen_movl_reg_T1(rs2
);
481 cond
= GET_FIELD(insn
, 3, 6);
489 } else if (xop
== 0x28) {
490 rs1
= GET_FIELD(insn
, 13, 17);
499 } else if (xop
== 0x34 || xop
== 0x35) { /* FPU Operations */
502 rs1
= GET_FIELD(insn
, 13, 17);
503 gen_movl_reg_T0(rs1
);
504 if (IS_IMM
) { /* immediate */
505 rs2
= GET_FIELDs(insn
, 19, 31);
506 gen_movl_imm_T1(rs2
);
507 } else { /* register */
508 rs2
= GET_FIELD(insn
, 27, 31);
509 gen_movl_reg_T1(rs2
);
512 switch (xop
& ~0x10) {
515 gen_op_add_T1_T0_cc();
522 gen_op_logic_T0_cc();
527 gen_op_logic_T0_cc();
532 gen_op_logic_T0_cc();
536 gen_op_sub_T1_T0_cc();
543 gen_op_logic_T0_cc();
548 gen_op_logic_T0_cc();
553 gen_op_logic_T0_cc();
563 gen_op_logic_T0_cc();
568 gen_op_logic_T0_cc();
591 case 0x24: /* mulscc */
592 gen_op_mulscc_T1_T0();
619 case 0x38: /* jmpl */
622 gen_op_movl_npc_T0();
624 gen_op_movl_T0_im((long) (dc
->pc
));
631 case 0x3b: /* flush */
634 case 0x3c: /* save */
640 case 0x3d: /* restore */
653 case 3: /* load/store instructions */
655 unsigned int xop
= GET_FIELD(insn
, 7, 12);
656 rs1
= GET_FIELD(insn
, 13, 17);
657 gen_movl_reg_T0(rs1
);
658 if (IS_IMM
) { /* immediate */
659 rs2
= GET_FIELDs(insn
, 19, 31);
660 gen_movl_imm_T1(rs2
);
661 } else { /* register */
662 rs2
= GET_FIELD(insn
, 27, 31);
663 gen_movl_reg_T1(rs2
);
666 if (xop
< 4 || xop
> 7) {
668 case 0x0: /* load word */
671 case 0x1: /* load unsigned byte */
674 case 0x2: /* load unsigned halfword */
677 case 0x3: /* load double word */
679 gen_movl_T0_reg(rd
+ 1);
681 case 0x9: /* load signed byte */
684 case 0xa: /* load signed halfword */
687 case 0xd: /* ldstub -- XXX: should be atomically */
690 case 0x0f: /* swap register with memory. Also atomically */
695 } else if (xop
< 8) {
708 gen_movl_reg_T2(rd
+ 1);
715 /* default case for non jump instructions */
716 if (dc
->npc
!= NULL
) {
718 dc
->npc
= dc
->npc
+ 4;
726 gen_op_jmp_im((uint32_t)dc
->pc
);
728 gen_op_movl_npc_im((long) dc
->npc
);
729 gen_op_exception(TT_ILL_INSN
);
733 static inline int gen_intermediate_code_internal(TranslationBlock
* tb
,
736 uint8_t *pc_start
, *last_pc
;
737 uint16_t *gen_opc_end
;
738 DisasContext dc1
, *dc
= &dc1
;
740 memset(dc
, 0, sizeof(DisasContext
));
742 printf("SearchPC not yet supported\n");
746 pc_start
= (uint8_t *) tb
->pc
;
748 dc
->npc
= (uint8_t *) tb
->cs_base
;
750 gen_opc_ptr
= gen_opc_buf
;
751 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
752 gen_opparam_ptr
= gen_opparam_buf
;
756 disas_sparc_insn(dc
);
759 /* if the next PC is different, we abort now */
760 if (dc
->pc
!= (last_pc
+ 4))
762 } while ((gen_opc_ptr
< gen_opc_end
) &&
763 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32));
765 gen_op_jmp_im((long) dc
->pc
);
767 gen_op_movl_npc_im((long) dc
->npc
);
771 *gen_opc_ptr
= INDEX_op_end
;
774 fprintf(logfile
, "--------------\n");
775 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
776 disas(logfile
, pc_start
, last_pc
+ 4 - pc_start
, 0, 0);
777 fprintf(logfile
, "\n");
778 fprintf(logfile
, "OP:\n");
779 dump_ops(gen_opc_buf
, gen_opparam_buf
);
780 fprintf(logfile
, "\n");
787 int gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
789 return gen_intermediate_code_internal(tb
, 0);
792 int gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
794 return gen_intermediate_code_internal(tb
, 1);
797 CPUSPARCState
*cpu_sparc_init(void)
803 if (!(env
= malloc(sizeof(CPUSPARCState
))))
805 memset(env
, 0, sizeof(*env
));
808 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
809 env
->user_mode_only
= 1;
813 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
815 void cpu_sparc_dump_state(CPUSPARCState
* env
, FILE * f
, int flags
)
819 fprintf(f
, "pc: 0x%08x npc: 0x%08x\n", (int) env
->pc
, (int) env
->npc
);
820 fprintf(f
, "General Registers:\n");
821 for (i
= 0; i
< 4; i
++)
822 fprintf(f
, "%%g%c: 0x%08x\t", i
+ '0', env
->gregs
[i
]);
825 fprintf(f
, "%%g%c: 0x%08x\t", i
+ '0', env
->gregs
[i
]);
826 fprintf(f
, "\nCurrent Register Window:\n");
827 for (x
= 0; x
< 3; x
++) {
828 for (i
= 0; i
< 4; i
++)
829 fprintf(f
, "%%%c%d: 0x%08x\t",
830 (x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i')), i
,
831 env
->regwptr
[i
+ x
* 8]);
834 fprintf(f
, "%%%c%d: 0x%08x\t",
835 (x
== 0 ? 'o' : x
== 1 ? 'l' : 'i'), i
,
836 env
->regwptr
[i
+ x
* 8]);
839 fprintf(f
, "psr: 0x%08x -> %c%c%c%c wim: 0x%08x\n", env
->psr
| env
->cwp
,
840 GET_FLAG(PSR_ZERO
, 'Z'), GET_FLAG(PSR_OVF
, 'V'),
841 GET_FLAG(PSR_NEG
, 'N'), GET_FLAG(PSR_CARRY
, 'C'),
845 target_ulong
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)