4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
44 #define DYNAMIC_PC 1 /* dynamic pc value */
45 #define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
48 /* global register indexes */
49 static TCGv cpu_env
, cpu_T
[3], cpu_regwptr
, cpu_cc_src
, cpu_cc_dst
, cpu_psr
;
50 static TCGv cpu_gregs
[8];
54 /* local register indexes (only used inside old micro ops) */
57 typedef struct DisasContext
{
58 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
59 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
60 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
64 struct TranslationBlock
*tb
;
67 typedef struct sparc_def_t sparc_def_t
;
70 const unsigned char *name
;
71 target_ulong iu_version
;
75 uint32_t mmu_ctpr_mask
;
76 uint32_t mmu_cxr_mask
;
77 uint32_t mmu_sfsr_mask
;
78 uint32_t mmu_trcr_mask
;
81 static const sparc_def_t
*cpu_sparc_find_by_name(const unsigned char *name
);
86 // This function uses non-native bit order
87 #define GET_FIELD(X, FROM, TO) \
88 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
90 // This function uses the order in the manuals, i.e. bit 0 is 2^0
91 #define GET_FIELD_SP(X, FROM, TO) \
92 GET_FIELD(X, 31 - (TO), 31 - (FROM))
94 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
95 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
99 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
100 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
102 #define FFPREG(r) (r)
103 #define DFPREG(r) (r & 0x1e)
104 #define QFPREG(r) (r & 0x1c)
107 static int sign_extend(int x
, int len
)
110 return (x
<< len
) >> len
;
113 #define IS_IMM (insn & (1<<13))
115 static void disas_sparc_insn(DisasContext
* dc
);
117 #ifdef TARGET_SPARC64
118 #define GEN32(func, NAME) \
119 static GenOpFunc * const NAME ## _table [64] = { \
120 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
121 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
122 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
123 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
124 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
125 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
126 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
127 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
128 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
129 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
130 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
131 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
133 static inline void func(int n) \
135 NAME ## _table[n](); \
138 #define GEN32(func, NAME) \
139 static GenOpFunc *const NAME ## _table [32] = { \
140 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
141 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
142 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
143 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
144 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
145 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
146 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
147 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
149 static inline void func(int n) \
151 NAME ## _table[n](); \
155 /* floating point registers moves */
156 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fprf
);
157 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fprf
);
158 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fprf
);
159 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fprf
);
161 GEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fprf
);
162 GEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fprf
);
163 GEN32(gen_op_store_DT0_fpr
, gen_op_store_DT0_fpr_fprf
);
164 GEN32(gen_op_store_DT1_fpr
, gen_op_store_DT1_fpr_fprf
);
166 #if defined(CONFIG_USER_ONLY)
167 GEN32(gen_op_load_fpr_QT0
, gen_op_load_fpr_QT0_fprf
);
168 GEN32(gen_op_load_fpr_QT1
, gen_op_load_fpr_QT1_fprf
);
169 GEN32(gen_op_store_QT0_fpr
, gen_op_store_QT0_fpr_fprf
);
170 GEN32(gen_op_store_QT1_fpr
, gen_op_store_QT1_fpr_fprf
);
174 #ifdef CONFIG_USER_ONLY
175 #define supervisor(dc) 0
176 #ifdef TARGET_SPARC64
177 #define hypervisor(dc) 0
179 #define gen_op_ldst(name) gen_op_##name##_raw()
181 #define supervisor(dc) (dc->mem_idx >= 1)
182 #ifdef TARGET_SPARC64
183 #define hypervisor(dc) (dc->mem_idx == 2)
184 #define OP_LD_TABLE(width) \
185 static GenOpFunc * const gen_op_##width[] = { \
186 &gen_op_##width##_user, \
187 &gen_op_##width##_kernel, \
188 &gen_op_##width##_hypv, \
191 #define OP_LD_TABLE(width) \
192 static GenOpFunc * const gen_op_##width[] = { \
193 &gen_op_##width##_user, \
194 &gen_op_##width##_kernel, \
197 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
200 #ifndef CONFIG_USER_ONLY
203 #endif /* __i386__ */
211 #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
213 #define ABI32_MASK(addr)
216 static inline void gen_movl_simm_T1(int32_t val
)
218 tcg_gen_movi_tl(cpu_T
[1], val
);
221 static inline void gen_movl_reg_TN(int reg
, TCGv tn
)
224 tcg_gen_movi_tl(tn
, 0);
226 tcg_gen_mov_tl(tn
, cpu_gregs
[reg
]);
228 tcg_gen_ld_tl(tn
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
232 static inline void gen_movl_reg_T0(int reg
)
234 gen_movl_reg_TN(reg
, cpu_T
[0]);
237 static inline void gen_movl_reg_T1(int reg
)
239 gen_movl_reg_TN(reg
, cpu_T
[1]);
243 static inline void gen_movl_reg_T2(int reg
)
245 gen_movl_reg_TN(reg
, cpu_T
[2]);
248 #endif /* __i386__ */
249 static inline void gen_movl_TN_reg(int reg
, TCGv tn
)
254 tcg_gen_mov_tl(cpu_gregs
[reg
], tn
);
256 tcg_gen_st_tl(tn
, cpu_regwptr
, (reg
- 8) * sizeof(target_ulong
));
260 static inline void gen_movl_T0_reg(int reg
)
262 gen_movl_TN_reg(reg
, cpu_T
[0]);
265 static inline void gen_movl_T1_reg(int reg
)
267 gen_movl_TN_reg(reg
, cpu_T
[1]);
270 static inline void gen_op_movl_T0_env(size_t offset
)
272 tcg_gen_ld_i32(cpu_T
[0], cpu_env
, offset
);
275 static inline void gen_op_movl_env_T0(size_t offset
)
277 tcg_gen_st_i32(cpu_T
[0], cpu_env
, offset
);
280 static inline void gen_op_movtl_T0_env(size_t offset
)
282 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offset
);
285 static inline void gen_op_movtl_env_T0(size_t offset
)
287 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offset
);
290 static inline void gen_op_add_T1_T0(void)
292 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
295 static inline void gen_op_or_T1_T0(void)
297 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
300 static inline void gen_op_xor_T1_T0(void)
302 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
305 static inline void gen_jmp_im(target_ulong pc
)
307 tcg_gen_movi_tl(cpu_tmp0
, pc
);
308 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, pc
));
311 static inline void gen_movl_npc_im(target_ulong npc
)
313 tcg_gen_movi_tl(cpu_tmp0
, npc
);
314 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, npc
));
317 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
,
318 target_ulong pc
, target_ulong npc
)
320 TranslationBlock
*tb
;
323 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
324 (npc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
)) {
325 /* jump to same page: we can use a direct jump */
326 tcg_gen_goto_tb(tb_num
);
328 gen_movl_npc_im(npc
);
329 tcg_gen_exit_tb((long)tb
+ tb_num
);
331 /* jump to another page: currently not optimized */
333 gen_movl_npc_im(npc
);
339 static inline void gen_mov_reg_N(TCGv reg
, TCGv src
)
341 tcg_gen_shri_i32(reg
, src
, 23);
342 tcg_gen_andi_tl(reg
, reg
, 0x1);
345 static inline void gen_mov_reg_Z(TCGv reg
, TCGv src
)
347 tcg_gen_shri_i32(reg
, src
, 22);
348 tcg_gen_andi_tl(reg
, reg
, 0x1);
351 static inline void gen_mov_reg_V(TCGv reg
, TCGv src
)
353 tcg_gen_shri_i32(reg
, src
, 21);
354 tcg_gen_andi_tl(reg
, reg
, 0x1);
357 static inline void gen_mov_reg_C(TCGv reg
, TCGv src
)
359 tcg_gen_shri_i32(reg
, src
, 20);
360 tcg_gen_andi_tl(reg
, reg
, 0x1);
363 static inline void gen_op_exception(int exception
)
367 r_except
= tcg_temp_new(TCG_TYPE_I32
);
368 tcg_gen_movi_i32(r_except
, exception
);
369 tcg_gen_helper_0_1(raise_exception
, r_except
);
372 static inline void gen_cc_clear(void)
374 tcg_gen_movi_i32(cpu_psr
, 0);
375 #ifdef TARGET_SPARC64
376 tcg_gen_movi_i32(cpu_xcc
, 0);
382 env->psr |= PSR_ZERO;
383 if ((int32_t) T0 < 0)
386 static inline void gen_cc_NZ(TCGv dst
)
391 l1
= gen_new_label();
392 l2
= gen_new_label();
393 r_zero
= tcg_const_tl(0);
394 tcg_gen_brcond_i32(TCG_COND_NE
, dst
, r_zero
, l1
);
395 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_ZERO
);
397 tcg_gen_brcond_i32(TCG_COND_GE
, dst
, r_zero
, l2
);
398 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_NEG
);
400 #ifdef TARGET_SPARC64
404 l3
= gen_new_label();
405 l4
= gen_new_label();
406 tcg_gen_brcond_tl(TCG_COND_NE
, dst
, r_zero
, l3
);
407 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_ZERO
);
409 tcg_gen_brcond_tl(TCG_COND_GE
, dst
, r_zero
, l4
);
410 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_NEG
);
418 env->psr |= PSR_CARRY;
420 static inline void gen_cc_C_add(TCGv dst
, TCGv src1
)
424 l1
= gen_new_label();
425 tcg_gen_brcond_i32(TCG_COND_GEU
, dst
, src1
, l1
);
426 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_CARRY
);
428 #ifdef TARGET_SPARC64
432 l2
= gen_new_label();
433 tcg_gen_brcond_tl(TCG_COND_GEU
, dst
, src1
, l2
);
434 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_CARRY
);
441 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
444 static inline void gen_cc_V_add(TCGv dst
, TCGv src1
, TCGv src2
)
446 TCGv r_temp
, r_temp2
, r_temp3
, r_zero
;
449 l1
= gen_new_label();
451 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
452 r_temp2
= tcg_temp_new(TCG_TYPE_TL
);
453 r_temp3
= tcg_temp_new(TCG_TYPE_TL
);
454 r_zero
= tcg_const_tl(0);
455 tcg_gen_xor_tl(r_temp
, src1
, src2
);
456 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
457 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
458 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
459 tcg_gen_andi_tl(r_temp3
, r_temp
, (1 << 31));
460 tcg_gen_brcond_i32(TCG_COND_EQ
, r_temp3
, r_zero
, l1
);
461 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_OVF
);
463 #ifdef TARGET_SPARC64
467 l2
= gen_new_label();
468 tcg_gen_xor_tl(r_temp
, src1
, src2
);
469 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
470 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
471 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
472 tcg_gen_andi_tl(r_temp3
, r_temp
, (1ULL << 63));
473 tcg_gen_brcond_tl(TCG_COND_EQ
, r_temp3
, r_zero
, l2
);
474 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_OVF
);
480 static inline void gen_add_tv(TCGv dst
, TCGv src1
, TCGv src2
)
482 TCGv r_temp
, r_temp2
, r_temp3
, r_zero
;
485 l1
= gen_new_label();
487 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
488 r_temp2
= tcg_temp_new(TCG_TYPE_TL
);
489 r_temp3
= tcg_temp_new(TCG_TYPE_TL
);
490 r_zero
= tcg_const_tl(0);
491 tcg_gen_xor_tl(r_temp
, src1
, src2
);
492 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
493 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
494 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
495 tcg_gen_andi_tl(r_temp3
, r_temp
, (1 << 31));
496 tcg_gen_brcond_i32(TCG_COND_EQ
, r_temp3
, r_zero
, l1
);
497 gen_op_exception(TT_TOVF
);
499 #ifdef TARGET_SPARC64
503 l2
= gen_new_label();
504 tcg_gen_xor_tl(r_temp
, src1
, src2
);
505 tcg_gen_xori_tl(r_temp
, r_temp
, -1);
506 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
507 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
508 tcg_gen_andi_tl(r_temp3
, r_temp
, (1ULL << 63));
509 tcg_gen_brcond_tl(TCG_COND_EQ
, r_temp3
, r_zero
, l2
);
510 gen_op_exception(TT_TOVF
);
516 static inline void gen_cc_V_tag(TCGv src1
, TCGv src2
)
521 l1
= gen_new_label();
522 r_zero
= tcg_const_tl(0);
523 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
524 tcg_gen_or_tl(r_temp
, src1
, src2
);
525 tcg_gen_andi_tl(r_temp
, r_temp
, 0x3);
526 tcg_gen_brcond_tl(TCG_COND_EQ
, r_temp
, r_zero
, l1
);
527 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_OVF
);
531 static inline void gen_tag_tv(TCGv src1
, TCGv src2
)
536 l1
= gen_new_label();
537 r_zero
= tcg_const_tl(0);
538 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
539 tcg_gen_or_tl(r_temp
, src1
, src2
);
540 tcg_gen_andi_tl(r_temp
, r_temp
, 0x3);
541 tcg_gen_brcond_tl(TCG_COND_EQ
, r_temp
, r_zero
, l1
);
542 gen_op_exception(TT_TOVF
);
546 static inline void gen_op_add_T1_T0_cc(void)
548 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
549 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
552 gen_cc_C_add(cpu_T
[0], cpu_cc_src
);
553 gen_cc_V_add(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
556 static inline void gen_op_addx_T1_T0_cc(void)
558 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
559 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
560 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
562 gen_cc_C_add(cpu_T
[0], cpu_cc_src
);
563 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
564 gen_cc_C_add(cpu_T
[0], cpu_cc_src
);
566 gen_cc_V_add(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
569 static inline void gen_op_tadd_T1_T0_cc(void)
571 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
572 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
575 gen_cc_C_add(cpu_T
[0], cpu_cc_src
);
576 gen_cc_V_add(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
577 gen_cc_V_tag(cpu_cc_src
, cpu_T
[1]);
580 static inline void gen_op_tadd_T1_T0_ccTV(void)
582 gen_tag_tv(cpu_T
[0], cpu_T
[1]);
583 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
584 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
585 gen_add_tv(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
588 gen_cc_C_add(cpu_T
[0], cpu_cc_src
);
593 env->psr |= PSR_CARRY;
595 static inline void gen_cc_C_sub(TCGv src1
, TCGv src2
)
599 l1
= gen_new_label();
600 tcg_gen_brcond_i32(TCG_COND_GEU
, src1
, src2
, l1
);
601 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_CARRY
);
603 #ifdef TARGET_SPARC64
607 l2
= gen_new_label();
608 tcg_gen_brcond_tl(TCG_COND_GEU
, src1
, src2
, l2
);
609 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_CARRY
);
616 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
619 static inline void gen_cc_V_sub(TCGv dst
, TCGv src1
, TCGv src2
)
621 TCGv r_temp
, r_temp2
, r_temp3
, r_zero
;
624 l1
= gen_new_label();
626 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
627 r_temp2
= tcg_temp_new(TCG_TYPE_TL
);
628 r_temp3
= tcg_temp_new(TCG_TYPE_TL
);
629 r_zero
= tcg_const_tl(0);
630 tcg_gen_xor_tl(r_temp
, src1
, src2
);
631 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
632 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
633 tcg_gen_andi_tl(r_temp3
, r_temp
, (1 << 31));
634 tcg_gen_brcond_i32(TCG_COND_EQ
, r_temp3
, r_zero
, l1
);
635 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_OVF
);
637 #ifdef TARGET_SPARC64
641 l2
= gen_new_label();
642 tcg_gen_xor_tl(r_temp
, src1
, src2
);
643 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
644 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
645 tcg_gen_andi_tl(r_temp3
, r_temp
, (1ULL << 63));
646 tcg_gen_brcond_tl(TCG_COND_EQ
, r_temp3
, r_zero
, l2
);
647 tcg_gen_ori_i32(cpu_xcc
, cpu_xcc
, PSR_OVF
);
653 static inline void gen_sub_tv(TCGv dst
, TCGv src1
, TCGv src2
)
655 TCGv r_temp
, r_temp2
, r_temp3
, r_zero
;
658 l1
= gen_new_label();
660 r_temp
= tcg_temp_new(TCG_TYPE_TL
);
661 r_temp2
= tcg_temp_new(TCG_TYPE_TL
);
662 r_temp3
= tcg_temp_new(TCG_TYPE_TL
);
663 r_zero
= tcg_const_tl(0);
664 tcg_gen_xor_tl(r_temp
, src1
, src2
);
665 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
666 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
667 tcg_gen_andi_tl(r_temp3
, r_temp
, (1 << 31));
668 tcg_gen_brcond_i32(TCG_COND_EQ
, r_temp3
, r_zero
, l1
);
669 gen_op_exception(TT_TOVF
);
671 #ifdef TARGET_SPARC64
675 l2
= gen_new_label();
676 tcg_gen_xor_tl(r_temp
, src1
, src2
);
677 tcg_gen_xor_tl(r_temp2
, src1
, dst
);
678 tcg_gen_and_tl(r_temp
, r_temp
, r_temp2
);
679 tcg_gen_andi_tl(r_temp3
, r_temp
, (1ULL << 63));
680 tcg_gen_brcond_tl(TCG_COND_EQ
, r_temp3
, r_zero
, l2
);
681 gen_op_exception(TT_TOVF
);
687 static inline void gen_op_sub_T1_T0_cc(void)
689 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
690 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
693 gen_cc_C_sub(cpu_cc_src
, cpu_T
[1]);
694 gen_cc_V_sub(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
697 static inline void gen_op_subx_T1_T0_cc(void)
699 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
700 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
701 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
703 gen_cc_C_sub(cpu_T
[0], cpu_cc_src
);
704 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
705 gen_cc_C_sub(cpu_T
[0], cpu_cc_src
);
707 gen_cc_V_sub(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
710 static inline void gen_op_tsub_T1_T0_cc(void)
712 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
713 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
716 gen_cc_C_sub(cpu_cc_src
, cpu_T
[1]);
717 gen_cc_V_sub(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
718 gen_cc_V_tag(cpu_cc_src
, cpu_T
[1]);
721 static inline void gen_op_tsub_T1_T0_ccTV(void)
723 gen_tag_tv(cpu_T
[0], cpu_T
[1]);
724 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
725 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
726 gen_sub_tv(cpu_T
[0], cpu_cc_src
, cpu_T
[1]);
729 gen_cc_C_sub(cpu_cc_src
, cpu_T
[1]);
732 static inline void gen_op_div_cc(void)
739 l1
= gen_new_label();
740 r_zero
= tcg_const_tl(0);
741 tcg_gen_brcond_i32(TCG_COND_EQ
, cpu_T
[1], r_zero
, l1
);
742 tcg_gen_ori_i32(cpu_psr
, cpu_psr
, PSR_OVF
);
746 static inline void gen_op_logic_T0_cc(void)
753 static inline void gen_op_eval_ba(TCGv dst
)
755 tcg_gen_movi_tl(dst
, 1);
759 static inline void gen_op_eval_be(TCGv dst
, TCGv src
)
761 gen_mov_reg_Z(dst
, src
);
765 static inline void gen_op_eval_ble(TCGv dst
, TCGv src
)
769 r_flag
= tcg_temp_new(TCG_TYPE_TL
);
770 gen_mov_reg_N(r_flag
, src
);
771 gen_mov_reg_V(dst
, src
);
772 tcg_gen_xor_tl(dst
, dst
, r_flag
);
773 gen_mov_reg_Z(r_flag
, src
);
774 tcg_gen_or_tl(dst
, dst
, r_flag
);
778 static inline void gen_op_eval_bl(TCGv dst
, TCGv src
)
782 r_V
= tcg_temp_new(TCG_TYPE_TL
);
783 gen_mov_reg_V(r_V
, src
);
784 gen_mov_reg_N(dst
, src
);
785 tcg_gen_xor_tl(dst
, dst
, r_V
);
789 static inline void gen_op_eval_bleu(TCGv dst
, TCGv src
)
793 r_Z
= tcg_temp_new(TCG_TYPE_TL
);
794 gen_mov_reg_Z(r_Z
, src
);
795 gen_mov_reg_C(dst
, src
);
796 tcg_gen_or_tl(dst
, dst
, r_Z
);
800 static inline void gen_op_eval_bcs(TCGv dst
, TCGv src
)
802 gen_mov_reg_C(dst
, src
);
806 static inline void gen_op_eval_bvs(TCGv dst
, TCGv src
)
808 gen_mov_reg_V(dst
, src
);
812 static inline void gen_op_eval_bn(TCGv dst
)
814 tcg_gen_movi_tl(dst
, 0);
818 static inline void gen_op_eval_bneg(TCGv dst
, TCGv src
)
820 gen_mov_reg_N(dst
, src
);
824 static inline void gen_op_eval_bne(TCGv dst
, TCGv src
)
826 gen_mov_reg_Z(dst
, src
);
827 tcg_gen_xori_tl(dst
, dst
, 0x1);
831 static inline void gen_op_eval_bg(TCGv dst
, TCGv src
)
835 r_flag
= tcg_temp_new(TCG_TYPE_TL
);
836 gen_mov_reg_N(r_flag
, src
);
837 gen_mov_reg_V(dst
, src
);
838 tcg_gen_xor_tl(dst
, dst
, r_flag
);
839 gen_mov_reg_Z(r_flag
, src
);
840 tcg_gen_or_tl(dst
, dst
, r_flag
);
841 tcg_gen_xori_tl(dst
, dst
, 0x1);
845 static inline void gen_op_eval_bge(TCGv dst
, TCGv src
)
849 r_V
= tcg_temp_new(TCG_TYPE_TL
);
850 gen_mov_reg_V(r_V
, src
);
851 gen_mov_reg_N(dst
, src
);
852 tcg_gen_xor_tl(dst
, dst
, r_V
);
853 tcg_gen_xori_tl(dst
, dst
, 0x1);
857 static inline void gen_op_eval_bgu(TCGv dst
, TCGv src
)
861 r_Z
= tcg_temp_new(TCG_TYPE_TL
);
862 gen_mov_reg_Z(r_Z
, src
);
863 gen_mov_reg_C(dst
, src
);
864 tcg_gen_or_tl(dst
, dst
, r_Z
);
865 tcg_gen_xori_tl(dst
, dst
, 0x1);
869 static inline void gen_op_eval_bcc(TCGv dst
, TCGv src
)
871 gen_mov_reg_C(dst
, src
);
872 tcg_gen_xori_tl(dst
, dst
, 0x1);
876 static inline void gen_op_eval_bpos(TCGv dst
, TCGv src
)
878 gen_mov_reg_N(dst
, src
);
879 tcg_gen_xori_tl(dst
, dst
, 0x1);
883 static inline void gen_op_eval_bvc(TCGv dst
, TCGv src
)
885 gen_mov_reg_V(dst
, src
);
886 tcg_gen_xori_tl(dst
, dst
, 0x1);
890 FPSR bit field FCC1 | FCC0:
896 static inline void gen_mov_reg_FCC0(TCGv reg
, TCGv src
,
897 unsigned int fcc_offset
)
899 tcg_gen_shri_i32(reg
, src
, 10 + fcc_offset
);
900 tcg_gen_andi_tl(reg
, reg
, 0x1);
903 static inline void gen_mov_reg_FCC1(TCGv reg
, TCGv src
,
904 unsigned int fcc_offset
)
906 tcg_gen_shri_i32(reg
, src
, 11 + fcc_offset
);
907 tcg_gen_andi_tl(reg
, reg
, 0x1);
911 static inline void gen_op_eval_fbne(TCGv dst
, TCGv src
,
912 unsigned int fcc_offset
)
916 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
917 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
918 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
919 tcg_gen_or_tl(dst
, dst
, r_fcc1
);
922 // 1 or 2: FCC0 ^ FCC1
923 static inline void gen_op_eval_fblg(TCGv dst
, TCGv src
,
924 unsigned int fcc_offset
)
928 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
929 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
930 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
931 tcg_gen_xor_tl(dst
, dst
, r_fcc1
);
935 static inline void gen_op_eval_fbul(TCGv dst
, TCGv src
,
936 unsigned int fcc_offset
)
938 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
942 static inline void gen_op_eval_fbl(TCGv dst
, TCGv src
,
943 unsigned int fcc_offset
)
947 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
948 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
949 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
950 tcg_gen_xori_tl(r_fcc1
, r_fcc1
, 0x1);
951 tcg_gen_and_tl(dst
, dst
, r_fcc1
);
955 static inline void gen_op_eval_fbug(TCGv dst
, TCGv src
,
956 unsigned int fcc_offset
)
958 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
962 static inline void gen_op_eval_fbg(TCGv dst
, TCGv src
,
963 unsigned int fcc_offset
)
967 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
968 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
969 tcg_gen_xori_tl(dst
, dst
, 0x1);
970 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
971 tcg_gen_and_tl(dst
, dst
, r_fcc1
);
975 static inline void gen_op_eval_fbu(TCGv dst
, TCGv src
,
976 unsigned int fcc_offset
)
980 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
981 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
982 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
983 tcg_gen_and_tl(dst
, dst
, r_fcc1
);
987 static inline void gen_op_eval_fbe(TCGv dst
, TCGv src
,
988 unsigned int fcc_offset
)
992 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
993 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
994 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
995 tcg_gen_or_tl(dst
, dst
, r_fcc1
);
996 tcg_gen_xori_tl(dst
, dst
, 0x1);
999 // 0 or 3: !(FCC0 ^ FCC1)
1000 static inline void gen_op_eval_fbue(TCGv dst
, TCGv src
,
1001 unsigned int fcc_offset
)
1005 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
1006 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1007 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
1008 tcg_gen_xor_tl(dst
, dst
, r_fcc1
);
1009 tcg_gen_xori_tl(dst
, dst
, 0x1);
1013 static inline void gen_op_eval_fbge(TCGv dst
, TCGv src
,
1014 unsigned int fcc_offset
)
1016 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1017 tcg_gen_xori_tl(dst
, dst
, 0x1);
1020 // !1: !(FCC0 & !FCC1)
1021 static inline void gen_op_eval_fbuge(TCGv dst
, TCGv src
,
1022 unsigned int fcc_offset
)
1026 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
1027 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1028 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
1029 tcg_gen_xori_tl(r_fcc1
, r_fcc1
, 0x1);
1030 tcg_gen_and_tl(dst
, dst
, r_fcc1
);
1031 tcg_gen_xori_tl(dst
, dst
, 0x1);
1035 static inline void gen_op_eval_fble(TCGv dst
, TCGv src
,
1036 unsigned int fcc_offset
)
1038 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
1039 tcg_gen_xori_tl(dst
, dst
, 0x1);
1042 // !2: !(!FCC0 & FCC1)
1043 static inline void gen_op_eval_fbule(TCGv dst
, TCGv src
,
1044 unsigned int fcc_offset
)
1048 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
1049 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1050 tcg_gen_xori_tl(dst
, dst
, 0x1);
1051 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
1052 tcg_gen_and_tl(dst
, dst
, r_fcc1
);
1053 tcg_gen_xori_tl(dst
, dst
, 0x1);
1056 // !3: !(FCC0 & FCC1)
1057 static inline void gen_op_eval_fbo(TCGv dst
, TCGv src
,
1058 unsigned int fcc_offset
)
1062 r_fcc1
= tcg_temp_new(TCG_TYPE_TL
);
1063 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
1064 gen_mov_reg_FCC1(r_fcc1
, src
, fcc_offset
);
1065 tcg_gen_and_tl(dst
, dst
, r_fcc1
);
1066 tcg_gen_xori_tl(dst
, dst
, 0x1);
1069 static inline void gen_branch2(DisasContext
*dc
, target_ulong pc1
,
1070 target_ulong pc2
, TCGv r_cond
)
1075 l1
= gen_new_label();
1076 r_zero
= tcg_const_tl(0);
1078 tcg_gen_brcond_tl(TCG_COND_EQ
, r_cond
, r_zero
, l1
);
1080 gen_goto_tb(dc
, 0, pc1
, pc1
+ 4);
1083 gen_goto_tb(dc
, 1, pc2
, pc2
+ 4);
1086 static inline void gen_branch_a(DisasContext
*dc
, target_ulong pc1
,
1087 target_ulong pc2
, TCGv r_cond
)
1092 l1
= gen_new_label();
1093 r_zero
= tcg_const_tl(0);
1095 tcg_gen_brcond_tl(TCG_COND_EQ
, r_cond
, r_zero
, l1
);
1097 gen_goto_tb(dc
, 0, pc2
, pc1
);
1100 gen_goto_tb(dc
, 1, pc2
+ 4, pc2
+ 8);
1103 static inline void gen_branch(DisasContext
*dc
, target_ulong pc
,
1106 gen_goto_tb(dc
, 0, pc
, npc
);
1109 static inline void gen_generic_branch(target_ulong npc1
, target_ulong npc2
,
1115 l1
= gen_new_label();
1116 l2
= gen_new_label();
1117 r_zero
= tcg_const_tl(0);
1119 tcg_gen_brcond_tl(TCG_COND_EQ
, r_cond
, r_zero
, l1
);
1121 gen_movl_npc_im(npc1
);
1122 gen_op_jmp_label(l2
);
1125 gen_movl_npc_im(npc2
);
1129 /* call this function before using T2 as it may have been set for a jump */
1130 static inline void flush_T2(DisasContext
* dc
)
1132 if (dc
->npc
== JUMP_PC
) {
1133 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_T
[2]);
1134 dc
->npc
= DYNAMIC_PC
;
1138 static inline void save_npc(DisasContext
* dc
)
1140 if (dc
->npc
== JUMP_PC
) {
1141 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_T
[2]);
1142 dc
->npc
= DYNAMIC_PC
;
1143 } else if (dc
->npc
!= DYNAMIC_PC
) {
1144 gen_movl_npc_im(dc
->npc
);
1148 static inline void save_state(DisasContext
* dc
)
1154 static inline void gen_mov_pc_npc(DisasContext
* dc
)
1156 if (dc
->npc
== JUMP_PC
) {
1157 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_T
[2]);
1158 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, npc
));
1159 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, pc
));
1160 dc
->pc
= DYNAMIC_PC
;
1161 } else if (dc
->npc
== DYNAMIC_PC
) {
1162 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, npc
));
1163 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, pc
));
1164 dc
->pc
= DYNAMIC_PC
;
1170 static inline void gen_op_next_insn(void)
1172 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, npc
));
1173 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, pc
));
1174 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, 4);
1175 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, npc
));
1178 static inline void gen_cond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1182 #ifdef TARGET_SPARC64
1192 gen_op_eval_bn(r_dst
);
1195 gen_op_eval_be(r_dst
, r_src
);
1198 gen_op_eval_ble(r_dst
, r_src
);
1201 gen_op_eval_bl(r_dst
, r_src
);
1204 gen_op_eval_bleu(r_dst
, r_src
);
1207 gen_op_eval_bcs(r_dst
, r_src
);
1210 gen_op_eval_bneg(r_dst
, r_src
);
1213 gen_op_eval_bvs(r_dst
, r_src
);
1216 gen_op_eval_ba(r_dst
);
1219 gen_op_eval_bne(r_dst
, r_src
);
1222 gen_op_eval_bg(r_dst
, r_src
);
1225 gen_op_eval_bge(r_dst
, r_src
);
1228 gen_op_eval_bgu(r_dst
, r_src
);
1231 gen_op_eval_bcc(r_dst
, r_src
);
1234 gen_op_eval_bpos(r_dst
, r_src
);
1237 gen_op_eval_bvc(r_dst
, r_src
);
1242 static inline void gen_fcond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1245 unsigned int offset
;
1247 r_src
= tcg_temp_new(TCG_TYPE_TL
);
1248 tcg_gen_ld_tl(r_src
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
1268 gen_op_eval_bn(r_dst
);
1271 gen_op_eval_fbne(r_dst
, r_src
, offset
);
1274 gen_op_eval_fblg(r_dst
, r_src
, offset
);
1277 gen_op_eval_fbul(r_dst
, r_src
, offset
);
1280 gen_op_eval_fbl(r_dst
, r_src
, offset
);
1283 gen_op_eval_fbug(r_dst
, r_src
, offset
);
1286 gen_op_eval_fbg(r_dst
, r_src
, offset
);
1289 gen_op_eval_fbu(r_dst
, r_src
, offset
);
1292 gen_op_eval_ba(r_dst
);
1295 gen_op_eval_fbe(r_dst
, r_src
, offset
);
1298 gen_op_eval_fbue(r_dst
, r_src
, offset
);
1301 gen_op_eval_fbge(r_dst
, r_src
, offset
);
1304 gen_op_eval_fbuge(r_dst
, r_src
, offset
);
1307 gen_op_eval_fble(r_dst
, r_src
, offset
);
1310 gen_op_eval_fbule(r_dst
, r_src
, offset
);
1313 gen_op_eval_fbo(r_dst
, r_src
, offset
);
1318 #ifdef TARGET_SPARC64
1320 static const int gen_tcg_cond_reg
[8] = {
1331 static inline void gen_cond_reg(TCGv r_dst
, int cond
)
1336 l1
= gen_new_label();
1337 r_zero
= tcg_const_tl(0);
1338 tcg_gen_mov_tl(r_dst
, r_zero
);
1339 tcg_gen_brcond_tl(gen_tcg_cond_reg
[cond
], cpu_T
[0], r_zero
, l1
);
1340 tcg_gen_movi_tl(r_dst
, 1);
1345 /* XXX: potentially incorrect if dynamic npc */
1346 static void do_branch(DisasContext
* dc
, int32_t offset
, uint32_t insn
, int cc
)
1348 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1349 target_ulong target
= dc
->pc
+ offset
;
1352 /* unconditional not taken */
1354 dc
->pc
= dc
->npc
+ 4;
1355 dc
->npc
= dc
->pc
+ 4;
1358 dc
->npc
= dc
->pc
+ 4;
1360 } else if (cond
== 0x8) {
1361 /* unconditional taken */
1364 dc
->npc
= dc
->pc
+ 4;
1371 gen_cond(cpu_T
[2], cc
, cond
);
1373 gen_branch_a(dc
, target
, dc
->npc
, cpu_T
[2]);
1377 dc
->jump_pc
[0] = target
;
1378 dc
->jump_pc
[1] = dc
->npc
+ 4;
1384 /* XXX: potentially incorrect if dynamic npc */
1385 static void do_fbranch(DisasContext
* dc
, int32_t offset
, uint32_t insn
, int cc
)
1387 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1388 target_ulong target
= dc
->pc
+ offset
;
1391 /* unconditional not taken */
1393 dc
->pc
= dc
->npc
+ 4;
1394 dc
->npc
= dc
->pc
+ 4;
1397 dc
->npc
= dc
->pc
+ 4;
1399 } else if (cond
== 0x8) {
1400 /* unconditional taken */
1403 dc
->npc
= dc
->pc
+ 4;
1410 gen_fcond(cpu_T
[2], cc
, cond
);
1412 gen_branch_a(dc
, target
, dc
->npc
, cpu_T
[2]);
1416 dc
->jump_pc
[0] = target
;
1417 dc
->jump_pc
[1] = dc
->npc
+ 4;
1423 #ifdef TARGET_SPARC64
1424 /* XXX: potentially incorrect if dynamic npc */
1425 static void do_branch_reg(DisasContext
* dc
, int32_t offset
, uint32_t insn
)
1427 unsigned int cond
= GET_FIELD_SP(insn
, 25, 27), a
= (insn
& (1 << 29));
1428 target_ulong target
= dc
->pc
+ offset
;
1431 gen_cond_reg(cpu_T
[2], cond
);
1433 gen_branch_a(dc
, target
, dc
->npc
, cpu_T
[2]);
1437 dc
->jump_pc
[0] = target
;
1438 dc
->jump_pc
[1] = dc
->npc
+ 4;
1443 static GenOpFunc
* const gen_fcmps
[4] = {
1450 static GenOpFunc
* const gen_fcmpd
[4] = {
1457 #if defined(CONFIG_USER_ONLY)
1458 static GenOpFunc
* const gen_fcmpq
[4] = {
1466 static GenOpFunc
* const gen_fcmpes
[4] = {
1473 static GenOpFunc
* const gen_fcmped
[4] = {
1480 #if defined(CONFIG_USER_ONLY)
1481 static GenOpFunc
* const gen_fcmpeq
[4] = {
1489 static inline void gen_op_fcmps(int fccno
)
1491 tcg_gen_helper_0_0(gen_fcmps
[fccno
]);
1494 static inline void gen_op_fcmpd(int fccno
)
1496 tcg_gen_helper_0_0(gen_fcmpd
[fccno
]);
1499 #if defined(CONFIG_USER_ONLY)
1500 static inline void gen_op_fcmpq(int fccno
)
1502 tcg_gen_helper_0_0(gen_fcmpq
[fccno
]);
1506 static inline void gen_op_fcmpes(int fccno
)
1508 tcg_gen_helper_0_0(gen_fcmpes
[fccno
]);
1511 static inline void gen_op_fcmped(int fccno
)
1513 tcg_gen_helper_0_0(gen_fcmped
[fccno
]);
1516 #if defined(CONFIG_USER_ONLY)
1517 static inline void gen_op_fcmpeq(int fccno
)
1519 tcg_gen_helper_0_0(gen_fcmpeq
[fccno
]);
1525 static inline void gen_op_fcmps(int fccno
)
1527 tcg_gen_helper_0_0(helper_fcmps
);
1530 static inline void gen_op_fcmpd(int fccno
)
1532 tcg_gen_helper_0_0(helper_fcmpd
);
1535 #if defined(CONFIG_USER_ONLY)
1536 static inline void gen_op_fcmpq(int fccno
)
1538 tcg_gen_helper_0_0(helper_fcmpq
);
1542 static inline void gen_op_fcmpes(int fccno
)
1544 tcg_gen_helper_0_0(helper_fcmpes
);
1547 static inline void gen_op_fcmped(int fccno
)
1549 tcg_gen_helper_0_0(helper_fcmped
);
1552 #if defined(CONFIG_USER_ONLY)
1553 static inline void gen_op_fcmpeq(int fccno
)
1555 tcg_gen_helper_0_0(helper_fcmpeq
);
1561 static inline void gen_op_fpexception_im(int fsr_flags
)
1563 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
1564 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, ~FSR_FTT_MASK
);
1565 tcg_gen_ori_tl(cpu_tmp0
, cpu_tmp0
, fsr_flags
);
1566 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
1567 gen_op_exception(TT_FP_EXCP
);
1570 static int gen_trap_ifnofpu(DisasContext
* dc
)
1572 #if !defined(CONFIG_USER_ONLY)
1573 if (!dc
->fpu_enabled
) {
1575 gen_op_exception(TT_NFPU_INSN
);
1583 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1585 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
1586 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, ~(FSR_FTT_MASK
| FSR_CEXC_MASK
));
1587 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
1590 static inline void gen_clear_float_exceptions(void)
1592 tcg_gen_helper_0_0(helper_clear_float_exceptions
);
1596 #ifdef TARGET_SPARC64
1597 static inline void gen_ld_asi(int insn
, int size
, int sign
)
1600 TCGv r_size
, r_sign
;
1602 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1603 r_sign
= tcg_temp_new(TCG_TYPE_I32
);
1604 tcg_gen_movi_i32(r_size
, size
);
1605 tcg_gen_movi_i32(r_sign
, sign
);
1607 offset
= GET_FIELD(insn
, 25, 31);
1608 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1609 tcg_gen_ld_i32(cpu_T
[1], cpu_env
, offsetof(CPUSPARCState
, asi
));
1611 asi
= GET_FIELD(insn
, 19, 26);
1612 tcg_gen_movi_i32(cpu_T
[1], asi
);
1614 tcg_gen_helper_1_4(helper_ld_asi
, cpu_T
[1], cpu_T
[0], cpu_T
[1], r_size
,
1618 static inline void gen_st_asi(int insn
, int size
)
1623 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1624 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1625 tcg_gen_movi_i32(r_size
, size
);
1627 offset
= GET_FIELD(insn
, 25, 31);
1628 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1629 tcg_gen_ld_i32(r_asi
, cpu_env
, offsetof(CPUSPARCState
, asi
));
1631 asi
= GET_FIELD(insn
, 19, 26);
1632 tcg_gen_movi_i32(r_asi
, asi
);
1634 tcg_gen_helper_0_4(helper_st_asi
, cpu_T
[0], cpu_T
[1], r_asi
, r_size
);
1637 static inline void gen_ldf_asi(int insn
, int size
, int rd
)
1640 TCGv r_asi
, r_size
, r_rd
;
1642 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1643 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1644 r_rd
= tcg_temp_new(TCG_TYPE_I32
);
1645 tcg_gen_movi_i32(r_size
, size
);
1646 tcg_gen_movi_i32(r_rd
, rd
);
1648 offset
= GET_FIELD(insn
, 25, 31);
1649 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1650 tcg_gen_ld_i32(r_asi
, cpu_env
, offsetof(CPUSPARCState
, asi
));
1652 asi
= GET_FIELD(insn
, 19, 26);
1653 tcg_gen_movi_i32(r_asi
, asi
);
1655 tcg_gen_helper_0_4(helper_ldf_asi
, cpu_T
[0], r_asi
, r_size
, r_rd
);
1658 static inline void gen_stf_asi(int insn
, int size
, int rd
)
1661 TCGv r_asi
, r_size
, r_rd
;
1663 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1664 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1665 r_rd
= tcg_temp_new(TCG_TYPE_I32
);
1666 tcg_gen_movi_i32(r_size
, size
);
1667 tcg_gen_movi_i32(r_rd
, rd
);
1669 offset
= GET_FIELD(insn
, 25, 31);
1670 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1671 tcg_gen_ld_i32(r_asi
, cpu_env
, offsetof(CPUSPARCState
, asi
));
1673 asi
= GET_FIELD(insn
, 19, 26);
1674 tcg_gen_movi_i32(r_asi
, asi
);
1676 tcg_gen_helper_0_4(helper_stf_asi
, cpu_T
[0], r_asi
, r_size
, r_rd
);
1679 static inline void gen_swap_asi(int insn
)
1682 TCGv r_size
, r_sign
, r_temp
;
1684 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1685 r_sign
= tcg_temp_new(TCG_TYPE_I32
);
1686 r_temp
= tcg_temp_new(TCG_TYPE_I32
);
1687 tcg_gen_movi_i32(r_size
, 4);
1688 tcg_gen_movi_i32(r_sign
, 0);
1690 offset
= GET_FIELD(insn
, 25, 31);
1691 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1692 tcg_gen_ld_i32(cpu_T
[1], cpu_env
, offsetof(CPUSPARCState
, asi
));
1694 asi
= GET_FIELD(insn
, 19, 26);
1695 tcg_gen_movi_i32(cpu_T
[1], asi
);
1697 tcg_gen_helper_1_4(helper_ld_asi
, r_temp
, cpu_T
[0], cpu_T
[1], r_size
,
1699 tcg_gen_helper_0_4(helper_st_asi
, cpu_T
[0], cpu_T
[1], r_size
, r_sign
);
1700 tcg_gen_mov_i32(cpu_T
[1], r_temp
);
1703 static inline void gen_ldda_asi(int insn
)
1706 TCGv r_size
, r_sign
, r_dword
;
1708 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1709 r_sign
= tcg_temp_new(TCG_TYPE_I32
);
1710 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
1711 tcg_gen_movi_i32(r_size
, 8);
1712 tcg_gen_movi_i32(r_sign
, 0);
1714 offset
= GET_FIELD(insn
, 25, 31);
1715 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1716 tcg_gen_ld_i32(cpu_T
[1], cpu_env
, offsetof(CPUSPARCState
, asi
));
1718 asi
= GET_FIELD(insn
, 19, 26);
1719 tcg_gen_movi_i32(cpu_T
[1], asi
);
1721 tcg_gen_helper_1_4(helper_ld_asi
, r_dword
, cpu_T
[0], cpu_T
[1], r_size
,
1723 tcg_gen_trunc_i64_i32(cpu_T
[0], r_dword
);
1724 tcg_gen_shri_i64(r_dword
, r_dword
, 32);
1725 tcg_gen_trunc_i64_i32(cpu_T
[1], r_dword
);
1728 static inline void gen_cas_asi(int insn
, int rd
)
1733 r_val1
= tcg_temp_new(TCG_TYPE_I32
);
1734 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1735 gen_movl_reg_TN(rd
, r_val1
);
1737 offset
= GET_FIELD(insn
, 25, 31);
1738 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1739 tcg_gen_ld_i32(r_asi
, cpu_env
, offsetof(CPUSPARCState
, asi
));
1741 asi
= GET_FIELD(insn
, 19, 26);
1742 tcg_gen_movi_i32(r_asi
, asi
);
1744 tcg_gen_helper_1_4(helper_cas_asi
, cpu_T
[1], cpu_T
[0], r_val1
, cpu_T
[1],
1748 static inline void gen_casx_asi(int insn
, int rd
)
1753 r_val1
= tcg_temp_new(TCG_TYPE_I64
);
1754 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1755 gen_movl_reg_TN(rd
, r_val1
);
1757 offset
= GET_FIELD(insn
, 25, 31);
1758 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
1759 tcg_gen_ld_i32(r_asi
, cpu_env
, offsetof(CPUSPARCState
, asi
));
1761 asi
= GET_FIELD(insn
, 19, 26);
1762 tcg_gen_movi_i32(r_asi
, asi
);
1764 tcg_gen_helper_1_4(helper_casx_asi
, cpu_T
[1], cpu_T
[0], r_val1
, cpu_T
[1],
1768 #elif !defined(CONFIG_USER_ONLY)
1770 static inline void gen_ld_asi(int insn
, int size
, int sign
)
1773 TCGv r_size
, r_sign
, r_dword
;
1775 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1776 r_sign
= tcg_temp_new(TCG_TYPE_I32
);
1777 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
1778 tcg_gen_movi_i32(r_size
, size
);
1779 tcg_gen_movi_i32(r_sign
, sign
);
1780 asi
= GET_FIELD(insn
, 19, 26);
1781 tcg_gen_movi_i32(cpu_T
[1], asi
);
1782 tcg_gen_helper_1_4(helper_ld_asi
, r_dword
, cpu_T
[0], cpu_T
[1], r_size
,
1784 tcg_gen_trunc_i64_i32(cpu_T
[1], r_dword
);
1787 static inline void gen_st_asi(int insn
, int size
)
1790 TCGv r_dword
, r_asi
, r_size
;
1792 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
1793 tcg_gen_extu_i32_i64(r_dword
, cpu_T
[1]);
1794 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1795 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1796 asi
= GET_FIELD(insn
, 19, 26);
1797 tcg_gen_movi_i32(r_asi
, asi
);
1798 tcg_gen_movi_i32(r_size
, size
);
1799 tcg_gen_helper_0_4(helper_st_asi
, cpu_T
[0], r_dword
, r_asi
, r_size
);
1802 static inline void gen_swap_asi(int insn
)
1805 TCGv r_size
, r_sign
, r_temp
;
1807 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1808 r_sign
= tcg_temp_new(TCG_TYPE_I32
);
1809 r_temp
= tcg_temp_new(TCG_TYPE_I32
);
1810 tcg_gen_movi_i32(r_size
, 4);
1811 tcg_gen_movi_i32(r_sign
, 0);
1812 asi
= GET_FIELD(insn
, 19, 26);
1813 tcg_gen_movi_i32(cpu_T
[1], asi
);
1814 tcg_gen_helper_1_4(helper_ld_asi
, r_temp
, cpu_T
[0], cpu_T
[1], r_size
,
1816 tcg_gen_helper_0_4(helper_st_asi
, cpu_T
[0], cpu_T
[1], r_size
, r_sign
);
1817 tcg_gen_mov_i32(cpu_T
[1], r_temp
);
1820 static inline void gen_ldda_asi(int insn
)
1823 TCGv r_size
, r_sign
, r_dword
;
1825 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1826 r_sign
= tcg_temp_new(TCG_TYPE_I32
);
1827 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
1828 tcg_gen_movi_i32(r_size
, 8);
1829 tcg_gen_movi_i32(r_sign
, 0);
1830 asi
= GET_FIELD(insn
, 19, 26);
1831 tcg_gen_movi_i32(cpu_T
[1], asi
);
1832 tcg_gen_helper_1_4(helper_ld_asi
, r_dword
, cpu_T
[0], cpu_T
[1], r_size
,
1834 tcg_gen_trunc_i64_i32(cpu_T
[0], r_dword
);
1835 tcg_gen_shri_i64(r_dword
, r_dword
, 32);
1836 tcg_gen_trunc_i64_i32(cpu_T
[1], r_dword
);
1840 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1841 static inline void gen_ldstub_asi(int insn
)
1844 TCGv r_dword
, r_asi
, r_size
;
1846 gen_ld_asi(insn
, 1, 0);
1848 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
1849 r_asi
= tcg_temp_new(TCG_TYPE_I32
);
1850 r_size
= tcg_temp_new(TCG_TYPE_I32
);
1851 asi
= GET_FIELD(insn
, 19, 26);
1852 tcg_gen_movi_i32(r_dword
, 0xff);
1853 tcg_gen_movi_i32(r_asi
, asi
);
1854 tcg_gen_movi_i32(r_size
, 1);
1855 tcg_gen_helper_0_4(helper_st_asi
, cpu_T
[0], r_dword
, r_asi
, r_size
);
1859 /* before an instruction, dc->pc must be static */
1860 static void disas_sparc_insn(DisasContext
* dc
)
1862 unsigned int insn
, opc
, rs1
, rs2
, rd
;
1864 insn
= ldl_code(dc
->pc
);
1865 opc
= GET_FIELD(insn
, 0, 1);
1867 rd
= GET_FIELD(insn
, 2, 6);
1869 case 0: /* branches/sethi */
1871 unsigned int xop
= GET_FIELD(insn
, 7, 9);
1874 #ifdef TARGET_SPARC64
1875 case 0x1: /* V9 BPcc */
1879 target
= GET_FIELD_SP(insn
, 0, 18);
1880 target
= sign_extend(target
, 18);
1882 cc
= GET_FIELD_SP(insn
, 20, 21);
1884 do_branch(dc
, target
, insn
, 0);
1886 do_branch(dc
, target
, insn
, 1);
1891 case 0x3: /* V9 BPr */
1893 target
= GET_FIELD_SP(insn
, 0, 13) |
1894 (GET_FIELD_SP(insn
, 20, 21) << 14);
1895 target
= sign_extend(target
, 16);
1897 rs1
= GET_FIELD(insn
, 13, 17);
1898 gen_movl_reg_T0(rs1
);
1899 do_branch_reg(dc
, target
, insn
);
1902 case 0x5: /* V9 FBPcc */
1904 int cc
= GET_FIELD_SP(insn
, 20, 21);
1905 if (gen_trap_ifnofpu(dc
))
1907 target
= GET_FIELD_SP(insn
, 0, 18);
1908 target
= sign_extend(target
, 19);
1910 do_fbranch(dc
, target
, insn
, cc
);
1914 case 0x7: /* CBN+x */
1919 case 0x2: /* BN+x */
1921 target
= GET_FIELD(insn
, 10, 31);
1922 target
= sign_extend(target
, 22);
1924 do_branch(dc
, target
, insn
, 0);
1927 case 0x6: /* FBN+x */
1929 if (gen_trap_ifnofpu(dc
))
1931 target
= GET_FIELD(insn
, 10, 31);
1932 target
= sign_extend(target
, 22);
1934 do_fbranch(dc
, target
, insn
, 0);
1937 case 0x4: /* SETHI */
1942 uint32_t value
= GET_FIELD(insn
, 10, 31);
1943 tcg_gen_movi_tl(cpu_T
[0], value
<< 10);
1944 gen_movl_T0_reg(rd
);
1949 case 0x0: /* UNIMPL */
1958 target_long target
= GET_FIELDs(insn
, 2, 31) << 2;
1960 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
1961 gen_movl_T0_reg(15);
1967 case 2: /* FPU & Logical Operations */
1969 unsigned int xop
= GET_FIELD(insn
, 7, 12);
1970 if (xop
== 0x3a) { /* generate trap */
1973 rs1
= GET_FIELD(insn
, 13, 17);
1974 gen_movl_reg_T0(rs1
);
1976 rs2
= GET_FIELD(insn
, 25, 31);
1977 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], rs2
);
1979 rs2
= GET_FIELD(insn
, 27, 31);
1983 gen_movl_reg_T1(rs2
);
1989 cond
= GET_FIELD(insn
, 3, 6);
1992 tcg_gen_helper_0_1(helper_trap
, cpu_T
[0]);
1993 } else if (cond
!= 0) {
1994 #ifdef TARGET_SPARC64
1996 int cc
= GET_FIELD_SP(insn
, 11, 12);
2000 gen_cond(cpu_T
[2], 0, cond
);
2002 gen_cond(cpu_T
[2], 1, cond
);
2008 gen_cond(cpu_T
[2], 0, cond
);
2010 tcg_gen_helper_0_2(helper_trapcc
, cpu_T
[0], cpu_T
[2]);
2016 } else if (xop
== 0x28) {
2017 rs1
= GET_FIELD(insn
, 13, 17);
2020 #ifndef TARGET_SPARC64
2021 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2022 manual, rdy on the microSPARC
2024 case 0x0f: /* stbar in the SPARCv8 manual,
2025 rdy on the microSPARC II */
2026 case 0x10 ... 0x1f: /* implementation-dependent in the
2027 SPARCv8 manual, rdy on the
2030 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, y
));
2031 gen_movl_T0_reg(rd
);
2033 #ifdef TARGET_SPARC64
2034 case 0x2: /* V9 rdccr */
2036 gen_movl_T0_reg(rd
);
2038 case 0x3: /* V9 rdasi */
2039 gen_op_movl_T0_env(offsetof(CPUSPARCState
, asi
));
2040 gen_movl_T0_reg(rd
);
2042 case 0x4: /* V9 rdtick */
2046 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
2047 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2048 offsetof(CPUState
, tick
));
2049 tcg_gen_helper_1_1(helper_tick_get_count
, cpu_T
[0],
2051 gen_movl_T0_reg(rd
);
2054 case 0x5: /* V9 rdpc */
2055 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
2056 gen_movl_T0_reg(rd
);
2058 case 0x6: /* V9 rdfprs */
2059 gen_op_movl_T0_env(offsetof(CPUSPARCState
, fprs
));
2060 gen_movl_T0_reg(rd
);
2062 case 0xf: /* V9 membar */
2063 break; /* no effect */
2064 case 0x13: /* Graphics Status */
2065 if (gen_trap_ifnofpu(dc
))
2067 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, gsr
));
2068 gen_movl_T0_reg(rd
);
2070 case 0x17: /* Tick compare */
2071 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, tick_cmpr
));
2072 gen_movl_T0_reg(rd
);
2074 case 0x18: /* System tick */
2078 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
2079 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2080 offsetof(CPUState
, stick
));
2081 tcg_gen_helper_1_1(helper_tick_get_count
, cpu_T
[0],
2083 gen_movl_T0_reg(rd
);
2086 case 0x19: /* System tick compare */
2087 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, stick_cmpr
));
2088 gen_movl_T0_reg(rd
);
2090 case 0x10: /* Performance Control */
2091 case 0x11: /* Performance Instrumentation Counter */
2092 case 0x12: /* Dispatch Control */
2093 case 0x14: /* Softint set, WO */
2094 case 0x15: /* Softint clear, WO */
2095 case 0x16: /* Softint write */
2100 #if !defined(CONFIG_USER_ONLY)
2101 } else if (xop
== 0x29) { /* rdpsr / UA2005 rdhpr */
2102 #ifndef TARGET_SPARC64
2103 if (!supervisor(dc
))
2105 tcg_gen_helper_1_0(helper_rdpsr
, cpu_T
[0]);
2107 if (!hypervisor(dc
))
2109 rs1
= GET_FIELD(insn
, 13, 17);
2112 // gen_op_rdhpstate();
2115 // gen_op_rdhtstate();
2118 gen_op_movl_T0_env(offsetof(CPUSPARCState
, hintp
));
2121 gen_op_movl_T0_env(offsetof(CPUSPARCState
, htba
));
2124 gen_op_movl_T0_env(offsetof(CPUSPARCState
, hver
));
2126 case 31: // hstick_cmpr
2127 gen_op_movl_env_T0(offsetof(CPUSPARCState
, hstick_cmpr
));
2133 gen_movl_T0_reg(rd
);
2135 } else if (xop
== 0x2a) { /* rdwim / V9 rdpr */
2136 if (!supervisor(dc
))
2138 #ifdef TARGET_SPARC64
2139 rs1
= GET_FIELD(insn
, 13, 17);
2145 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2146 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2147 offsetof(CPUState
, tsptr
));
2148 tcg_gen_ld_tl(cpu_T
[0], r_tsptr
,
2149 offsetof(trap_state
, tpc
));
2156 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2157 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2158 offsetof(CPUState
, tsptr
));
2159 tcg_gen_ld_tl(cpu_T
[0], r_tsptr
,
2160 offsetof(trap_state
, tnpc
));
2167 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2168 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2169 offsetof(CPUState
, tsptr
));
2170 tcg_gen_ld_tl(cpu_T
[0], r_tsptr
,
2171 offsetof(trap_state
, tstate
));
2178 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
2179 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
2180 offsetof(CPUState
, tsptr
));
2181 tcg_gen_ld_i32(cpu_T
[0], r_tsptr
,
2182 offsetof(trap_state
, tt
));
2189 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
2190 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2191 offsetof(CPUState
, tick
));
2192 tcg_gen_helper_1_1(helper_tick_get_count
, cpu_T
[0],
2194 gen_movl_T0_reg(rd
);
2198 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, tbr
));
2201 gen_op_movl_T0_env(offsetof(CPUSPARCState
, pstate
));
2204 gen_op_movl_T0_env(offsetof(CPUSPARCState
, tl
));
2207 gen_op_movl_T0_env(offsetof(CPUSPARCState
, psrpil
));
2213 gen_op_movl_T0_env(offsetof(CPUSPARCState
, cansave
));
2215 case 11: // canrestore
2216 gen_op_movl_T0_env(offsetof(CPUSPARCState
, canrestore
));
2218 case 12: // cleanwin
2219 gen_op_movl_T0_env(offsetof(CPUSPARCState
, cleanwin
));
2221 case 13: // otherwin
2222 gen_op_movl_T0_env(offsetof(CPUSPARCState
, otherwin
));
2225 gen_op_movl_T0_env(offsetof(CPUSPARCState
, wstate
));
2227 case 16: // UA2005 gl
2228 gen_op_movl_T0_env(offsetof(CPUSPARCState
, gl
));
2230 case 26: // UA2005 strand status
2231 if (!hypervisor(dc
))
2233 gen_op_movl_T0_env(offsetof(CPUSPARCState
, ssr
));
2236 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, version
));
2243 gen_op_movl_T0_env(offsetof(CPUSPARCState
, wim
));
2245 gen_movl_T0_reg(rd
);
2247 } else if (xop
== 0x2b) { /* rdtbr / V9 flushw */
2248 #ifdef TARGET_SPARC64
2251 if (!supervisor(dc
))
2253 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, tbr
));
2254 gen_movl_T0_reg(rd
);
2258 } else if (xop
== 0x34) { /* FPU Operations */
2259 if (gen_trap_ifnofpu(dc
))
2261 gen_op_clear_ieee_excp_and_FTT();
2262 rs1
= GET_FIELD(insn
, 13, 17);
2263 rs2
= GET_FIELD(insn
, 27, 31);
2264 xop
= GET_FIELD(insn
, 18, 26);
2266 case 0x1: /* fmovs */
2267 gen_op_load_fpr_FT0(rs2
);
2268 gen_op_store_FT0_fpr(rd
);
2270 case 0x5: /* fnegs */
2271 gen_op_load_fpr_FT1(rs2
);
2273 gen_op_store_FT0_fpr(rd
);
2275 case 0x9: /* fabss */
2276 gen_op_load_fpr_FT1(rs2
);
2277 tcg_gen_helper_0_0(helper_fabss
);
2278 gen_op_store_FT0_fpr(rd
);
2280 case 0x29: /* fsqrts */
2281 gen_op_load_fpr_FT1(rs2
);
2282 gen_clear_float_exceptions();
2283 tcg_gen_helper_0_0(helper_fsqrts
);
2284 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2285 gen_op_store_FT0_fpr(rd
);
2287 case 0x2a: /* fsqrtd */
2288 gen_op_load_fpr_DT1(DFPREG(rs2
));
2289 gen_clear_float_exceptions();
2290 tcg_gen_helper_0_0(helper_fsqrtd
);
2291 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2292 gen_op_store_DT0_fpr(DFPREG(rd
));
2294 case 0x2b: /* fsqrtq */
2295 #if defined(CONFIG_USER_ONLY)
2296 gen_op_load_fpr_QT1(QFPREG(rs2
));
2297 gen_clear_float_exceptions();
2298 tcg_gen_helper_0_0(helper_fsqrtq
);
2299 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2300 gen_op_store_QT0_fpr(QFPREG(rd
));
2306 gen_op_load_fpr_FT0(rs1
);
2307 gen_op_load_fpr_FT1(rs2
);
2308 gen_clear_float_exceptions();
2310 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2311 gen_op_store_FT0_fpr(rd
);
2314 gen_op_load_fpr_DT0(DFPREG(rs1
));
2315 gen_op_load_fpr_DT1(DFPREG(rs2
));
2316 gen_clear_float_exceptions();
2318 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2319 gen_op_store_DT0_fpr(DFPREG(rd
));
2321 case 0x43: /* faddq */
2322 #if defined(CONFIG_USER_ONLY)
2323 gen_op_load_fpr_QT0(QFPREG(rs1
));
2324 gen_op_load_fpr_QT1(QFPREG(rs2
));
2325 gen_clear_float_exceptions();
2327 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2328 gen_op_store_QT0_fpr(QFPREG(rd
));
2334 gen_op_load_fpr_FT0(rs1
);
2335 gen_op_load_fpr_FT1(rs2
);
2336 gen_clear_float_exceptions();
2338 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2339 gen_op_store_FT0_fpr(rd
);
2342 gen_op_load_fpr_DT0(DFPREG(rs1
));
2343 gen_op_load_fpr_DT1(DFPREG(rs2
));
2344 gen_clear_float_exceptions();
2346 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2347 gen_op_store_DT0_fpr(DFPREG(rd
));
2349 case 0x47: /* fsubq */
2350 #if defined(CONFIG_USER_ONLY)
2351 gen_op_load_fpr_QT0(QFPREG(rs1
));
2352 gen_op_load_fpr_QT1(QFPREG(rs2
));
2353 gen_clear_float_exceptions();
2355 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2356 gen_op_store_QT0_fpr(QFPREG(rd
));
2362 gen_op_load_fpr_FT0(rs1
);
2363 gen_op_load_fpr_FT1(rs2
);
2364 gen_clear_float_exceptions();
2366 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2367 gen_op_store_FT0_fpr(rd
);
2370 gen_op_load_fpr_DT0(DFPREG(rs1
));
2371 gen_op_load_fpr_DT1(DFPREG(rs2
));
2372 gen_clear_float_exceptions();
2374 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2375 gen_op_store_DT0_fpr(DFPREG(rd
));
2377 case 0x4b: /* fmulq */
2378 #if defined(CONFIG_USER_ONLY)
2379 gen_op_load_fpr_QT0(QFPREG(rs1
));
2380 gen_op_load_fpr_QT1(QFPREG(rs2
));
2381 gen_clear_float_exceptions();
2383 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2384 gen_op_store_QT0_fpr(QFPREG(rd
));
2390 gen_op_load_fpr_FT0(rs1
);
2391 gen_op_load_fpr_FT1(rs2
);
2392 gen_clear_float_exceptions();
2394 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2395 gen_op_store_FT0_fpr(rd
);
2398 gen_op_load_fpr_DT0(DFPREG(rs1
));
2399 gen_op_load_fpr_DT1(DFPREG(rs2
));
2400 gen_clear_float_exceptions();
2402 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2403 gen_op_store_DT0_fpr(DFPREG(rd
));
2405 case 0x4f: /* fdivq */
2406 #if defined(CONFIG_USER_ONLY)
2407 gen_op_load_fpr_QT0(QFPREG(rs1
));
2408 gen_op_load_fpr_QT1(QFPREG(rs2
));
2409 gen_clear_float_exceptions();
2411 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2412 gen_op_store_QT0_fpr(QFPREG(rd
));
2418 gen_op_load_fpr_FT0(rs1
);
2419 gen_op_load_fpr_FT1(rs2
);
2420 gen_clear_float_exceptions();
2422 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2423 gen_op_store_DT0_fpr(DFPREG(rd
));
2425 case 0x6e: /* fdmulq */
2426 #if defined(CONFIG_USER_ONLY)
2427 gen_op_load_fpr_DT0(DFPREG(rs1
));
2428 gen_op_load_fpr_DT1(DFPREG(rs2
));
2429 gen_clear_float_exceptions();
2431 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2432 gen_op_store_QT0_fpr(QFPREG(rd
));
2438 gen_op_load_fpr_FT1(rs2
);
2439 gen_clear_float_exceptions();
2441 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2442 gen_op_store_FT0_fpr(rd
);
2445 gen_op_load_fpr_DT1(DFPREG(rs2
));
2446 gen_clear_float_exceptions();
2448 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2449 gen_op_store_FT0_fpr(rd
);
2451 case 0xc7: /* fqtos */
2452 #if defined(CONFIG_USER_ONLY)
2453 gen_op_load_fpr_QT1(QFPREG(rs2
));
2454 gen_clear_float_exceptions();
2456 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2457 gen_op_store_FT0_fpr(rd
);
2463 gen_op_load_fpr_FT1(rs2
);
2465 gen_op_store_DT0_fpr(DFPREG(rd
));
2468 gen_op_load_fpr_FT1(rs2
);
2470 gen_op_store_DT0_fpr(DFPREG(rd
));
2472 case 0xcb: /* fqtod */
2473 #if defined(CONFIG_USER_ONLY)
2474 gen_op_load_fpr_QT1(QFPREG(rs2
));
2475 gen_clear_float_exceptions();
2477 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2478 gen_op_store_DT0_fpr(DFPREG(rd
));
2483 case 0xcc: /* fitoq */
2484 #if defined(CONFIG_USER_ONLY)
2485 gen_op_load_fpr_FT1(rs2
);
2487 gen_op_store_QT0_fpr(QFPREG(rd
));
2492 case 0xcd: /* fstoq */
2493 #if defined(CONFIG_USER_ONLY)
2494 gen_op_load_fpr_FT1(rs2
);
2496 gen_op_store_QT0_fpr(QFPREG(rd
));
2501 case 0xce: /* fdtoq */
2502 #if defined(CONFIG_USER_ONLY)
2503 gen_op_load_fpr_DT1(DFPREG(rs2
));
2505 gen_op_store_QT0_fpr(QFPREG(rd
));
2511 gen_op_load_fpr_FT1(rs2
);
2512 gen_clear_float_exceptions();
2514 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2515 gen_op_store_FT0_fpr(rd
);
2518 gen_op_load_fpr_DT1(DFPREG(rs2
));
2519 gen_clear_float_exceptions();
2521 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2522 gen_op_store_FT0_fpr(rd
);
2524 case 0xd3: /* fqtoi */
2525 #if defined(CONFIG_USER_ONLY)
2526 gen_op_load_fpr_QT1(QFPREG(rs2
));
2527 gen_clear_float_exceptions();
2529 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2530 gen_op_store_FT0_fpr(rd
);
2535 #ifdef TARGET_SPARC64
2536 case 0x2: /* V9 fmovd */
2537 gen_op_load_fpr_DT0(DFPREG(rs2
));
2538 gen_op_store_DT0_fpr(DFPREG(rd
));
2540 case 0x3: /* V9 fmovq */
2541 #if defined(CONFIG_USER_ONLY)
2542 gen_op_load_fpr_QT0(QFPREG(rs2
));
2543 gen_op_store_QT0_fpr(QFPREG(rd
));
2548 case 0x6: /* V9 fnegd */
2549 gen_op_load_fpr_DT1(DFPREG(rs2
));
2551 gen_op_store_DT0_fpr(DFPREG(rd
));
2553 case 0x7: /* V9 fnegq */
2554 #if defined(CONFIG_USER_ONLY)
2555 gen_op_load_fpr_QT1(QFPREG(rs2
));
2557 gen_op_store_QT0_fpr(QFPREG(rd
));
2562 case 0xa: /* V9 fabsd */
2563 gen_op_load_fpr_DT1(DFPREG(rs2
));
2564 tcg_gen_helper_0_0(helper_fabsd
);
2565 gen_op_store_DT0_fpr(DFPREG(rd
));
2567 case 0xb: /* V9 fabsq */
2568 #if defined(CONFIG_USER_ONLY)
2569 gen_op_load_fpr_QT1(QFPREG(rs2
));
2570 tcg_gen_helper_0_0(helper_fabsq
);
2571 gen_op_store_QT0_fpr(QFPREG(rd
));
2576 case 0x81: /* V9 fstox */
2577 gen_op_load_fpr_FT1(rs2
);
2578 gen_clear_float_exceptions();
2580 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2581 gen_op_store_DT0_fpr(DFPREG(rd
));
2583 case 0x82: /* V9 fdtox */
2584 gen_op_load_fpr_DT1(DFPREG(rs2
));
2585 gen_clear_float_exceptions();
2587 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2588 gen_op_store_DT0_fpr(DFPREG(rd
));
2590 case 0x83: /* V9 fqtox */
2591 #if defined(CONFIG_USER_ONLY)
2592 gen_op_load_fpr_QT1(QFPREG(rs2
));
2593 gen_clear_float_exceptions();
2595 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2596 gen_op_store_DT0_fpr(DFPREG(rd
));
2601 case 0x84: /* V9 fxtos */
2602 gen_op_load_fpr_DT1(DFPREG(rs2
));
2603 gen_clear_float_exceptions();
2605 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2606 gen_op_store_FT0_fpr(rd
);
2608 case 0x88: /* V9 fxtod */
2609 gen_op_load_fpr_DT1(DFPREG(rs2
));
2610 gen_clear_float_exceptions();
2612 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2613 gen_op_store_DT0_fpr(DFPREG(rd
));
2615 case 0x8c: /* V9 fxtoq */
2616 #if defined(CONFIG_USER_ONLY)
2617 gen_op_load_fpr_DT1(DFPREG(rs2
));
2618 gen_clear_float_exceptions();
2620 tcg_gen_helper_0_0(helper_check_ieee_exceptions
);
2621 gen_op_store_QT0_fpr(QFPREG(rd
));
2630 } else if (xop
== 0x35) { /* FPU Operations */
2631 #ifdef TARGET_SPARC64
2634 if (gen_trap_ifnofpu(dc
))
2636 gen_op_clear_ieee_excp_and_FTT();
2637 rs1
= GET_FIELD(insn
, 13, 17);
2638 rs2
= GET_FIELD(insn
, 27, 31);
2639 xop
= GET_FIELD(insn
, 18, 26);
2640 #ifdef TARGET_SPARC64
2641 if ((xop
& 0x11f) == 0x005) { // V9 fmovsr
2645 l1
= gen_new_label();
2646 r_zero
= tcg_const_tl(0);
2647 cond
= GET_FIELD_SP(insn
, 14, 17);
2648 rs1
= GET_FIELD(insn
, 13, 17);
2649 gen_movl_reg_T0(rs1
);
2650 tcg_gen_brcond_tl(gen_tcg_cond_reg
[cond
], cpu_T
[0], r_zero
, l1
);
2651 gen_op_load_fpr_FT0(rs2
);
2652 gen_op_store_FT0_fpr(rd
);
2655 } else if ((xop
& 0x11f) == 0x006) { // V9 fmovdr
2659 l1
= gen_new_label();
2660 r_zero
= tcg_const_tl(0);
2661 cond
= GET_FIELD_SP(insn
, 14, 17);
2662 rs1
= GET_FIELD(insn
, 13, 17);
2663 gen_movl_reg_T0(rs1
);
2664 tcg_gen_brcond_tl(gen_tcg_cond_reg
[cond
], cpu_T
[0], r_zero
, l1
);
2665 gen_op_load_fpr_DT0(DFPREG(rs2
));
2666 gen_op_store_DT0_fpr(DFPREG(rd
));
2669 } else if ((xop
& 0x11f) == 0x007) { // V9 fmovqr
2670 #if defined(CONFIG_USER_ONLY)
2674 l1
= gen_new_label();
2675 r_zero
= tcg_const_tl(0);
2676 cond
= GET_FIELD_SP(insn
, 14, 17);
2677 rs1
= GET_FIELD(insn
, 13, 17);
2678 gen_movl_reg_T0(rs1
);
2679 tcg_gen_brcond_tl(gen_tcg_cond_reg
[cond
], cpu_T
[0], r_zero
, l1
);
2680 gen_op_load_fpr_QT0(QFPREG(rs2
));
2681 gen_op_store_QT0_fpr(QFPREG(rd
));
2690 #ifdef TARGET_SPARC64
2691 #define FMOVCC(size_FDQ, fcc) \
2693 TCGv r_zero, r_cond; \
2696 l1 = gen_new_label(); \
2697 r_zero = tcg_const_tl(0); \
2698 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2699 cond = GET_FIELD_SP(insn, 14, 17); \
2700 gen_fcond(r_cond, fcc, cond); \
2701 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2702 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2703 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2704 gen_set_label(l1); \
2706 case 0x001: /* V9 fmovscc %fcc0 */
2709 case 0x002: /* V9 fmovdcc %fcc0 */
2712 case 0x003: /* V9 fmovqcc %fcc0 */
2713 #if defined(CONFIG_USER_ONLY)
2719 case 0x041: /* V9 fmovscc %fcc1 */
2722 case 0x042: /* V9 fmovdcc %fcc1 */
2725 case 0x043: /* V9 fmovqcc %fcc1 */
2726 #if defined(CONFIG_USER_ONLY)
2732 case 0x081: /* V9 fmovscc %fcc2 */
2735 case 0x082: /* V9 fmovdcc %fcc2 */
2738 case 0x083: /* V9 fmovqcc %fcc2 */
2739 #if defined(CONFIG_USER_ONLY)
2745 case 0x0c1: /* V9 fmovscc %fcc3 */
2748 case 0x0c2: /* V9 fmovdcc %fcc3 */
2751 case 0x0c3: /* V9 fmovqcc %fcc3 */
2752 #if defined(CONFIG_USER_ONLY)
2759 #define FMOVCC(size_FDQ, icc) \
2761 TCGv r_zero, r_cond; \
2764 l1 = gen_new_label(); \
2765 r_zero = tcg_const_tl(0); \
2766 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2767 cond = GET_FIELD_SP(insn, 14, 17); \
2768 gen_cond(r_cond, icc, cond); \
2769 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2770 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2771 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2772 gen_set_label(l1); \
2775 case 0x101: /* V9 fmovscc %icc */
2778 case 0x102: /* V9 fmovdcc %icc */
2780 case 0x103: /* V9 fmovqcc %icc */
2781 #if defined(CONFIG_USER_ONLY)
2787 case 0x181: /* V9 fmovscc %xcc */
2790 case 0x182: /* V9 fmovdcc %xcc */
2793 case 0x183: /* V9 fmovqcc %xcc */
2794 #if defined(CONFIG_USER_ONLY)
2802 case 0x51: /* fcmps, V9 %fcc */
2803 gen_op_load_fpr_FT0(rs1
);
2804 gen_op_load_fpr_FT1(rs2
);
2805 gen_op_fcmps(rd
& 3);
2807 case 0x52: /* fcmpd, V9 %fcc */
2808 gen_op_load_fpr_DT0(DFPREG(rs1
));
2809 gen_op_load_fpr_DT1(DFPREG(rs2
));
2810 gen_op_fcmpd(rd
& 3);
2812 case 0x53: /* fcmpq, V9 %fcc */
2813 #if defined(CONFIG_USER_ONLY)
2814 gen_op_load_fpr_QT0(QFPREG(rs1
));
2815 gen_op_load_fpr_QT1(QFPREG(rs2
));
2816 gen_op_fcmpq(rd
& 3);
2818 #else /* !defined(CONFIG_USER_ONLY) */
2821 case 0x55: /* fcmpes, V9 %fcc */
2822 gen_op_load_fpr_FT0(rs1
);
2823 gen_op_load_fpr_FT1(rs2
);
2824 gen_op_fcmpes(rd
& 3);
2826 case 0x56: /* fcmped, V9 %fcc */
2827 gen_op_load_fpr_DT0(DFPREG(rs1
));
2828 gen_op_load_fpr_DT1(DFPREG(rs2
));
2829 gen_op_fcmped(rd
& 3);
2831 case 0x57: /* fcmpeq, V9 %fcc */
2832 #if defined(CONFIG_USER_ONLY)
2833 gen_op_load_fpr_QT0(QFPREG(rs1
));
2834 gen_op_load_fpr_QT1(QFPREG(rs2
));
2835 gen_op_fcmpeq(rd
& 3);
2837 #else/* !defined(CONFIG_USER_ONLY) */
2844 } else if (xop
== 0x2) {
2847 rs1
= GET_FIELD(insn
, 13, 17);
2849 // or %g0, x, y -> mov T0, x; mov y, T0
2850 if (IS_IMM
) { /* immediate */
2851 rs2
= GET_FIELDs(insn
, 19, 31);
2852 tcg_gen_movi_tl(cpu_T
[0], (int)rs2
);
2853 } else { /* register */
2854 rs2
= GET_FIELD(insn
, 27, 31);
2855 gen_movl_reg_T0(rs2
);
2858 gen_movl_reg_T0(rs1
);
2859 if (IS_IMM
) { /* immediate */
2860 rs2
= GET_FIELDs(insn
, 19, 31);
2861 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], (int)rs2
);
2862 } else { /* register */
2863 // or x, %g0, y -> mov T1, x; mov y, T1
2864 rs2
= GET_FIELD(insn
, 27, 31);
2866 gen_movl_reg_T1(rs2
);
2871 gen_movl_T0_reg(rd
);
2873 #ifdef TARGET_SPARC64
2874 } else if (xop
== 0x25) { /* sll, V9 sllx */
2875 rs1
= GET_FIELD(insn
, 13, 17);
2876 gen_movl_reg_T0(rs1
);
2877 if (IS_IMM
) { /* immediate */
2878 rs2
= GET_FIELDs(insn
, 20, 31);
2879 if (insn
& (1 << 12)) {
2880 tcg_gen_shli_i64(cpu_T
[0], cpu_T
[0], rs2
& 0x3f);
2882 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], 0xffffffffULL
);
2883 tcg_gen_shli_i64(cpu_T
[0], cpu_T
[0], rs2
& 0x1f);
2885 } else { /* register */
2886 rs2
= GET_FIELD(insn
, 27, 31);
2887 gen_movl_reg_T1(rs2
);
2888 if (insn
& (1 << 12)) {
2889 tcg_gen_andi_i64(cpu_T
[1], cpu_T
[1], 0x3f);
2890 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2892 tcg_gen_andi_i64(cpu_T
[1], cpu_T
[1], 0x1f);
2893 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], 0xffffffffULL
);
2894 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2897 gen_movl_T0_reg(rd
);
2898 } else if (xop
== 0x26) { /* srl, V9 srlx */
2899 rs1
= GET_FIELD(insn
, 13, 17);
2900 gen_movl_reg_T0(rs1
);
2901 if (IS_IMM
) { /* immediate */
2902 rs2
= GET_FIELDs(insn
, 20, 31);
2903 if (insn
& (1 << 12)) {
2904 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], rs2
& 0x3f);
2906 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], 0xffffffffULL
);
2907 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], rs2
& 0x1f);
2909 } else { /* register */
2910 rs2
= GET_FIELD(insn
, 27, 31);
2911 gen_movl_reg_T1(rs2
);
2912 if (insn
& (1 << 12)) {
2913 tcg_gen_andi_i64(cpu_T
[1], cpu_T
[1], 0x3f);
2914 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2916 tcg_gen_andi_i64(cpu_T
[1], cpu_T
[1], 0x1f);
2917 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], 0xffffffffULL
);
2918 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2921 gen_movl_T0_reg(rd
);
2922 } else if (xop
== 0x27) { /* sra, V9 srax */
2923 rs1
= GET_FIELD(insn
, 13, 17);
2924 gen_movl_reg_T0(rs1
);
2925 if (IS_IMM
) { /* immediate */
2926 rs2
= GET_FIELDs(insn
, 20, 31);
2927 if (insn
& (1 << 12)) {
2928 tcg_gen_sari_i64(cpu_T
[0], cpu_T
[0], rs2
& 0x3f);
2930 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], 0xffffffffULL
);
2931 tcg_gen_ext_i32_i64(cpu_T
[0], cpu_T
[0]);
2932 tcg_gen_sari_i64(cpu_T
[0], cpu_T
[0], rs2
& 0x1f);
2934 } else { /* register */
2935 rs2
= GET_FIELD(insn
, 27, 31);
2936 gen_movl_reg_T1(rs2
);
2937 if (insn
& (1 << 12)) {
2938 tcg_gen_andi_i64(cpu_T
[1], cpu_T
[1], 0x3f);
2939 tcg_gen_sar_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2941 tcg_gen_andi_i64(cpu_T
[1], cpu_T
[1], 0x1f);
2942 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], 0xffffffffULL
);
2943 tcg_gen_sar_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2946 gen_movl_T0_reg(rd
);
2948 } else if (xop
< 0x36) {
2949 rs1
= GET_FIELD(insn
, 13, 17);
2950 gen_movl_reg_T0(rs1
);
2951 if (IS_IMM
) { /* immediate */
2952 rs2
= GET_FIELDs(insn
, 19, 31);
2953 gen_movl_simm_T1(rs2
);
2954 } else { /* register */
2955 rs2
= GET_FIELD(insn
, 27, 31);
2956 gen_movl_reg_T1(rs2
);
2959 switch (xop
& ~0x10) {
2962 gen_op_add_T1_T0_cc();
2967 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2969 gen_op_logic_T0_cc();
2972 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2974 gen_op_logic_T0_cc();
2977 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2979 gen_op_logic_T0_cc();
2983 gen_op_sub_T1_T0_cc();
2985 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2988 tcg_gen_xori_tl(cpu_T
[1], cpu_T
[1], -1);
2989 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2991 gen_op_logic_T0_cc();
2994 tcg_gen_xori_tl(cpu_T
[1], cpu_T
[1], -1);
2995 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2997 gen_op_logic_T0_cc();
3000 tcg_gen_xori_tl(cpu_T
[1], cpu_T
[1], -1);
3001 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3003 gen_op_logic_T0_cc();
3007 gen_op_addx_T1_T0_cc();
3009 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
3010 tcg_gen_add_tl(cpu_T
[1], cpu_T
[1], cpu_tmp0
);
3011 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3014 #ifdef TARGET_SPARC64
3015 case 0x9: /* V9 mulx */
3016 tcg_gen_mul_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3020 gen_op_umul_T1_T0();
3022 gen_op_logic_T0_cc();
3025 gen_op_smul_T1_T0();
3027 gen_op_logic_T0_cc();
3031 gen_op_subx_T1_T0_cc();
3033 gen_mov_reg_C(cpu_tmp0
, cpu_psr
);
3034 tcg_gen_add_tl(cpu_T
[1], cpu_T
[1], cpu_tmp0
);
3035 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3038 #ifdef TARGET_SPARC64
3039 case 0xd: /* V9 udivx */
3040 gen_op_udivx_T1_T0();
3044 gen_op_udiv_T1_T0();
3049 gen_op_sdiv_T1_T0();
3056 gen_movl_T0_reg(rd
);
3059 case 0x20: /* taddcc */
3060 gen_op_tadd_T1_T0_cc();
3061 gen_movl_T0_reg(rd
);
3063 case 0x21: /* tsubcc */
3064 gen_op_tsub_T1_T0_cc();
3065 gen_movl_T0_reg(rd
);
3067 case 0x22: /* taddcctv */
3069 gen_op_tadd_T1_T0_ccTV();
3070 gen_movl_T0_reg(rd
);
3072 case 0x23: /* tsubcctv */
3074 gen_op_tsub_T1_T0_ccTV();
3075 gen_movl_T0_reg(rd
);
3077 case 0x24: /* mulscc */
3078 gen_op_mulscc_T1_T0();
3079 gen_movl_T0_reg(rd
);
3081 #ifndef TARGET_SPARC64
3082 case 0x25: /* sll */
3083 tcg_gen_andi_i32(cpu_T
[1], cpu_T
[1], 0x1f);
3084 tcg_gen_shl_i32(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3085 gen_movl_T0_reg(rd
);
3087 case 0x26: /* srl */
3088 tcg_gen_andi_i32(cpu_T
[1], cpu_T
[1], 0x1f);
3089 tcg_gen_shr_i32(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3090 gen_movl_T0_reg(rd
);
3092 case 0x27: /* sra */
3093 tcg_gen_andi_i32(cpu_T
[1], cpu_T
[1], 0x1f);
3094 tcg_gen_sar_i32(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3095 gen_movl_T0_reg(rd
);
3103 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, y
));
3105 #ifndef TARGET_SPARC64
3106 case 0x01 ... 0x0f: /* undefined in the
3110 case 0x10 ... 0x1f: /* implementation-dependent
3116 case 0x2: /* V9 wrccr */
3120 case 0x3: /* V9 wrasi */
3122 gen_op_movl_env_T0(offsetof(CPUSPARCState
, asi
));
3124 case 0x6: /* V9 wrfprs */
3126 gen_op_movl_env_T0(offsetof(CPUSPARCState
, fprs
));
3132 case 0xf: /* V9 sir, nop if user */
3133 #if !defined(CONFIG_USER_ONLY)
3138 case 0x13: /* Graphics Status */
3139 if (gen_trap_ifnofpu(dc
))
3142 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, gsr
));
3144 case 0x17: /* Tick compare */
3145 #if !defined(CONFIG_USER_ONLY)
3146 if (!supervisor(dc
))
3153 gen_op_movtl_env_T0(offsetof(CPUSPARCState
,
3155 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3156 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3157 offsetof(CPUState
, tick
));
3158 tcg_gen_helper_0_2(helper_tick_set_limit
,
3159 r_tickptr
, cpu_T
[0]);
3162 case 0x18: /* System tick */
3163 #if !defined(CONFIG_USER_ONLY)
3164 if (!supervisor(dc
))
3171 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3172 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3173 offsetof(CPUState
, stick
));
3174 tcg_gen_helper_0_2(helper_tick_set_count
,
3175 r_tickptr
, cpu_T
[0]);
3178 case 0x19: /* System tick compare */
3179 #if !defined(CONFIG_USER_ONLY)
3180 if (!supervisor(dc
))
3187 gen_op_movtl_env_T0(offsetof(CPUSPARCState
,
3189 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3190 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3191 offsetof(CPUState
, stick
));
3192 tcg_gen_helper_0_2(helper_tick_set_limit
,
3193 r_tickptr
, cpu_T
[0]);
3197 case 0x10: /* Performance Control */
3198 case 0x11: /* Performance Instrumentation Counter */
3199 case 0x12: /* Dispatch Control */
3200 case 0x14: /* Softint set */
3201 case 0x15: /* Softint clear */
3202 case 0x16: /* Softint write */
3209 #if !defined(CONFIG_USER_ONLY)
3210 case 0x31: /* wrpsr, V9 saved, restored */
3212 if (!supervisor(dc
))
3214 #ifdef TARGET_SPARC64
3222 case 2: /* UA2005 allclean */
3223 case 3: /* UA2005 otherw */
3224 case 4: /* UA2005 normalw */
3225 case 5: /* UA2005 invalw */
3232 tcg_gen_helper_0_1(helper_wrpsr
, cpu_T
[0]);
3240 case 0x32: /* wrwim, V9 wrpr */
3242 if (!supervisor(dc
))
3245 #ifdef TARGET_SPARC64
3251 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3252 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3253 offsetof(CPUState
, tsptr
));
3254 tcg_gen_st_tl(cpu_T
[0], r_tsptr
,
3255 offsetof(trap_state
, tpc
));
3262 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3263 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3264 offsetof(CPUState
, tsptr
));
3265 tcg_gen_st_tl(cpu_T
[0], r_tsptr
,
3266 offsetof(trap_state
, tnpc
));
3273 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3274 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3275 offsetof(CPUState
, tsptr
));
3276 tcg_gen_st_tl(cpu_T
[0], r_tsptr
,
3277 offsetof(trap_state
, tstate
));
3284 r_tsptr
= tcg_temp_new(TCG_TYPE_PTR
);
3285 tcg_gen_ld_ptr(r_tsptr
, cpu_env
,
3286 offsetof(CPUState
, tsptr
));
3287 tcg_gen_st_i32(cpu_T
[0], r_tsptr
,
3288 offsetof(trap_state
, tt
));
3295 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3296 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3297 offsetof(CPUState
, tick
));
3298 tcg_gen_helper_0_2(helper_tick_set_count
,
3299 r_tickptr
, cpu_T
[0]);
3303 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, tbr
));
3307 tcg_gen_helper_0_1(helper_wrpstate
, cpu_T
[0]);
3313 gen_op_movl_env_T0(offsetof(CPUSPARCState
, tl
));
3316 gen_op_movl_env_T0(offsetof(CPUSPARCState
, psrpil
));
3322 gen_op_movl_env_T0(offsetof(CPUSPARCState
, cansave
));
3324 case 11: // canrestore
3325 gen_op_movl_env_T0(offsetof(CPUSPARCState
, canrestore
));
3327 case 12: // cleanwin
3328 gen_op_movl_env_T0(offsetof(CPUSPARCState
, cleanwin
));
3330 case 13: // otherwin
3331 gen_op_movl_env_T0(offsetof(CPUSPARCState
, otherwin
));
3334 gen_op_movl_env_T0(offsetof(CPUSPARCState
, wstate
));
3336 case 16: // UA2005 gl
3337 gen_op_movl_env_T0(offsetof(CPUSPARCState
, gl
));
3339 case 26: // UA2005 strand status
3340 if (!hypervisor(dc
))
3342 gen_op_movl_env_T0(offsetof(CPUSPARCState
, ssr
));
3348 tcg_gen_andi_i32(cpu_T
[0], cpu_T
[0], ((1 << NWINDOWS
) - 1));
3349 gen_op_movl_env_T0(offsetof(CPUSPARCState
, wim
));
3353 case 0x33: /* wrtbr, UA2005 wrhpr */
3355 #ifndef TARGET_SPARC64
3356 if (!supervisor(dc
))
3359 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, tbr
));
3361 if (!hypervisor(dc
))
3366 // XXX gen_op_wrhpstate();
3373 // XXX gen_op_wrhtstate();
3376 gen_op_movl_env_T0(offsetof(CPUSPARCState
, hintp
));
3379 gen_op_movl_env_T0(offsetof(CPUSPARCState
, htba
));
3381 case 31: // hstick_cmpr
3385 gen_op_movtl_env_T0(offsetof(CPUSPARCState
,
3387 r_tickptr
= tcg_temp_new(TCG_TYPE_PTR
);
3388 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3389 offsetof(CPUState
, hstick
));
3390 tcg_gen_helper_0_2(helper_tick_set_limit
,
3391 r_tickptr
, cpu_T
[0]);
3394 case 6: // hver readonly
3402 #ifdef TARGET_SPARC64
3403 case 0x2c: /* V9 movcc */
3405 int cc
= GET_FIELD_SP(insn
, 11, 12);
3406 int cond
= GET_FIELD_SP(insn
, 14, 17);
3411 if (insn
& (1 << 18)) {
3413 gen_cond(cpu_T
[2], 0, cond
);
3415 gen_cond(cpu_T
[2], 1, cond
);
3419 gen_fcond(cpu_T
[2], cc
, cond
);
3422 l1
= gen_new_label();
3424 r_zero
= tcg_const_tl(0);
3425 tcg_gen_brcond_tl(TCG_COND_EQ
, cpu_T
[2], r_zero
, l1
);
3426 if (IS_IMM
) { /* immediate */
3427 rs2
= GET_FIELD_SPs(insn
, 0, 10);
3428 gen_movl_simm_T1(rs2
);
3430 rs2
= GET_FIELD_SP(insn
, 0, 4);
3431 gen_movl_reg_T1(rs2
);
3433 gen_movl_T1_reg(rd
);
3437 case 0x2d: /* V9 sdivx */
3438 gen_op_sdivx_T1_T0();
3439 gen_movl_T0_reg(rd
);
3441 case 0x2e: /* V9 popc */
3443 if (IS_IMM
) { /* immediate */
3444 rs2
= GET_FIELD_SPs(insn
, 0, 12);
3445 gen_movl_simm_T1(rs2
);
3446 // XXX optimize: popc(constant)
3449 rs2
= GET_FIELD_SP(insn
, 0, 4);
3450 gen_movl_reg_T1(rs2
);
3452 tcg_gen_helper_1_1(helper_popc
, cpu_T
[0],
3454 gen_movl_T0_reg(rd
);
3456 case 0x2f: /* V9 movr */
3458 int cond
= GET_FIELD_SP(insn
, 10, 12);
3462 rs1
= GET_FIELD(insn
, 13, 17);
3463 gen_movl_reg_T0(rs1
);
3465 l1
= gen_new_label();
3467 r_zero
= tcg_const_tl(0);
3468 tcg_gen_brcond_tl(gen_tcg_cond_reg
[cond
], cpu_T
[0], r_zero
, l1
);
3469 if (IS_IMM
) { /* immediate */
3470 rs2
= GET_FIELD_SPs(insn
, 0, 9);
3471 gen_movl_simm_T1(rs2
);
3473 rs2
= GET_FIELD_SP(insn
, 0, 4);
3474 gen_movl_reg_T1(rs2
);
3476 gen_movl_T1_reg(rd
);
3485 } else if (xop
== 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3486 #ifdef TARGET_SPARC64
3487 int opf
= GET_FIELD_SP(insn
, 5, 13);
3488 rs1
= GET_FIELD(insn
, 13, 17);
3489 rs2
= GET_FIELD(insn
, 27, 31);
3490 if (gen_trap_ifnofpu(dc
))
3494 case 0x000: /* VIS I edge8cc */
3495 case 0x001: /* VIS II edge8n */
3496 case 0x002: /* VIS I edge8lcc */
3497 case 0x003: /* VIS II edge8ln */
3498 case 0x004: /* VIS I edge16cc */
3499 case 0x005: /* VIS II edge16n */
3500 case 0x006: /* VIS I edge16lcc */
3501 case 0x007: /* VIS II edge16ln */
3502 case 0x008: /* VIS I edge32cc */
3503 case 0x009: /* VIS II edge32n */
3504 case 0x00a: /* VIS I edge32lcc */
3505 case 0x00b: /* VIS II edge32ln */
3508 case 0x010: /* VIS I array8 */
3509 gen_movl_reg_T0(rs1
);
3510 gen_movl_reg_T1(rs2
);
3512 gen_movl_T0_reg(rd
);
3514 case 0x012: /* VIS I array16 */
3515 gen_movl_reg_T0(rs1
);
3516 gen_movl_reg_T1(rs2
);
3518 gen_movl_T0_reg(rd
);
3520 case 0x014: /* VIS I array32 */
3521 gen_movl_reg_T0(rs1
);
3522 gen_movl_reg_T1(rs2
);
3524 gen_movl_T0_reg(rd
);
3526 case 0x018: /* VIS I alignaddr */
3527 gen_movl_reg_T0(rs1
);
3528 gen_movl_reg_T1(rs2
);
3530 gen_movl_T0_reg(rd
);
3532 case 0x019: /* VIS II bmask */
3533 case 0x01a: /* VIS I alignaddrl */
3536 case 0x020: /* VIS I fcmple16 */
3537 gen_op_load_fpr_DT0(DFPREG(rs1
));
3538 gen_op_load_fpr_DT1(DFPREG(rs2
));
3540 gen_op_store_DT0_fpr(DFPREG(rd
));
3542 case 0x022: /* VIS I fcmpne16 */
3543 gen_op_load_fpr_DT0(DFPREG(rs1
));
3544 gen_op_load_fpr_DT1(DFPREG(rs2
));
3546 gen_op_store_DT0_fpr(DFPREG(rd
));
3548 case 0x024: /* VIS I fcmple32 */
3549 gen_op_load_fpr_DT0(DFPREG(rs1
));
3550 gen_op_load_fpr_DT1(DFPREG(rs2
));
3552 gen_op_store_DT0_fpr(DFPREG(rd
));
3554 case 0x026: /* VIS I fcmpne32 */
3555 gen_op_load_fpr_DT0(DFPREG(rs1
));
3556 gen_op_load_fpr_DT1(DFPREG(rs2
));
3558 gen_op_store_DT0_fpr(DFPREG(rd
));
3560 case 0x028: /* VIS I fcmpgt16 */
3561 gen_op_load_fpr_DT0(DFPREG(rs1
));
3562 gen_op_load_fpr_DT1(DFPREG(rs2
));
3564 gen_op_store_DT0_fpr(DFPREG(rd
));
3566 case 0x02a: /* VIS I fcmpeq16 */
3567 gen_op_load_fpr_DT0(DFPREG(rs1
));
3568 gen_op_load_fpr_DT1(DFPREG(rs2
));
3570 gen_op_store_DT0_fpr(DFPREG(rd
));
3572 case 0x02c: /* VIS I fcmpgt32 */
3573 gen_op_load_fpr_DT0(DFPREG(rs1
));
3574 gen_op_load_fpr_DT1(DFPREG(rs2
));
3576 gen_op_store_DT0_fpr(DFPREG(rd
));
3578 case 0x02e: /* VIS I fcmpeq32 */
3579 gen_op_load_fpr_DT0(DFPREG(rs1
));
3580 gen_op_load_fpr_DT1(DFPREG(rs2
));
3582 gen_op_store_DT0_fpr(DFPREG(rd
));
3584 case 0x031: /* VIS I fmul8x16 */
3585 gen_op_load_fpr_DT0(DFPREG(rs1
));
3586 gen_op_load_fpr_DT1(DFPREG(rs2
));
3588 gen_op_store_DT0_fpr(DFPREG(rd
));
3590 case 0x033: /* VIS I fmul8x16au */
3591 gen_op_load_fpr_DT0(DFPREG(rs1
));
3592 gen_op_load_fpr_DT1(DFPREG(rs2
));
3593 gen_op_fmul8x16au();
3594 gen_op_store_DT0_fpr(DFPREG(rd
));
3596 case 0x035: /* VIS I fmul8x16al */
3597 gen_op_load_fpr_DT0(DFPREG(rs1
));
3598 gen_op_load_fpr_DT1(DFPREG(rs2
));
3599 gen_op_fmul8x16al();
3600 gen_op_store_DT0_fpr(DFPREG(rd
));
3602 case 0x036: /* VIS I fmul8sux16 */
3603 gen_op_load_fpr_DT0(DFPREG(rs1
));
3604 gen_op_load_fpr_DT1(DFPREG(rs2
));
3605 gen_op_fmul8sux16();
3606 gen_op_store_DT0_fpr(DFPREG(rd
));
3608 case 0x037: /* VIS I fmul8ulx16 */
3609 gen_op_load_fpr_DT0(DFPREG(rs1
));
3610 gen_op_load_fpr_DT1(DFPREG(rs2
));
3611 gen_op_fmul8ulx16();
3612 gen_op_store_DT0_fpr(DFPREG(rd
));
3614 case 0x038: /* VIS I fmuld8sux16 */
3615 gen_op_load_fpr_DT0(DFPREG(rs1
));
3616 gen_op_load_fpr_DT1(DFPREG(rs2
));
3617 gen_op_fmuld8sux16();
3618 gen_op_store_DT0_fpr(DFPREG(rd
));
3620 case 0x039: /* VIS I fmuld8ulx16 */
3621 gen_op_load_fpr_DT0(DFPREG(rs1
));
3622 gen_op_load_fpr_DT1(DFPREG(rs2
));
3623 gen_op_fmuld8ulx16();
3624 gen_op_store_DT0_fpr(DFPREG(rd
));
3626 case 0x03a: /* VIS I fpack32 */
3627 case 0x03b: /* VIS I fpack16 */
3628 case 0x03d: /* VIS I fpackfix */
3629 case 0x03e: /* VIS I pdist */
3632 case 0x048: /* VIS I faligndata */
3633 gen_op_load_fpr_DT0(DFPREG(rs1
));
3634 gen_op_load_fpr_DT1(DFPREG(rs2
));
3635 gen_op_faligndata();
3636 gen_op_store_DT0_fpr(DFPREG(rd
));
3638 case 0x04b: /* VIS I fpmerge */
3639 gen_op_load_fpr_DT0(DFPREG(rs1
));
3640 gen_op_load_fpr_DT1(DFPREG(rs2
));
3642 gen_op_store_DT0_fpr(DFPREG(rd
));
3644 case 0x04c: /* VIS II bshuffle */
3647 case 0x04d: /* VIS I fexpand */
3648 gen_op_load_fpr_DT0(DFPREG(rs1
));
3649 gen_op_load_fpr_DT1(DFPREG(rs2
));
3651 gen_op_store_DT0_fpr(DFPREG(rd
));
3653 case 0x050: /* VIS I fpadd16 */
3654 gen_op_load_fpr_DT0(DFPREG(rs1
));
3655 gen_op_load_fpr_DT1(DFPREG(rs2
));
3657 gen_op_store_DT0_fpr(DFPREG(rd
));
3659 case 0x051: /* VIS I fpadd16s */
3660 gen_op_load_fpr_FT0(rs1
);
3661 gen_op_load_fpr_FT1(rs2
);
3663 gen_op_store_FT0_fpr(rd
);
3665 case 0x052: /* VIS I fpadd32 */
3666 gen_op_load_fpr_DT0(DFPREG(rs1
));
3667 gen_op_load_fpr_DT1(DFPREG(rs2
));
3669 gen_op_store_DT0_fpr(DFPREG(rd
));
3671 case 0x053: /* VIS I fpadd32s */
3672 gen_op_load_fpr_FT0(rs1
);
3673 gen_op_load_fpr_FT1(rs2
);
3675 gen_op_store_FT0_fpr(rd
);
3677 case 0x054: /* VIS I fpsub16 */
3678 gen_op_load_fpr_DT0(DFPREG(rs1
));
3679 gen_op_load_fpr_DT1(DFPREG(rs2
));
3681 gen_op_store_DT0_fpr(DFPREG(rd
));
3683 case 0x055: /* VIS I fpsub16s */
3684 gen_op_load_fpr_FT0(rs1
);
3685 gen_op_load_fpr_FT1(rs2
);
3687 gen_op_store_FT0_fpr(rd
);
3689 case 0x056: /* VIS I fpsub32 */
3690 gen_op_load_fpr_DT0(DFPREG(rs1
));
3691 gen_op_load_fpr_DT1(DFPREG(rs2
));
3693 gen_op_store_DT0_fpr(DFPREG(rd
));
3695 case 0x057: /* VIS I fpsub32s */
3696 gen_op_load_fpr_FT0(rs1
);
3697 gen_op_load_fpr_FT1(rs2
);
3699 gen_op_store_FT0_fpr(rd
);
3701 case 0x060: /* VIS I fzero */
3702 gen_op_movl_DT0_0();
3703 gen_op_store_DT0_fpr(DFPREG(rd
));
3705 case 0x061: /* VIS I fzeros */
3706 gen_op_movl_FT0_0();
3707 gen_op_store_FT0_fpr(rd
);
3709 case 0x062: /* VIS I fnor */
3710 gen_op_load_fpr_DT0(DFPREG(rs1
));
3711 gen_op_load_fpr_DT1(DFPREG(rs2
));
3713 gen_op_store_DT0_fpr(DFPREG(rd
));
3715 case 0x063: /* VIS I fnors */
3716 gen_op_load_fpr_FT0(rs1
);
3717 gen_op_load_fpr_FT1(rs2
);
3719 gen_op_store_FT0_fpr(rd
);
3721 case 0x064: /* VIS I fandnot2 */
3722 gen_op_load_fpr_DT1(DFPREG(rs1
));
3723 gen_op_load_fpr_DT0(DFPREG(rs2
));
3725 gen_op_store_DT0_fpr(DFPREG(rd
));
3727 case 0x065: /* VIS I fandnot2s */
3728 gen_op_load_fpr_FT1(rs1
);
3729 gen_op_load_fpr_FT0(rs2
);
3731 gen_op_store_FT0_fpr(rd
);
3733 case 0x066: /* VIS I fnot2 */
3734 gen_op_load_fpr_DT1(DFPREG(rs2
));
3736 gen_op_store_DT0_fpr(DFPREG(rd
));
3738 case 0x067: /* VIS I fnot2s */
3739 gen_op_load_fpr_FT1(rs2
);
3741 gen_op_store_FT0_fpr(rd
);
3743 case 0x068: /* VIS I fandnot1 */
3744 gen_op_load_fpr_DT0(DFPREG(rs1
));
3745 gen_op_load_fpr_DT1(DFPREG(rs2
));
3747 gen_op_store_DT0_fpr(DFPREG(rd
));
3749 case 0x069: /* VIS I fandnot1s */
3750 gen_op_load_fpr_FT0(rs1
);
3751 gen_op_load_fpr_FT1(rs2
);
3753 gen_op_store_FT0_fpr(rd
);
3755 case 0x06a: /* VIS I fnot1 */
3756 gen_op_load_fpr_DT1(DFPREG(rs1
));
3758 gen_op_store_DT0_fpr(DFPREG(rd
));
3760 case 0x06b: /* VIS I fnot1s */
3761 gen_op_load_fpr_FT1(rs1
);
3763 gen_op_store_FT0_fpr(rd
);
3765 case 0x06c: /* VIS I fxor */
3766 gen_op_load_fpr_DT0(DFPREG(rs1
));
3767 gen_op_load_fpr_DT1(DFPREG(rs2
));
3769 gen_op_store_DT0_fpr(DFPREG(rd
));
3771 case 0x06d: /* VIS I fxors */
3772 gen_op_load_fpr_FT0(rs1
);
3773 gen_op_load_fpr_FT1(rs2
);
3775 gen_op_store_FT0_fpr(rd
);
3777 case 0x06e: /* VIS I fnand */
3778 gen_op_load_fpr_DT0(DFPREG(rs1
));
3779 gen_op_load_fpr_DT1(DFPREG(rs2
));
3781 gen_op_store_DT0_fpr(DFPREG(rd
));
3783 case 0x06f: /* VIS I fnands */
3784 gen_op_load_fpr_FT0(rs1
);
3785 gen_op_load_fpr_FT1(rs2
);
3787 gen_op_store_FT0_fpr(rd
);
3789 case 0x070: /* VIS I fand */
3790 gen_op_load_fpr_DT0(DFPREG(rs1
));
3791 gen_op_load_fpr_DT1(DFPREG(rs2
));
3793 gen_op_store_DT0_fpr(DFPREG(rd
));
3795 case 0x071: /* VIS I fands */
3796 gen_op_load_fpr_FT0(rs1
);
3797 gen_op_load_fpr_FT1(rs2
);
3799 gen_op_store_FT0_fpr(rd
);
3801 case 0x072: /* VIS I fxnor */
3802 gen_op_load_fpr_DT0(DFPREG(rs1
));
3803 gen_op_load_fpr_DT1(DFPREG(rs2
));
3805 gen_op_store_DT0_fpr(DFPREG(rd
));
3807 case 0x073: /* VIS I fxnors */
3808 gen_op_load_fpr_FT0(rs1
);
3809 gen_op_load_fpr_FT1(rs2
);
3811 gen_op_store_FT0_fpr(rd
);
3813 case 0x074: /* VIS I fsrc1 */
3814 gen_op_load_fpr_DT0(DFPREG(rs1
));
3815 gen_op_store_DT0_fpr(DFPREG(rd
));
3817 case 0x075: /* VIS I fsrc1s */
3818 gen_op_load_fpr_FT0(rs1
);
3819 gen_op_store_FT0_fpr(rd
);
3821 case 0x076: /* VIS I fornot2 */
3822 gen_op_load_fpr_DT1(DFPREG(rs1
));
3823 gen_op_load_fpr_DT0(DFPREG(rs2
));
3825 gen_op_store_DT0_fpr(DFPREG(rd
));
3827 case 0x077: /* VIS I fornot2s */
3828 gen_op_load_fpr_FT1(rs1
);
3829 gen_op_load_fpr_FT0(rs2
);
3831 gen_op_store_FT0_fpr(rd
);
3833 case 0x078: /* VIS I fsrc2 */
3834 gen_op_load_fpr_DT0(DFPREG(rs2
));
3835 gen_op_store_DT0_fpr(DFPREG(rd
));
3837 case 0x079: /* VIS I fsrc2s */
3838 gen_op_load_fpr_FT0(rs2
);
3839 gen_op_store_FT0_fpr(rd
);
3841 case 0x07a: /* VIS I fornot1 */
3842 gen_op_load_fpr_DT0(DFPREG(rs1
));
3843 gen_op_load_fpr_DT1(DFPREG(rs2
));
3845 gen_op_store_DT0_fpr(DFPREG(rd
));
3847 case 0x07b: /* VIS I fornot1s */
3848 gen_op_load_fpr_FT0(rs1
);
3849 gen_op_load_fpr_FT1(rs2
);
3851 gen_op_store_FT0_fpr(rd
);
3853 case 0x07c: /* VIS I for */
3854 gen_op_load_fpr_DT0(DFPREG(rs1
));
3855 gen_op_load_fpr_DT1(DFPREG(rs2
));
3857 gen_op_store_DT0_fpr(DFPREG(rd
));
3859 case 0x07d: /* VIS I fors */
3860 gen_op_load_fpr_FT0(rs1
);
3861 gen_op_load_fpr_FT1(rs2
);
3863 gen_op_store_FT0_fpr(rd
);
3865 case 0x07e: /* VIS I fone */
3866 gen_op_movl_DT0_1();
3867 gen_op_store_DT0_fpr(DFPREG(rd
));
3869 case 0x07f: /* VIS I fones */
3870 gen_op_movl_FT0_1();
3871 gen_op_store_FT0_fpr(rd
);
3873 case 0x080: /* VIS I shutdown */
3874 case 0x081: /* VIS II siam */
3883 } else if (xop
== 0x37) { /* V8 CPop2, V9 impdep2 */
3884 #ifdef TARGET_SPARC64
3889 #ifdef TARGET_SPARC64
3890 } else if (xop
== 0x39) { /* V9 return */
3891 rs1
= GET_FIELD(insn
, 13, 17);
3893 gen_movl_reg_T0(rs1
);
3894 if (IS_IMM
) { /* immediate */
3895 rs2
= GET_FIELDs(insn
, 19, 31);
3896 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], (int)rs2
);
3897 } else { /* register */
3898 rs2
= GET_FIELD(insn
, 27, 31);
3902 gen_movl_reg_T1(rs2
);
3910 gen_op_check_align_T0_3();
3911 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUSPARCState
, npc
));
3912 dc
->npc
= DYNAMIC_PC
;
3916 rs1
= GET_FIELD(insn
, 13, 17);
3917 gen_movl_reg_T0(rs1
);
3918 if (IS_IMM
) { /* immediate */
3919 rs2
= GET_FIELDs(insn
, 19, 31);
3920 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], (int)rs2
);
3921 } else { /* register */
3922 rs2
= GET_FIELD(insn
, 27, 31);
3926 gen_movl_reg_T1(rs2
);
3933 case 0x38: /* jmpl */
3936 tcg_gen_movi_tl(cpu_T
[1], dc
->pc
);
3937 gen_movl_T1_reg(rd
);
3940 gen_op_check_align_T0_3();
3941 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUSPARCState
, npc
));
3942 dc
->npc
= DYNAMIC_PC
;
3945 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3946 case 0x39: /* rett, V9 return */
3948 if (!supervisor(dc
))
3951 gen_op_check_align_T0_3();
3952 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUSPARCState
, npc
));
3953 dc
->npc
= DYNAMIC_PC
;
3954 tcg_gen_helper_0_0(helper_rett
);
3958 case 0x3b: /* flush */
3959 tcg_gen_helper_0_1(helper_flush
, cpu_T
[0]);
3961 case 0x3c: /* save */
3964 gen_movl_T0_reg(rd
);
3966 case 0x3d: /* restore */
3969 gen_movl_T0_reg(rd
);
3971 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3972 case 0x3e: /* V9 done/retry */
3976 if (!supervisor(dc
))
3978 dc
->npc
= DYNAMIC_PC
;
3979 dc
->pc
= DYNAMIC_PC
;
3980 tcg_gen_helper_0_0(helper_done
);
3983 if (!supervisor(dc
))
3985 dc
->npc
= DYNAMIC_PC
;
3986 dc
->pc
= DYNAMIC_PC
;
3987 tcg_gen_helper_0_0(helper_retry
);
4002 case 3: /* load/store instructions */
4004 unsigned int xop
= GET_FIELD(insn
, 7, 12);
4005 rs1
= GET_FIELD(insn
, 13, 17);
4007 gen_movl_reg_T0(rs1
);
4008 if (xop
== 0x3c || xop
== 0x3e)
4010 rs2
= GET_FIELD(insn
, 27, 31);
4011 gen_movl_reg_T1(rs2
);
4013 else if (IS_IMM
) { /* immediate */
4014 rs2
= GET_FIELDs(insn
, 19, 31);
4015 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], (int)rs2
);
4016 } else { /* register */
4017 rs2
= GET_FIELD(insn
, 27, 31);
4021 gen_movl_reg_T1(rs2
);
4027 if (xop
< 4 || (xop
> 7 && xop
< 0x14 && xop
!= 0x0e) ||
4028 (xop
> 0x17 && xop
<= 0x1d ) ||
4029 (xop
> 0x2c && xop
<= 0x33) || xop
== 0x1f || xop
== 0x3d) {
4031 case 0x0: /* load unsigned word */
4032 gen_op_check_align_T0_3();
4033 ABI32_MASK(cpu_T
[0]);
4034 tcg_gen_qemu_ld32u(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4036 case 0x1: /* load unsigned byte */
4037 ABI32_MASK(cpu_T
[0]);
4038 tcg_gen_qemu_ld8u(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4040 case 0x2: /* load unsigned halfword */
4041 gen_op_check_align_T0_1();
4042 ABI32_MASK(cpu_T
[0]);
4043 tcg_gen_qemu_ld16u(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4045 case 0x3: /* load double word */
4051 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
4052 gen_op_check_align_T0_7();
4053 ABI32_MASK(cpu_T
[0]);
4054 tcg_gen_qemu_ld64(r_dword
, cpu_T
[0], dc
->mem_idx
);
4055 tcg_gen_trunc_i64_i32(cpu_T
[0], r_dword
);
4056 gen_movl_T0_reg(rd
+ 1);
4057 tcg_gen_shri_i64(r_dword
, r_dword
, 32);
4058 tcg_gen_trunc_i64_i32(cpu_T
[1], r_dword
);
4061 case 0x9: /* load signed byte */
4062 ABI32_MASK(cpu_T
[0]);
4063 tcg_gen_qemu_ld8s(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4065 case 0xa: /* load signed halfword */
4066 gen_op_check_align_T0_1();
4067 ABI32_MASK(cpu_T
[0]);
4068 tcg_gen_qemu_ld16s(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4070 case 0xd: /* ldstub -- XXX: should be atomically */
4071 tcg_gen_movi_i32(cpu_tmp0
, 0xff);
4072 ABI32_MASK(cpu_T
[0]);
4073 tcg_gen_qemu_ld8s(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4074 tcg_gen_qemu_st8(cpu_tmp0
, cpu_T
[0], dc
->mem_idx
);
4076 case 0x0f: /* swap register with memory. Also atomically */
4077 gen_op_check_align_T0_3();
4078 gen_movl_reg_T1(rd
);
4079 ABI32_MASK(cpu_T
[0]);
4080 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_T
[0], dc
->mem_idx
);
4081 tcg_gen_qemu_st32(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4082 tcg_gen_mov_i32(cpu_T
[1], cpu_tmp0
);
4084 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4085 case 0x10: /* load word alternate */
4086 #ifndef TARGET_SPARC64
4089 if (!supervisor(dc
))
4092 gen_op_check_align_T0_3();
4093 gen_ld_asi(insn
, 4, 0);
4095 case 0x11: /* load unsigned byte alternate */
4096 #ifndef TARGET_SPARC64
4099 if (!supervisor(dc
))
4102 gen_ld_asi(insn
, 1, 0);
4104 case 0x12: /* load unsigned halfword alternate */
4105 #ifndef TARGET_SPARC64
4108 if (!supervisor(dc
))
4111 gen_op_check_align_T0_1();
4112 gen_ld_asi(insn
, 2, 0);
4114 case 0x13: /* load double word alternate */
4115 #ifndef TARGET_SPARC64
4118 if (!supervisor(dc
))
4123 gen_op_check_align_T0_7();
4125 gen_movl_T0_reg(rd
+ 1);
4127 case 0x19: /* load signed byte alternate */
4128 #ifndef TARGET_SPARC64
4131 if (!supervisor(dc
))
4134 gen_ld_asi(insn
, 1, 1);
4136 case 0x1a: /* load signed halfword alternate */
4137 #ifndef TARGET_SPARC64
4140 if (!supervisor(dc
))
4143 gen_op_check_align_T0_1();
4144 gen_ld_asi(insn
, 2, 1);
4146 case 0x1d: /* ldstuba -- XXX: should be atomically */
4147 #ifndef TARGET_SPARC64
4150 if (!supervisor(dc
))
4153 gen_ldstub_asi(insn
);
4155 case 0x1f: /* swap reg with alt. memory. Also atomically */
4156 #ifndef TARGET_SPARC64
4159 if (!supervisor(dc
))
4162 gen_op_check_align_T0_3();
4163 gen_movl_reg_T1(rd
);
4167 #ifndef TARGET_SPARC64
4168 case 0x30: /* ldc */
4169 case 0x31: /* ldcsr */
4170 case 0x33: /* lddc */
4174 #ifdef TARGET_SPARC64
4175 case 0x08: /* V9 ldsw */
4176 gen_op_check_align_T0_3();
4177 ABI32_MASK(cpu_T
[0]);
4178 tcg_gen_qemu_ld32s(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4180 case 0x0b: /* V9 ldx */
4181 gen_op_check_align_T0_7();
4182 ABI32_MASK(cpu_T
[0]);
4183 tcg_gen_qemu_ld64(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4185 case 0x18: /* V9 ldswa */
4186 gen_op_check_align_T0_3();
4187 gen_ld_asi(insn
, 4, 1);
4189 case 0x1b: /* V9 ldxa */
4190 gen_op_check_align_T0_7();
4191 gen_ld_asi(insn
, 8, 0);
4193 case 0x2d: /* V9 prefetch, no effect */
4195 case 0x30: /* V9 ldfa */
4196 gen_op_check_align_T0_3();
4197 gen_ldf_asi(insn
, 4, rd
);
4199 case 0x33: /* V9 lddfa */
4200 gen_op_check_align_T0_3();
4201 gen_ldf_asi(insn
, 8, DFPREG(rd
));
4203 case 0x3d: /* V9 prefetcha, no effect */
4205 case 0x32: /* V9 ldqfa */
4206 #if defined(CONFIG_USER_ONLY)
4207 gen_op_check_align_T0_3();
4208 gen_ldf_asi(insn
, 16, QFPREG(rd
));
4217 gen_movl_T1_reg(rd
);
4218 #ifdef TARGET_SPARC64
4221 } else if (xop
>= 0x20 && xop
< 0x24) {
4222 if (gen_trap_ifnofpu(dc
))
4225 case 0x20: /* load fpreg */
4226 gen_op_check_align_T0_3();
4228 gen_op_store_FT0_fpr(rd
);
4230 case 0x21: /* load fsr */
4231 gen_op_check_align_T0_3();
4234 tcg_gen_helper_0_0(helper_ldfsr
);
4236 case 0x22: /* load quad fpreg */
4237 #if defined(CONFIG_USER_ONLY)
4238 gen_op_check_align_T0_7();
4240 gen_op_store_QT0_fpr(QFPREG(rd
));
4245 case 0x23: /* load double fpreg */
4246 gen_op_check_align_T0_7();
4248 gen_op_store_DT0_fpr(DFPREG(rd
));
4253 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18) || \
4254 xop
== 0xe || xop
== 0x1e) {
4255 gen_movl_reg_T1(rd
);
4257 case 0x4: /* store word */
4258 gen_op_check_align_T0_3();
4259 ABI32_MASK(cpu_T
[0]);
4260 tcg_gen_qemu_st32(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4262 case 0x5: /* store byte */
4263 ABI32_MASK(cpu_T
[0]);
4264 tcg_gen_qemu_st8(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4266 case 0x6: /* store halfword */
4267 gen_op_check_align_T0_1();
4268 ABI32_MASK(cpu_T
[0]);
4269 tcg_gen_qemu_st16(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4271 case 0x7: /* store double word */
4276 TCGv r_dword
, r_low
;
4278 gen_op_check_align_T0_7();
4279 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
4280 r_low
= tcg_temp_new(TCG_TYPE_I32
);
4281 gen_movl_reg_TN(rd
+ 1, r_low
);
4282 tcg_gen_helper_1_2(helper_pack64
, r_dword
, cpu_T
[1],
4284 tcg_gen_qemu_st64(r_dword
, cpu_T
[0], dc
->mem_idx
);
4286 #else /* __i386__ */
4287 gen_op_check_align_T0_7();
4289 gen_movl_reg_T2(rd
+ 1);
4291 #endif /* __i386__ */
4293 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4294 case 0x14: /* store word alternate */
4295 #ifndef TARGET_SPARC64
4298 if (!supervisor(dc
))
4301 gen_op_check_align_T0_3();
4302 gen_st_asi(insn
, 4);
4304 case 0x15: /* store byte alternate */
4305 #ifndef TARGET_SPARC64
4308 if (!supervisor(dc
))
4311 gen_st_asi(insn
, 1);
4313 case 0x16: /* store halfword alternate */
4314 #ifndef TARGET_SPARC64
4317 if (!supervisor(dc
))
4320 gen_op_check_align_T0_1();
4321 gen_st_asi(insn
, 2);
4323 case 0x17: /* store double word alternate */
4324 #ifndef TARGET_SPARC64
4327 if (!supervisor(dc
))
4334 TCGv r_dword
, r_temp
, r_size
;
4336 gen_op_check_align_T0_7();
4337 r_dword
= tcg_temp_new(TCG_TYPE_I64
);
4338 r_temp
= tcg_temp_new(TCG_TYPE_I32
);
4339 r_size
= tcg_temp_new(TCG_TYPE_I32
);
4340 gen_movl_reg_TN(rd
+ 1, r_temp
);
4341 tcg_gen_helper_1_2(helper_pack64
, r_dword
, cpu_T
[1],
4343 #ifdef TARGET_SPARC64
4347 offset
= GET_FIELD(insn
, 25, 31);
4348 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], offset
);
4349 tcg_gen_ld_i32(r_dword
, cpu_env
, offsetof(CPUSPARCState
, asi
));
4352 asi
= GET_FIELD(insn
, 19, 26);
4353 tcg_gen_movi_i32(r_temp
, asi
);
4354 #ifdef TARGET_SPARC64
4357 tcg_gen_movi_i32(r_size
, 8);
4358 tcg_gen_helper_0_4(helper_st_asi
, cpu_T
[0], r_dword
, r_temp
, r_size
);
4362 #ifdef TARGET_SPARC64
4363 case 0x0e: /* V9 stx */
4364 gen_op_check_align_T0_7();
4365 ABI32_MASK(cpu_T
[0]);
4366 tcg_gen_qemu_st64(cpu_T
[1], cpu_T
[0], dc
->mem_idx
);
4368 case 0x1e: /* V9 stxa */
4369 gen_op_check_align_T0_7();
4370 gen_st_asi(insn
, 8);
4376 } else if (xop
> 0x23 && xop
< 0x28) {
4377 if (gen_trap_ifnofpu(dc
))
4381 gen_op_check_align_T0_3();
4382 gen_op_load_fpr_FT0(rd
);
4385 case 0x25: /* stfsr, V9 stxfsr */
4386 #ifdef CONFIG_USER_ONLY
4387 gen_op_check_align_T0_3();
4393 #ifdef TARGET_SPARC64
4394 #if defined(CONFIG_USER_ONLY)
4395 /* V9 stqf, store quad fpreg */
4396 gen_op_check_align_T0_7();
4397 gen_op_load_fpr_QT0(QFPREG(rd
));
4403 #else /* !TARGET_SPARC64 */
4404 /* stdfq, store floating point queue */
4405 #if defined(CONFIG_USER_ONLY)
4408 if (!supervisor(dc
))
4410 if (gen_trap_ifnofpu(dc
))
4416 gen_op_check_align_T0_7();
4417 gen_op_load_fpr_DT0(DFPREG(rd
));
4423 } else if (xop
> 0x33 && xop
< 0x3f) {
4425 #ifdef TARGET_SPARC64
4426 case 0x34: /* V9 stfa */
4427 gen_op_check_align_T0_3();
4428 gen_op_load_fpr_FT0(rd
);
4429 gen_stf_asi(insn
, 4, rd
);
4431 case 0x36: /* V9 stqfa */
4432 #if defined(CONFIG_USER_ONLY)
4433 gen_op_check_align_T0_7();
4434 gen_op_load_fpr_QT0(QFPREG(rd
));
4435 gen_stf_asi(insn
, 16, QFPREG(rd
));
4440 case 0x37: /* V9 stdfa */
4441 gen_op_check_align_T0_3();
4442 gen_op_load_fpr_DT0(DFPREG(rd
));
4443 gen_stf_asi(insn
, 8, DFPREG(rd
));
4445 case 0x3c: /* V9 casa */
4446 gen_op_check_align_T0_3();
4447 gen_cas_asi(insn
, rd
);
4448 gen_movl_T1_reg(rd
);
4450 case 0x3e: /* V9 casxa */
4451 gen_op_check_align_T0_7();
4452 gen_casx_asi(insn
, rd
);
4453 gen_movl_T1_reg(rd
);
4456 case 0x34: /* stc */
4457 case 0x35: /* stcsr */
4458 case 0x36: /* stdcq */
4459 case 0x37: /* stdc */
4471 /* default case for non jump instructions */
4472 if (dc
->npc
== DYNAMIC_PC
) {
4473 dc
->pc
= DYNAMIC_PC
;
4475 } else if (dc
->npc
== JUMP_PC
) {
4476 /* we can do a static jump */
4477 gen_branch2(dc
, dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_T
[2]);
4481 dc
->npc
= dc
->npc
+ 4;
4487 gen_op_exception(TT_ILL_INSN
);
4490 #if !defined(CONFIG_USER_ONLY)
4493 gen_op_exception(TT_PRIV_INSN
);
4498 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP
);
4501 #ifndef TARGET_SPARC64
4504 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR
);
4509 #ifndef TARGET_SPARC64
4512 gen_op_exception(TT_NCP_INSN
);
4518 static void tcg_macro_func(TCGContext
*s
, int macro_id
, const int *dead_args
)
4522 static inline int gen_intermediate_code_internal(TranslationBlock
* tb
,
4523 int spc
, CPUSPARCState
*env
)
4525 target_ulong pc_start
, last_pc
;
4526 uint16_t *gen_opc_end
;
4527 DisasContext dc1
, *dc
= &dc1
;
4530 memset(dc
, 0, sizeof(DisasContext
));
4535 dc
->npc
= (target_ulong
) tb
->cs_base
;
4536 dc
->mem_idx
= cpu_mmu_index(env
);
4537 dc
->fpu_enabled
= cpu_fpu_enabled(env
);
4538 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
4540 cpu_tmp0
= tcg_temp_new(TCG_TYPE_TL
);
4543 if (env
->nb_breakpoints
> 0) {
4544 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
4545 if (env
->breakpoints
[j
] == dc
->pc
) {
4546 if (dc
->pc
!= pc_start
)
4548 tcg_gen_helper_0_0(helper_debug
);
4557 fprintf(logfile
, "Search PC...\n");
4558 j
= gen_opc_ptr
- gen_opc_buf
;
4562 gen_opc_instr_start
[lj
++] = 0;
4563 gen_opc_pc
[lj
] = dc
->pc
;
4564 gen_opc_npc
[lj
] = dc
->npc
;
4565 gen_opc_instr_start
[lj
] = 1;
4569 disas_sparc_insn(dc
);
4573 /* if the next PC is different, we abort now */
4574 if (dc
->pc
!= (last_pc
+ 4))
4576 /* if we reach a page boundary, we stop generation so that the
4577 PC of a TT_TFAULT exception is always in the right page */
4578 if ((dc
->pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
4580 /* if single step mode, we generate only one instruction and
4581 generate an exception */
4582 if (env
->singlestep_enabled
) {
4587 } while ((gen_opc_ptr
< gen_opc_end
) &&
4588 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32));
4592 if (dc
->pc
!= DYNAMIC_PC
&&
4593 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
4594 /* static PC and NPC: we can use direct chaining */
4595 gen_branch(dc
, dc
->pc
, dc
->npc
);
4597 if (dc
->pc
!= DYNAMIC_PC
)
4603 *gen_opc_ptr
= INDEX_op_end
;
4605 j
= gen_opc_ptr
- gen_opc_buf
;
4608 gen_opc_instr_start
[lj
++] = 0;
4614 gen_opc_jump_pc
[0] = dc
->jump_pc
[0];
4615 gen_opc_jump_pc
[1] = dc
->jump_pc
[1];
4617 tb
->size
= last_pc
+ 4 - pc_start
;
4620 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4621 fprintf(logfile
, "--------------\n");
4622 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
4623 target_disas(logfile
, pc_start
, last_pc
+ 4 - pc_start
, 0);
4624 fprintf(logfile
, "\n");
4630 int gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
4632 return gen_intermediate_code_internal(tb
, 0, env
);
4635 int gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
4637 return gen_intermediate_code_internal(tb
, 1, env
);
4640 void cpu_reset(CPUSPARCState
*env
)
4645 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
4646 #if defined(CONFIG_USER_ONLY)
4647 env
->user_mode_only
= 1;
4648 #ifdef TARGET_SPARC64
4649 env
->cleanwin
= NWINDOWS
- 2;
4650 env
->cansave
= NWINDOWS
- 2;
4651 env
->pstate
= PS_RMO
| PS_PEF
| PS_IE
;
4652 env
->asi
= 0x82; // Primary no-fault
4658 #ifdef TARGET_SPARC64
4659 env
->pstate
= PS_PRIV
;
4660 env
->hpstate
= HS_PRIV
;
4661 env
->pc
= 0x1fff0000000ULL
;
4662 env
->tsptr
= &env
->ts
[env
->tl
];
4665 env
->mmuregs
[0] &= ~(MMU_E
| MMU_NF
);
4666 env
->mmuregs
[0] |= env
->mmu_bm
;
4668 env
->npc
= env
->pc
+ 4;
4672 CPUSPARCState
*cpu_sparc_init(const char *cpu_model
)
4675 const sparc_def_t
*def
;
4678 static const char * const gregnames
[8] = {
4679 NULL
, // g0 not used
4689 def
= cpu_sparc_find_by_name(cpu_model
);
4693 env
= qemu_mallocz(sizeof(CPUSPARCState
));
4697 env
->cpu_model_str
= cpu_model
;
4698 env
->version
= def
->iu_version
;
4699 env
->fsr
= def
->fpu_version
;
4700 #if !defined(TARGET_SPARC64)
4701 env
->mmu_bm
= def
->mmu_bm
;
4702 env
->mmu_ctpr_mask
= def
->mmu_ctpr_mask
;
4703 env
->mmu_cxr_mask
= def
->mmu_cxr_mask
;
4704 env
->mmu_sfsr_mask
= def
->mmu_sfsr_mask
;
4705 env
->mmu_trcr_mask
= def
->mmu_trcr_mask
;
4706 env
->mmuregs
[0] |= def
->mmu_version
;
4707 cpu_sparc_set_id(env
, 0);
4710 /* init various static tables */
4714 tcg_set_macro_func(&tcg_ctx
, tcg_macro_func
);
4715 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
4716 cpu_regwptr
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
4717 offsetof(CPUState
, regwptr
),
4719 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4720 #ifdef TARGET_SPARC64
4721 cpu_T
[0] = tcg_global_mem_new(TCG_TYPE_TL
,
4722 TCG_AREG0
, offsetof(CPUState
, t0
), "T0");
4723 cpu_T
[1] = tcg_global_mem_new(TCG_TYPE_TL
,
4724 TCG_AREG0
, offsetof(CPUState
, t1
), "T1");
4725 cpu_T
[2] = tcg_global_mem_new(TCG_TYPE_TL
,
4726 TCG_AREG0
, offsetof(CPUState
, t2
), "T2");
4727 cpu_xcc
= tcg_global_mem_new(TCG_TYPE_I32
,
4728 TCG_AREG0
, offsetof(CPUState
, xcc
),
4731 cpu_T
[0] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG1
, "T0");
4732 cpu_T
[1] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG2
, "T1");
4733 cpu_T
[2] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG3
, "T2");
4735 cpu_cc_src
= tcg_global_mem_new(TCG_TYPE_TL
,
4736 TCG_AREG0
, offsetof(CPUState
, cc_src
),
4738 cpu_cc_dst
= tcg_global_mem_new(TCG_TYPE_TL
,
4739 TCG_AREG0
, offsetof(CPUState
, cc_dst
),
4741 cpu_psr
= tcg_global_mem_new(TCG_TYPE_I32
,
4742 TCG_AREG0
, offsetof(CPUState
, psr
),
4744 for (i
= 1; i
< 8; i
++)
4745 cpu_gregs
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
4746 offsetof(CPUState
, gregs
[i
]),
4755 void cpu_sparc_set_id(CPUSPARCState
*env
, unsigned int cpu
)
4757 #if !defined(TARGET_SPARC64)
4758 env
->mxccregs
[7] = ((cpu
+ 8) & 0xf) << 24;
4762 static const sparc_def_t sparc_defs
[] = {
4763 #ifdef TARGET_SPARC64
4765 .name
= "Fujitsu Sparc64",
4766 .iu_version
= ((0x04ULL
<< 48) | (0x02ULL
<< 32) | (0ULL << 24)
4767 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4768 .fpu_version
= 0x00000000,
4772 .name
= "Fujitsu Sparc64 III",
4773 .iu_version
= ((0x04ULL
<< 48) | (0x03ULL
<< 32) | (0ULL << 24)
4774 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4775 .fpu_version
= 0x00000000,
4779 .name
= "Fujitsu Sparc64 IV",
4780 .iu_version
= ((0x04ULL
<< 48) | (0x04ULL
<< 32) | (0ULL << 24)
4781 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4782 .fpu_version
= 0x00000000,
4786 .name
= "Fujitsu Sparc64 V",
4787 .iu_version
= ((0x04ULL
<< 48) | (0x05ULL
<< 32) | (0x51ULL
<< 24)
4788 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4789 .fpu_version
= 0x00000000,
4793 .name
= "TI UltraSparc I",
4794 .iu_version
= ((0x17ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)
4795 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4796 .fpu_version
= 0x00000000,
4800 .name
= "TI UltraSparc II",
4801 .iu_version
= ((0x17ULL
<< 48) | (0x11ULL
<< 32) | (0x20ULL
<< 24)
4802 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4803 .fpu_version
= 0x00000000,
4807 .name
= "TI UltraSparc IIi",
4808 .iu_version
= ((0x17ULL
<< 48) | (0x12ULL
<< 32) | (0x91ULL
<< 24)
4809 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4810 .fpu_version
= 0x00000000,
4814 .name
= "TI UltraSparc IIe",
4815 .iu_version
= ((0x17ULL
<< 48) | (0x13ULL
<< 32) | (0x14ULL
<< 24)
4816 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4817 .fpu_version
= 0x00000000,
4821 .name
= "Sun UltraSparc III",
4822 .iu_version
= ((0x3eULL
<< 48) | (0x14ULL
<< 32) | (0x34ULL
<< 24)
4823 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4824 .fpu_version
= 0x00000000,
4828 .name
= "Sun UltraSparc III Cu",
4829 .iu_version
= ((0x3eULL
<< 48) | (0x15ULL
<< 32) | (0x41ULL
<< 24)
4830 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4831 .fpu_version
= 0x00000000,
4835 .name
= "Sun UltraSparc IIIi",
4836 .iu_version
= ((0x3eULL
<< 48) | (0x16ULL
<< 32) | (0x34ULL
<< 24)
4837 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4838 .fpu_version
= 0x00000000,
4842 .name
= "Sun UltraSparc IV",
4843 .iu_version
= ((0x3eULL
<< 48) | (0x18ULL
<< 32) | (0x31ULL
<< 24)
4844 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4845 .fpu_version
= 0x00000000,
4849 .name
= "Sun UltraSparc IV+",
4850 .iu_version
= ((0x3eULL
<< 48) | (0x19ULL
<< 32) | (0x22ULL
<< 24)
4851 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4852 .fpu_version
= 0x00000000,
4856 .name
= "Sun UltraSparc IIIi+",
4857 .iu_version
= ((0x3eULL
<< 48) | (0x22ULL
<< 32) | (0ULL << 24)
4858 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4859 .fpu_version
= 0x00000000,
4863 .name
= "NEC UltraSparc I",
4864 .iu_version
= ((0x22ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)
4865 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
4866 .fpu_version
= 0x00000000,
4871 .name
= "Fujitsu MB86900",
4872 .iu_version
= 0x00 << 24, /* Impl 0, ver 0 */
4873 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
4874 .mmu_version
= 0x00 << 24, /* Impl 0, ver 0 */
4875 .mmu_bm
= 0x00004000,
4876 .mmu_ctpr_mask
= 0x007ffff0,
4877 .mmu_cxr_mask
= 0x0000003f,
4878 .mmu_sfsr_mask
= 0xffffffff,
4879 .mmu_trcr_mask
= 0xffffffff,
4882 .name
= "Fujitsu MB86904",
4883 .iu_version
= 0x04 << 24, /* Impl 0, ver 4 */
4884 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
4885 .mmu_version
= 0x04 << 24, /* Impl 0, ver 4 */
4886 .mmu_bm
= 0x00004000,
4887 .mmu_ctpr_mask
= 0x00ffffc0,
4888 .mmu_cxr_mask
= 0x000000ff,
4889 .mmu_sfsr_mask
= 0x00016fff,
4890 .mmu_trcr_mask
= 0x00ffffff,
4893 .name
= "Fujitsu MB86907",
4894 .iu_version
= 0x05 << 24, /* Impl 0, ver 5 */
4895 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
4896 .mmu_version
= 0x05 << 24, /* Impl 0, ver 5 */
4897 .mmu_bm
= 0x00004000,
4898 .mmu_ctpr_mask
= 0xffffffc0,
4899 .mmu_cxr_mask
= 0x000000ff,
4900 .mmu_sfsr_mask
= 0x00016fff,
4901 .mmu_trcr_mask
= 0xffffffff,
4904 .name
= "LSI L64811",
4905 .iu_version
= 0x10 << 24, /* Impl 1, ver 0 */
4906 .fpu_version
= 1 << 17, /* FPU version 1 (LSI L64814) */
4907 .mmu_version
= 0x10 << 24,
4908 .mmu_bm
= 0x00004000,
4909 .mmu_ctpr_mask
= 0x007ffff0,
4910 .mmu_cxr_mask
= 0x0000003f,
4911 .mmu_sfsr_mask
= 0xffffffff,
4912 .mmu_trcr_mask
= 0xffffffff,
4915 .name
= "Cypress CY7C601",
4916 .iu_version
= 0x11 << 24, /* Impl 1, ver 1 */
4917 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4918 .mmu_version
= 0x10 << 24,
4919 .mmu_bm
= 0x00004000,
4920 .mmu_ctpr_mask
= 0x007ffff0,
4921 .mmu_cxr_mask
= 0x0000003f,
4922 .mmu_sfsr_mask
= 0xffffffff,
4923 .mmu_trcr_mask
= 0xffffffff,
4926 .name
= "Cypress CY7C611",
4927 .iu_version
= 0x13 << 24, /* Impl 1, ver 3 */
4928 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4929 .mmu_version
= 0x10 << 24,
4930 .mmu_bm
= 0x00004000,
4931 .mmu_ctpr_mask
= 0x007ffff0,
4932 .mmu_cxr_mask
= 0x0000003f,
4933 .mmu_sfsr_mask
= 0xffffffff,
4934 .mmu_trcr_mask
= 0xffffffff,
4937 .name
= "TI SuperSparc II",
4938 .iu_version
= 0x40000000,
4939 .fpu_version
= 0 << 17,
4940 .mmu_version
= 0x04000000,
4941 .mmu_bm
= 0x00002000,
4942 .mmu_ctpr_mask
= 0xffffffc0,
4943 .mmu_cxr_mask
= 0x0000ffff,
4944 .mmu_sfsr_mask
= 0xffffffff,
4945 .mmu_trcr_mask
= 0xffffffff,
4948 .name
= "TI MicroSparc I",
4949 .iu_version
= 0x41000000,
4950 .fpu_version
= 4 << 17,
4951 .mmu_version
= 0x41000000,
4952 .mmu_bm
= 0x00004000,
4953 .mmu_ctpr_mask
= 0x007ffff0,
4954 .mmu_cxr_mask
= 0x0000003f,
4955 .mmu_sfsr_mask
= 0x00016fff,
4956 .mmu_trcr_mask
= 0x0000003f,
4959 .name
= "TI MicroSparc II",
4960 .iu_version
= 0x42000000,
4961 .fpu_version
= 4 << 17,
4962 .mmu_version
= 0x02000000,
4963 .mmu_bm
= 0x00004000,
4964 .mmu_ctpr_mask
= 0x00ffffc0,
4965 .mmu_cxr_mask
= 0x000000ff,
4966 .mmu_sfsr_mask
= 0x00016fff,
4967 .mmu_trcr_mask
= 0x00ffffff,
4970 .name
= "TI MicroSparc IIep",
4971 .iu_version
= 0x42000000,
4972 .fpu_version
= 4 << 17,
4973 .mmu_version
= 0x04000000,
4974 .mmu_bm
= 0x00004000,
4975 .mmu_ctpr_mask
= 0x00ffffc0,
4976 .mmu_cxr_mask
= 0x000000ff,
4977 .mmu_sfsr_mask
= 0x00016bff,
4978 .mmu_trcr_mask
= 0x00ffffff,
4981 .name
= "TI SuperSparc 51",
4982 .iu_version
= 0x43000000,
4983 .fpu_version
= 0 << 17,
4984 .mmu_version
= 0x04000000,
4985 .mmu_bm
= 0x00002000,
4986 .mmu_ctpr_mask
= 0xffffffc0,
4987 .mmu_cxr_mask
= 0x0000ffff,
4988 .mmu_sfsr_mask
= 0xffffffff,
4989 .mmu_trcr_mask
= 0xffffffff,
4992 .name
= "TI SuperSparc 61",
4993 .iu_version
= 0x44000000,
4994 .fpu_version
= 0 << 17,
4995 .mmu_version
= 0x04000000,
4996 .mmu_bm
= 0x00002000,
4997 .mmu_ctpr_mask
= 0xffffffc0,
4998 .mmu_cxr_mask
= 0x0000ffff,
4999 .mmu_sfsr_mask
= 0xffffffff,
5000 .mmu_trcr_mask
= 0xffffffff,
5003 .name
= "Ross RT625",
5004 .iu_version
= 0x1e000000,
5005 .fpu_version
= 1 << 17,
5006 .mmu_version
= 0x1e000000,
5007 .mmu_bm
= 0x00004000,
5008 .mmu_ctpr_mask
= 0x007ffff0,
5009 .mmu_cxr_mask
= 0x0000003f,
5010 .mmu_sfsr_mask
= 0xffffffff,
5011 .mmu_trcr_mask
= 0xffffffff,
5014 .name
= "Ross RT620",
5015 .iu_version
= 0x1f000000,
5016 .fpu_version
= 1 << 17,
5017 .mmu_version
= 0x1f000000,
5018 .mmu_bm
= 0x00004000,
5019 .mmu_ctpr_mask
= 0x007ffff0,
5020 .mmu_cxr_mask
= 0x0000003f,
5021 .mmu_sfsr_mask
= 0xffffffff,
5022 .mmu_trcr_mask
= 0xffffffff,
5025 .name
= "BIT B5010",
5026 .iu_version
= 0x20000000,
5027 .fpu_version
= 0 << 17, /* B5010/B5110/B5120/B5210 */
5028 .mmu_version
= 0x20000000,
5029 .mmu_bm
= 0x00004000,
5030 .mmu_ctpr_mask
= 0x007ffff0,
5031 .mmu_cxr_mask
= 0x0000003f,
5032 .mmu_sfsr_mask
= 0xffffffff,
5033 .mmu_trcr_mask
= 0xffffffff,
5036 .name
= "Matsushita MN10501",
5037 .iu_version
= 0x50000000,
5038 .fpu_version
= 0 << 17,
5039 .mmu_version
= 0x50000000,
5040 .mmu_bm
= 0x00004000,
5041 .mmu_ctpr_mask
= 0x007ffff0,
5042 .mmu_cxr_mask
= 0x0000003f,
5043 .mmu_sfsr_mask
= 0xffffffff,
5044 .mmu_trcr_mask
= 0xffffffff,
5047 .name
= "Weitek W8601",
5048 .iu_version
= 0x90 << 24, /* Impl 9, ver 0 */
5049 .fpu_version
= 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
5050 .mmu_version
= 0x10 << 24,
5051 .mmu_bm
= 0x00004000,
5052 .mmu_ctpr_mask
= 0x007ffff0,
5053 .mmu_cxr_mask
= 0x0000003f,
5054 .mmu_sfsr_mask
= 0xffffffff,
5055 .mmu_trcr_mask
= 0xffffffff,
5059 .iu_version
= 0xf2000000,
5060 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
5061 .mmu_version
= 0xf2000000,
5062 .mmu_bm
= 0x00004000,
5063 .mmu_ctpr_mask
= 0x007ffff0,
5064 .mmu_cxr_mask
= 0x0000003f,
5065 .mmu_sfsr_mask
= 0xffffffff,
5066 .mmu_trcr_mask
= 0xffffffff,
5070 .iu_version
= 0xf3000000,
5071 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
5072 .mmu_version
= 0xf3000000,
5073 .mmu_bm
= 0x00004000,
5074 .mmu_ctpr_mask
= 0x007ffff0,
5075 .mmu_cxr_mask
= 0x0000003f,
5076 .mmu_sfsr_mask
= 0xffffffff,
5077 .mmu_trcr_mask
= 0xffffffff,
5082 static const sparc_def_t
*cpu_sparc_find_by_name(const unsigned char *name
)
5086 for (i
= 0; i
< sizeof(sparc_defs
) / sizeof(sparc_def_t
); i
++) {
5087 if (strcasecmp(name
, sparc_defs
[i
].name
) == 0) {
5088 return &sparc_defs
[i
];
5094 void sparc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
5098 for (i
= 0; i
< sizeof(sparc_defs
) / sizeof(sparc_def_t
); i
++) {
5099 (*cpu_fprintf
)(f
, "Sparc %16s IU " TARGET_FMT_lx
" FPU %08x MMU %08x\n",
5101 sparc_defs
[i
].iu_version
,
5102 sparc_defs
[i
].fpu_version
,
5103 sparc_defs
[i
].mmu_version
);
5107 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
5109 void cpu_dump_state(CPUState
*env
, FILE *f
,
5110 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
5115 cpu_fprintf(f
, "pc: " TARGET_FMT_lx
" npc: " TARGET_FMT_lx
"\n", env
->pc
, env
->npc
);
5116 cpu_fprintf(f
, "General Registers:\n");
5117 for (i
= 0; i
< 4; i
++)
5118 cpu_fprintf(f
, "%%g%c: " TARGET_FMT_lx
"\t", i
+ '0', env
->gregs
[i
]);
5119 cpu_fprintf(f
, "\n");
5121 cpu_fprintf(f
, "%%g%c: " TARGET_FMT_lx
"\t", i
+ '0', env
->gregs
[i
]);
5122 cpu_fprintf(f
, "\nCurrent Register Window:\n");
5123 for (x
= 0; x
< 3; x
++) {
5124 for (i
= 0; i
< 4; i
++)
5125 cpu_fprintf(f
, "%%%c%d: " TARGET_FMT_lx
"\t",
5126 (x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i')), i
,
5127 env
->regwptr
[i
+ x
* 8]);
5128 cpu_fprintf(f
, "\n");
5130 cpu_fprintf(f
, "%%%c%d: " TARGET_FMT_lx
"\t",
5131 (x
== 0 ? 'o' : x
== 1 ? 'l' : 'i'), i
,
5132 env
->regwptr
[i
+ x
* 8]);
5133 cpu_fprintf(f
, "\n");
5135 cpu_fprintf(f
, "\nFloating Point Registers:\n");
5136 for (i
= 0; i
< 32; i
++) {
5138 cpu_fprintf(f
, "%%f%02d:", i
);
5139 cpu_fprintf(f
, " %016lf", env
->fpr
[i
]);
5141 cpu_fprintf(f
, "\n");
5143 #ifdef TARGET_SPARC64
5144 cpu_fprintf(f
, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
5145 env
->pstate
, GET_CCR(env
), env
->asi
, env
->tl
, env
->fprs
);
5146 cpu_fprintf(f
, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
5147 env
->cansave
, env
->canrestore
, env
->otherwin
, env
->wstate
,
5148 env
->cleanwin
, NWINDOWS
- 1 - env
->cwp
);
5150 cpu_fprintf(f
, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env
),
5151 GET_FLAG(PSR_ZERO
, 'Z'), GET_FLAG(PSR_OVF
, 'V'),
5152 GET_FLAG(PSR_NEG
, 'N'), GET_FLAG(PSR_CARRY
, 'C'),
5153 env
->psrs
?'S':'-', env
->psrps
?'P':'-',
5154 env
->psret
?'E':'-', env
->wim
);
5156 cpu_fprintf(f
, "fsr: 0x%08x\n", GET_FSR32(env
));
5159 #if defined(CONFIG_USER_ONLY)
5160 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
5166 extern int get_physical_address (CPUState
*env
, target_phys_addr_t
*physical
, int *prot
,
5167 int *access_index
, target_ulong address
, int rw
,
5170 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
5172 target_phys_addr_t phys_addr
;
5173 int prot
, access_index
;
5175 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
, 2,
5176 MMU_KERNEL_IDX
) != 0)
5177 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
,
5178 0, MMU_KERNEL_IDX
) != 0)
5180 if (cpu_get_physical_page_desc(phys_addr
) == IO_MEM_UNASSIGNED
)
5186 void helper_flush(target_ulong addr
)
5189 tb_invalidate_page_range(addr
, addr
+ 8);