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[mirror_qemu.git] / target-tilegx / translate.c
1 /*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "exec/cpu_ldst.h"
26 #include "opcode_tilegx.h"
27
28 #define FMT64X "%016" PRIx64
29
30 static TCGv_ptr cpu_env;
31 static TCGv cpu_pc;
32 static TCGv cpu_regs[TILEGX_R_COUNT];
33
34 static const char * const reg_names[64] = {
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
39 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
40 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
41 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
42 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
43 };
44
45 /* Modified registers are cached in temporaries until the end of the bundle. */
46 typedef struct {
47 unsigned reg;
48 TCGv val;
49 } DisasContextTemp;
50
51 #define MAX_WRITEBACK 4
52
53 /* This is the state at translation time. */
54 typedef struct {
55 uint64_t pc; /* Current pc */
56
57 TCGv zero; /* For zero register */
58
59 DisasContextTemp wb[MAX_WRITEBACK];
60 int num_wb;
61 int mmuidx;
62 bool exit_tb;
63
64 struct {
65 TCGCond cond; /* branch condition */
66 TCGv dest; /* branch destination */
67 TCGv val1; /* value to be compared against zero, for cond */
68 } jmp; /* Jump object, only once in each TB block */
69 } DisasContext;
70
71 #include "exec/gen-icount.h"
72
73 /* Differentiate the various pipe encodings. */
74 #define TY_X0 0
75 #define TY_X1 1
76 #define TY_Y0 2
77 #define TY_Y1 3
78
79 /* Remerge the base opcode and extension fields for switching.
80 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
81 Y2 opcode field is 2 bits. */
82 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
83
84 /* Similar, but for Y2 only. */
85 #define OEY2(OP, MODE) (OP + MODE * 4)
86
87 /* Similar, but make sure opcode names match up. */
88 #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
89 #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
90 #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
91 #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
92 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
93 #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
94 #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
95
96
97 static void gen_exception(DisasContext *dc, TileExcp num)
98 {
99 TCGv_i32 tmp;
100
101 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
102
103 tmp = tcg_const_i32(num);
104 gen_helper_exception(cpu_env, tmp);
105 tcg_temp_free_i32(tmp);
106 dc->exit_tb = true;
107 }
108
109 static bool check_gr(DisasContext *dc, uint8_t reg)
110 {
111 if (likely(reg < TILEGX_R_COUNT)) {
112 return true;
113 }
114
115 switch (reg) {
116 case TILEGX_R_SN:
117 case TILEGX_R_ZERO:
118 break;
119 case TILEGX_R_IDN0:
120 case TILEGX_R_IDN1:
121 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
122 break;
123 case TILEGX_R_UDN0:
124 case TILEGX_R_UDN1:
125 case TILEGX_R_UDN2:
126 case TILEGX_R_UDN3:
127 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
128 break;
129 default:
130 g_assert_not_reached();
131 }
132 return false;
133 }
134
135 static TCGv load_zero(DisasContext *dc)
136 {
137 if (TCGV_IS_UNUSED_I64(dc->zero)) {
138 dc->zero = tcg_const_i64(0);
139 }
140 return dc->zero;
141 }
142
143 static TCGv load_gr(DisasContext *dc, unsigned reg)
144 {
145 if (check_gr(dc, reg)) {
146 return cpu_regs[reg];
147 }
148 return load_zero(dc);
149 }
150
151 static TCGv dest_gr(DisasContext *dc, unsigned reg)
152 {
153 int n;
154
155 /* Skip the result, mark the exception if necessary, and continue */
156 check_gr(dc, reg);
157
158 n = dc->num_wb++;
159 dc->wb[n].reg = reg;
160 return dc->wb[n].val = tcg_temp_new_i64();
161 }
162
163 static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
164 void (*operate)(TCGv, TCGv, TCGv))
165 {
166 TCGv t0 = tcg_temp_new();
167
168 tcg_gen_ext32s_tl(tdest, tsrca);
169 tcg_gen_ext32s_tl(t0, tsrcb);
170 operate(tdest, tdest, t0);
171
172 tcg_gen_movi_tl(t0, 0x7fffffff);
173 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
174 tcg_gen_movi_tl(t0, -0x80000000LL);
175 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
176
177 tcg_temp_free(t0);
178 }
179
180 /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
181 specified by the bottom 3 bits of TSRCB, and set TDEST to the
182 low 64 bits of the resulting value. */
183 static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
184 {
185 TCGv t0 = tcg_temp_new();
186
187 tcg_gen_andi_tl(t0, tsrcb, 7);
188 tcg_gen_shli_tl(t0, t0, 3);
189 tcg_gen_shr_tl(tdest, tsrcd, t0);
190
191 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
192 arithmetic on a 6-bit field tells us that 64 - t0 is equal
193 to (t0 ^ 63) + 1. So we can do the shift in two parts,
194 neither of which will be an invalid shift by 64. */
195 tcg_gen_xori_tl(t0, t0, 63);
196 tcg_gen_shl_tl(t0, tsrca, t0);
197 tcg_gen_shli_tl(t0, t0, 1);
198 tcg_gen_or_tl(tdest, tdest, t0);
199
200 tcg_temp_free(t0);
201 }
202
203 /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
204 right shift is an immediate. */
205 static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
206 {
207 TCGv t0 = tcg_temp_new();
208
209 tcg_gen_shri_tl(t0, tsrcb, shr);
210 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
211 tcg_gen_or_tl(tdest, tdest, t0);
212
213 tcg_temp_free(t0);
214 }
215
216 static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
217 unsigned srcb, TCGMemOp memop, const char *name)
218 {
219 if (dest) {
220 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
221 }
222
223 tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
224 dc->mmuidx, memop);
225
226 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
227 reg_names[srca], reg_names[srcb]);
228 return TILEGX_EXCP_NONE;
229 }
230
231 static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
232 int imm, TCGMemOp memop, const char *name)
233 {
234 TCGv tsrca = load_gr(dc, srca);
235 TCGv tsrcb = load_gr(dc, srcb);
236
237 tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
238 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
239
240 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
241 reg_names[srca], reg_names[srcb], imm);
242 return TILEGX_EXCP_NONE;
243 }
244
245 static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
246 unsigned dest, unsigned srca)
247 {
248 TCGv tdest, tsrca;
249 const char *mnemonic;
250 TCGMemOp memop;
251 TileExcp ret = TILEGX_EXCP_NONE;
252
253 /* Eliminate instructions with no output before doing anything else. */
254 switch (opext) {
255 case OE_RR_Y0(NOP):
256 case OE_RR_Y1(NOP):
257 case OE_RR_X0(NOP):
258 case OE_RR_X1(NOP):
259 mnemonic = "nop";
260 goto done0;
261 case OE_RR_Y0(FNOP):
262 case OE_RR_Y1(FNOP):
263 case OE_RR_X0(FNOP):
264 case OE_RR_X1(FNOP):
265 mnemonic = "fnop";
266 goto done0;
267 case OE_RR_X1(DRAIN):
268 mnemonic = "drain";
269 goto done0;
270 case OE_RR_X1(FLUSHWB):
271 mnemonic = "flushwb";
272 goto done0;
273 case OE_RR_X1(ILL):
274 case OE_RR_Y1(ILL):
275 mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
276 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
277 return TILEGX_EXCP_OPCODE_UNKNOWN;
278 case OE_RR_X1(MF):
279 mnemonic = "mf";
280 goto done0;
281 case OE_RR_X1(NAP):
282 /* ??? This should yield, especially in system mode. */
283 mnemonic = "nap";
284 goto done0;
285 case OE_RR_X1(SWINT0):
286 case OE_RR_X1(SWINT2):
287 case OE_RR_X1(SWINT3):
288 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
289 case OE_RR_X1(SWINT1):
290 ret = TILEGX_EXCP_SYSCALL;
291 mnemonic = "swint1";
292 done0:
293 if (srca || dest) {
294 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
295 }
296 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
297 return ret;
298
299 case OE_RR_X1(DTLBPR):
300 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
301 case OE_RR_X1(FINV):
302 mnemonic = "finv";
303 goto done1;
304 case OE_RR_X1(FLUSH):
305 mnemonic = "flush";
306 goto done1;
307 case OE_RR_X1(ICOH):
308 mnemonic = "icoh";
309 goto done1;
310 case OE_RR_X1(INV):
311 mnemonic = "inv";
312 goto done1;
313 case OE_RR_X1(WH64):
314 mnemonic = "wh64";
315 goto done1;
316 case OE_RR_X1(JRP):
317 case OE_RR_Y1(JRP):
318 mnemonic = "jrp";
319 goto do_jr;
320 case OE_RR_X1(JR):
321 case OE_RR_Y1(JR):
322 mnemonic = "jr";
323 goto do_jr;
324 case OE_RR_X1(JALRP):
325 case OE_RR_Y1(JALRP):
326 mnemonic = "jalrp";
327 goto do_jalr;
328 case OE_RR_X1(JALR):
329 case OE_RR_Y1(JALR):
330 mnemonic = "jalr";
331 do_jalr:
332 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
333 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
334 do_jr:
335 dc->jmp.cond = TCG_COND_ALWAYS;
336 dc->jmp.dest = tcg_temp_new();
337 tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
338 done1:
339 if (dest) {
340 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
341 }
342 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
343 return ret;
344 }
345
346 tdest = dest_gr(dc, dest);
347 tsrca = load_gr(dc, srca);
348
349 switch (opext) {
350 case OE_RR_X0(CNTLZ):
351 case OE_RR_Y0(CNTLZ):
352 gen_helper_cntlz(tdest, tsrca);
353 mnemonic = "cntlz";
354 break;
355 case OE_RR_X0(CNTTZ):
356 case OE_RR_Y0(CNTTZ):
357 gen_helper_cnttz(tdest, tsrca);
358 mnemonic = "cnttz";
359 break;
360 case OE_RR_X0(FSINGLE_PACK1):
361 case OE_RR_Y0(FSINGLE_PACK1):
362 case OE_RR_X1(IRET):
363 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
364 case OE_RR_X1(LD1S):
365 memop = MO_SB;
366 mnemonic = "ld1s";
367 goto do_load;
368 case OE_RR_X1(LD1U):
369 memop = MO_UB;
370 mnemonic = "ld1u";
371 goto do_load;
372 case OE_RR_X1(LD2S):
373 memop = MO_TESW;
374 mnemonic = "ld2s";
375 goto do_load;
376 case OE_RR_X1(LD2U):
377 memop = MO_TEUW;
378 mnemonic = "ld2u";
379 goto do_load;
380 case OE_RR_X1(LD4S):
381 memop = MO_TESL;
382 mnemonic = "ld4s";
383 goto do_load;
384 case OE_RR_X1(LD4U):
385 memop = MO_TEUL;
386 mnemonic = "ld4u";
387 goto do_load;
388 case OE_RR_X1(LDNT1S):
389 memop = MO_SB;
390 mnemonic = "ldnt1s";
391 goto do_load;
392 case OE_RR_X1(LDNT1U):
393 memop = MO_UB;
394 mnemonic = "ldnt1u";
395 goto do_load;
396 case OE_RR_X1(LDNT2S):
397 memop = MO_TESW;
398 mnemonic = "ldnt2s";
399 goto do_load;
400 case OE_RR_X1(LDNT2U):
401 memop = MO_TEUW;
402 mnemonic = "ldnt2u";
403 goto do_load;
404 case OE_RR_X1(LDNT4S):
405 memop = MO_TESL;
406 mnemonic = "ldnt4s";
407 goto do_load;
408 case OE_RR_X1(LDNT4U):
409 memop = MO_TEUL;
410 mnemonic = "ldnt4u";
411 goto do_load;
412 case OE_RR_X1(LDNT):
413 memop = MO_TEQ;
414 mnemonic = "ldnt";
415 goto do_load;
416 case OE_RR_X1(LD):
417 memop = MO_TEQ;
418 mnemonic = "ld";
419 do_load:
420 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
421 break;
422 case OE_RR_X1(LDNA):
423 tcg_gen_andi_tl(tdest, tsrca, ~7);
424 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
425 mnemonic = "ldna";
426 break;
427 case OE_RR_X1(LNK):
428 case OE_RR_Y1(LNK):
429 if (srca) {
430 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
431 }
432 tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
433 mnemonic = "lnk";
434 break;
435 case OE_RR_X0(PCNT):
436 case OE_RR_Y0(PCNT):
437 gen_helper_pcnt(tdest, tsrca);
438 mnemonic = "pcnt";
439 break;
440 case OE_RR_X0(REVBITS):
441 case OE_RR_Y0(REVBITS):
442 gen_helper_revbits(tdest, tsrca);
443 mnemonic = "revbits";
444 break;
445 case OE_RR_X0(REVBYTES):
446 case OE_RR_Y0(REVBYTES):
447 tcg_gen_bswap64_tl(tdest, tsrca);
448 mnemonic = "revbytes";
449 break;
450 case OE_RR_X0(TBLIDXB0):
451 case OE_RR_Y0(TBLIDXB0):
452 case OE_RR_X0(TBLIDXB1):
453 case OE_RR_Y0(TBLIDXB1):
454 case OE_RR_X0(TBLIDXB2):
455 case OE_RR_Y0(TBLIDXB2):
456 case OE_RR_X0(TBLIDXB3):
457 case OE_RR_Y0(TBLIDXB3):
458 default:
459 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
460 }
461
462 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
463 reg_names[dest], reg_names[srca]);
464 return ret;
465 }
466
467 static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
468 unsigned dest, unsigned srca, unsigned srcb)
469 {
470 TCGv tdest = dest_gr(dc, dest);
471 TCGv tsrca = load_gr(dc, srca);
472 TCGv tsrcb = load_gr(dc, srcb);
473 const char *mnemonic;
474
475 switch (opext) {
476 case OE_RRR(ADDXSC, 0, X0):
477 case OE_RRR(ADDXSC, 0, X1):
478 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
479 mnemonic = "addxsc";
480 break;
481 case OE_RRR(ADDX, 0, X0):
482 case OE_RRR(ADDX, 0, X1):
483 case OE_RRR(ADDX, 0, Y0):
484 case OE_RRR(ADDX, 0, Y1):
485 tcg_gen_add_tl(tdest, tsrca, tsrcb);
486 tcg_gen_ext32s_tl(tdest, tdest);
487 mnemonic = "addx";
488 break;
489 case OE_RRR(ADD, 0, X0):
490 case OE_RRR(ADD, 0, X1):
491 case OE_RRR(ADD, 0, Y0):
492 case OE_RRR(ADD, 0, Y1):
493 tcg_gen_add_tl(tdest, tsrca, tsrcb);
494 mnemonic = "add";
495 break;
496 case OE_RRR(AND, 0, X0):
497 case OE_RRR(AND, 0, X1):
498 case OE_RRR(AND, 5, Y0):
499 case OE_RRR(AND, 5, Y1):
500 tcg_gen_and_tl(tdest, tsrca, tsrcb);
501 mnemonic = "and";
502 break;
503 case OE_RRR(CMOVEQZ, 0, X0):
504 case OE_RRR(CMOVEQZ, 4, Y0):
505 case OE_RRR(CMOVNEZ, 0, X0):
506 case OE_RRR(CMOVNEZ, 4, Y0):
507 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
508 case OE_RRR(CMPEQ, 0, X0):
509 case OE_RRR(CMPEQ, 0, X1):
510 case OE_RRR(CMPEQ, 3, Y0):
511 case OE_RRR(CMPEQ, 3, Y1):
512 tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
513 mnemonic = "cmpeq";
514 break;
515 case OE_RRR(CMPEXCH4, 0, X1):
516 case OE_RRR(CMPEXCH, 0, X1):
517 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
518 case OE_RRR(CMPLES, 0, X0):
519 case OE_RRR(CMPLES, 0, X1):
520 case OE_RRR(CMPLES, 2, Y0):
521 case OE_RRR(CMPLES, 2, Y1):
522 tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
523 mnemonic = "cmples";
524 break;
525 case OE_RRR(CMPLEU, 0, X0):
526 case OE_RRR(CMPLEU, 0, X1):
527 case OE_RRR(CMPLEU, 2, Y0):
528 case OE_RRR(CMPLEU, 2, Y1):
529 tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
530 mnemonic = "cmpleu";
531 break;
532 case OE_RRR(CMPLTS, 0, X0):
533 case OE_RRR(CMPLTS, 0, X1):
534 case OE_RRR(CMPLTS, 2, Y0):
535 case OE_RRR(CMPLTS, 2, Y1):
536 tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
537 mnemonic = "cmplts";
538 break;
539 case OE_RRR(CMPLTU, 0, X0):
540 case OE_RRR(CMPLTU, 0, X1):
541 case OE_RRR(CMPLTU, 2, Y0):
542 case OE_RRR(CMPLTU, 2, Y1):
543 tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
544 mnemonic = "cmpltu";
545 break;
546 case OE_RRR(CMPNE, 0, X0):
547 case OE_RRR(CMPNE, 0, X1):
548 case OE_RRR(CMPNE, 3, Y0):
549 case OE_RRR(CMPNE, 3, Y1):
550 tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
551 mnemonic = "cmpne";
552 break;
553 case OE_RRR(CMULAF, 0, X0):
554 case OE_RRR(CMULA, 0, X0):
555 case OE_RRR(CMULFR, 0, X0):
556 case OE_RRR(CMULF, 0, X0):
557 case OE_RRR(CMULHR, 0, X0):
558 case OE_RRR(CMULH, 0, X0):
559 case OE_RRR(CMUL, 0, X0):
560 case OE_RRR(CRC32_32, 0, X0):
561 case OE_RRR(CRC32_8, 0, X0):
562 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
563 case OE_RRR(DBLALIGN2, 0, X0):
564 case OE_RRR(DBLALIGN2, 0, X1):
565 gen_dblaligni(tdest, tsrca, tsrcb, 16);
566 mnemonic = "dblalign2";
567 break;
568 case OE_RRR(DBLALIGN4, 0, X0):
569 case OE_RRR(DBLALIGN4, 0, X1):
570 gen_dblaligni(tdest, tsrca, tsrcb, 32);
571 mnemonic = "dblalign4";
572 break;
573 case OE_RRR(DBLALIGN6, 0, X0):
574 case OE_RRR(DBLALIGN6, 0, X1):
575 gen_dblaligni(tdest, tsrca, tsrcb, 48);
576 mnemonic = "dblalign6";
577 break;
578 case OE_RRR(DBLALIGN, 0, X0):
579 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
580 mnemonic = "dblalign";
581 break;
582 case OE_RRR(EXCH4, 0, X1):
583 case OE_RRR(EXCH, 0, X1):
584 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
585 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
586 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
587 case OE_RRR(FDOUBLE_PACK1, 0, X0):
588 case OE_RRR(FDOUBLE_PACK2, 0, X0):
589 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
590 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
591 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
592 case OE_RRR(FETCHADD4, 0, X1):
593 case OE_RRR(FETCHADDGEZ4, 0, X1):
594 case OE_RRR(FETCHADDGEZ, 0, X1):
595 case OE_RRR(FETCHADD, 0, X1):
596 case OE_RRR(FETCHAND4, 0, X1):
597 case OE_RRR(FETCHAND, 0, X1):
598 case OE_RRR(FETCHOR4, 0, X1):
599 case OE_RRR(FETCHOR, 0, X1):
600 case OE_RRR(FSINGLE_ADD1, 0, X0):
601 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
602 case OE_RRR(FSINGLE_MUL1, 0, X0):
603 case OE_RRR(FSINGLE_MUL2, 0, X0):
604 case OE_RRR(FSINGLE_PACK2, 0, X0):
605 case OE_RRR(FSINGLE_SUB1, 0, X0):
606 case OE_RRR(MNZ, 0, X0):
607 case OE_RRR(MNZ, 0, X1):
608 case OE_RRR(MNZ, 4, Y0):
609 case OE_RRR(MNZ, 4, Y1):
610 case OE_RRR(MULAX, 0, X0):
611 case OE_RRR(MULAX, 3, Y0):
612 case OE_RRR(MULA_HS_HS, 0, X0):
613 case OE_RRR(MULA_HS_HS, 9, Y0):
614 case OE_RRR(MULA_HS_HU, 0, X0):
615 case OE_RRR(MULA_HS_LS, 0, X0):
616 case OE_RRR(MULA_HS_LU, 0, X0):
617 case OE_RRR(MULA_HU_HU, 0, X0):
618 case OE_RRR(MULA_HU_HU, 9, Y0):
619 case OE_RRR(MULA_HU_LS, 0, X0):
620 case OE_RRR(MULA_HU_LU, 0, X0):
621 case OE_RRR(MULA_LS_LS, 0, X0):
622 case OE_RRR(MULA_LS_LS, 9, Y0):
623 case OE_RRR(MULA_LS_LU, 0, X0):
624 case OE_RRR(MULA_LU_LU, 0, X0):
625 case OE_RRR(MULA_LU_LU, 9, Y0):
626 case OE_RRR(MULX, 0, X0):
627 case OE_RRR(MULX, 3, Y0):
628 case OE_RRR(MUL_HS_HS, 0, X0):
629 case OE_RRR(MUL_HS_HS, 8, Y0):
630 case OE_RRR(MUL_HS_HU, 0, X0):
631 case OE_RRR(MUL_HS_LS, 0, X0):
632 case OE_RRR(MUL_HS_LU, 0, X0):
633 case OE_RRR(MUL_HU_HU, 0, X0):
634 case OE_RRR(MUL_HU_HU, 8, Y0):
635 case OE_RRR(MUL_HU_LS, 0, X0):
636 case OE_RRR(MUL_HU_LU, 0, X0):
637 case OE_RRR(MUL_LS_LS, 0, X0):
638 case OE_RRR(MUL_LS_LS, 8, Y0):
639 case OE_RRR(MUL_LS_LU, 0, X0):
640 case OE_RRR(MUL_LU_LU, 0, X0):
641 case OE_RRR(MUL_LU_LU, 8, Y0):
642 case OE_RRR(MZ, 0, X0):
643 case OE_RRR(MZ, 0, X1):
644 case OE_RRR(MZ, 4, Y0):
645 case OE_RRR(MZ, 4, Y1):
646 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
647 case OE_RRR(NOR, 0, X0):
648 case OE_RRR(NOR, 0, X1):
649 case OE_RRR(NOR, 5, Y0):
650 case OE_RRR(NOR, 5, Y1):
651 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
652 mnemonic = "nor";
653 break;
654 case OE_RRR(OR, 0, X0):
655 case OE_RRR(OR, 0, X1):
656 case OE_RRR(OR, 5, Y0):
657 case OE_RRR(OR, 5, Y1):
658 tcg_gen_or_tl(tdest, tsrca, tsrcb);
659 mnemonic = "or";
660 break;
661 case OE_RRR(ROTL, 0, X0):
662 case OE_RRR(ROTL, 0, X1):
663 case OE_RRR(ROTL, 6, Y0):
664 case OE_RRR(ROTL, 6, Y1):
665 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
666 case OE_RRR(SHL1ADDX, 0, X0):
667 case OE_RRR(SHL1ADDX, 0, X1):
668 case OE_RRR(SHL1ADDX, 7, Y0):
669 case OE_RRR(SHL1ADDX, 7, Y1):
670 tcg_gen_shli_tl(tdest, tsrca, 1);
671 tcg_gen_add_tl(tdest, tdest, tsrcb);
672 tcg_gen_ext32s_tl(tdest, tdest);
673 mnemonic = "shl1addx";
674 break;
675 case OE_RRR(SHL1ADD, 0, X0):
676 case OE_RRR(SHL1ADD, 0, X1):
677 case OE_RRR(SHL1ADD, 1, Y0):
678 case OE_RRR(SHL1ADD, 1, Y1):
679 tcg_gen_shli_tl(tdest, tsrca, 1);
680 tcg_gen_add_tl(tdest, tdest, tsrcb);
681 mnemonic = "shl1add";
682 break;
683 case OE_RRR(SHL2ADDX, 0, X0):
684 case OE_RRR(SHL2ADDX, 0, X1):
685 case OE_RRR(SHL2ADDX, 7, Y0):
686 case OE_RRR(SHL2ADDX, 7, Y1):
687 tcg_gen_shli_tl(tdest, tsrca, 2);
688 tcg_gen_add_tl(tdest, tdest, tsrcb);
689 tcg_gen_ext32s_tl(tdest, tdest);
690 mnemonic = "shl2addx";
691 break;
692 case OE_RRR(SHL2ADD, 0, X0):
693 case OE_RRR(SHL2ADD, 0, X1):
694 case OE_RRR(SHL2ADD, 1, Y0):
695 case OE_RRR(SHL2ADD, 1, Y1):
696 tcg_gen_shli_tl(tdest, tsrca, 2);
697 tcg_gen_add_tl(tdest, tdest, tsrcb);
698 mnemonic = "shl2add";
699 break;
700 case OE_RRR(SHL3ADDX, 0, X0):
701 case OE_RRR(SHL3ADDX, 0, X1):
702 case OE_RRR(SHL3ADDX, 7, Y0):
703 case OE_RRR(SHL3ADDX, 7, Y1):
704 tcg_gen_shli_tl(tdest, tsrca, 3);
705 tcg_gen_add_tl(tdest, tdest, tsrcb);
706 tcg_gen_ext32s_tl(tdest, tdest);
707 mnemonic = "shl3addx";
708 break;
709 case OE_RRR(SHL3ADD, 0, X0):
710 case OE_RRR(SHL3ADD, 0, X1):
711 case OE_RRR(SHL3ADD, 1, Y0):
712 case OE_RRR(SHL3ADD, 1, Y1):
713 tcg_gen_shli_tl(tdest, tsrca, 3);
714 tcg_gen_add_tl(tdest, tdest, tsrcb);
715 mnemonic = "shl3add";
716 break;
717 case OE_RRR(SHLX, 0, X0):
718 case OE_RRR(SHLX, 0, X1):
719 case OE_RRR(SHL, 0, X0):
720 case OE_RRR(SHL, 0, X1):
721 case OE_RRR(SHL, 6, Y0):
722 case OE_RRR(SHL, 6, Y1):
723 case OE_RRR(SHRS, 0, X0):
724 case OE_RRR(SHRS, 0, X1):
725 case OE_RRR(SHRS, 6, Y0):
726 case OE_RRR(SHRS, 6, Y1):
727 case OE_RRR(SHRUX, 0, X0):
728 case OE_RRR(SHRUX, 0, X1):
729 case OE_RRR(SHRU, 0, X0):
730 case OE_RRR(SHRU, 0, X1):
731 case OE_RRR(SHRU, 6, Y0):
732 case OE_RRR(SHRU, 6, Y1):
733 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
734 case OE_RRR(SHUFFLEBYTES, 0, X0):
735 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
736 mnemonic = "shufflebytes";
737 break;
738 case OE_RRR(SUBXSC, 0, X0):
739 case OE_RRR(SUBXSC, 0, X1):
740 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
741 mnemonic = "subxsc";
742 break;
743 case OE_RRR(SUBX, 0, X0):
744 case OE_RRR(SUBX, 0, X1):
745 case OE_RRR(SUBX, 0, Y0):
746 case OE_RRR(SUBX, 0, Y1):
747 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
748 tcg_gen_ext32s_tl(tdest, tdest);
749 mnemonic = "subx";
750 break;
751 case OE_RRR(SUB, 0, X0):
752 case OE_RRR(SUB, 0, X1):
753 case OE_RRR(SUB, 0, Y0):
754 case OE_RRR(SUB, 0, Y1):
755 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
756 mnemonic = "sub";
757 break;
758 case OE_RRR(V1ADDUC, 0, X0):
759 case OE_RRR(V1ADDUC, 0, X1):
760 case OE_RRR(V1ADD, 0, X0):
761 case OE_RRR(V1ADD, 0, X1):
762 case OE_RRR(V1ADIFFU, 0, X0):
763 case OE_RRR(V1AVGU, 0, X0):
764 case OE_RRR(V1CMPEQ, 0, X0):
765 case OE_RRR(V1CMPEQ, 0, X1):
766 case OE_RRR(V1CMPLES, 0, X0):
767 case OE_RRR(V1CMPLES, 0, X1):
768 case OE_RRR(V1CMPLEU, 0, X0):
769 case OE_RRR(V1CMPLEU, 0, X1):
770 case OE_RRR(V1CMPLTS, 0, X0):
771 case OE_RRR(V1CMPLTS, 0, X1):
772 case OE_RRR(V1CMPLTU, 0, X0):
773 case OE_RRR(V1CMPLTU, 0, X1):
774 case OE_RRR(V1CMPNE, 0, X0):
775 case OE_RRR(V1CMPNE, 0, X1):
776 case OE_RRR(V1DDOTPUA, 0, X0):
777 case OE_RRR(V1DDOTPUSA, 0, X0):
778 case OE_RRR(V1DDOTPUS, 0, X0):
779 case OE_RRR(V1DDOTPU, 0, X0):
780 case OE_RRR(V1DOTPA, 0, X0):
781 case OE_RRR(V1DOTPUA, 0, X0):
782 case OE_RRR(V1DOTPUSA, 0, X0):
783 case OE_RRR(V1DOTPUS, 0, X0):
784 case OE_RRR(V1DOTPU, 0, X0):
785 case OE_RRR(V1DOTP, 0, X0):
786 case OE_RRR(V1INT_H, 0, X0):
787 case OE_RRR(V1INT_H, 0, X1):
788 case OE_RRR(V1INT_L, 0, X0):
789 case OE_RRR(V1INT_L, 0, X1):
790 case OE_RRR(V1MAXU, 0, X0):
791 case OE_RRR(V1MAXU, 0, X1):
792 case OE_RRR(V1MINU, 0, X0):
793 case OE_RRR(V1MINU, 0, X1):
794 case OE_RRR(V1MNZ, 0, X0):
795 case OE_RRR(V1MNZ, 0, X1):
796 case OE_RRR(V1MULTU, 0, X0):
797 case OE_RRR(V1MULUS, 0, X0):
798 case OE_RRR(V1MULU, 0, X0):
799 case OE_RRR(V1MZ, 0, X0):
800 case OE_RRR(V1MZ, 0, X1):
801 case OE_RRR(V1SADAU, 0, X0):
802 case OE_RRR(V1SADU, 0, X0):
803 case OE_RRR(V1SHL, 0, X0):
804 case OE_RRR(V1SHL, 0, X1):
805 case OE_RRR(V1SHRS, 0, X0):
806 case OE_RRR(V1SHRS, 0, X1):
807 case OE_RRR(V1SHRU, 0, X0):
808 case OE_RRR(V1SHRU, 0, X1):
809 case OE_RRR(V1SUBUC, 0, X0):
810 case OE_RRR(V1SUBUC, 0, X1):
811 case OE_RRR(V1SUB, 0, X0):
812 case OE_RRR(V1SUB, 0, X1):
813 case OE_RRR(V2ADDSC, 0, X0):
814 case OE_RRR(V2ADDSC, 0, X1):
815 case OE_RRR(V2ADD, 0, X0):
816 case OE_RRR(V2ADD, 0, X1):
817 case OE_RRR(V2ADIFFS, 0, X0):
818 case OE_RRR(V2AVGS, 0, X0):
819 case OE_RRR(V2CMPEQ, 0, X0):
820 case OE_RRR(V2CMPEQ, 0, X1):
821 case OE_RRR(V2CMPLES, 0, X0):
822 case OE_RRR(V2CMPLES, 0, X1):
823 case OE_RRR(V2CMPLEU, 0, X0):
824 case OE_RRR(V2CMPLEU, 0, X1):
825 case OE_RRR(V2CMPLTS, 0, X0):
826 case OE_RRR(V2CMPLTS, 0, X1):
827 case OE_RRR(V2CMPLTU, 0, X0):
828 case OE_RRR(V2CMPLTU, 0, X1):
829 case OE_RRR(V2CMPNE, 0, X0):
830 case OE_RRR(V2CMPNE, 0, X1):
831 case OE_RRR(V2DOTPA, 0, X0):
832 case OE_RRR(V2DOTP, 0, X0):
833 case OE_RRR(V2INT_H, 0, X0):
834 case OE_RRR(V2INT_H, 0, X1):
835 case OE_RRR(V2INT_L, 0, X0):
836 case OE_RRR(V2INT_L, 0, X1):
837 case OE_RRR(V2MAXS, 0, X0):
838 case OE_RRR(V2MAXS, 0, X1):
839 case OE_RRR(V2MINS, 0, X0):
840 case OE_RRR(V2MINS, 0, X1):
841 case OE_RRR(V2MNZ, 0, X0):
842 case OE_RRR(V2MNZ, 0, X1):
843 case OE_RRR(V2MULFSC, 0, X0):
844 case OE_RRR(V2MULS, 0, X0):
845 case OE_RRR(V2MULTS, 0, X0):
846 case OE_RRR(V2MZ, 0, X0):
847 case OE_RRR(V2MZ, 0, X1):
848 case OE_RRR(V2PACKH, 0, X0):
849 case OE_RRR(V2PACKH, 0, X1):
850 case OE_RRR(V2PACKL, 0, X0):
851 case OE_RRR(V2PACKL, 0, X1):
852 case OE_RRR(V2PACKUC, 0, X0):
853 case OE_RRR(V2PACKUC, 0, X1):
854 case OE_RRR(V2SADAS, 0, X0):
855 case OE_RRR(V2SADAU, 0, X0):
856 case OE_RRR(V2SADS, 0, X0):
857 case OE_RRR(V2SADU, 0, X0):
858 case OE_RRR(V2SHLSC, 0, X0):
859 case OE_RRR(V2SHLSC, 0, X1):
860 case OE_RRR(V2SHL, 0, X0):
861 case OE_RRR(V2SHL, 0, X1):
862 case OE_RRR(V2SHRS, 0, X0):
863 case OE_RRR(V2SHRS, 0, X1):
864 case OE_RRR(V2SHRU, 0, X0):
865 case OE_RRR(V2SHRU, 0, X1):
866 case OE_RRR(V2SUBSC, 0, X0):
867 case OE_RRR(V2SUBSC, 0, X1):
868 case OE_RRR(V2SUB, 0, X0):
869 case OE_RRR(V2SUB, 0, X1):
870 case OE_RRR(V4ADDSC, 0, X0):
871 case OE_RRR(V4ADDSC, 0, X1):
872 case OE_RRR(V4ADD, 0, X0):
873 case OE_RRR(V4ADD, 0, X1):
874 case OE_RRR(V4INT_H, 0, X0):
875 case OE_RRR(V4INT_H, 0, X1):
876 case OE_RRR(V4INT_L, 0, X0):
877 case OE_RRR(V4INT_L, 0, X1):
878 case OE_RRR(V4PACKSC, 0, X0):
879 case OE_RRR(V4PACKSC, 0, X1):
880 case OE_RRR(V4SHLSC, 0, X0):
881 case OE_RRR(V4SHLSC, 0, X1):
882 case OE_RRR(V4SHL, 0, X0):
883 case OE_RRR(V4SHL, 0, X1):
884 case OE_RRR(V4SHRS, 0, X0):
885 case OE_RRR(V4SHRS, 0, X1):
886 case OE_RRR(V4SHRU, 0, X0):
887 case OE_RRR(V4SHRU, 0, X1):
888 case OE_RRR(V4SUBSC, 0, X0):
889 case OE_RRR(V4SUBSC, 0, X1):
890 case OE_RRR(V4SUB, 0, X0):
891 case OE_RRR(V4SUB, 0, X1):
892 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
893 case OE_RRR(XOR, 0, X0):
894 case OE_RRR(XOR, 0, X1):
895 case OE_RRR(XOR, 5, Y0):
896 case OE_RRR(XOR, 5, Y1):
897 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
898 mnemonic = "xor";
899 break;
900 default:
901 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
902 }
903
904 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
905 reg_names[dest], reg_names[srca], reg_names[srcb]);
906 return TILEGX_EXCP_NONE;
907 }
908
909 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
910 unsigned dest, unsigned srca, int imm)
911 {
912 TCGv tdest = dest_gr(dc, dest);
913 TCGv tsrca = load_gr(dc, srca);
914 const char *mnemonic;
915 TCGMemOp memop;
916
917 switch (opext) {
918 case OE(ADDI_OPCODE_Y0, 0, Y0):
919 case OE(ADDI_OPCODE_Y1, 0, Y1):
920 case OE_IM(ADDI, X0):
921 case OE_IM(ADDI, X1):
922 tcg_gen_addi_tl(tdest, tsrca, imm);
923 mnemonic = "addi";
924 break;
925 case OE(ADDXI_OPCODE_Y0, 0, Y0):
926 case OE(ADDXI_OPCODE_Y1, 0, Y1):
927 case OE_IM(ADDXI, X0):
928 case OE_IM(ADDXI, X1):
929 tcg_gen_addi_tl(tdest, tsrca, imm);
930 tcg_gen_ext32s_tl(tdest, tdest);
931 mnemonic = "addxi";
932 break;
933 case OE(ANDI_OPCODE_Y0, 0, Y0):
934 case OE(ANDI_OPCODE_Y1, 0, Y1):
935 case OE_IM(ANDI, X0):
936 case OE_IM(ANDI, X1):
937 tcg_gen_andi_tl(tdest, tsrca, imm);
938 mnemonic = "andi";
939 break;
940 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
941 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
942 case OE_IM(CMPEQI, X0):
943 case OE_IM(CMPEQI, X1):
944 tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
945 mnemonic = "cmpeqi";
946 break;
947 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
948 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
949 case OE_IM(CMPLTSI, X0):
950 case OE_IM(CMPLTSI, X1):
951 tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
952 mnemonic = "cmpltsi";
953 break;
954 case OE_IM(CMPLTUI, X0):
955 case OE_IM(CMPLTUI, X1):
956 tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
957 mnemonic = "cmpltui";
958 break;
959 case OE_IM(LD1S_ADD, X1):
960 memop = MO_SB;
961 mnemonic = "ld1s_add";
962 goto do_load_add;
963 case OE_IM(LD1U_ADD, X1):
964 memop = MO_UB;
965 mnemonic = "ld1u_add";
966 goto do_load_add;
967 case OE_IM(LD2S_ADD, X1):
968 memop = MO_TESW;
969 mnemonic = "ld2s_add";
970 goto do_load_add;
971 case OE_IM(LD2U_ADD, X1):
972 memop = MO_TEUW;
973 mnemonic = "ld2u_add";
974 goto do_load_add;
975 case OE_IM(LD4S_ADD, X1):
976 memop = MO_TESL;
977 mnemonic = "ld4s_add";
978 goto do_load_add;
979 case OE_IM(LD4U_ADD, X1):
980 memop = MO_TEUL;
981 mnemonic = "ld4u_add";
982 goto do_load_add;
983 case OE_IM(LDNT1S_ADD, X1):
984 memop = MO_SB;
985 mnemonic = "ldnt1s_add";
986 goto do_load_add;
987 case OE_IM(LDNT1U_ADD, X1):
988 memop = MO_UB;
989 mnemonic = "ldnt1u_add";
990 goto do_load_add;
991 case OE_IM(LDNT2S_ADD, X1):
992 memop = MO_TESW;
993 mnemonic = "ldnt2s_add";
994 goto do_load_add;
995 case OE_IM(LDNT2U_ADD, X1):
996 memop = MO_TEUW;
997 mnemonic = "ldnt2u_add";
998 goto do_load_add;
999 case OE_IM(LDNT4S_ADD, X1):
1000 memop = MO_TESL;
1001 mnemonic = "ldnt4s_add";
1002 goto do_load_add;
1003 case OE_IM(LDNT4U_ADD, X1):
1004 memop = MO_TEUL;
1005 mnemonic = "ldnt4u_add";
1006 goto do_load_add;
1007 case OE_IM(LDNT_ADD, X1):
1008 memop = MO_TEQ;
1009 mnemonic = "ldnt_add";
1010 goto do_load_add;
1011 case OE_IM(LD_ADD, X1):
1012 memop = MO_TEQ;
1013 mnemonic = "ldnt_add";
1014 do_load_add:
1015 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
1016 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1017 break;
1018 case OE_IM(LDNA_ADD, X1):
1019 tcg_gen_andi_tl(tdest, tsrca, ~7);
1020 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
1021 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1022 mnemonic = "ldna_add";
1023 break;
1024 case OE_IM(MFSPR, X1):
1025 case OE_IM(MTSPR, X1):
1026 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1027 case OE_IM(ORI, X0):
1028 case OE_IM(ORI, X1):
1029 tcg_gen_ori_tl(tdest, tsrca, imm);
1030 mnemonic = "ori";
1031 break;
1032 case OE_IM(V1ADDI, X0):
1033 case OE_IM(V1ADDI, X1):
1034 case OE_IM(V1CMPEQI, X0):
1035 case OE_IM(V1CMPEQI, X1):
1036 case OE_IM(V1CMPLTSI, X0):
1037 case OE_IM(V1CMPLTSI, X1):
1038 case OE_IM(V1CMPLTUI, X0):
1039 case OE_IM(V1CMPLTUI, X1):
1040 case OE_IM(V1MAXUI, X0):
1041 case OE_IM(V1MAXUI, X1):
1042 case OE_IM(V1MINUI, X0):
1043 case OE_IM(V1MINUI, X1):
1044 case OE_IM(V2ADDI, X0):
1045 case OE_IM(V2ADDI, X1):
1046 case OE_IM(V2CMPEQI, X0):
1047 case OE_IM(V2CMPEQI, X1):
1048 case OE_IM(V2CMPLTSI, X0):
1049 case OE_IM(V2CMPLTSI, X1):
1050 case OE_IM(V2CMPLTUI, X0):
1051 case OE_IM(V2CMPLTUI, X1):
1052 case OE_IM(V2MAXSI, X0):
1053 case OE_IM(V2MAXSI, X1):
1054 case OE_IM(V2MINSI, X0):
1055 case OE_IM(V2MINSI, X1):
1056 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1057 case OE_IM(XORI, X0):
1058 case OE_IM(XORI, X1):
1059 tcg_gen_xori_tl(tdest, tsrca, imm);
1060 mnemonic = "xori";
1061 break;
1062
1063 case OE_SH(ROTLI, X0):
1064 case OE_SH(ROTLI, X1):
1065 case OE_SH(ROTLI, Y0):
1066 case OE_SH(ROTLI, Y1):
1067 case OE_SH(SHLI, X0):
1068 case OE_SH(SHLI, X1):
1069 case OE_SH(SHLI, Y0):
1070 case OE_SH(SHLI, Y1):
1071 case OE_SH(SHLXI, X0):
1072 case OE_SH(SHLXI, X1):
1073 case OE_SH(SHRSI, X0):
1074 case OE_SH(SHRSI, X1):
1075 case OE_SH(SHRSI, Y0):
1076 case OE_SH(SHRSI, Y1):
1077 case OE_SH(SHRUI, X0):
1078 case OE_SH(SHRUI, X1):
1079 case OE_SH(SHRUI, Y0):
1080 case OE_SH(SHRUI, Y1):
1081 case OE_SH(SHRUXI, X0):
1082 case OE_SH(SHRUXI, X1):
1083 case OE_SH(V1SHLI, X0):
1084 case OE_SH(V1SHLI, X1):
1085 case OE_SH(V1SHRSI, X0):
1086 case OE_SH(V1SHRSI, X1):
1087 case OE_SH(V1SHRUI, X0):
1088 case OE_SH(V1SHRUI, X1):
1089 case OE_SH(V2SHLI, X0):
1090 case OE_SH(V2SHLI, X1):
1091 case OE_SH(V2SHRSI, X0):
1092 case OE_SH(V2SHRSI, X1):
1093 case OE_SH(V2SHRUI, X0):
1094 case OE_SH(V2SHRUI, X1):
1095 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1096
1097 case OE(ADDLI_OPCODE_X0, 0, X0):
1098 case OE(ADDLI_OPCODE_X1, 0, X1):
1099 tcg_gen_addi_tl(tdest, tsrca, imm);
1100 mnemonic = "addli";
1101 break;
1102 case OE(ADDXLI_OPCODE_X0, 0, X0):
1103 case OE(ADDXLI_OPCODE_X1, 0, X1):
1104 tcg_gen_addi_tl(tdest, tsrca, imm);
1105 tcg_gen_ext32s_tl(tdest, tdest);
1106 mnemonic = "addxli";
1107 break;
1108 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
1109 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
1110 tcg_gen_shli_tl(tdest, tsrca, 16);
1111 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
1112 mnemonic = "shl16insli";
1113 break;
1114
1115 default:
1116 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1117 }
1118
1119 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
1120 reg_names[dest], reg_names[srca], imm);
1121 return TILEGX_EXCP_NONE;
1122 }
1123
1124 static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
1125 unsigned dest, unsigned srca,
1126 unsigned bfs, unsigned bfe)
1127 {
1128 TCGv tdest = dest_gr(dc, dest);
1129 TCGv tsrca = load_gr(dc, srca);
1130 TCGv tsrcd;
1131 int len;
1132 const char *mnemonic;
1133
1134 /* The bitfield is either between E and S inclusive,
1135 or up from S and down from E inclusive. */
1136 if (bfs <= bfe) {
1137 len = bfe - bfs + 1;
1138 } else {
1139 len = (64 - bfs) + (bfe + 1);
1140 }
1141
1142 switch (ext) {
1143 case BFEXTU_BF_OPCODE_X0:
1144 if (bfs == 0 && bfe == 7) {
1145 tcg_gen_ext8u_tl(tdest, tsrca);
1146 } else if (bfs == 0 && bfe == 15) {
1147 tcg_gen_ext16u_tl(tdest, tsrca);
1148 } else if (bfs == 0 && bfe == 31) {
1149 tcg_gen_ext32u_tl(tdest, tsrca);
1150 } else {
1151 int rol = 63 - bfe;
1152 if (bfs <= bfe) {
1153 tcg_gen_shli_tl(tdest, tsrca, rol);
1154 } else {
1155 tcg_gen_rotli_tl(tdest, tsrca, rol);
1156 }
1157 tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
1158 }
1159 mnemonic = "bfextu";
1160 break;
1161
1162 case BFEXTS_BF_OPCODE_X0:
1163 if (bfs == 0 && bfe == 7) {
1164 tcg_gen_ext8s_tl(tdest, tsrca);
1165 } else if (bfs == 0 && bfe == 15) {
1166 tcg_gen_ext16s_tl(tdest, tsrca);
1167 } else if (bfs == 0 && bfe == 31) {
1168 tcg_gen_ext32s_tl(tdest, tsrca);
1169 } else {
1170 int rol = 63 - bfe;
1171 if (bfs <= bfe) {
1172 tcg_gen_shli_tl(tdest, tsrca, rol);
1173 } else {
1174 tcg_gen_rotli_tl(tdest, tsrca, rol);
1175 }
1176 tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
1177 }
1178 mnemonic = "bfexts";
1179 break;
1180
1181 case BFINS_BF_OPCODE_X0:
1182 tsrcd = load_gr(dc, dest);
1183 if (bfs <= bfe) {
1184 tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
1185 } else {
1186 tcg_gen_rotri_tl(tdest, tsrcd, bfs);
1187 tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
1188 tcg_gen_rotli_tl(tdest, tdest, bfs);
1189 }
1190 mnemonic = "bfins";
1191 break;
1192
1193 case MM_BF_OPCODE_X0:
1194 tsrcd = load_gr(dc, dest);
1195 if (bfs == 0) {
1196 tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
1197 } else {
1198 uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
1199 TCGv tmp = tcg_const_tl(mask);
1200
1201 tcg_gen_and_tl(tdest, tsrcd, tmp);
1202 tcg_gen_andc_tl(tmp, tsrca, tmp);
1203 tcg_gen_or_tl(tdest, tdest, tmp);
1204 tcg_temp_free(tmp);
1205 }
1206 mnemonic = "mm";
1207 break;
1208
1209 default:
1210 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1211 }
1212
1213 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
1214 reg_names[dest], reg_names[srca], bfs, bfe);
1215 return TILEGX_EXCP_NONE;
1216 }
1217
1218 static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
1219 unsigned srca, int off)
1220 {
1221 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1222 const char *mnemonic;
1223
1224 dc->jmp.dest = tcg_const_tl(tgt);
1225 dc->jmp.val1 = tcg_temp_new();
1226 tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
1227
1228 /* Note that the "predict taken" opcodes have bit 0 clear.
1229 Therefore, fold the two cases together by setting bit 0. */
1230 switch (ext | 1) {
1231 case BEQZ_BRANCH_OPCODE_X1:
1232 dc->jmp.cond = TCG_COND_EQ;
1233 mnemonic = "beqz";
1234 break;
1235 case BNEZ_BRANCH_OPCODE_X1:
1236 dc->jmp.cond = TCG_COND_NE;
1237 mnemonic = "bnez";
1238 break;
1239 case BGEZ_BRANCH_OPCODE_X1:
1240 dc->jmp.cond = TCG_COND_GE;
1241 mnemonic = "bgez";
1242 break;
1243 case BGTZ_BRANCH_OPCODE_X1:
1244 dc->jmp.cond = TCG_COND_GT;
1245 mnemonic = "bgtz";
1246 break;
1247 case BLEZ_BRANCH_OPCODE_X1:
1248 dc->jmp.cond = TCG_COND_LE;
1249 mnemonic = "blez";
1250 break;
1251 case BLTZ_BRANCH_OPCODE_X1:
1252 dc->jmp.cond = TCG_COND_LT;
1253 mnemonic = "bltz";
1254 break;
1255 case BLBC_BRANCH_OPCODE_X1:
1256 dc->jmp.cond = TCG_COND_EQ;
1257 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1258 mnemonic = "blbc";
1259 break;
1260 case BLBS_BRANCH_OPCODE_X1:
1261 dc->jmp.cond = TCG_COND_NE;
1262 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1263 mnemonic = "blbs";
1264 break;
1265 default:
1266 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1267 }
1268
1269 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1270 qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
1271 mnemonic, ext & 1 ? "" : "t",
1272 reg_names[srca], tgt, lookup_symbol(tgt));
1273 }
1274 return TILEGX_EXCP_NONE;
1275 }
1276
1277 static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
1278 {
1279 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1280 const char *mnemonic = "j";
1281
1282 /* The extension field is 1 bit, therefore we only have JAL and J. */
1283 if (ext == JAL_JUMP_OPCODE_X1) {
1284 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
1285 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1286 mnemonic = "jal";
1287 }
1288 dc->jmp.cond = TCG_COND_ALWAYS;
1289 dc->jmp.dest = tcg_const_tl(tgt);
1290
1291 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1292 qemu_log("%s " TARGET_FMT_lx " <%s>",
1293 mnemonic, tgt, lookup_symbol(tgt));
1294 }
1295 return TILEGX_EXCP_NONE;
1296 }
1297
1298 static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
1299 {
1300 unsigned opc = get_Opcode_Y0(bundle);
1301 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
1302 unsigned dest = get_Dest_Y0(bundle);
1303 unsigned srca = get_SrcA_Y0(bundle);
1304 unsigned srcb;
1305 int imm;
1306
1307 switch (opc) {
1308 case RRR_1_OPCODE_Y0:
1309 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1310 ext = get_UnaryOpcodeExtension_Y0(bundle);
1311 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
1312 }
1313 /* fallthru */
1314 case RRR_0_OPCODE_Y0:
1315 case RRR_2_OPCODE_Y0:
1316 case RRR_3_OPCODE_Y0:
1317 case RRR_4_OPCODE_Y0:
1318 case RRR_5_OPCODE_Y0:
1319 case RRR_6_OPCODE_Y0:
1320 case RRR_7_OPCODE_Y0:
1321 case RRR_8_OPCODE_Y0:
1322 case RRR_9_OPCODE_Y0:
1323 srcb = get_SrcB_Y0(bundle);
1324 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
1325
1326 case SHIFT_OPCODE_Y0:
1327 ext = get_ShiftOpcodeExtension_Y0(bundle);
1328 imm = get_ShAmt_Y0(bundle);
1329 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
1330
1331 case ADDI_OPCODE_Y0:
1332 case ADDXI_OPCODE_Y0:
1333 case ANDI_OPCODE_Y0:
1334 case CMPEQI_OPCODE_Y0:
1335 case CMPLTSI_OPCODE_Y0:
1336 imm = (int8_t)get_Imm8_Y0(bundle);
1337 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
1338
1339 default:
1340 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1341 }
1342 }
1343
1344 static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
1345 {
1346 unsigned opc = get_Opcode_Y1(bundle);
1347 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
1348 unsigned dest = get_Dest_Y1(bundle);
1349 unsigned srca = get_SrcA_Y1(bundle);
1350 unsigned srcb;
1351 int imm;
1352
1353 switch (get_Opcode_Y1(bundle)) {
1354 case RRR_1_OPCODE_Y1:
1355 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1356 ext = get_UnaryOpcodeExtension_Y1(bundle);
1357 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
1358 }
1359 /* fallthru */
1360 case RRR_0_OPCODE_Y1:
1361 case RRR_2_OPCODE_Y1:
1362 case RRR_3_OPCODE_Y1:
1363 case RRR_4_OPCODE_Y1:
1364 case RRR_5_OPCODE_Y1:
1365 case RRR_6_OPCODE_Y1:
1366 case RRR_7_OPCODE_Y1:
1367 srcb = get_SrcB_Y1(bundle);
1368 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
1369
1370 case SHIFT_OPCODE_Y1:
1371 ext = get_ShiftOpcodeExtension_Y1(bundle);
1372 imm = get_ShAmt_Y1(bundle);
1373 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
1374
1375 case ADDI_OPCODE_Y1:
1376 case ADDXI_OPCODE_Y1:
1377 case ANDI_OPCODE_Y1:
1378 case CMPEQI_OPCODE_Y1:
1379 case CMPLTSI_OPCODE_Y1:
1380 imm = (int8_t)get_Imm8_Y1(bundle);
1381 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
1382
1383 default:
1384 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1385 }
1386 }
1387
1388 static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
1389 {
1390 unsigned mode = get_Mode(bundle);
1391 unsigned opc = get_Opcode_Y2(bundle);
1392 unsigned srca = get_SrcA_Y2(bundle);
1393 unsigned srcbdest = get_SrcBDest_Y2(bundle);
1394 const char *mnemonic;
1395 TCGMemOp memop;
1396
1397 switch (OEY2(opc, mode)) {
1398 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
1399 memop = MO_SB;
1400 mnemonic = "ld1s";
1401 goto do_load;
1402 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
1403 memop = MO_UB;
1404 mnemonic = "ld1u";
1405 goto do_load;
1406 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
1407 memop = MO_TESW;
1408 mnemonic = "ld2s";
1409 goto do_load;
1410 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
1411 memop = MO_TEUW;
1412 mnemonic = "ld2u";
1413 goto do_load;
1414 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
1415 memop = MO_TESL;
1416 mnemonic = "ld4s";
1417 goto do_load;
1418 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
1419 memop = MO_TEUL;
1420 mnemonic = "ld4u";
1421 goto do_load;
1422 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
1423 memop = MO_TEQ;
1424 mnemonic = "ld";
1425 do_load:
1426 tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
1427 dc->mmuidx, memop);
1428 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
1429 reg_names[srcbdest], reg_names[srca]);
1430 return TILEGX_EXCP_NONE;
1431
1432 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
1433 return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
1434 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
1435 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
1436 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
1437 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
1438 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
1439 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
1440
1441 default:
1442 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1443 }
1444 }
1445
1446 static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
1447 {
1448 unsigned opc = get_Opcode_X0(bundle);
1449 unsigned dest = get_Dest_X0(bundle);
1450 unsigned srca = get_SrcA_X0(bundle);
1451 unsigned ext, srcb, bfs, bfe;
1452 int imm;
1453
1454 switch (opc) {
1455 case RRR_0_OPCODE_X0:
1456 ext = get_RRROpcodeExtension_X0(bundle);
1457 if (ext == UNARY_RRR_0_OPCODE_X0) {
1458 ext = get_UnaryOpcodeExtension_X0(bundle);
1459 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
1460 }
1461 srcb = get_SrcB_X0(bundle);
1462 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
1463
1464 case SHIFT_OPCODE_X0:
1465 ext = get_ShiftOpcodeExtension_X0(bundle);
1466 imm = get_ShAmt_X0(bundle);
1467 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1468
1469 case IMM8_OPCODE_X0:
1470 ext = get_Imm8OpcodeExtension_X0(bundle);
1471 imm = (int8_t)get_Imm8_X0(bundle);
1472 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1473
1474 case BF_OPCODE_X0:
1475 ext = get_BFOpcodeExtension_X0(bundle);
1476 bfs = get_BFStart_X0(bundle);
1477 bfe = get_BFEnd_X0(bundle);
1478 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
1479
1480 case ADDLI_OPCODE_X0:
1481 case SHL16INSLI_OPCODE_X0:
1482 case ADDXLI_OPCODE_X0:
1483 imm = (int16_t)get_Imm16_X0(bundle);
1484 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
1485
1486 default:
1487 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1488 }
1489 }
1490
1491 static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
1492 {
1493 unsigned opc = get_Opcode_X1(bundle);
1494 unsigned dest = get_Dest_X1(bundle);
1495 unsigned srca = get_SrcA_X1(bundle);
1496 unsigned ext, srcb;
1497 int imm;
1498
1499 switch (opc) {
1500 case RRR_0_OPCODE_X1:
1501 ext = get_RRROpcodeExtension_X1(bundle);
1502 srcb = get_SrcB_X1(bundle);
1503 switch (ext) {
1504 case UNARY_RRR_0_OPCODE_X1:
1505 ext = get_UnaryOpcodeExtension_X1(bundle);
1506 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
1507 case ST1_RRR_0_OPCODE_X1:
1508 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
1509 case ST2_RRR_0_OPCODE_X1:
1510 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
1511 case ST4_RRR_0_OPCODE_X1:
1512 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
1513 case STNT1_RRR_0_OPCODE_X1:
1514 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
1515 case STNT2_RRR_0_OPCODE_X1:
1516 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
1517 case STNT4_RRR_0_OPCODE_X1:
1518 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
1519 case STNT_RRR_0_OPCODE_X1:
1520 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
1521 case ST_RRR_0_OPCODE_X1:
1522 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
1523 }
1524 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
1525
1526 case SHIFT_OPCODE_X1:
1527 ext = get_ShiftOpcodeExtension_X1(bundle);
1528 imm = get_ShAmt_X1(bundle);
1529 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1530
1531 case IMM8_OPCODE_X1:
1532 ext = get_Imm8OpcodeExtension_X1(bundle);
1533 imm = (int8_t)get_Dest_Imm8_X1(bundle);
1534 srcb = get_SrcB_X1(bundle);
1535 switch (ext) {
1536 case ST1_ADD_IMM8_OPCODE_X1:
1537 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add");
1538 case ST2_ADD_IMM8_OPCODE_X1:
1539 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add");
1540 case ST4_ADD_IMM8_OPCODE_X1:
1541 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add");
1542 case STNT1_ADD_IMM8_OPCODE_X1:
1543 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add");
1544 case STNT2_ADD_IMM8_OPCODE_X1:
1545 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add");
1546 case STNT4_ADD_IMM8_OPCODE_X1:
1547 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add");
1548 case STNT_ADD_IMM8_OPCODE_X1:
1549 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
1550 case ST_ADD_IMM8_OPCODE_X1:
1551 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
1552 }
1553 imm = (int8_t)get_Imm8_X1(bundle);
1554 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1555
1556 case BRANCH_OPCODE_X1:
1557 ext = get_BrType_X1(bundle);
1558 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
1559 return gen_branch_opcode_x1(dc, ext, srca, imm);
1560
1561 case JUMP_OPCODE_X1:
1562 ext = get_JumpOpcodeExtension_X1(bundle);
1563 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
1564 return gen_jump_opcode_x1(dc, ext, imm);
1565
1566 case ADDLI_OPCODE_X1:
1567 case SHL16INSLI_OPCODE_X1:
1568 case ADDXLI_OPCODE_X1:
1569 imm = (int16_t)get_Imm16_X1(bundle);
1570 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
1571
1572 default:
1573 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1574 }
1575 }
1576
1577 static void notice_excp(DisasContext *dc, uint64_t bundle,
1578 const char *type, TileExcp excp)
1579 {
1580 if (likely(excp == TILEGX_EXCP_NONE)) {
1581 return;
1582 }
1583 gen_exception(dc, excp);
1584 if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
1585 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
1586 }
1587 }
1588
1589 static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
1590 {
1591 int i;
1592
1593 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
1594 DisasContextTemp *wb = &dc->wb[i];
1595 wb->reg = TILEGX_R_NOREG;
1596 TCGV_UNUSED_I64(wb->val);
1597 }
1598 dc->num_wb = 0;
1599
1600 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1601 tcg_gen_debug_insn_start(dc->pc);
1602 }
1603
1604 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
1605 if (get_Mode(bundle)) {
1606 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
1607 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1608 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
1609 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1610 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
1611 } else {
1612 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
1613 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1614 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
1615 }
1616 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
1617
1618 for (i = dc->num_wb - 1; i >= 0; --i) {
1619 DisasContextTemp *wb = &dc->wb[i];
1620 if (wb->reg < TILEGX_R_COUNT) {
1621 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
1622 }
1623 tcg_temp_free_i64(wb->val);
1624 }
1625
1626 if (dc->jmp.cond != TCG_COND_NEVER) {
1627 if (dc->jmp.cond == TCG_COND_ALWAYS) {
1628 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
1629 } else {
1630 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1631 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
1632 dc->jmp.val1, load_zero(dc),
1633 dc->jmp.dest, next);
1634 tcg_temp_free_i64(dc->jmp.val1);
1635 tcg_temp_free_i64(next);
1636 }
1637 tcg_temp_free_i64(dc->jmp.dest);
1638 tcg_gen_exit_tb(0);
1639 dc->exit_tb = true;
1640 }
1641 }
1642
1643 static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
1644 TranslationBlock *tb,
1645 bool search_pc)
1646 {
1647 DisasContext ctx;
1648 DisasContext *dc = &ctx;
1649 CPUState *cs = CPU(cpu);
1650 CPUTLGState *env = &cpu->env;
1651 uint64_t pc_start = tb->pc;
1652 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1653 int j, lj = -1;
1654 int num_insns = 0;
1655 int max_insns = tb->cflags & CF_COUNT_MASK;
1656
1657 dc->pc = pc_start;
1658 dc->mmuidx = 0;
1659 dc->exit_tb = false;
1660 dc->jmp.cond = TCG_COND_NEVER;
1661 TCGV_UNUSED_I64(dc->jmp.dest);
1662 TCGV_UNUSED_I64(dc->jmp.val1);
1663 TCGV_UNUSED_I64(dc->zero);
1664
1665 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1666 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1667 }
1668 if (!max_insns) {
1669 max_insns = CF_COUNT_MASK;
1670 }
1671 if (cs->singlestep_enabled || singlestep) {
1672 max_insns = 1;
1673 }
1674 gen_tb_start(tb);
1675
1676 while (1) {
1677 if (search_pc) {
1678 j = tcg_op_buf_count();
1679 if (lj < j) {
1680 lj++;
1681 while (lj < j) {
1682 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1683 }
1684 }
1685 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1686 tcg_ctx.gen_opc_instr_start[lj] = 1;
1687 tcg_ctx.gen_opc_icount[lj] = num_insns;
1688 }
1689 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
1690
1691 if (dc->exit_tb) {
1692 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
1693 break;
1694 }
1695 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
1696 if (++num_insns >= max_insns
1697 || dc->pc >= next_page_start
1698 || tcg_op_buf_full()) {
1699 /* Ending the TB due to TB size or page boundary. Set PC. */
1700 tcg_gen_movi_tl(cpu_pc, dc->pc);
1701 tcg_gen_exit_tb(0);
1702 break;
1703 }
1704 }
1705
1706 gen_tb_end(tb, num_insns);
1707 if (search_pc) {
1708 j = tcg_op_buf_count();
1709 lj++;
1710 while (lj <= j) {
1711 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1712 }
1713 } else {
1714 tb->size = dc->pc - pc_start;
1715 tb->icount = num_insns;
1716 }
1717
1718 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1719 }
1720
1721 void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
1722 {
1723 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
1724 }
1725
1726 void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
1727 {
1728 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
1729 }
1730
1731 void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
1732 {
1733 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1734 }
1735
1736 void tilegx_tcg_init(void)
1737 {
1738 int i;
1739
1740 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1741 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
1742 for (i = 0; i < TILEGX_R_COUNT; i++) {
1743 cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
1744 offsetof(CPUTLGState, regs[i]),
1745 reg_names[i]);
1746 }
1747 }
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