4 * Copyright (c) 2015 Chen Gang
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
23 #include "disas/disas.h"
25 #include "exec/cpu_ldst.h"
26 #include "opcode_tilegx.h"
28 #define FMT64X "%016" PRIx64
30 static TCGv_ptr cpu_env
;
32 static TCGv cpu_regs
[TILEGX_R_COUNT
];
34 static const char * const reg_names
[64] = {
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
39 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
40 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
41 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
42 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
45 /* Modified registers are cached in temporaries until the end of the bundle. */
51 #define MAX_WRITEBACK 4
53 /* This is the state at translation time. */
55 uint64_t pc
; /* Current pc */
57 TCGv zero
; /* For zero register */
59 DisasContextTemp wb
[MAX_WRITEBACK
];
65 TCGCond cond
; /* branch condition */
66 TCGv dest
; /* branch destination */
67 TCGv val1
; /* value to be compared against zero, for cond */
68 } jmp
; /* Jump object, only once in each TB block */
71 #include "exec/gen-icount.h"
73 /* Differentiate the various pipe encodings. */
79 /* Remerge the base opcode and extension fields for switching.
80 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
81 Y2 opcode field is 2 bits. */
82 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
84 /* Similar, but for Y2 only. */
85 #define OEY2(OP, MODE) (OP + MODE * 4)
87 /* Similar, but make sure opcode names match up. */
88 #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
89 #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
90 #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
91 #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
92 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
93 #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
94 #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
97 static void gen_exception(DisasContext
*dc
, TileExcp num
)
101 tcg_gen_movi_tl(cpu_pc
, dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
103 tmp
= tcg_const_i32(num
);
104 gen_helper_exception(cpu_env
, tmp
);
105 tcg_temp_free_i32(tmp
);
109 static bool check_gr(DisasContext
*dc
, uint8_t reg
)
111 if (likely(reg
< TILEGX_R_COUNT
)) {
121 gen_exception(dc
, TILEGX_EXCP_REG_IDN_ACCESS
);
127 gen_exception(dc
, TILEGX_EXCP_REG_UDN_ACCESS
);
130 g_assert_not_reached();
135 static TCGv
load_zero(DisasContext
*dc
)
137 if (TCGV_IS_UNUSED_I64(dc
->zero
)) {
138 dc
->zero
= tcg_const_i64(0);
143 static TCGv
load_gr(DisasContext
*dc
, unsigned reg
)
145 if (check_gr(dc
, reg
)) {
146 return cpu_regs
[reg
];
148 return load_zero(dc
);
151 static TCGv
dest_gr(DisasContext
*dc
, unsigned reg
)
155 /* Skip the result, mark the exception if necessary, and continue */
160 return dc
->wb
[n
].val
= tcg_temp_new_i64();
163 static void gen_saturate_op(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
,
164 void (*operate
)(TCGv
, TCGv
, TCGv
))
166 TCGv t0
= tcg_temp_new();
168 tcg_gen_ext32s_tl(tdest
, tsrca
);
169 tcg_gen_ext32s_tl(t0
, tsrcb
);
170 operate(tdest
, tdest
, t0
);
172 tcg_gen_movi_tl(t0
, 0x7fffffff);
173 tcg_gen_movcond_tl(TCG_COND_GT
, tdest
, tdest
, t0
, t0
, tdest
);
174 tcg_gen_movi_tl(t0
, -0x80000000LL
);
175 tcg_gen_movcond_tl(TCG_COND_LT
, tdest
, tdest
, t0
, t0
, tdest
);
180 /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
181 specified by the bottom 3 bits of TSRCB, and set TDEST to the
182 low 64 bits of the resulting value. */
183 static void gen_dblalign(TCGv tdest
, TCGv tsrcd
, TCGv tsrca
, TCGv tsrcb
)
185 TCGv t0
= tcg_temp_new();
187 tcg_gen_andi_tl(t0
, tsrcb
, 7);
188 tcg_gen_shli_tl(t0
, t0
, 3);
189 tcg_gen_shr_tl(tdest
, tsrcd
, t0
);
191 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
192 arithmetic on a 6-bit field tells us that 64 - t0 is equal
193 to (t0 ^ 63) + 1. So we can do the shift in two parts,
194 neither of which will be an invalid shift by 64. */
195 tcg_gen_xori_tl(t0
, t0
, 63);
196 tcg_gen_shl_tl(t0
, tsrca
, t0
);
197 tcg_gen_shli_tl(t0
, t0
, 1);
198 tcg_gen_or_tl(tdest
, tdest
, t0
);
203 /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
204 right shift is an immediate. */
205 static void gen_dblaligni(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
, int shr
)
207 TCGv t0
= tcg_temp_new();
209 tcg_gen_shri_tl(t0
, tsrcb
, shr
);
210 tcg_gen_shli_tl(tdest
, tsrca
, 64 - shr
);
211 tcg_gen_or_tl(tdest
, tdest
, t0
);
216 static TileExcp
gen_st_opcode(DisasContext
*dc
, unsigned dest
, unsigned srca
,
217 unsigned srcb
, TCGMemOp memop
, const char *name
)
220 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
223 tcg_gen_qemu_st_tl(load_gr(dc
, srcb
), load_gr(dc
, srca
),
226 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s", name
,
227 reg_names
[srca
], reg_names
[srcb
]);
228 return TILEGX_EXCP_NONE
;
231 static TileExcp
gen_rr_opcode(DisasContext
*dc
, unsigned opext
,
232 unsigned dest
, unsigned srca
)
235 const char *mnemonic
;
238 /* Eliminate nops before doing anything else. */
253 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
255 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s", mnemonic
);
256 return TILEGX_EXCP_NONE
;
259 tdest
= dest_gr(dc
, dest
);
260 tsrca
= load_gr(dc
, srca
);
263 case OE_RR_X0(CNTLZ
):
264 case OE_RR_Y0(CNTLZ
):
265 gen_helper_cntlz(tdest
, tsrca
);
268 case OE_RR_X0(CNTTZ
):
269 case OE_RR_Y0(CNTTZ
):
270 gen_helper_cnttz(tdest
, tsrca
);
273 case OE_RR_X1(DRAIN
):
274 case OE_RR_X1(DTLBPR
):
276 case OE_RR_X1(FLUSHWB
):
277 case OE_RR_X1(FLUSH
):
278 case OE_RR_X0(FSINGLE_PACK1
):
279 case OE_RR_Y0(FSINGLE_PACK1
):
285 case OE_RR_X1(JALRP
):
286 case OE_RR_Y1(JALRP
):
293 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
318 case OE_RR_X1(LDNT1S
):
322 case OE_RR_X1(LDNT1U
):
326 case OE_RR_X1(LDNT2S
):
330 case OE_RR_X1(LDNT2U
):
334 case OE_RR_X1(LDNT4S
):
338 case OE_RR_X1(LDNT4U
):
350 tcg_gen_qemu_ld_tl(tdest
, tsrca
, dc
->mmuidx
, memop
);
353 tcg_gen_andi_tl(tdest
, tsrca
, ~7);
354 tcg_gen_qemu_ld_tl(tdest
, tdest
, dc
->mmuidx
, MO_TEQ
);
361 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
364 gen_helper_pcnt(tdest
, tsrca
);
367 case OE_RR_X0(REVBITS
):
368 case OE_RR_Y0(REVBITS
):
369 gen_helper_revbits(tdest
, tsrca
);
370 mnemonic
= "revbits";
372 case OE_RR_X0(REVBYTES
):
373 case OE_RR_Y0(REVBYTES
):
374 tcg_gen_bswap64_tl(tdest
, tsrca
);
375 mnemonic
= "revbytes";
377 case OE_RR_X1(SWINT0
):
378 case OE_RR_X1(SWINT1
):
379 case OE_RR_X1(SWINT2
):
380 case OE_RR_X1(SWINT3
):
381 case OE_RR_X0(TBLIDXB0
):
382 case OE_RR_Y0(TBLIDXB0
):
383 case OE_RR_X0(TBLIDXB1
):
384 case OE_RR_Y0(TBLIDXB1
):
385 case OE_RR_X0(TBLIDXB2
):
386 case OE_RR_Y0(TBLIDXB2
):
387 case OE_RR_X0(TBLIDXB3
):
388 case OE_RR_Y0(TBLIDXB3
):
391 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
394 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s", mnemonic
,
395 reg_names
[dest
], reg_names
[srca
]);
396 return TILEGX_EXCP_NONE
;
399 static TileExcp
gen_rrr_opcode(DisasContext
*dc
, unsigned opext
,
400 unsigned dest
, unsigned srca
, unsigned srcb
)
402 TCGv tdest
= dest_gr(dc
, dest
);
403 TCGv tsrca
= load_gr(dc
, srca
);
404 TCGv tsrcb
= load_gr(dc
, srcb
);
405 const char *mnemonic
;
408 case OE_RRR(ADDXSC
, 0, X0
):
409 case OE_RRR(ADDXSC
, 0, X1
):
410 gen_saturate_op(tdest
, tsrca
, tsrcb
, tcg_gen_add_tl
);
413 case OE_RRR(ADDX
, 0, X0
):
414 case OE_RRR(ADDX
, 0, X1
):
415 case OE_RRR(ADDX
, 0, Y0
):
416 case OE_RRR(ADDX
, 0, Y1
):
417 tcg_gen_add_tl(tdest
, tsrca
, tsrcb
);
418 tcg_gen_ext32s_tl(tdest
, tdest
);
421 case OE_RRR(ADD
, 0, X0
):
422 case OE_RRR(ADD
, 0, X1
):
423 case OE_RRR(ADD
, 0, Y0
):
424 case OE_RRR(ADD
, 0, Y1
):
425 tcg_gen_add_tl(tdest
, tsrca
, tsrcb
);
428 case OE_RRR(AND
, 0, X0
):
429 case OE_RRR(AND
, 0, X1
):
430 case OE_RRR(AND
, 5, Y0
):
431 case OE_RRR(AND
, 5, Y1
):
432 tcg_gen_and_tl(tdest
, tsrca
, tsrcb
);
435 case OE_RRR(CMOVEQZ
, 0, X0
):
436 case OE_RRR(CMOVEQZ
, 4, Y0
):
437 case OE_RRR(CMOVNEZ
, 0, X0
):
438 case OE_RRR(CMOVNEZ
, 4, Y0
):
439 case OE_RRR(CMPEQ
, 0, X0
):
440 case OE_RRR(CMPEQ
, 0, X1
):
441 case OE_RRR(CMPEQ
, 3, Y0
):
442 case OE_RRR(CMPEQ
, 3, Y1
):
443 case OE_RRR(CMPEXCH4
, 0, X1
):
444 case OE_RRR(CMPEXCH
, 0, X1
):
445 case OE_RRR(CMPLES
, 0, X0
):
446 case OE_RRR(CMPLES
, 0, X1
):
447 case OE_RRR(CMPLES
, 2, Y0
):
448 case OE_RRR(CMPLES
, 2, Y1
):
449 case OE_RRR(CMPLEU
, 0, X0
):
450 case OE_RRR(CMPLEU
, 0, X1
):
451 case OE_RRR(CMPLEU
, 2, Y0
):
452 case OE_RRR(CMPLEU
, 2, Y1
):
453 case OE_RRR(CMPLTS
, 0, X0
):
454 case OE_RRR(CMPLTS
, 0, X1
):
455 case OE_RRR(CMPLTS
, 2, Y0
):
456 case OE_RRR(CMPLTS
, 2, Y1
):
457 case OE_RRR(CMPLTU
, 0, X0
):
458 case OE_RRR(CMPLTU
, 0, X1
):
459 case OE_RRR(CMPLTU
, 2, Y0
):
460 case OE_RRR(CMPLTU
, 2, Y1
):
461 case OE_RRR(CMPNE
, 0, X0
):
462 case OE_RRR(CMPNE
, 0, X1
):
463 case OE_RRR(CMPNE
, 3, Y0
):
464 case OE_RRR(CMPNE
, 3, Y1
):
465 case OE_RRR(CMULAF
, 0, X0
):
466 case OE_RRR(CMULA
, 0, X0
):
467 case OE_RRR(CMULFR
, 0, X0
):
468 case OE_RRR(CMULF
, 0, X0
):
469 case OE_RRR(CMULHR
, 0, X0
):
470 case OE_RRR(CMULH
, 0, X0
):
471 case OE_RRR(CMUL
, 0, X0
):
472 case OE_RRR(CRC32_32
, 0, X0
):
473 case OE_RRR(CRC32_8
, 0, X0
):
474 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
475 case OE_RRR(DBLALIGN2
, 0, X0
):
476 case OE_RRR(DBLALIGN2
, 0, X1
):
477 gen_dblaligni(tdest
, tsrca
, tsrcb
, 16);
478 mnemonic
= "dblalign2";
480 case OE_RRR(DBLALIGN4
, 0, X0
):
481 case OE_RRR(DBLALIGN4
, 0, X1
):
482 gen_dblaligni(tdest
, tsrca
, tsrcb
, 32);
483 mnemonic
= "dblalign4";
485 case OE_RRR(DBLALIGN6
, 0, X0
):
486 case OE_RRR(DBLALIGN6
, 0, X1
):
487 gen_dblaligni(tdest
, tsrca
, tsrcb
, 48);
488 mnemonic
= "dblalign6";
490 case OE_RRR(DBLALIGN
, 0, X0
):
491 gen_dblalign(tdest
, load_gr(dc
, dest
), tsrca
, tsrcb
);
492 mnemonic
= "dblalign";
494 case OE_RRR(EXCH4
, 0, X1
):
495 case OE_RRR(EXCH
, 0, X1
):
496 case OE_RRR(FDOUBLE_ADDSUB
, 0, X0
):
497 case OE_RRR(FDOUBLE_ADD_FLAGS
, 0, X0
):
498 case OE_RRR(FDOUBLE_MUL_FLAGS
, 0, X0
):
499 case OE_RRR(FDOUBLE_PACK1
, 0, X0
):
500 case OE_RRR(FDOUBLE_PACK2
, 0, X0
):
501 case OE_RRR(FDOUBLE_SUB_FLAGS
, 0, X0
):
502 case OE_RRR(FDOUBLE_UNPACK_MAX
, 0, X0
):
503 case OE_RRR(FDOUBLE_UNPACK_MIN
, 0, X0
):
504 case OE_RRR(FETCHADD4
, 0, X1
):
505 case OE_RRR(FETCHADDGEZ4
, 0, X1
):
506 case OE_RRR(FETCHADDGEZ
, 0, X1
):
507 case OE_RRR(FETCHADD
, 0, X1
):
508 case OE_RRR(FETCHAND4
, 0, X1
):
509 case OE_RRR(FETCHAND
, 0, X1
):
510 case OE_RRR(FETCHOR4
, 0, X1
):
511 case OE_RRR(FETCHOR
, 0, X1
):
512 case OE_RRR(FSINGLE_ADD1
, 0, X0
):
513 case OE_RRR(FSINGLE_ADDSUB2
, 0, X0
):
514 case OE_RRR(FSINGLE_MUL1
, 0, X0
):
515 case OE_RRR(FSINGLE_MUL2
, 0, X0
):
516 case OE_RRR(FSINGLE_PACK2
, 0, X0
):
517 case OE_RRR(FSINGLE_SUB1
, 0, X0
):
518 case OE_RRR(MNZ
, 0, X0
):
519 case OE_RRR(MNZ
, 0, X1
):
520 case OE_RRR(MNZ
, 4, Y0
):
521 case OE_RRR(MNZ
, 4, Y1
):
522 case OE_RRR(MULAX
, 0, X0
):
523 case OE_RRR(MULAX
, 3, Y0
):
524 case OE_RRR(MULA_HS_HS
, 0, X0
):
525 case OE_RRR(MULA_HS_HS
, 9, Y0
):
526 case OE_RRR(MULA_HS_HU
, 0, X0
):
527 case OE_RRR(MULA_HS_LS
, 0, X0
):
528 case OE_RRR(MULA_HS_LU
, 0, X0
):
529 case OE_RRR(MULA_HU_HU
, 0, X0
):
530 case OE_RRR(MULA_HU_HU
, 9, Y0
):
531 case OE_RRR(MULA_HU_LS
, 0, X0
):
532 case OE_RRR(MULA_HU_LU
, 0, X0
):
533 case OE_RRR(MULA_LS_LS
, 0, X0
):
534 case OE_RRR(MULA_LS_LS
, 9, Y0
):
535 case OE_RRR(MULA_LS_LU
, 0, X0
):
536 case OE_RRR(MULA_LU_LU
, 0, X0
):
537 case OE_RRR(MULA_LU_LU
, 9, Y0
):
538 case OE_RRR(MULX
, 0, X0
):
539 case OE_RRR(MULX
, 3, Y0
):
540 case OE_RRR(MUL_HS_HS
, 0, X0
):
541 case OE_RRR(MUL_HS_HS
, 8, Y0
):
542 case OE_RRR(MUL_HS_HU
, 0, X0
):
543 case OE_RRR(MUL_HS_LS
, 0, X0
):
544 case OE_RRR(MUL_HS_LU
, 0, X0
):
545 case OE_RRR(MUL_HU_HU
, 0, X0
):
546 case OE_RRR(MUL_HU_HU
, 8, Y0
):
547 case OE_RRR(MUL_HU_LS
, 0, X0
):
548 case OE_RRR(MUL_HU_LU
, 0, X0
):
549 case OE_RRR(MUL_LS_LS
, 0, X0
):
550 case OE_RRR(MUL_LS_LS
, 8, Y0
):
551 case OE_RRR(MUL_LS_LU
, 0, X0
):
552 case OE_RRR(MUL_LU_LU
, 0, X0
):
553 case OE_RRR(MUL_LU_LU
, 8, Y0
):
554 case OE_RRR(MZ
, 0, X0
):
555 case OE_RRR(MZ
, 0, X1
):
556 case OE_RRR(MZ
, 4, Y0
):
557 case OE_RRR(MZ
, 4, Y1
):
558 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
559 case OE_RRR(NOR
, 0, X0
):
560 case OE_RRR(NOR
, 0, X1
):
561 case OE_RRR(NOR
, 5, Y0
):
562 case OE_RRR(NOR
, 5, Y1
):
563 tcg_gen_nor_tl(tdest
, tsrca
, tsrcb
);
566 case OE_RRR(OR
, 0, X0
):
567 case OE_RRR(OR
, 0, X1
):
568 case OE_RRR(OR
, 5, Y0
):
569 case OE_RRR(OR
, 5, Y1
):
570 tcg_gen_or_tl(tdest
, tsrca
, tsrcb
);
573 case OE_RRR(ROTL
, 0, X0
):
574 case OE_RRR(ROTL
, 0, X1
):
575 case OE_RRR(ROTL
, 6, Y0
):
576 case OE_RRR(ROTL
, 6, Y1
):
577 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
578 case OE_RRR(SHL1ADDX
, 0, X0
):
579 case OE_RRR(SHL1ADDX
, 0, X1
):
580 case OE_RRR(SHL1ADDX
, 7, Y0
):
581 case OE_RRR(SHL1ADDX
, 7, Y1
):
582 tcg_gen_shli_tl(tdest
, tsrca
, 1);
583 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
584 tcg_gen_ext32s_tl(tdest
, tdest
);
585 mnemonic
= "shl1addx";
587 case OE_RRR(SHL1ADD
, 0, X0
):
588 case OE_RRR(SHL1ADD
, 0, X1
):
589 case OE_RRR(SHL1ADD
, 1, Y0
):
590 case OE_RRR(SHL1ADD
, 1, Y1
):
591 tcg_gen_shli_tl(tdest
, tsrca
, 1);
592 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
593 mnemonic
= "shl1add";
595 case OE_RRR(SHL2ADDX
, 0, X0
):
596 case OE_RRR(SHL2ADDX
, 0, X1
):
597 case OE_RRR(SHL2ADDX
, 7, Y0
):
598 case OE_RRR(SHL2ADDX
, 7, Y1
):
599 tcg_gen_shli_tl(tdest
, tsrca
, 2);
600 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
601 tcg_gen_ext32s_tl(tdest
, tdest
);
602 mnemonic
= "shl2addx";
604 case OE_RRR(SHL2ADD
, 0, X0
):
605 case OE_RRR(SHL2ADD
, 0, X1
):
606 case OE_RRR(SHL2ADD
, 1, Y0
):
607 case OE_RRR(SHL2ADD
, 1, Y1
):
608 tcg_gen_shli_tl(tdest
, tsrca
, 2);
609 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
610 mnemonic
= "shl2add";
612 case OE_RRR(SHL3ADDX
, 0, X0
):
613 case OE_RRR(SHL3ADDX
, 0, X1
):
614 case OE_RRR(SHL3ADDX
, 7, Y0
):
615 case OE_RRR(SHL3ADDX
, 7, Y1
):
616 tcg_gen_shli_tl(tdest
, tsrca
, 3);
617 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
618 tcg_gen_ext32s_tl(tdest
, tdest
);
619 mnemonic
= "shl3addx";
621 case OE_RRR(SHL3ADD
, 0, X0
):
622 case OE_RRR(SHL3ADD
, 0, X1
):
623 case OE_RRR(SHL3ADD
, 1, Y0
):
624 case OE_RRR(SHL3ADD
, 1, Y1
):
625 tcg_gen_shli_tl(tdest
, tsrca
, 3);
626 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
627 mnemonic
= "shl3add";
629 case OE_RRR(SHLX
, 0, X0
):
630 case OE_RRR(SHLX
, 0, X1
):
631 case OE_RRR(SHL
, 0, X0
):
632 case OE_RRR(SHL
, 0, X1
):
633 case OE_RRR(SHL
, 6, Y0
):
634 case OE_RRR(SHL
, 6, Y1
):
635 case OE_RRR(SHRS
, 0, X0
):
636 case OE_RRR(SHRS
, 0, X1
):
637 case OE_RRR(SHRS
, 6, Y0
):
638 case OE_RRR(SHRS
, 6, Y1
):
639 case OE_RRR(SHRUX
, 0, X0
):
640 case OE_RRR(SHRUX
, 0, X1
):
641 case OE_RRR(SHRU
, 0, X0
):
642 case OE_RRR(SHRU
, 0, X1
):
643 case OE_RRR(SHRU
, 6, Y0
):
644 case OE_RRR(SHRU
, 6, Y1
):
645 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
646 case OE_RRR(SHUFFLEBYTES
, 0, X0
):
647 gen_helper_shufflebytes(tdest
, load_gr(dc
, dest
), tsrca
, tsrca
);
648 mnemonic
= "shufflebytes";
650 case OE_RRR(SUBXSC
, 0, X0
):
651 case OE_RRR(SUBXSC
, 0, X1
):
652 gen_saturate_op(tdest
, tsrca
, tsrcb
, tcg_gen_sub_tl
);
655 case OE_RRR(SUBX
, 0, X0
):
656 case OE_RRR(SUBX
, 0, X1
):
657 case OE_RRR(SUBX
, 0, Y0
):
658 case OE_RRR(SUBX
, 0, Y1
):
659 tcg_gen_sub_tl(tdest
, tsrca
, tsrcb
);
660 tcg_gen_ext32s_tl(tdest
, tdest
);
663 case OE_RRR(SUB
, 0, X0
):
664 case OE_RRR(SUB
, 0, X1
):
665 case OE_RRR(SUB
, 0, Y0
):
666 case OE_RRR(SUB
, 0, Y1
):
667 tcg_gen_sub_tl(tdest
, tsrca
, tsrcb
);
670 case OE_RRR(V1ADDUC
, 0, X0
):
671 case OE_RRR(V1ADDUC
, 0, X1
):
672 case OE_RRR(V1ADD
, 0, X0
):
673 case OE_RRR(V1ADD
, 0, X1
):
674 case OE_RRR(V1ADIFFU
, 0, X0
):
675 case OE_RRR(V1AVGU
, 0, X0
):
676 case OE_RRR(V1CMPEQ
, 0, X0
):
677 case OE_RRR(V1CMPEQ
, 0, X1
):
678 case OE_RRR(V1CMPLES
, 0, X0
):
679 case OE_RRR(V1CMPLES
, 0, X1
):
680 case OE_RRR(V1CMPLEU
, 0, X0
):
681 case OE_RRR(V1CMPLEU
, 0, X1
):
682 case OE_RRR(V1CMPLTS
, 0, X0
):
683 case OE_RRR(V1CMPLTS
, 0, X1
):
684 case OE_RRR(V1CMPLTU
, 0, X0
):
685 case OE_RRR(V1CMPLTU
, 0, X1
):
686 case OE_RRR(V1CMPNE
, 0, X0
):
687 case OE_RRR(V1CMPNE
, 0, X1
):
688 case OE_RRR(V1DDOTPUA
, 0, X0
):
689 case OE_RRR(V1DDOTPUSA
, 0, X0
):
690 case OE_RRR(V1DDOTPUS
, 0, X0
):
691 case OE_RRR(V1DDOTPU
, 0, X0
):
692 case OE_RRR(V1DOTPA
, 0, X0
):
693 case OE_RRR(V1DOTPUA
, 0, X0
):
694 case OE_RRR(V1DOTPUSA
, 0, X0
):
695 case OE_RRR(V1DOTPUS
, 0, X0
):
696 case OE_RRR(V1DOTPU
, 0, X0
):
697 case OE_RRR(V1DOTP
, 0, X0
):
698 case OE_RRR(V1INT_H
, 0, X0
):
699 case OE_RRR(V1INT_H
, 0, X1
):
700 case OE_RRR(V1INT_L
, 0, X0
):
701 case OE_RRR(V1INT_L
, 0, X1
):
702 case OE_RRR(V1MAXU
, 0, X0
):
703 case OE_RRR(V1MAXU
, 0, X1
):
704 case OE_RRR(V1MINU
, 0, X0
):
705 case OE_RRR(V1MINU
, 0, X1
):
706 case OE_RRR(V1MNZ
, 0, X0
):
707 case OE_RRR(V1MNZ
, 0, X1
):
708 case OE_RRR(V1MULTU
, 0, X0
):
709 case OE_RRR(V1MULUS
, 0, X0
):
710 case OE_RRR(V1MULU
, 0, X0
):
711 case OE_RRR(V1MZ
, 0, X0
):
712 case OE_RRR(V1MZ
, 0, X1
):
713 case OE_RRR(V1SADAU
, 0, X0
):
714 case OE_RRR(V1SADU
, 0, X0
):
715 case OE_RRR(V1SHL
, 0, X0
):
716 case OE_RRR(V1SHL
, 0, X1
):
717 case OE_RRR(V1SHRS
, 0, X0
):
718 case OE_RRR(V1SHRS
, 0, X1
):
719 case OE_RRR(V1SHRU
, 0, X0
):
720 case OE_RRR(V1SHRU
, 0, X1
):
721 case OE_RRR(V1SUBUC
, 0, X0
):
722 case OE_RRR(V1SUBUC
, 0, X1
):
723 case OE_RRR(V1SUB
, 0, X0
):
724 case OE_RRR(V1SUB
, 0, X1
):
725 case OE_RRR(V2ADDSC
, 0, X0
):
726 case OE_RRR(V2ADDSC
, 0, X1
):
727 case OE_RRR(V2ADD
, 0, X0
):
728 case OE_RRR(V2ADD
, 0, X1
):
729 case OE_RRR(V2ADIFFS
, 0, X0
):
730 case OE_RRR(V2AVGS
, 0, X0
):
731 case OE_RRR(V2CMPEQ
, 0, X0
):
732 case OE_RRR(V2CMPEQ
, 0, X1
):
733 case OE_RRR(V2CMPLES
, 0, X0
):
734 case OE_RRR(V2CMPLES
, 0, X1
):
735 case OE_RRR(V2CMPLEU
, 0, X0
):
736 case OE_RRR(V2CMPLEU
, 0, X1
):
737 case OE_RRR(V2CMPLTS
, 0, X0
):
738 case OE_RRR(V2CMPLTS
, 0, X1
):
739 case OE_RRR(V2CMPLTU
, 0, X0
):
740 case OE_RRR(V2CMPLTU
, 0, X1
):
741 case OE_RRR(V2CMPNE
, 0, X0
):
742 case OE_RRR(V2CMPNE
, 0, X1
):
743 case OE_RRR(V2DOTPA
, 0, X0
):
744 case OE_RRR(V2DOTP
, 0, X0
):
745 case OE_RRR(V2INT_H
, 0, X0
):
746 case OE_RRR(V2INT_H
, 0, X1
):
747 case OE_RRR(V2INT_L
, 0, X0
):
748 case OE_RRR(V2INT_L
, 0, X1
):
749 case OE_RRR(V2MAXS
, 0, X0
):
750 case OE_RRR(V2MAXS
, 0, X1
):
751 case OE_RRR(V2MINS
, 0, X0
):
752 case OE_RRR(V2MINS
, 0, X1
):
753 case OE_RRR(V2MNZ
, 0, X0
):
754 case OE_RRR(V2MNZ
, 0, X1
):
755 case OE_RRR(V2MULFSC
, 0, X0
):
756 case OE_RRR(V2MULS
, 0, X0
):
757 case OE_RRR(V2MULTS
, 0, X0
):
758 case OE_RRR(V2MZ
, 0, X0
):
759 case OE_RRR(V2MZ
, 0, X1
):
760 case OE_RRR(V2PACKH
, 0, X0
):
761 case OE_RRR(V2PACKH
, 0, X1
):
762 case OE_RRR(V2PACKL
, 0, X0
):
763 case OE_RRR(V2PACKL
, 0, X1
):
764 case OE_RRR(V2PACKUC
, 0, X0
):
765 case OE_RRR(V2PACKUC
, 0, X1
):
766 case OE_RRR(V2SADAS
, 0, X0
):
767 case OE_RRR(V2SADAU
, 0, X0
):
768 case OE_RRR(V2SADS
, 0, X0
):
769 case OE_RRR(V2SADU
, 0, X0
):
770 case OE_RRR(V2SHLSC
, 0, X0
):
771 case OE_RRR(V2SHLSC
, 0, X1
):
772 case OE_RRR(V2SHL
, 0, X0
):
773 case OE_RRR(V2SHL
, 0, X1
):
774 case OE_RRR(V2SHRS
, 0, X0
):
775 case OE_RRR(V2SHRS
, 0, X1
):
776 case OE_RRR(V2SHRU
, 0, X0
):
777 case OE_RRR(V2SHRU
, 0, X1
):
778 case OE_RRR(V2SUBSC
, 0, X0
):
779 case OE_RRR(V2SUBSC
, 0, X1
):
780 case OE_RRR(V2SUB
, 0, X0
):
781 case OE_RRR(V2SUB
, 0, X1
):
782 case OE_RRR(V4ADDSC
, 0, X0
):
783 case OE_RRR(V4ADDSC
, 0, X1
):
784 case OE_RRR(V4ADD
, 0, X0
):
785 case OE_RRR(V4ADD
, 0, X1
):
786 case OE_RRR(V4INT_H
, 0, X0
):
787 case OE_RRR(V4INT_H
, 0, X1
):
788 case OE_RRR(V4INT_L
, 0, X0
):
789 case OE_RRR(V4INT_L
, 0, X1
):
790 case OE_RRR(V4PACKSC
, 0, X0
):
791 case OE_RRR(V4PACKSC
, 0, X1
):
792 case OE_RRR(V4SHLSC
, 0, X0
):
793 case OE_RRR(V4SHLSC
, 0, X1
):
794 case OE_RRR(V4SHL
, 0, X0
):
795 case OE_RRR(V4SHL
, 0, X1
):
796 case OE_RRR(V4SHRS
, 0, X0
):
797 case OE_RRR(V4SHRS
, 0, X1
):
798 case OE_RRR(V4SHRU
, 0, X0
):
799 case OE_RRR(V4SHRU
, 0, X1
):
800 case OE_RRR(V4SUBSC
, 0, X0
):
801 case OE_RRR(V4SUBSC
, 0, X1
):
802 case OE_RRR(V4SUB
, 0, X0
):
803 case OE_RRR(V4SUB
, 0, X1
):
804 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
805 case OE_RRR(XOR
, 0, X0
):
806 case OE_RRR(XOR
, 0, X1
):
807 case OE_RRR(XOR
, 5, Y0
):
808 case OE_RRR(XOR
, 5, Y1
):
809 tcg_gen_xor_tl(tdest
, tsrca
, tsrcb
);
813 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
816 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %s", mnemonic
,
817 reg_names
[dest
], reg_names
[srca
], reg_names
[srcb
]);
818 return TILEGX_EXCP_NONE
;
821 static TileExcp
gen_rri_opcode(DisasContext
*dc
, unsigned opext
,
822 unsigned dest
, unsigned srca
, int imm
)
824 TCGv tdest
= dest_gr(dc
, dest
);
825 TCGv tsrca
= load_gr(dc
, srca
);
826 const char *mnemonic
;
829 case OE(ADDI_OPCODE_Y0
, 0, Y0
):
830 case OE(ADDI_OPCODE_Y1
, 0, Y1
):
831 case OE_IM(ADDI
, X0
):
832 case OE_IM(ADDI
, X1
):
833 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
836 case OE(ADDXI_OPCODE_Y0
, 0, Y0
):
837 case OE(ADDXI_OPCODE_Y1
, 0, Y1
):
838 case OE_IM(ADDXI
, X0
):
839 case OE_IM(ADDXI
, X1
):
840 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
841 tcg_gen_ext32s_tl(tdest
, tdest
);
844 case OE(ANDI_OPCODE_Y0
, 0, Y0
):
845 case OE(ANDI_OPCODE_Y1
, 0, Y1
):
846 case OE_IM(ANDI
, X0
):
847 case OE_IM(ANDI
, X1
):
848 tcg_gen_andi_tl(tdest
, tsrca
, imm
);
851 case OE_IM(CMPEQI
, X0
):
852 case OE_IM(CMPEQI
, X1
):
853 case OE_IM(CMPLTSI
, X0
):
854 case OE_IM(CMPLTSI
, X1
):
855 case OE_IM(CMPLTUI
, X0
):
856 case OE_IM(CMPLTUI
, X1
):
857 case OE_IM(LD1S_ADD
, X1
):
858 case OE_IM(LD1U_ADD
, X1
):
859 case OE_IM(LD2S_ADD
, X1
):
860 case OE_IM(LD2U_ADD
, X1
):
861 case OE_IM(LD4S_ADD
, X1
):
862 case OE_IM(LD4U_ADD
, X1
):
863 case OE_IM(LDNT1S_ADD
, X1
):
864 case OE_IM(LDNT1U_ADD
, X1
):
865 case OE_IM(LDNT2S_ADD
, X1
):
866 case OE_IM(LDNT2U_ADD
, X1
):
867 case OE_IM(LDNT4S_ADD
, X1
):
868 case OE_IM(LDNT4U_ADD
, X1
):
869 case OE_IM(LDNT_ADD
, X1
):
870 case OE_IM(LD_ADD
, X1
):
871 case OE_IM(LDNA_ADD
, X1
):
872 case OE_IM(MFSPR
, X1
):
873 case OE_IM(MTSPR
, X1
):
874 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
877 tcg_gen_ori_tl(tdest
, tsrca
, imm
);
880 case OE_IM(ST1_ADD
, X1
):
881 case OE_IM(ST2_ADD
, X1
):
882 case OE_IM(ST4_ADD
, X1
):
883 case OE_IM(STNT1_ADD
, X1
):
884 case OE_IM(STNT2_ADD
, X1
):
885 case OE_IM(STNT4_ADD
, X1
):
886 case OE_IM(STNT_ADD
, X1
):
887 case OE_IM(ST_ADD
, X1
):
888 case OE_IM(V1ADDI
, X0
):
889 case OE_IM(V1ADDI
, X1
):
890 case OE_IM(V1CMPEQI
, X0
):
891 case OE_IM(V1CMPEQI
, X1
):
892 case OE_IM(V1CMPLTSI
, X0
):
893 case OE_IM(V1CMPLTSI
, X1
):
894 case OE_IM(V1CMPLTUI
, X0
):
895 case OE_IM(V1CMPLTUI
, X1
):
896 case OE_IM(V1MAXUI
, X0
):
897 case OE_IM(V1MAXUI
, X1
):
898 case OE_IM(V1MINUI
, X0
):
899 case OE_IM(V1MINUI
, X1
):
900 case OE_IM(V2ADDI
, X0
):
901 case OE_IM(V2ADDI
, X1
):
902 case OE_IM(V2CMPEQI
, X0
):
903 case OE_IM(V2CMPEQI
, X1
):
904 case OE_IM(V2CMPLTSI
, X0
):
905 case OE_IM(V2CMPLTSI
, X1
):
906 case OE_IM(V2CMPLTUI
, X0
):
907 case OE_IM(V2CMPLTUI
, X1
):
908 case OE_IM(V2MAXSI
, X0
):
909 case OE_IM(V2MAXSI
, X1
):
910 case OE_IM(V2MINSI
, X0
):
911 case OE_IM(V2MINSI
, X1
):
912 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
913 case OE_IM(XORI
, X0
):
914 case OE_IM(XORI
, X1
):
915 tcg_gen_xori_tl(tdest
, tsrca
, imm
);
919 case OE_SH(ROTLI
, X0
):
920 case OE_SH(ROTLI
, X1
):
921 case OE_SH(ROTLI
, Y0
):
922 case OE_SH(ROTLI
, Y1
):
923 case OE_SH(SHLI
, X0
):
924 case OE_SH(SHLI
, X1
):
925 case OE_SH(SHLI
, Y0
):
926 case OE_SH(SHLI
, Y1
):
927 case OE_SH(SHLXI
, X0
):
928 case OE_SH(SHLXI
, X1
):
929 case OE_SH(SHRSI
, X0
):
930 case OE_SH(SHRSI
, X1
):
931 case OE_SH(SHRSI
, Y0
):
932 case OE_SH(SHRSI
, Y1
):
933 case OE_SH(SHRUI
, X0
):
934 case OE_SH(SHRUI
, X1
):
935 case OE_SH(SHRUI
, Y0
):
936 case OE_SH(SHRUI
, Y1
):
937 case OE_SH(SHRUXI
, X0
):
938 case OE_SH(SHRUXI
, X1
):
939 case OE_SH(V1SHLI
, X0
):
940 case OE_SH(V1SHLI
, X1
):
941 case OE_SH(V1SHRSI
, X0
):
942 case OE_SH(V1SHRSI
, X1
):
943 case OE_SH(V1SHRUI
, X0
):
944 case OE_SH(V1SHRUI
, X1
):
945 case OE_SH(V2SHLI
, X0
):
946 case OE_SH(V2SHLI
, X1
):
947 case OE_SH(V2SHRSI
, X0
):
948 case OE_SH(V2SHRSI
, X1
):
949 case OE_SH(V2SHRUI
, X0
):
950 case OE_SH(V2SHRUI
, X1
):
951 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
953 case OE(ADDLI_OPCODE_X0
, 0, X0
):
954 case OE(ADDLI_OPCODE_X1
, 0, X1
):
955 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
958 case OE(ADDXLI_OPCODE_X0
, 0, X0
):
959 case OE(ADDXLI_OPCODE_X1
, 0, X1
):
960 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
961 tcg_gen_ext32s_tl(tdest
, tdest
);
964 case OE(CMPEQI_OPCODE_Y0
, 0, Y0
):
965 case OE(CMPEQI_OPCODE_Y1
, 0, Y1
):
966 case OE(CMPLTSI_OPCODE_Y0
, 0, Y0
):
967 case OE(CMPLTSI_OPCODE_Y1
, 0, Y1
):
968 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
969 case OE(SHL16INSLI_OPCODE_X0
, 0, X0
):
970 case OE(SHL16INSLI_OPCODE_X1
, 0, X1
):
971 tcg_gen_shli_tl(tdest
, tsrca
, 16);
972 tcg_gen_ori_tl(tdest
, tdest
, imm
& 0xffff);
973 mnemonic
= "shl16insli";
977 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
980 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %d", mnemonic
,
981 reg_names
[dest
], reg_names
[srca
], imm
);
982 return TILEGX_EXCP_NONE
;
985 static TileExcp
gen_bf_opcode_x0(DisasContext
*dc
, unsigned ext
,
986 unsigned dest
, unsigned srca
,
987 unsigned bfs
, unsigned bfe
)
989 const char *mnemonic
;
992 case BFEXTU_BF_OPCODE_X0
:
993 case BFEXTS_BF_OPCODE_X0
:
994 case BFINS_BF_OPCODE_X0
:
995 case MM_BF_OPCODE_X0
:
997 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1000 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %u, %u", mnemonic
,
1001 reg_names
[dest
], reg_names
[srca
], bfs
, bfe
);
1002 return TILEGX_EXCP_NONE
;
1005 static TileExcp
gen_branch_opcode_x1(DisasContext
*dc
, unsigned ext
,
1006 unsigned srca
, int off
)
1008 target_ulong tgt
= dc
->pc
+ off
* TILEGX_BUNDLE_SIZE_IN_BYTES
;
1009 const char *mnemonic
;
1012 case BEQZT_BRANCH_OPCODE_X1
:
1013 case BEQZ_BRANCH_OPCODE_X1
:
1014 case BNEZT_BRANCH_OPCODE_X1
:
1015 case BNEZ_BRANCH_OPCODE_X1
:
1016 case BLBC_BRANCH_OPCODE_X1
:
1017 case BGEZT_BRANCH_OPCODE_X1
:
1018 case BGEZ_BRANCH_OPCODE_X1
:
1019 case BGTZT_BRANCH_OPCODE_X1
:
1020 case BGTZ_BRANCH_OPCODE_X1
:
1021 case BLBCT_BRANCH_OPCODE_X1
:
1022 case BLBST_BRANCH_OPCODE_X1
:
1023 case BLBS_BRANCH_OPCODE_X1
:
1024 case BLEZT_BRANCH_OPCODE_X1
:
1025 case BLEZ_BRANCH_OPCODE_X1
:
1026 case BLTZT_BRANCH_OPCODE_X1
:
1027 case BLTZ_BRANCH_OPCODE_X1
:
1029 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1032 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1033 qemu_log("%s %s, " TARGET_FMT_lx
" <%s>",
1034 mnemonic
, reg_names
[srca
], tgt
, lookup_symbol(tgt
));
1036 return TILEGX_EXCP_NONE
;
1039 static TileExcp
gen_jump_opcode_x1(DisasContext
*dc
, unsigned ext
,
1042 target_ulong tgt
= dc
->pc
+ off
* TILEGX_BUNDLE_SIZE_IN_BYTES
;
1043 const char *mnemonic
;
1046 case JAL_JUMP_OPCODE_X1
:
1047 case J_JUMP_OPCODE_X1
:
1049 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1052 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1053 qemu_log("%s " TARGET_FMT_lx
" <%s>",
1054 mnemonic
, tgt
, lookup_symbol(tgt
));
1056 return TILEGX_EXCP_NONE
;
1059 static TileExcp
decode_y0(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1061 unsigned opc
= get_Opcode_Y0(bundle
);
1062 unsigned ext
= get_RRROpcodeExtension_Y0(bundle
);
1063 unsigned dest
= get_Dest_Y0(bundle
);
1064 unsigned srca
= get_SrcA_Y0(bundle
);
1069 case RRR_1_OPCODE_Y0
:
1070 if (ext
== UNARY_RRR_1_OPCODE_Y0
) {
1071 ext
= get_UnaryOpcodeExtension_Y0(bundle
);
1072 return gen_rr_opcode(dc
, OE(opc
, ext
, Y0
), dest
, srca
);
1075 case RRR_0_OPCODE_Y0
:
1076 case RRR_2_OPCODE_Y0
:
1077 case RRR_3_OPCODE_Y0
:
1078 case RRR_4_OPCODE_Y0
:
1079 case RRR_5_OPCODE_Y0
:
1080 case RRR_6_OPCODE_Y0
:
1081 case RRR_7_OPCODE_Y0
:
1082 case RRR_8_OPCODE_Y0
:
1083 case RRR_9_OPCODE_Y0
:
1084 srcb
= get_SrcB_Y0(bundle
);
1085 return gen_rrr_opcode(dc
, OE(opc
, ext
, Y0
), dest
, srca
, srcb
);
1087 case SHIFT_OPCODE_Y0
:
1088 ext
= get_ShiftOpcodeExtension_Y0(bundle
);
1089 imm
= get_ShAmt_Y0(bundle
);
1090 return gen_rri_opcode(dc
, OE(opc
, ext
, Y0
), dest
, srca
, imm
);
1092 case ADDI_OPCODE_Y0
:
1093 case ADDXI_OPCODE_Y0
:
1094 case ANDI_OPCODE_Y0
:
1095 case CMPEQI_OPCODE_Y0
:
1096 case CMPLTSI_OPCODE_Y0
:
1097 imm
= (int8_t)get_Imm8_Y0(bundle
);
1098 return gen_rri_opcode(dc
, OE(opc
, 0, Y0
), dest
, srca
, imm
);
1101 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1105 static TileExcp
decode_y1(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1107 unsigned opc
= get_Opcode_Y1(bundle
);
1108 unsigned ext
= get_RRROpcodeExtension_Y1(bundle
);
1109 unsigned dest
= get_Dest_Y1(bundle
);
1110 unsigned srca
= get_SrcA_Y1(bundle
);
1114 switch (get_Opcode_Y1(bundle
)) {
1115 case RRR_1_OPCODE_Y1
:
1116 if (ext
== UNARY_RRR_1_OPCODE_Y0
) {
1117 ext
= get_UnaryOpcodeExtension_Y1(bundle
);
1118 return gen_rr_opcode(dc
, OE(opc
, ext
, Y1
), dest
, srca
);
1121 case RRR_0_OPCODE_Y1
:
1122 case RRR_2_OPCODE_Y1
:
1123 case RRR_3_OPCODE_Y1
:
1124 case RRR_4_OPCODE_Y1
:
1125 case RRR_5_OPCODE_Y1
:
1126 case RRR_6_OPCODE_Y1
:
1127 case RRR_7_OPCODE_Y1
:
1128 srcb
= get_SrcB_Y1(bundle
);
1129 return gen_rrr_opcode(dc
, OE(opc
, ext
, Y1
), dest
, srca
, srcb
);
1131 case SHIFT_OPCODE_Y1
:
1132 ext
= get_ShiftOpcodeExtension_Y1(bundle
);
1133 imm
= get_ShAmt_Y1(bundle
);
1134 return gen_rri_opcode(dc
, OE(opc
, ext
, Y1
), dest
, srca
, imm
);
1136 case ADDI_OPCODE_Y1
:
1137 case ADDXI_OPCODE_Y1
:
1138 case ANDI_OPCODE_Y1
:
1139 case CMPEQI_OPCODE_Y1
:
1140 case CMPLTSI_OPCODE_Y1
:
1141 imm
= (int8_t)get_Imm8_Y1(bundle
);
1142 return gen_rri_opcode(dc
, OE(opc
, 0, Y1
), dest
, srca
, imm
);
1145 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1149 static TileExcp
decode_y2(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1151 unsigned mode
= get_Mode(bundle
);
1152 unsigned opc
= get_Opcode_Y2(bundle
);
1153 unsigned srca
= get_SrcA_Y2(bundle
);
1154 unsigned srcbdest
= get_SrcBDest_Y2(bundle
);
1155 const char *mnemonic
;
1158 switch (OEY2(opc
, mode
)) {
1159 case OEY2(LD1S_OPCODE_Y2
, MODE_OPCODE_YA2
):
1163 case OEY2(LD1U_OPCODE_Y2
, MODE_OPCODE_YA2
):
1167 case OEY2(LD2S_OPCODE_Y2
, MODE_OPCODE_YA2
):
1171 case OEY2(LD2U_OPCODE_Y2
, MODE_OPCODE_YA2
):
1175 case OEY2(LD4S_OPCODE_Y2
, MODE_OPCODE_YB2
):
1179 case OEY2(LD4U_OPCODE_Y2
, MODE_OPCODE_YB2
):
1183 case OEY2(LD_OPCODE_Y2
, MODE_OPCODE_YB2
):
1187 tcg_gen_qemu_ld_tl(dest_gr(dc
, srcbdest
), load_gr(dc
, srca
),
1189 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s", mnemonic
,
1190 reg_names
[srcbdest
], reg_names
[srca
]);
1191 return TILEGX_EXCP_NONE
;
1193 case OEY2(ST1_OPCODE_Y2
, MODE_OPCODE_YC2
):
1194 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_UB
, "st1");
1195 case OEY2(ST2_OPCODE_Y2
, MODE_OPCODE_YC2
):
1196 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_TEUW
, "st2");
1197 case OEY2(ST4_OPCODE_Y2
, MODE_OPCODE_YC2
):
1198 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_TEUL
, "st4");
1199 case OEY2(ST_OPCODE_Y2
, MODE_OPCODE_YC2
):
1200 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_TEQ
, "st");
1203 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1207 static TileExcp
decode_x0(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1209 unsigned opc
= get_Opcode_X0(bundle
);
1210 unsigned dest
= get_Dest_X0(bundle
);
1211 unsigned srca
= get_SrcA_X0(bundle
);
1212 unsigned ext
, srcb
, bfs
, bfe
;
1216 case RRR_0_OPCODE_X0
:
1217 ext
= get_RRROpcodeExtension_X0(bundle
);
1218 if (ext
== UNARY_RRR_0_OPCODE_X0
) {
1219 ext
= get_UnaryOpcodeExtension_X0(bundle
);
1220 return gen_rr_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
);
1222 srcb
= get_SrcB_X0(bundle
);
1223 return gen_rrr_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
, srcb
);
1225 case SHIFT_OPCODE_X0
:
1226 ext
= get_ShiftOpcodeExtension_X0(bundle
);
1227 imm
= get_ShAmt_X0(bundle
);
1228 return gen_rri_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
, imm
);
1230 case IMM8_OPCODE_X0
:
1231 ext
= get_Imm8OpcodeExtension_X0(bundle
);
1232 imm
= (int8_t)get_Imm8_X0(bundle
);
1233 return gen_rri_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
, imm
);
1236 ext
= get_BFOpcodeExtension_X0(bundle
);
1237 bfs
= get_BFStart_X0(bundle
);
1238 bfe
= get_BFEnd_X0(bundle
);
1239 return gen_bf_opcode_x0(dc
, ext
, dest
, srca
, bfs
, bfe
);
1241 case ADDLI_OPCODE_X0
:
1242 case SHL16INSLI_OPCODE_X0
:
1243 case ADDXLI_OPCODE_X0
:
1244 imm
= (int16_t)get_Imm16_X0(bundle
);
1245 return gen_rri_opcode(dc
, OE(opc
, 0, X0
), dest
, srca
, imm
);
1248 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1252 static TileExcp
decode_x1(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1254 unsigned opc
= get_Opcode_X1(bundle
);
1255 unsigned dest
= get_Dest_X1(bundle
);
1256 unsigned srca
= get_SrcA_X1(bundle
);
1261 case RRR_0_OPCODE_X1
:
1262 ext
= get_RRROpcodeExtension_X1(bundle
);
1263 srcb
= get_SrcB_X1(bundle
);
1265 case UNARY_RRR_0_OPCODE_X1
:
1266 ext
= get_UnaryOpcodeExtension_X1(bundle
);
1267 return gen_rr_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
);
1268 case ST1_RRR_0_OPCODE_X1
:
1269 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_UB
, "st1");
1270 case ST2_RRR_0_OPCODE_X1
:
1271 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUW
, "st2");
1272 case ST4_RRR_0_OPCODE_X1
:
1273 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUL
, "st4");
1274 case STNT1_RRR_0_OPCODE_X1
:
1275 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_UB
, "stnt1");
1276 case STNT2_RRR_0_OPCODE_X1
:
1277 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUW
, "stnt2");
1278 case STNT4_RRR_0_OPCODE_X1
:
1279 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUL
, "stnt4");
1280 case STNT_RRR_0_OPCODE_X1
:
1281 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEQ
, "stnt");
1282 case ST_RRR_0_OPCODE_X1
:
1283 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEQ
, "st");
1285 return gen_rrr_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
, srcb
);
1287 case SHIFT_OPCODE_X1
:
1288 ext
= get_ShiftOpcodeExtension_X1(bundle
);
1289 imm
= get_ShAmt_X1(bundle
);
1290 return gen_rri_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
, imm
);
1292 case IMM8_OPCODE_X1
:
1293 ext
= get_Imm8OpcodeExtension_X1(bundle
);
1294 imm
= (int8_t)get_Imm8_X1(bundle
);
1295 return gen_rri_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
, imm
);
1297 case BRANCH_OPCODE_X1
:
1298 ext
= get_BrType_X1(bundle
);
1299 imm
= sextract32(get_BrOff_X1(bundle
), 0, 17);
1300 return gen_branch_opcode_x1(dc
, ext
, srca
, imm
);
1302 case JUMP_OPCODE_X1
:
1303 ext
= get_JumpOpcodeExtension_X1(bundle
);
1304 imm
= sextract32(get_JumpOff_X1(bundle
), 0, 27);
1305 return gen_jump_opcode_x1(dc
, ext
, imm
);
1307 case ADDLI_OPCODE_X1
:
1308 case SHL16INSLI_OPCODE_X1
:
1309 case ADDXLI_OPCODE_X1
:
1310 imm
= (int16_t)get_Imm16_X1(bundle
);
1311 return gen_rri_opcode(dc
, OE(opc
, 0, X1
), dest
, srca
, imm
);
1314 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1318 static void notice_excp(DisasContext
*dc
, uint64_t bundle
,
1319 const char *type
, TileExcp excp
)
1321 if (likely(excp
== TILEGX_EXCP_NONE
)) {
1324 gen_exception(dc
, excp
);
1325 if (excp
== TILEGX_EXCP_OPCODE_UNIMPLEMENTED
) {
1326 qemu_log_mask(LOG_UNIMP
, "UNIMP %s, [" FMT64X
"]\n", type
, bundle
);
1330 static void translate_one_bundle(DisasContext
*dc
, uint64_t bundle
)
1334 for (i
= 0; i
< ARRAY_SIZE(dc
->wb
); i
++) {
1335 DisasContextTemp
*wb
= &dc
->wb
[i
];
1336 wb
->reg
= TILEGX_R_NOREG
;
1337 TCGV_UNUSED_I64(wb
->val
);
1341 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
1342 tcg_gen_debug_insn_start(dc
->pc
);
1345 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " %" PRIx64
": { ", dc
->pc
);
1346 if (get_Mode(bundle
)) {
1347 notice_excp(dc
, bundle
, "y0", decode_y0(dc
, bundle
));
1348 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " ; ");
1349 notice_excp(dc
, bundle
, "y1", decode_y1(dc
, bundle
));
1350 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " ; ");
1351 notice_excp(dc
, bundle
, "y2", decode_y2(dc
, bundle
));
1353 notice_excp(dc
, bundle
, "x0", decode_x0(dc
, bundle
));
1354 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " ; ");
1355 notice_excp(dc
, bundle
, "x1", decode_x1(dc
, bundle
));
1357 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " }\n");
1359 for (i
= dc
->num_wb
- 1; i
>= 0; --i
) {
1360 DisasContextTemp
*wb
= &dc
->wb
[i
];
1361 if (wb
->reg
< TILEGX_R_COUNT
) {
1362 tcg_gen_mov_i64(cpu_regs
[wb
->reg
], wb
->val
);
1364 tcg_temp_free_i64(wb
->val
);
1367 if (dc
->jmp
.cond
!= TCG_COND_NEVER
) {
1368 if (dc
->jmp
.cond
== TCG_COND_ALWAYS
) {
1369 tcg_gen_mov_i64(cpu_pc
, dc
->jmp
.dest
);
1371 TCGv next
= tcg_const_i64(dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
1372 tcg_gen_movcond_i64(dc
->jmp
.cond
, cpu_pc
,
1373 dc
->jmp
.val1
, load_zero(dc
),
1374 dc
->jmp
.dest
, next
);
1375 tcg_temp_free_i64(dc
->jmp
.val1
);
1376 tcg_temp_free_i64(next
);
1378 tcg_temp_free_i64(dc
->jmp
.dest
);
1384 static inline void gen_intermediate_code_internal(TileGXCPU
*cpu
,
1385 TranslationBlock
*tb
,
1389 DisasContext
*dc
= &ctx
;
1390 CPUState
*cs
= CPU(cpu
);
1391 CPUTLGState
*env
= &cpu
->env
;
1392 uint64_t pc_start
= tb
->pc
;
1393 uint64_t next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1396 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1400 dc
->exit_tb
= false;
1401 dc
->jmp
.cond
= TCG_COND_NEVER
;
1402 TCGV_UNUSED_I64(dc
->jmp
.dest
);
1403 TCGV_UNUSED_I64(dc
->jmp
.val1
);
1404 TCGV_UNUSED_I64(dc
->zero
);
1406 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1407 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
1410 max_insns
= CF_COUNT_MASK
;
1412 if (cs
->singlestep_enabled
|| singlestep
) {
1419 j
= tcg_op_buf_count();
1423 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
1426 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
1427 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
1428 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
1430 translate_one_bundle(dc
, cpu_ldq_data(env
, dc
->pc
));
1433 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
1436 dc
->pc
+= TILEGX_BUNDLE_SIZE_IN_BYTES
;
1437 if (++num_insns
>= max_insns
1438 || dc
->pc
>= next_page_start
1439 || tcg_op_buf_full()) {
1440 /* Ending the TB due to TB size or page boundary. Set PC. */
1441 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1447 gen_tb_end(tb
, num_insns
);
1449 j
= tcg_op_buf_count();
1452 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
1455 tb
->size
= dc
->pc
- pc_start
;
1456 tb
->icount
= num_insns
;
1459 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "\n");
1462 void gen_intermediate_code(CPUTLGState
*env
, struct TranslationBlock
*tb
)
1464 gen_intermediate_code_internal(tilegx_env_get_cpu(env
), tb
, false);
1467 void gen_intermediate_code_pc(CPUTLGState
*env
, struct TranslationBlock
*tb
)
1469 gen_intermediate_code_internal(tilegx_env_get_cpu(env
), tb
, true);
1472 void restore_state_to_opc(CPUTLGState
*env
, TranslationBlock
*tb
, int pc_pos
)
1474 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];
1477 void tilegx_tcg_init(void)
1481 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1482 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUTLGState
, pc
), "pc");
1483 for (i
= 0; i
< TILEGX_R_COUNT
; i
++) {
1484 cpu_regs
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
1485 offsetof(CPUTLGState
, regs
[i
]),