4 * Copyright (c) 2015 Chen Gang
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
23 #include "disas/disas.h"
25 #include "exec/cpu_ldst.h"
26 #include "opcode_tilegx.h"
27 #include "spr_def_64.h"
29 #define FMT64X "%016" PRIx64
31 static TCGv_ptr cpu_env
;
33 static TCGv cpu_regs
[TILEGX_R_COUNT
];
35 static const char * const reg_names
[64] = {
36 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
37 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
38 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
39 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
40 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
41 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
42 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
43 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
46 /* Modified registers are cached in temporaries until the end of the bundle. */
52 #define MAX_WRITEBACK 4
54 /* This is the state at translation time. */
56 uint64_t pc
; /* Current pc */
58 TCGv zero
; /* For zero register */
60 DisasContextTemp wb
[MAX_WRITEBACK
];
67 TCGCond cond
; /* branch condition */
68 TCGv dest
; /* branch destination */
69 TCGv val1
; /* value to be compared against zero, for cond */
70 } jmp
; /* Jump object, only once in each TB block */
73 #include "exec/gen-icount.h"
75 /* Differentiate the various pipe encodings. */
81 /* Remerge the base opcode and extension fields for switching.
82 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
83 Y2 opcode field is 2 bits. */
84 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
86 /* Similar, but for Y2 only. */
87 #define OEY2(OP, MODE) (OP + MODE * 4)
89 /* Similar, but make sure opcode names match up. */
90 #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
91 #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
92 #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
93 #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
94 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
95 #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
96 #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
98 #define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
99 #define V2_IMM(X) (((X) & 0xffff) * 0x0001000100010001ull)
102 static void gen_exception(DisasContext
*dc
, TileExcp num
)
106 tcg_gen_movi_tl(cpu_pc
, dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
108 tmp
= tcg_const_i32(num
);
109 gen_helper_exception(cpu_env
, tmp
);
110 tcg_temp_free_i32(tmp
);
114 static bool check_gr(DisasContext
*dc
, uint8_t reg
)
116 if (likely(reg
< TILEGX_R_COUNT
)) {
126 gen_exception(dc
, TILEGX_EXCP_REG_IDN_ACCESS
);
132 gen_exception(dc
, TILEGX_EXCP_REG_UDN_ACCESS
);
135 g_assert_not_reached();
140 static TCGv
load_zero(DisasContext
*dc
)
142 if (TCGV_IS_UNUSED_I64(dc
->zero
)) {
143 dc
->zero
= tcg_const_i64(0);
148 static TCGv
load_gr(DisasContext
*dc
, unsigned reg
)
150 if (check_gr(dc
, reg
)) {
151 return cpu_regs
[reg
];
153 return load_zero(dc
);
156 static TCGv
dest_gr(DisasContext
*dc
, unsigned reg
)
160 /* Skip the result, mark the exception if necessary, and continue */
165 return dc
->wb
[n
].val
= tcg_temp_new_i64();
168 static void gen_saturate_op(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
,
169 void (*operate
)(TCGv
, TCGv
, TCGv
))
171 TCGv t0
= tcg_temp_new();
173 tcg_gen_ext32s_tl(tdest
, tsrca
);
174 tcg_gen_ext32s_tl(t0
, tsrcb
);
175 operate(tdest
, tdest
, t0
);
177 tcg_gen_movi_tl(t0
, 0x7fffffff);
178 tcg_gen_movcond_tl(TCG_COND_GT
, tdest
, tdest
, t0
, t0
, tdest
);
179 tcg_gen_movi_tl(t0
, -0x80000000LL
);
180 tcg_gen_movcond_tl(TCG_COND_LT
, tdest
, tdest
, t0
, t0
, tdest
);
185 static void gen_atomic_excp(DisasContext
*dc
, unsigned dest
, TCGv tdest
,
186 TCGv tsrca
, TCGv tsrcb
, TileExcp excp
)
188 #ifdef CONFIG_USER_ONLY
191 tcg_gen_st_tl(tsrca
, cpu_env
, offsetof(CPUTLGState
, atomic_srca
));
192 tcg_gen_st_tl(tsrcb
, cpu_env
, offsetof(CPUTLGState
, atomic_srcb
));
193 t
= tcg_const_i32(dest
);
194 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUTLGState
, atomic_dstr
));
195 tcg_temp_free_i32(t
);
197 /* We're going to write the real result in the exception. But in
198 the meantime we've already created a writeback register, and
199 we don't want that to remain uninitialized. */
200 tcg_gen_movi_tl(tdest
, 0);
202 /* Note that we need to delay issuing the exception that implements
203 the atomic operation until after writing back the results of the
204 instruction occupying the X0 pipe. */
205 dc
->atomic_excp
= excp
;
207 gen_exception(dc
, TILEGX_EXCP_OPCODE_UNIMPLEMENTED
);
211 /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
212 specified by the bottom 3 bits of TSRCB, and set TDEST to the
213 low 64 bits of the resulting value. */
214 static void gen_dblalign(TCGv tdest
, TCGv tsrcd
, TCGv tsrca
, TCGv tsrcb
)
216 TCGv t0
= tcg_temp_new();
218 tcg_gen_andi_tl(t0
, tsrcb
, 7);
219 tcg_gen_shli_tl(t0
, t0
, 3);
220 tcg_gen_shr_tl(tdest
, tsrcd
, t0
);
222 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
223 arithmetic on a 6-bit field tells us that 64 - t0 is equal
224 to (t0 ^ 63) + 1. So we can do the shift in two parts,
225 neither of which will be an invalid shift by 64. */
226 tcg_gen_xori_tl(t0
, t0
, 63);
227 tcg_gen_shl_tl(t0
, tsrca
, t0
);
228 tcg_gen_shli_tl(t0
, t0
, 1);
229 tcg_gen_or_tl(tdest
, tdest
, t0
);
234 /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
235 right shift is an immediate. */
236 static void gen_dblaligni(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
, int shr
)
238 TCGv t0
= tcg_temp_new();
240 tcg_gen_shri_tl(t0
, tsrcb
, shr
);
241 tcg_gen_shli_tl(tdest
, tsrca
, 64 - shr
);
242 tcg_gen_or_tl(tdest
, tdest
, t0
);
251 static void gen_ext_half(TCGv d
, TCGv s
, MulHalf h
)
255 tcg_gen_ext32u_tl(d
, s
);
258 tcg_gen_ext32s_tl(d
, s
);
261 tcg_gen_shri_tl(d
, s
, 32);
264 tcg_gen_sari_tl(d
, s
, 32);
269 static void gen_mul_half(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
,
270 MulHalf ha
, MulHalf hb
)
272 TCGv t
= tcg_temp_new();
273 gen_ext_half(t
, tsrca
, ha
);
274 gen_ext_half(tdest
, tsrcb
, hb
);
275 tcg_gen_mul_tl(tdest
, tdest
, t
);
279 static void gen_cmul2(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
, int sh
, int rd
)
281 TCGv_i32 tsh
= tcg_const_i32(sh
);
282 TCGv_i32 trd
= tcg_const_i32(rd
);
283 gen_helper_cmul2(tdest
, tsrca
, tsrcb
, tsh
, trd
);
284 tcg_temp_free_i32(tsh
);
285 tcg_temp_free_i32(trd
);
288 static TileExcp
gen_st_opcode(DisasContext
*dc
, unsigned dest
, unsigned srca
,
289 unsigned srcb
, TCGMemOp memop
, const char *name
)
292 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
295 tcg_gen_qemu_st_tl(load_gr(dc
, srcb
), load_gr(dc
, srca
),
298 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s", name
,
299 reg_names
[srca
], reg_names
[srcb
]);
300 return TILEGX_EXCP_NONE
;
303 static TileExcp
gen_st_add_opcode(DisasContext
*dc
, unsigned srca
, unsigned srcb
,
304 int imm
, TCGMemOp memop
, const char *name
)
306 TCGv tsrca
= load_gr(dc
, srca
);
307 TCGv tsrcb
= load_gr(dc
, srcb
);
309 tcg_gen_qemu_st_tl(tsrcb
, tsrca
, dc
->mmuidx
, memop
);
310 tcg_gen_addi_tl(dest_gr(dc
, srca
), tsrca
, imm
);
312 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %d", name
,
313 reg_names
[srca
], reg_names
[srcb
], imm
);
314 return TILEGX_EXCP_NONE
;
317 /* Equality comparison with zero can be done quickly and efficiently. */
318 static void gen_v1cmpeq0(TCGv v
)
320 TCGv m
= tcg_const_tl(V1_IMM(0x7f));
321 TCGv c
= tcg_temp_new();
323 /* ~(((v & m) + m) | m | v). Sets the msb for each byte == 0. */
324 tcg_gen_and_tl(c
, v
, m
);
325 tcg_gen_add_tl(c
, c
, m
);
326 tcg_gen_or_tl(c
, c
, m
);
327 tcg_gen_nor_tl(c
, c
, v
);
330 /* Shift the msb down to form the lsb boolean result. */
331 tcg_gen_shri_tl(v
, c
, 7);
335 static void gen_v1cmpne0(TCGv v
)
337 TCGv m
= tcg_const_tl(V1_IMM(0x7f));
338 TCGv c
= tcg_temp_new();
340 /* (((v & m) + m) | v) & ~m. Sets the msb for each byte != 0. */
341 tcg_gen_and_tl(c
, v
, m
);
342 tcg_gen_add_tl(c
, c
, m
);
343 tcg_gen_or_tl(c
, c
, v
);
344 tcg_gen_andc_tl(c
, c
, m
);
347 /* Shift the msb down to form the lsb boolean result. */
348 tcg_gen_shri_tl(v
, c
, 7);
352 /* Vector addition can be performed via arithmetic plus masking. It is
353 efficient this way only for 4 or more elements. */
354 static void gen_v12add(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
, uint64_t sign
)
356 TCGv tmask
= tcg_const_tl(~sign
);
357 TCGv t0
= tcg_temp_new();
358 TCGv t1
= tcg_temp_new();
360 /* ((a & ~sign) + (b & ~sign)) ^ ((a ^ b) & sign). */
361 tcg_gen_and_tl(t0
, tsrca
, tmask
);
362 tcg_gen_and_tl(t1
, tsrcb
, tmask
);
363 tcg_gen_add_tl(tdest
, t0
, t1
);
364 tcg_gen_xor_tl(t0
, tsrca
, tsrcb
);
365 tcg_gen_andc_tl(t0
, t0
, tmask
);
366 tcg_gen_xor_tl(tdest
, tdest
, t0
);
370 tcg_temp_free(tmask
);
373 /* Similarly for vector subtraction. */
374 static void gen_v12sub(TCGv tdest
, TCGv tsrca
, TCGv tsrcb
, uint64_t sign
)
376 TCGv tsign
= tcg_const_tl(sign
);
377 TCGv t0
= tcg_temp_new();
378 TCGv t1
= tcg_temp_new();
380 /* ((a | sign) - (b & ~sign)) ^ ((a ^ ~b) & sign). */
381 tcg_gen_or_tl(t0
, tsrca
, tsign
);
382 tcg_gen_andc_tl(t1
, tsrcb
, tsign
);
383 tcg_gen_sub_tl(tdest
, t0
, t1
);
384 tcg_gen_eqv_tl(t0
, tsrca
, tsrcb
);
385 tcg_gen_and_tl(t0
, t0
, tsign
);
386 tcg_gen_xor_tl(tdest
, tdest
, t0
);
390 tcg_temp_free(tsign
);
393 static void gen_v4sh(TCGv d64
, TCGv a64
, TCGv b64
,
394 void (*generate
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
396 TCGv_i32 al
= tcg_temp_new_i32();
397 TCGv_i32 ah
= tcg_temp_new_i32();
398 TCGv_i32 bl
= tcg_temp_new_i32();
400 tcg_gen_extr_i64_i32(al
, ah
, a64
);
401 tcg_gen_extrl_i64_i32(bl
, b64
);
402 tcg_gen_andi_i32(bl
, bl
, 31);
403 generate(al
, al
, bl
);
404 generate(ah
, ah
, bl
);
405 tcg_gen_concat_i32_i64(d64
, al
, ah
);
407 tcg_temp_free_i32(al
);
408 tcg_temp_free_i32(ah
);
409 tcg_temp_free_i32(bl
);
412 static void gen_v4op(TCGv d64
, TCGv a64
, TCGv b64
,
413 void (*generate
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
415 TCGv_i32 al
= tcg_temp_new_i32();
416 TCGv_i32 ah
= tcg_temp_new_i32();
417 TCGv_i32 bl
= tcg_temp_new_i32();
418 TCGv_i32 bh
= tcg_temp_new_i32();
420 tcg_gen_extr_i64_i32(al
, ah
, a64
);
421 tcg_gen_extr_i64_i32(bl
, bh
, b64
);
422 generate(al
, al
, bl
);
423 generate(ah
, ah
, bh
);
424 tcg_gen_concat_i32_i64(d64
, al
, ah
);
426 tcg_temp_free_i32(al
);
427 tcg_temp_free_i32(ah
);
428 tcg_temp_free_i32(bl
);
429 tcg_temp_free_i32(bh
);
432 static TileExcp
gen_rr_opcode(DisasContext
*dc
, unsigned opext
,
433 unsigned dest
, unsigned srca
)
436 const char *mnemonic
;
438 TileExcp ret
= TILEGX_EXCP_NONE
;
440 /* Eliminate instructions with no output before doing anything else. */
454 case OE_RR_X1(DRAIN
):
457 case OE_RR_X1(FLUSHWB
):
458 mnemonic
= "flushwb";
461 if (dest
== 0x1c && srca
== 0x25) {
469 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s", mnemonic
);
470 return TILEGX_EXCP_OPCODE_UNKNOWN
;
475 /* ??? This should yield, especially in system mode. */
478 case OE_RR_X1(SWINT0
):
479 case OE_RR_X1(SWINT2
):
480 case OE_RR_X1(SWINT3
):
481 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
482 case OE_RR_X1(SWINT1
):
483 ret
= TILEGX_EXCP_SYSCALL
;
487 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
489 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s", mnemonic
);
492 case OE_RR_X1(DTLBPR
):
493 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
497 case OE_RR_X1(FLUSH
):
517 case OE_RR_X1(JALRP
):
518 case OE_RR_Y1(JALRP
):
525 tcg_gen_movi_tl(dest_gr(dc
, TILEGX_R_LR
),
526 dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
528 dc
->jmp
.cond
= TCG_COND_ALWAYS
;
529 dc
->jmp
.dest
= tcg_temp_new();
530 tcg_gen_andi_tl(dc
->jmp
.dest
, load_gr(dc
, srca
), ~7);
533 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
535 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s", mnemonic
, reg_names
[srca
]);
539 tdest
= dest_gr(dc
, dest
);
540 tsrca
= load_gr(dc
, srca
);
543 case OE_RR_X0(CNTLZ
):
544 case OE_RR_Y0(CNTLZ
):
545 gen_helper_cntlz(tdest
, tsrca
);
548 case OE_RR_X0(CNTTZ
):
549 case OE_RR_Y0(CNTTZ
):
550 gen_helper_cnttz(tdest
, tsrca
);
553 case OE_RR_X0(FSINGLE_PACK1
):
554 case OE_RR_Y0(FSINGLE_PACK1
):
556 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
581 case OE_RR_X1(LDNT1S
):
585 case OE_RR_X1(LDNT1U
):
589 case OE_RR_X1(LDNT2S
):
593 case OE_RR_X1(LDNT2U
):
597 case OE_RR_X1(LDNT4S
):
601 case OE_RR_X1(LDNT4U
):
613 tcg_gen_qemu_ld_tl(tdest
, tsrca
, dc
->mmuidx
, memop
);
616 tcg_gen_andi_tl(tdest
, tsrca
, ~7);
617 tcg_gen_qemu_ld_tl(tdest
, tdest
, dc
->mmuidx
, MO_TEQ
);
623 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
625 tcg_gen_movi_tl(tdest
, dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
630 gen_helper_pcnt(tdest
, tsrca
);
633 case OE_RR_X0(REVBITS
):
634 case OE_RR_Y0(REVBITS
):
635 gen_helper_revbits(tdest
, tsrca
);
636 mnemonic
= "revbits";
638 case OE_RR_X0(REVBYTES
):
639 case OE_RR_Y0(REVBYTES
):
640 tcg_gen_bswap64_tl(tdest
, tsrca
);
641 mnemonic
= "revbytes";
643 case OE_RR_X0(TBLIDXB0
):
644 case OE_RR_Y0(TBLIDXB0
):
645 tcg_gen_deposit_tl(tdest
, load_gr(dc
, dest
), tsrca
, 2, 8);
646 mnemonic
= "tblidxb0";
648 case OE_RR_X0(TBLIDXB1
):
649 case OE_RR_Y0(TBLIDXB1
):
650 tcg_gen_shri_tl(tdest
, tsrca
, 8);
651 tcg_gen_deposit_tl(tdest
, load_gr(dc
, dest
), tdest
, 2, 8);
652 mnemonic
= "tblidxb1";
654 case OE_RR_X0(TBLIDXB2
):
655 case OE_RR_Y0(TBLIDXB2
):
656 tcg_gen_shri_tl(tdest
, tsrca
, 16);
657 tcg_gen_deposit_tl(tdest
, load_gr(dc
, dest
), tdest
, 2, 8);
658 mnemonic
= "tblidxb2";
660 case OE_RR_X0(TBLIDXB3
):
661 case OE_RR_Y0(TBLIDXB3
):
662 tcg_gen_shri_tl(tdest
, tsrca
, 24);
663 tcg_gen_deposit_tl(tdest
, load_gr(dc
, dest
), tdest
, 2, 8);
664 mnemonic
= "tblidxb3";
667 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
670 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s", mnemonic
,
671 reg_names
[dest
], reg_names
[srca
]);
675 static TileExcp
gen_rrr_opcode(DisasContext
*dc
, unsigned opext
,
676 unsigned dest
, unsigned srca
, unsigned srcb
)
678 TCGv tdest
= dest_gr(dc
, dest
);
679 TCGv tsrca
= load_gr(dc
, srca
);
680 TCGv tsrcb
= load_gr(dc
, srcb
);
682 const char *mnemonic
;
685 case OE_RRR(ADDXSC
, 0, X0
):
686 case OE_RRR(ADDXSC
, 0, X1
):
687 gen_saturate_op(tdest
, tsrca
, tsrcb
, tcg_gen_add_tl
);
690 case OE_RRR(ADDX
, 0, X0
):
691 case OE_RRR(ADDX
, 0, X1
):
692 case OE_RRR(ADDX
, 0, Y0
):
693 case OE_RRR(ADDX
, 0, Y1
):
694 tcg_gen_add_tl(tdest
, tsrca
, tsrcb
);
695 tcg_gen_ext32s_tl(tdest
, tdest
);
698 case OE_RRR(ADD
, 0, X0
):
699 case OE_RRR(ADD
, 0, X1
):
700 case OE_RRR(ADD
, 0, Y0
):
701 case OE_RRR(ADD
, 0, Y1
):
702 tcg_gen_add_tl(tdest
, tsrca
, tsrcb
);
705 case OE_RRR(AND
, 0, X0
):
706 case OE_RRR(AND
, 0, X1
):
707 case OE_RRR(AND
, 5, Y0
):
708 case OE_RRR(AND
, 5, Y1
):
709 tcg_gen_and_tl(tdest
, tsrca
, tsrcb
);
712 case OE_RRR(CMOVEQZ
, 0, X0
):
713 case OE_RRR(CMOVEQZ
, 4, Y0
):
714 tcg_gen_movcond_tl(TCG_COND_EQ
, tdest
, tsrca
, load_zero(dc
),
715 tsrcb
, load_gr(dc
, dest
));
716 mnemonic
= "cmoveqz";
718 case OE_RRR(CMOVNEZ
, 0, X0
):
719 case OE_RRR(CMOVNEZ
, 4, Y0
):
720 tcg_gen_movcond_tl(TCG_COND_NE
, tdest
, tsrca
, load_zero(dc
),
721 tsrcb
, load_gr(dc
, dest
));
722 mnemonic
= "cmovnez";
724 case OE_RRR(CMPEQ
, 0, X0
):
725 case OE_RRR(CMPEQ
, 0, X1
):
726 case OE_RRR(CMPEQ
, 3, Y0
):
727 case OE_RRR(CMPEQ
, 3, Y1
):
728 tcg_gen_setcond_tl(TCG_COND_EQ
, tdest
, tsrca
, tsrcb
);
731 case OE_RRR(CMPEXCH4
, 0, X1
):
732 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
733 TILEGX_EXCP_OPCODE_CMPEXCH4
);
734 mnemonic
= "cmpexch4";
736 case OE_RRR(CMPEXCH
, 0, X1
):
737 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
738 TILEGX_EXCP_OPCODE_CMPEXCH
);
739 mnemonic
= "cmpexch";
741 case OE_RRR(CMPLES
, 0, X0
):
742 case OE_RRR(CMPLES
, 0, X1
):
743 case OE_RRR(CMPLES
, 2, Y0
):
744 case OE_RRR(CMPLES
, 2, Y1
):
745 tcg_gen_setcond_tl(TCG_COND_LE
, tdest
, tsrca
, tsrcb
);
748 case OE_RRR(CMPLEU
, 0, X0
):
749 case OE_RRR(CMPLEU
, 0, X1
):
750 case OE_RRR(CMPLEU
, 2, Y0
):
751 case OE_RRR(CMPLEU
, 2, Y1
):
752 tcg_gen_setcond_tl(TCG_COND_LEU
, tdest
, tsrca
, tsrcb
);
755 case OE_RRR(CMPLTS
, 0, X0
):
756 case OE_RRR(CMPLTS
, 0, X1
):
757 case OE_RRR(CMPLTS
, 2, Y0
):
758 case OE_RRR(CMPLTS
, 2, Y1
):
759 tcg_gen_setcond_tl(TCG_COND_LT
, tdest
, tsrca
, tsrcb
);
762 case OE_RRR(CMPLTU
, 0, X0
):
763 case OE_RRR(CMPLTU
, 0, X1
):
764 case OE_RRR(CMPLTU
, 2, Y0
):
765 case OE_RRR(CMPLTU
, 2, Y1
):
766 tcg_gen_setcond_tl(TCG_COND_LTU
, tdest
, tsrca
, tsrcb
);
769 case OE_RRR(CMPNE
, 0, X0
):
770 case OE_RRR(CMPNE
, 0, X1
):
771 case OE_RRR(CMPNE
, 3, Y0
):
772 case OE_RRR(CMPNE
, 3, Y1
):
773 tcg_gen_setcond_tl(TCG_COND_NE
, tdest
, tsrca
, tsrcb
);
776 case OE_RRR(CMULAF
, 0, X0
):
777 gen_helper_cmulaf(tdest
, load_gr(dc
, dest
), tsrca
, tsrcb
);
780 case OE_RRR(CMULA
, 0, X0
):
781 gen_helper_cmula(tdest
, load_gr(dc
, dest
), tsrca
, tsrcb
);
784 case OE_RRR(CMULFR
, 0, X0
):
785 gen_cmul2(tdest
, tsrca
, tsrcb
, 15, 1 << 14);
788 case OE_RRR(CMULF
, 0, X0
):
789 gen_cmul2(tdest
, tsrca
, tsrcb
, 15, 0);
792 case OE_RRR(CMULHR
, 0, X0
):
793 gen_cmul2(tdest
, tsrca
, tsrcb
, 16, 1 << 15);
796 case OE_RRR(CMULH
, 0, X0
):
797 gen_cmul2(tdest
, tsrca
, tsrcb
, 16, 0);
800 case OE_RRR(CMUL
, 0, X0
):
801 gen_helper_cmula(tdest
, load_zero(dc
), tsrca
, tsrcb
);
804 case OE_RRR(CRC32_32
, 0, X0
):
805 gen_helper_crc32_32(tdest
, tsrca
, tsrcb
);
806 mnemonic
= "crc32_32";
808 case OE_RRR(CRC32_8
, 0, X0
):
809 gen_helper_crc32_8(tdest
, tsrca
, tsrcb
);
810 mnemonic
= "crc32_8";
812 case OE_RRR(DBLALIGN2
, 0, X0
):
813 case OE_RRR(DBLALIGN2
, 0, X1
):
814 gen_dblaligni(tdest
, tsrca
, tsrcb
, 16);
815 mnemonic
= "dblalign2";
817 case OE_RRR(DBLALIGN4
, 0, X0
):
818 case OE_RRR(DBLALIGN4
, 0, X1
):
819 gen_dblaligni(tdest
, tsrca
, tsrcb
, 32);
820 mnemonic
= "dblalign4";
822 case OE_RRR(DBLALIGN6
, 0, X0
):
823 case OE_RRR(DBLALIGN6
, 0, X1
):
824 gen_dblaligni(tdest
, tsrca
, tsrcb
, 48);
825 mnemonic
= "dblalign6";
827 case OE_RRR(DBLALIGN
, 0, X0
):
828 gen_dblalign(tdest
, load_gr(dc
, dest
), tsrca
, tsrcb
);
829 mnemonic
= "dblalign";
831 case OE_RRR(EXCH4
, 0, X1
):
832 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
833 TILEGX_EXCP_OPCODE_EXCH4
);
836 case OE_RRR(EXCH
, 0, X1
):
837 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
838 TILEGX_EXCP_OPCODE_EXCH
);
841 case OE_RRR(FDOUBLE_ADDSUB
, 0, X0
):
842 case OE_RRR(FDOUBLE_ADD_FLAGS
, 0, X0
):
843 case OE_RRR(FDOUBLE_MUL_FLAGS
, 0, X0
):
844 case OE_RRR(FDOUBLE_PACK1
, 0, X0
):
845 case OE_RRR(FDOUBLE_PACK2
, 0, X0
):
846 case OE_RRR(FDOUBLE_SUB_FLAGS
, 0, X0
):
847 case OE_RRR(FDOUBLE_UNPACK_MAX
, 0, X0
):
848 case OE_RRR(FDOUBLE_UNPACK_MIN
, 0, X0
):
849 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
850 case OE_RRR(FETCHADD4
, 0, X1
):
851 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
852 TILEGX_EXCP_OPCODE_FETCHADD4
);
853 mnemonic
= "fetchadd4";
855 case OE_RRR(FETCHADDGEZ4
, 0, X1
):
856 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
857 TILEGX_EXCP_OPCODE_FETCHADDGEZ4
);
858 mnemonic
= "fetchaddgez4";
860 case OE_RRR(FETCHADDGEZ
, 0, X1
):
861 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
862 TILEGX_EXCP_OPCODE_FETCHADDGEZ
);
863 mnemonic
= "fetchaddgez";
865 case OE_RRR(FETCHADD
, 0, X1
):
866 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
867 TILEGX_EXCP_OPCODE_FETCHADD
);
868 mnemonic
= "fetchadd";
870 case OE_RRR(FETCHAND4
, 0, X1
):
871 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
872 TILEGX_EXCP_OPCODE_FETCHAND4
);
873 mnemonic
= "fetchand4";
875 case OE_RRR(FETCHAND
, 0, X1
):
876 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
877 TILEGX_EXCP_OPCODE_FETCHAND
);
878 mnemonic
= "fetchand";
880 case OE_RRR(FETCHOR4
, 0, X1
):
881 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
882 TILEGX_EXCP_OPCODE_FETCHOR4
);
883 mnemonic
= "fetchor4";
885 case OE_RRR(FETCHOR
, 0, X1
):
886 gen_atomic_excp(dc
, dest
, tdest
, tsrca
, tsrcb
,
887 TILEGX_EXCP_OPCODE_FETCHOR
);
888 mnemonic
= "fetchor";
890 case OE_RRR(FSINGLE_ADD1
, 0, X0
):
891 case OE_RRR(FSINGLE_ADDSUB2
, 0, X0
):
892 case OE_RRR(FSINGLE_MUL1
, 0, X0
):
893 case OE_RRR(FSINGLE_MUL2
, 0, X0
):
894 case OE_RRR(FSINGLE_PACK2
, 0, X0
):
895 case OE_RRR(FSINGLE_SUB1
, 0, X0
):
896 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
897 case OE_RRR(MNZ
, 0, X0
):
898 case OE_RRR(MNZ
, 0, X1
):
899 case OE_RRR(MNZ
, 4, Y0
):
900 case OE_RRR(MNZ
, 4, Y1
):
902 tcg_gen_movcond_tl(TCG_COND_NE
, tdest
, tsrca
, t0
, tsrcb
, t0
);
905 case OE_RRR(MULAX
, 0, X0
):
906 case OE_RRR(MULAX
, 3, Y0
):
907 tcg_gen_mul_tl(tdest
, tsrca
, tsrcb
);
908 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
909 tcg_gen_ext32s_tl(tdest
, tdest
);
912 case OE_RRR(MULA_HS_HS
, 0, X0
):
913 case OE_RRR(MULA_HS_HS
, 9, Y0
):
914 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, HS
);
915 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
916 mnemonic
= "mula_hs_hs";
918 case OE_RRR(MULA_HS_HU
, 0, X0
):
919 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, HU
);
920 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
921 mnemonic
= "mula_hs_hu";
923 case OE_RRR(MULA_HS_LS
, 0, X0
):
924 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, LS
);
925 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
926 mnemonic
= "mula_hs_ls";
928 case OE_RRR(MULA_HS_LU
, 0, X0
):
929 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, LU
);
930 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
931 mnemonic
= "mula_hs_lu";
933 case OE_RRR(MULA_HU_HU
, 0, X0
):
934 case OE_RRR(MULA_HU_HU
, 9, Y0
):
935 gen_mul_half(tdest
, tsrca
, tsrcb
, HU
, HU
);
936 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
937 mnemonic
= "mula_hu_hu";
939 case OE_RRR(MULA_HU_LS
, 0, X0
):
940 gen_mul_half(tdest
, tsrca
, tsrcb
, HU
, LS
);
941 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
942 mnemonic
= "mula_hu_ls";
944 case OE_RRR(MULA_HU_LU
, 0, X0
):
945 gen_mul_half(tdest
, tsrca
, tsrcb
, HU
, LU
);
946 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
947 mnemonic
= "mula_hu_lu";
949 case OE_RRR(MULA_LS_LS
, 0, X0
):
950 case OE_RRR(MULA_LS_LS
, 9, Y0
):
951 gen_mul_half(tdest
, tsrca
, tsrcb
, LS
, LS
);
952 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
953 mnemonic
= "mula_ls_ls";
955 case OE_RRR(MULA_LS_LU
, 0, X0
):
956 gen_mul_half(tdest
, tsrca
, tsrcb
, LS
, LU
);
957 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
958 mnemonic
= "mula_ls_lu";
960 case OE_RRR(MULA_LU_LU
, 0, X0
):
961 case OE_RRR(MULA_LU_LU
, 9, Y0
):
962 gen_mul_half(tdest
, tsrca
, tsrcb
, LU
, LU
);
963 tcg_gen_add_tl(tdest
, tdest
, load_gr(dc
, dest
));
964 mnemonic
= "mula_lu_lu";
966 case OE_RRR(MULX
, 0, X0
):
967 case OE_RRR(MULX
, 3, Y0
):
968 tcg_gen_mul_tl(tdest
, tsrca
, tsrcb
);
969 tcg_gen_ext32s_tl(tdest
, tdest
);
972 case OE_RRR(MUL_HS_HS
, 0, X0
):
973 case OE_RRR(MUL_HS_HS
, 8, Y0
):
974 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, HS
);
975 mnemonic
= "mul_hs_hs";
977 case OE_RRR(MUL_HS_HU
, 0, X0
):
978 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, HU
);
979 mnemonic
= "mul_hs_hu";
981 case OE_RRR(MUL_HS_LS
, 0, X0
):
982 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, LS
);
983 mnemonic
= "mul_hs_ls";
985 case OE_RRR(MUL_HS_LU
, 0, X0
):
986 gen_mul_half(tdest
, tsrca
, tsrcb
, HS
, LU
);
987 mnemonic
= "mul_hs_lu";
989 case OE_RRR(MUL_HU_HU
, 0, X0
):
990 case OE_RRR(MUL_HU_HU
, 8, Y0
):
991 gen_mul_half(tdest
, tsrca
, tsrcb
, HU
, HU
);
992 mnemonic
= "mul_hu_hu";
994 case OE_RRR(MUL_HU_LS
, 0, X0
):
995 gen_mul_half(tdest
, tsrca
, tsrcb
, HU
, LS
);
996 mnemonic
= "mul_hu_ls";
998 case OE_RRR(MUL_HU_LU
, 0, X0
):
999 gen_mul_half(tdest
, tsrca
, tsrcb
, HU
, LU
);
1000 mnemonic
= "mul_hu_lu";
1002 case OE_RRR(MUL_LS_LS
, 0, X0
):
1003 case OE_RRR(MUL_LS_LS
, 8, Y0
):
1004 gen_mul_half(tdest
, tsrca
, tsrcb
, LS
, LS
);
1005 mnemonic
= "mul_ls_ls";
1007 case OE_RRR(MUL_LS_LU
, 0, X0
):
1008 gen_mul_half(tdest
, tsrca
, tsrcb
, LS
, LU
);
1009 mnemonic
= "mul_ls_lu";
1011 case OE_RRR(MUL_LU_LU
, 0, X0
):
1012 case OE_RRR(MUL_LU_LU
, 8, Y0
):
1013 gen_mul_half(tdest
, tsrca
, tsrcb
, LU
, LU
);
1014 mnemonic
= "mul_lu_lu";
1016 case OE_RRR(MZ
, 0, X0
):
1017 case OE_RRR(MZ
, 0, X1
):
1018 case OE_RRR(MZ
, 4, Y0
):
1019 case OE_RRR(MZ
, 4, Y1
):
1021 tcg_gen_movcond_tl(TCG_COND_EQ
, tdest
, tsrca
, t0
, tsrcb
, t0
);
1024 case OE_RRR(NOR
, 0, X0
):
1025 case OE_RRR(NOR
, 0, X1
):
1026 case OE_RRR(NOR
, 5, Y0
):
1027 case OE_RRR(NOR
, 5, Y1
):
1028 tcg_gen_nor_tl(tdest
, tsrca
, tsrcb
);
1031 case OE_RRR(OR
, 0, X0
):
1032 case OE_RRR(OR
, 0, X1
):
1033 case OE_RRR(OR
, 5, Y0
):
1034 case OE_RRR(OR
, 5, Y1
):
1035 tcg_gen_or_tl(tdest
, tsrca
, tsrcb
);
1038 case OE_RRR(ROTL
, 0, X0
):
1039 case OE_RRR(ROTL
, 0, X1
):
1040 case OE_RRR(ROTL
, 6, Y0
):
1041 case OE_RRR(ROTL
, 6, Y1
):
1042 tcg_gen_andi_tl(tdest
, tsrcb
, 63);
1043 tcg_gen_rotl_tl(tdest
, tsrca
, tdest
);
1046 case OE_RRR(SHL1ADDX
, 0, X0
):
1047 case OE_RRR(SHL1ADDX
, 0, X1
):
1048 case OE_RRR(SHL1ADDX
, 7, Y0
):
1049 case OE_RRR(SHL1ADDX
, 7, Y1
):
1050 tcg_gen_shli_tl(tdest
, tsrca
, 1);
1051 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
1052 tcg_gen_ext32s_tl(tdest
, tdest
);
1053 mnemonic
= "shl1addx";
1055 case OE_RRR(SHL1ADD
, 0, X0
):
1056 case OE_RRR(SHL1ADD
, 0, X1
):
1057 case OE_RRR(SHL1ADD
, 1, Y0
):
1058 case OE_RRR(SHL1ADD
, 1, Y1
):
1059 tcg_gen_shli_tl(tdest
, tsrca
, 1);
1060 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
1061 mnemonic
= "shl1add";
1063 case OE_RRR(SHL2ADDX
, 0, X0
):
1064 case OE_RRR(SHL2ADDX
, 0, X1
):
1065 case OE_RRR(SHL2ADDX
, 7, Y0
):
1066 case OE_RRR(SHL2ADDX
, 7, Y1
):
1067 tcg_gen_shli_tl(tdest
, tsrca
, 2);
1068 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
1069 tcg_gen_ext32s_tl(tdest
, tdest
);
1070 mnemonic
= "shl2addx";
1072 case OE_RRR(SHL2ADD
, 0, X0
):
1073 case OE_RRR(SHL2ADD
, 0, X1
):
1074 case OE_RRR(SHL2ADD
, 1, Y0
):
1075 case OE_RRR(SHL2ADD
, 1, Y1
):
1076 tcg_gen_shli_tl(tdest
, tsrca
, 2);
1077 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
1078 mnemonic
= "shl2add";
1080 case OE_RRR(SHL3ADDX
, 0, X0
):
1081 case OE_RRR(SHL3ADDX
, 0, X1
):
1082 case OE_RRR(SHL3ADDX
, 7, Y0
):
1083 case OE_RRR(SHL3ADDX
, 7, Y1
):
1084 tcg_gen_shli_tl(tdest
, tsrca
, 3);
1085 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
1086 tcg_gen_ext32s_tl(tdest
, tdest
);
1087 mnemonic
= "shl3addx";
1089 case OE_RRR(SHL3ADD
, 0, X0
):
1090 case OE_RRR(SHL3ADD
, 0, X1
):
1091 case OE_RRR(SHL3ADD
, 1, Y0
):
1092 case OE_RRR(SHL3ADD
, 1, Y1
):
1093 tcg_gen_shli_tl(tdest
, tsrca
, 3);
1094 tcg_gen_add_tl(tdest
, tdest
, tsrcb
);
1095 mnemonic
= "shl3add";
1097 case OE_RRR(SHLX
, 0, X0
):
1098 case OE_RRR(SHLX
, 0, X1
):
1099 tcg_gen_andi_tl(tdest
, tsrcb
, 31);
1100 tcg_gen_shl_tl(tdest
, tsrca
, tdest
);
1101 tcg_gen_ext32s_tl(tdest
, tdest
);
1104 case OE_RRR(SHL
, 0, X0
):
1105 case OE_RRR(SHL
, 0, X1
):
1106 case OE_RRR(SHL
, 6, Y0
):
1107 case OE_RRR(SHL
, 6, Y1
):
1108 tcg_gen_andi_tl(tdest
, tsrcb
, 63);
1109 tcg_gen_shl_tl(tdest
, tsrca
, tdest
);
1112 case OE_RRR(SHRS
, 0, X0
):
1113 case OE_RRR(SHRS
, 0, X1
):
1114 case OE_RRR(SHRS
, 6, Y0
):
1115 case OE_RRR(SHRS
, 6, Y1
):
1116 tcg_gen_andi_tl(tdest
, tsrcb
, 63);
1117 tcg_gen_sar_tl(tdest
, tsrca
, tdest
);
1120 case OE_RRR(SHRUX
, 0, X0
):
1121 case OE_RRR(SHRUX
, 0, X1
):
1122 t0
= tcg_temp_new();
1123 tcg_gen_andi_tl(t0
, tsrcb
, 31);
1124 tcg_gen_ext32u_tl(tdest
, tsrca
);
1125 tcg_gen_shr_tl(tdest
, tdest
, t0
);
1126 tcg_gen_ext32s_tl(tdest
, tdest
);
1130 case OE_RRR(SHRU
, 0, X0
):
1131 case OE_RRR(SHRU
, 0, X1
):
1132 case OE_RRR(SHRU
, 6, Y0
):
1133 case OE_RRR(SHRU
, 6, Y1
):
1134 tcg_gen_andi_tl(tdest
, tsrcb
, 63);
1135 tcg_gen_shr_tl(tdest
, tsrca
, tdest
);
1138 case OE_RRR(SHUFFLEBYTES
, 0, X0
):
1139 gen_helper_shufflebytes(tdest
, load_gr(dc
, dest
), tsrca
, tsrca
);
1140 mnemonic
= "shufflebytes";
1142 case OE_RRR(SUBXSC
, 0, X0
):
1143 case OE_RRR(SUBXSC
, 0, X1
):
1144 gen_saturate_op(tdest
, tsrca
, tsrcb
, tcg_gen_sub_tl
);
1145 mnemonic
= "subxsc";
1147 case OE_RRR(SUBX
, 0, X0
):
1148 case OE_RRR(SUBX
, 0, X1
):
1149 case OE_RRR(SUBX
, 0, Y0
):
1150 case OE_RRR(SUBX
, 0, Y1
):
1151 tcg_gen_sub_tl(tdest
, tsrca
, tsrcb
);
1152 tcg_gen_ext32s_tl(tdest
, tdest
);
1155 case OE_RRR(SUB
, 0, X0
):
1156 case OE_RRR(SUB
, 0, X1
):
1157 case OE_RRR(SUB
, 0, Y0
):
1158 case OE_RRR(SUB
, 0, Y1
):
1159 tcg_gen_sub_tl(tdest
, tsrca
, tsrcb
);
1162 case OE_RRR(V1ADDUC
, 0, X0
):
1163 case OE_RRR(V1ADDUC
, 0, X1
):
1164 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1165 case OE_RRR(V1ADD
, 0, X0
):
1166 case OE_RRR(V1ADD
, 0, X1
):
1167 gen_v12add(tdest
, tsrca
, tsrcb
, V1_IMM(0x80));
1170 case OE_RRR(V1ADIFFU
, 0, X0
):
1171 case OE_RRR(V1AVGU
, 0, X0
):
1172 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1173 case OE_RRR(V1CMPEQ
, 0, X0
):
1174 case OE_RRR(V1CMPEQ
, 0, X1
):
1175 tcg_gen_xor_tl(tdest
, tsrca
, tsrcb
);
1176 gen_v1cmpeq0(tdest
);
1177 mnemonic
= "v1cmpeq";
1179 case OE_RRR(V1CMPLES
, 0, X0
):
1180 case OE_RRR(V1CMPLES
, 0, X1
):
1181 case OE_RRR(V1CMPLEU
, 0, X0
):
1182 case OE_RRR(V1CMPLEU
, 0, X1
):
1183 case OE_RRR(V1CMPLTS
, 0, X0
):
1184 case OE_RRR(V1CMPLTS
, 0, X1
):
1185 case OE_RRR(V1CMPLTU
, 0, X0
):
1186 case OE_RRR(V1CMPLTU
, 0, X1
):
1187 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1188 case OE_RRR(V1CMPNE
, 0, X0
):
1189 case OE_RRR(V1CMPNE
, 0, X1
):
1190 tcg_gen_xor_tl(tdest
, tsrca
, tsrcb
);
1191 gen_v1cmpne0(tdest
);
1192 mnemonic
= "v1cmpne";
1194 case OE_RRR(V1DDOTPUA
, 0, X0
):
1195 case OE_RRR(V1DDOTPUSA
, 0, X0
):
1196 case OE_RRR(V1DDOTPUS
, 0, X0
):
1197 case OE_RRR(V1DDOTPU
, 0, X0
):
1198 case OE_RRR(V1DOTPA
, 0, X0
):
1199 case OE_RRR(V1DOTPUA
, 0, X0
):
1200 case OE_RRR(V1DOTPUSA
, 0, X0
):
1201 case OE_RRR(V1DOTPUS
, 0, X0
):
1202 case OE_RRR(V1DOTPU
, 0, X0
):
1203 case OE_RRR(V1DOTP
, 0, X0
):
1204 case OE_RRR(V1INT_H
, 0, X0
):
1205 case OE_RRR(V1INT_H
, 0, X1
):
1206 case OE_RRR(V1INT_L
, 0, X0
):
1207 case OE_RRR(V1INT_L
, 0, X1
):
1208 case OE_RRR(V1MAXU
, 0, X0
):
1209 case OE_RRR(V1MAXU
, 0, X1
):
1210 case OE_RRR(V1MINU
, 0, X0
):
1211 case OE_RRR(V1MINU
, 0, X1
):
1212 case OE_RRR(V1MNZ
, 0, X0
):
1213 case OE_RRR(V1MNZ
, 0, X1
):
1214 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1215 case OE_RRR(V1MULTU
, 0, X0
):
1216 gen_helper_v1multu(tdest
, tsrca
, tsrcb
);
1217 mnemonic
= "v1multu";
1219 case OE_RRR(V1MULUS
, 0, X0
):
1220 case OE_RRR(V1MULU
, 0, X0
):
1221 case OE_RRR(V1MZ
, 0, X0
):
1222 case OE_RRR(V1MZ
, 0, X1
):
1223 case OE_RRR(V1SADAU
, 0, X0
):
1224 case OE_RRR(V1SADU
, 0, X0
):
1225 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1226 case OE_RRR(V1SHL
, 0, X0
):
1227 case OE_RRR(V1SHL
, 0, X1
):
1228 gen_helper_v1shl(tdest
, tsrca
, tsrcb
);
1231 case OE_RRR(V1SHRS
, 0, X0
):
1232 case OE_RRR(V1SHRS
, 0, X1
):
1233 gen_helper_v1shrs(tdest
, tsrca
, tsrcb
);
1234 mnemonic
= "v1shrs";
1236 case OE_RRR(V1SHRU
, 0, X0
):
1237 case OE_RRR(V1SHRU
, 0, X1
):
1238 gen_helper_v1shru(tdest
, tsrca
, tsrcb
);
1239 mnemonic
= "v1shru";
1241 case OE_RRR(V1SUBUC
, 0, X0
):
1242 case OE_RRR(V1SUBUC
, 0, X1
):
1243 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1244 case OE_RRR(V1SUB
, 0, X0
):
1245 case OE_RRR(V1SUB
, 0, X1
):
1246 gen_v12sub(tdest
, tsrca
, tsrcb
, V1_IMM(0x80));
1249 case OE_RRR(V2ADDSC
, 0, X0
):
1250 case OE_RRR(V2ADDSC
, 0, X1
):
1251 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1252 case OE_RRR(V2ADD
, 0, X0
):
1253 case OE_RRR(V2ADD
, 0, X1
):
1254 gen_v12add(tdest
, tsrca
, tsrcb
, V2_IMM(0x8000));
1257 case OE_RRR(V2ADIFFS
, 0, X0
):
1258 case OE_RRR(V2AVGS
, 0, X0
):
1259 case OE_RRR(V2CMPEQ
, 0, X0
):
1260 case OE_RRR(V2CMPEQ
, 0, X1
):
1261 case OE_RRR(V2CMPLES
, 0, X0
):
1262 case OE_RRR(V2CMPLES
, 0, X1
):
1263 case OE_RRR(V2CMPLEU
, 0, X0
):
1264 case OE_RRR(V2CMPLEU
, 0, X1
):
1265 case OE_RRR(V2CMPLTS
, 0, X0
):
1266 case OE_RRR(V2CMPLTS
, 0, X1
):
1267 case OE_RRR(V2CMPLTU
, 0, X0
):
1268 case OE_RRR(V2CMPLTU
, 0, X1
):
1269 case OE_RRR(V2CMPNE
, 0, X0
):
1270 case OE_RRR(V2CMPNE
, 0, X1
):
1271 case OE_RRR(V2DOTPA
, 0, X0
):
1272 case OE_RRR(V2DOTP
, 0, X0
):
1273 case OE_RRR(V2INT_H
, 0, X0
):
1274 case OE_RRR(V2INT_H
, 0, X1
):
1275 case OE_RRR(V2INT_L
, 0, X0
):
1276 case OE_RRR(V2INT_L
, 0, X1
):
1277 case OE_RRR(V2MAXS
, 0, X0
):
1278 case OE_RRR(V2MAXS
, 0, X1
):
1279 case OE_RRR(V2MINS
, 0, X0
):
1280 case OE_RRR(V2MINS
, 0, X1
):
1281 case OE_RRR(V2MNZ
, 0, X0
):
1282 case OE_RRR(V2MNZ
, 0, X1
):
1283 case OE_RRR(V2MULFSC
, 0, X0
):
1284 case OE_RRR(V2MULS
, 0, X0
):
1285 case OE_RRR(V2MULTS
, 0, X0
):
1286 case OE_RRR(V2MZ
, 0, X0
):
1287 case OE_RRR(V2MZ
, 0, X1
):
1288 case OE_RRR(V2PACKH
, 0, X0
):
1289 case OE_RRR(V2PACKH
, 0, X1
):
1290 case OE_RRR(V2PACKL
, 0, X0
):
1291 case OE_RRR(V2PACKL
, 0, X1
):
1292 case OE_RRR(V2PACKUC
, 0, X0
):
1293 case OE_RRR(V2PACKUC
, 0, X1
):
1294 case OE_RRR(V2SADAS
, 0, X0
):
1295 case OE_RRR(V2SADAU
, 0, X0
):
1296 case OE_RRR(V2SADS
, 0, X0
):
1297 case OE_RRR(V2SADU
, 0, X0
):
1298 case OE_RRR(V2SHLSC
, 0, X0
):
1299 case OE_RRR(V2SHLSC
, 0, X1
):
1300 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1301 case OE_RRR(V2SHL
, 0, X0
):
1302 case OE_RRR(V2SHL
, 0, X1
):
1303 gen_helper_v2shl(tdest
, tsrca
, tsrcb
);
1306 case OE_RRR(V2SHRS
, 0, X0
):
1307 case OE_RRR(V2SHRS
, 0, X1
):
1308 gen_helper_v2shrs(tdest
, tsrca
, tsrcb
);
1309 mnemonic
= "v2shrs";
1311 case OE_RRR(V2SHRU
, 0, X0
):
1312 case OE_RRR(V2SHRU
, 0, X1
):
1313 gen_helper_v2shru(tdest
, tsrca
, tsrcb
);
1314 mnemonic
= "v2shru";
1316 case OE_RRR(V2SUBSC
, 0, X0
):
1317 case OE_RRR(V2SUBSC
, 0, X1
):
1318 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1319 case OE_RRR(V2SUB
, 0, X0
):
1320 case OE_RRR(V2SUB
, 0, X1
):
1321 gen_v12sub(tdest
, tsrca
, tsrcb
, V2_IMM(0x8000));
1324 case OE_RRR(V4ADDSC
, 0, X0
):
1325 case OE_RRR(V4ADDSC
, 0, X1
):
1326 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1327 case OE_RRR(V4ADD
, 0, X0
):
1328 case OE_RRR(V4ADD
, 0, X1
):
1329 gen_v4op(tdest
, tsrca
, tsrcb
, tcg_gen_add_i32
);
1332 case OE_RRR(V4INT_H
, 0, X0
):
1333 case OE_RRR(V4INT_H
, 0, X1
):
1334 tcg_gen_shri_tl(tdest
, tsrcb
, 32);
1335 tcg_gen_deposit_tl(tdest
, tsrca
, tdest
, 0, 32);
1336 mnemonic
= "v4int_h";
1338 case OE_RRR(V4INT_L
, 0, X0
):
1339 case OE_RRR(V4INT_L
, 0, X1
):
1340 tcg_gen_deposit_tl(tdest
, tsrcb
, tsrca
, 32, 32);
1341 mnemonic
= "v4int_l";
1343 case OE_RRR(V4PACKSC
, 0, X0
):
1344 case OE_RRR(V4PACKSC
, 0, X1
):
1345 case OE_RRR(V4SHLSC
, 0, X0
):
1346 case OE_RRR(V4SHLSC
, 0, X1
):
1347 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1348 case OE_RRR(V4SHL
, 0, X0
):
1349 case OE_RRR(V4SHL
, 0, X1
):
1350 gen_v4sh(tdest
, tsrca
, tsrcb
, tcg_gen_shl_i32
);
1353 case OE_RRR(V4SHRS
, 0, X0
):
1354 case OE_RRR(V4SHRS
, 0, X1
):
1355 gen_v4sh(tdest
, tsrca
, tsrcb
, tcg_gen_sar_i32
);
1356 mnemonic
= "v4shrs";
1358 case OE_RRR(V4SHRU
, 0, X0
):
1359 case OE_RRR(V4SHRU
, 0, X1
):
1360 gen_v4sh(tdest
, tsrca
, tsrcb
, tcg_gen_shr_i32
);
1361 mnemonic
= "v4shru";
1363 case OE_RRR(V4SUBSC
, 0, X0
):
1364 case OE_RRR(V4SUBSC
, 0, X1
):
1365 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1366 case OE_RRR(V4SUB
, 0, X0
):
1367 case OE_RRR(V4SUB
, 0, X1
):
1368 gen_v4op(tdest
, tsrca
, tsrcb
, tcg_gen_sub_i32
);
1371 case OE_RRR(XOR
, 0, X0
):
1372 case OE_RRR(XOR
, 0, X1
):
1373 case OE_RRR(XOR
, 5, Y0
):
1374 case OE_RRR(XOR
, 5, Y1
):
1375 tcg_gen_xor_tl(tdest
, tsrca
, tsrcb
);
1379 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1382 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %s", mnemonic
,
1383 reg_names
[dest
], reg_names
[srca
], reg_names
[srcb
]);
1384 return TILEGX_EXCP_NONE
;
1387 static TileExcp
gen_rri_opcode(DisasContext
*dc
, unsigned opext
,
1388 unsigned dest
, unsigned srca
, int imm
)
1390 TCGv tdest
= dest_gr(dc
, dest
);
1391 TCGv tsrca
= load_gr(dc
, srca
);
1392 const char *mnemonic
;
1398 case OE(ADDI_OPCODE_Y0
, 0, Y0
):
1399 case OE(ADDI_OPCODE_Y1
, 0, Y1
):
1400 case OE_IM(ADDI
, X0
):
1401 case OE_IM(ADDI
, X1
):
1402 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
1405 case OE(ADDXI_OPCODE_Y0
, 0, Y0
):
1406 case OE(ADDXI_OPCODE_Y1
, 0, Y1
):
1407 case OE_IM(ADDXI
, X0
):
1408 case OE_IM(ADDXI
, X1
):
1409 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
1410 tcg_gen_ext32s_tl(tdest
, tdest
);
1413 case OE(ANDI_OPCODE_Y0
, 0, Y0
):
1414 case OE(ANDI_OPCODE_Y1
, 0, Y1
):
1415 case OE_IM(ANDI
, X0
):
1416 case OE_IM(ANDI
, X1
):
1417 tcg_gen_andi_tl(tdest
, tsrca
, imm
);
1420 case OE(CMPEQI_OPCODE_Y0
, 0, Y0
):
1421 case OE(CMPEQI_OPCODE_Y1
, 0, Y1
):
1422 case OE_IM(CMPEQI
, X0
):
1423 case OE_IM(CMPEQI
, X1
):
1424 tcg_gen_setcondi_tl(TCG_COND_EQ
, tdest
, tsrca
, imm
);
1425 mnemonic
= "cmpeqi";
1427 case OE(CMPLTSI_OPCODE_Y0
, 0, Y0
):
1428 case OE(CMPLTSI_OPCODE_Y1
, 0, Y1
):
1429 case OE_IM(CMPLTSI
, X0
):
1430 case OE_IM(CMPLTSI
, X1
):
1431 tcg_gen_setcondi_tl(TCG_COND_LT
, tdest
, tsrca
, imm
);
1432 mnemonic
= "cmpltsi";
1434 case OE_IM(CMPLTUI
, X0
):
1435 case OE_IM(CMPLTUI
, X1
):
1436 tcg_gen_setcondi_tl(TCG_COND_LTU
, tdest
, tsrca
, imm
);
1437 mnemonic
= "cmpltui";
1439 case OE_IM(LD1S_ADD
, X1
):
1441 mnemonic
= "ld1s_add";
1443 case OE_IM(LD1U_ADD
, X1
):
1445 mnemonic
= "ld1u_add";
1447 case OE_IM(LD2S_ADD
, X1
):
1449 mnemonic
= "ld2s_add";
1451 case OE_IM(LD2U_ADD
, X1
):
1453 mnemonic
= "ld2u_add";
1455 case OE_IM(LD4S_ADD
, X1
):
1457 mnemonic
= "ld4s_add";
1459 case OE_IM(LD4U_ADD
, X1
):
1461 mnemonic
= "ld4u_add";
1463 case OE_IM(LDNT1S_ADD
, X1
):
1465 mnemonic
= "ldnt1s_add";
1467 case OE_IM(LDNT1U_ADD
, X1
):
1469 mnemonic
= "ldnt1u_add";
1471 case OE_IM(LDNT2S_ADD
, X1
):
1473 mnemonic
= "ldnt2s_add";
1475 case OE_IM(LDNT2U_ADD
, X1
):
1477 mnemonic
= "ldnt2u_add";
1479 case OE_IM(LDNT4S_ADD
, X1
):
1481 mnemonic
= "ldnt4s_add";
1483 case OE_IM(LDNT4U_ADD
, X1
):
1485 mnemonic
= "ldnt4u_add";
1487 case OE_IM(LDNT_ADD
, X1
):
1489 mnemonic
= "ldnt_add";
1491 case OE_IM(LD_ADD
, X1
):
1493 mnemonic
= "ldnt_add";
1495 tcg_gen_qemu_ld_tl(tdest
, tsrca
, dc
->mmuidx
, memop
);
1496 tcg_gen_addi_tl(dest_gr(dc
, srca
), tsrca
, imm
);
1498 case OE_IM(LDNA_ADD
, X1
):
1499 tcg_gen_andi_tl(tdest
, tsrca
, ~7);
1500 tcg_gen_qemu_ld_tl(tdest
, tdest
, dc
->mmuidx
, MO_TEQ
);
1501 tcg_gen_addi_tl(dest_gr(dc
, srca
), tsrca
, imm
);
1502 mnemonic
= "ldna_add";
1504 case OE_IM(ORI
, X0
):
1505 case OE_IM(ORI
, X1
):
1506 tcg_gen_ori_tl(tdest
, tsrca
, imm
);
1509 case OE_IM(V1ADDI
, X0
):
1510 case OE_IM(V1ADDI
, X1
):
1511 t0
= tcg_const_tl(V1_IMM(imm
));
1512 gen_v12add(tdest
, tsrca
, t0
, V1_IMM(0x80));
1514 mnemonic
= "v1addi";
1516 case OE_IM(V1CMPEQI
, X0
):
1517 case OE_IM(V1CMPEQI
, X1
):
1518 tcg_gen_xori_tl(tdest
, tsrca
, V1_IMM(imm
));
1519 gen_v1cmpeq0(tdest
);
1520 mnemonic
= "v1cmpeqi";
1522 case OE_IM(V1CMPLTSI
, X0
):
1523 case OE_IM(V1CMPLTSI
, X1
):
1524 case OE_IM(V1CMPLTUI
, X0
):
1525 case OE_IM(V1CMPLTUI
, X1
):
1526 case OE_IM(V1MAXUI
, X0
):
1527 case OE_IM(V1MAXUI
, X1
):
1528 case OE_IM(V1MINUI
, X0
):
1529 case OE_IM(V1MINUI
, X1
):
1530 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1531 case OE_IM(V2ADDI
, X0
):
1532 case OE_IM(V2ADDI
, X1
):
1533 t0
= tcg_const_tl(V2_IMM(imm
));
1534 gen_v12add(tdest
, tsrca
, t0
, V2_IMM(0x8000));
1536 mnemonic
= "v2addi";
1538 case OE_IM(V2CMPEQI
, X0
):
1539 case OE_IM(V2CMPEQI
, X1
):
1540 case OE_IM(V2CMPLTSI
, X0
):
1541 case OE_IM(V2CMPLTSI
, X1
):
1542 case OE_IM(V2CMPLTUI
, X0
):
1543 case OE_IM(V2CMPLTUI
, X1
):
1544 case OE_IM(V2MAXSI
, X0
):
1545 case OE_IM(V2MAXSI
, X1
):
1546 case OE_IM(V2MINSI
, X0
):
1547 case OE_IM(V2MINSI
, X1
):
1548 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1549 case OE_IM(XORI
, X0
):
1550 case OE_IM(XORI
, X1
):
1551 tcg_gen_xori_tl(tdest
, tsrca
, imm
);
1555 case OE_SH(ROTLI
, X0
):
1556 case OE_SH(ROTLI
, X1
):
1557 case OE_SH(ROTLI
, Y0
):
1558 case OE_SH(ROTLI
, Y1
):
1559 tcg_gen_rotli_tl(tdest
, tsrca
, imm
);
1562 case OE_SH(SHLI
, X0
):
1563 case OE_SH(SHLI
, X1
):
1564 case OE_SH(SHLI
, Y0
):
1565 case OE_SH(SHLI
, Y1
):
1566 tcg_gen_shli_tl(tdest
, tsrca
, imm
);
1569 case OE_SH(SHLXI
, X0
):
1570 case OE_SH(SHLXI
, X1
):
1571 tcg_gen_shli_tl(tdest
, tsrca
, imm
& 31);
1572 tcg_gen_ext32s_tl(tdest
, tdest
);
1575 case OE_SH(SHRSI
, X0
):
1576 case OE_SH(SHRSI
, X1
):
1577 case OE_SH(SHRSI
, Y0
):
1578 case OE_SH(SHRSI
, Y1
):
1579 tcg_gen_sari_tl(tdest
, tsrca
, imm
);
1582 case OE_SH(SHRUI
, X0
):
1583 case OE_SH(SHRUI
, X1
):
1584 case OE_SH(SHRUI
, Y0
):
1585 case OE_SH(SHRUI
, Y1
):
1586 tcg_gen_shri_tl(tdest
, tsrca
, imm
);
1589 case OE_SH(SHRUXI
, X0
):
1590 case OE_SH(SHRUXI
, X1
):
1591 if ((imm
& 31) == 0) {
1592 tcg_gen_ext32s_tl(tdest
, tsrca
);
1594 tcg_gen_ext32u_tl(tdest
, tsrca
);
1595 tcg_gen_shri_tl(tdest
, tdest
, imm
& 31);
1599 case OE_SH(V1SHLI
, X0
):
1600 case OE_SH(V1SHLI
, X1
):
1603 tcg_gen_andi_tl(tdest
, tsrca
, V1_IMM(i3
));
1604 tcg_gen_shli_tl(tdest
, tdest
, i2
);
1605 mnemonic
= "v1shli";
1607 case OE_SH(V1SHRSI
, X0
):
1608 case OE_SH(V1SHRSI
, X1
):
1609 t0
= tcg_const_tl(imm
& 7);
1610 gen_helper_v1shrs(tdest
, tsrca
, t0
);
1612 mnemonic
= "v1shrsi";
1614 case OE_SH(V1SHRUI
, X0
):
1615 case OE_SH(V1SHRUI
, X1
):
1617 i3
= (0xff << i2
) & 0xff;
1618 tcg_gen_andi_tl(tdest
, tsrca
, V1_IMM(i3
));
1619 tcg_gen_shri_tl(tdest
, tdest
, i2
);
1620 mnemonic
= "v1shrui";
1622 case OE_SH(V2SHLI
, X0
):
1623 case OE_SH(V2SHLI
, X1
):
1624 case OE_SH(V2SHRSI
, X0
):
1625 case OE_SH(V2SHRSI
, X1
):
1626 case OE_SH(V2SHRUI
, X0
):
1627 case OE_SH(V2SHRUI
, X1
):
1628 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1630 case OE(ADDLI_OPCODE_X0
, 0, X0
):
1631 case OE(ADDLI_OPCODE_X1
, 0, X1
):
1632 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
1635 case OE(ADDXLI_OPCODE_X0
, 0, X0
):
1636 case OE(ADDXLI_OPCODE_X1
, 0, X1
):
1637 tcg_gen_addi_tl(tdest
, tsrca
, imm
);
1638 tcg_gen_ext32s_tl(tdest
, tdest
);
1639 mnemonic
= "addxli";
1641 case OE(SHL16INSLI_OPCODE_X0
, 0, X0
):
1642 case OE(SHL16INSLI_OPCODE_X1
, 0, X1
):
1643 tcg_gen_shli_tl(tdest
, tsrca
, 16);
1644 tcg_gen_ori_tl(tdest
, tdest
, imm
& 0xffff);
1645 mnemonic
= "shl16insli";
1649 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1652 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %d", mnemonic
,
1653 reg_names
[dest
], reg_names
[srca
], imm
);
1654 return TILEGX_EXCP_NONE
;
1657 static TileExcp
gen_bf_opcode_x0(DisasContext
*dc
, unsigned ext
,
1658 unsigned dest
, unsigned srca
,
1659 unsigned bfs
, unsigned bfe
)
1661 TCGv tdest
= dest_gr(dc
, dest
);
1662 TCGv tsrca
= load_gr(dc
, srca
);
1665 const char *mnemonic
;
1667 /* The bitfield is either between E and S inclusive,
1668 or up from S and down from E inclusive. */
1670 len
= bfe
- bfs
+ 1;
1672 len
= (64 - bfs
) + (bfe
+ 1);
1676 case BFEXTU_BF_OPCODE_X0
:
1677 if (bfs
== 0 && bfe
== 7) {
1678 tcg_gen_ext8u_tl(tdest
, tsrca
);
1679 } else if (bfs
== 0 && bfe
== 15) {
1680 tcg_gen_ext16u_tl(tdest
, tsrca
);
1681 } else if (bfs
== 0 && bfe
== 31) {
1682 tcg_gen_ext32u_tl(tdest
, tsrca
);
1686 tcg_gen_shli_tl(tdest
, tsrca
, rol
);
1688 tcg_gen_rotli_tl(tdest
, tsrca
, rol
);
1690 tcg_gen_shri_tl(tdest
, tdest
, (bfs
+ rol
) & 63);
1692 mnemonic
= "bfextu";
1695 case BFEXTS_BF_OPCODE_X0
:
1696 if (bfs
== 0 && bfe
== 7) {
1697 tcg_gen_ext8s_tl(tdest
, tsrca
);
1698 } else if (bfs
== 0 && bfe
== 15) {
1699 tcg_gen_ext16s_tl(tdest
, tsrca
);
1700 } else if (bfs
== 0 && bfe
== 31) {
1701 tcg_gen_ext32s_tl(tdest
, tsrca
);
1705 tcg_gen_shli_tl(tdest
, tsrca
, rol
);
1707 tcg_gen_rotli_tl(tdest
, tsrca
, rol
);
1709 tcg_gen_sari_tl(tdest
, tdest
, (bfs
+ rol
) & 63);
1711 mnemonic
= "bfexts";
1714 case BFINS_BF_OPCODE_X0
:
1715 tsrcd
= load_gr(dc
, dest
);
1717 tcg_gen_deposit_tl(tdest
, tsrcd
, tsrca
, bfs
, len
);
1719 tcg_gen_rotri_tl(tdest
, tsrcd
, bfs
);
1720 tcg_gen_deposit_tl(tdest
, tdest
, tsrca
, 0, len
);
1721 tcg_gen_rotli_tl(tdest
, tdest
, bfs
);
1726 case MM_BF_OPCODE_X0
:
1727 tsrcd
= load_gr(dc
, dest
);
1729 tcg_gen_deposit_tl(tdest
, tsrca
, tsrcd
, 0, len
);
1731 uint64_t mask
= len
== 64 ? -1 : rol64((1ULL << len
) - 1, bfs
);
1732 TCGv tmp
= tcg_const_tl(mask
);
1734 tcg_gen_and_tl(tdest
, tsrcd
, tmp
);
1735 tcg_gen_andc_tl(tmp
, tsrca
, tmp
);
1736 tcg_gen_or_tl(tdest
, tdest
, tmp
);
1743 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1746 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s, %u, %u", mnemonic
,
1747 reg_names
[dest
], reg_names
[srca
], bfs
, bfe
);
1748 return TILEGX_EXCP_NONE
;
1751 static TileExcp
gen_branch_opcode_x1(DisasContext
*dc
, unsigned ext
,
1752 unsigned srca
, int off
)
1754 target_ulong tgt
= dc
->pc
+ off
* TILEGX_BUNDLE_SIZE_IN_BYTES
;
1755 const char *mnemonic
;
1757 dc
->jmp
.dest
= tcg_const_tl(tgt
);
1758 dc
->jmp
.val1
= tcg_temp_new();
1759 tcg_gen_mov_tl(dc
->jmp
.val1
, load_gr(dc
, srca
));
1761 /* Note that the "predict taken" opcodes have bit 0 clear.
1762 Therefore, fold the two cases together by setting bit 0. */
1764 case BEQZ_BRANCH_OPCODE_X1
:
1765 dc
->jmp
.cond
= TCG_COND_EQ
;
1768 case BNEZ_BRANCH_OPCODE_X1
:
1769 dc
->jmp
.cond
= TCG_COND_NE
;
1772 case BGEZ_BRANCH_OPCODE_X1
:
1773 dc
->jmp
.cond
= TCG_COND_GE
;
1776 case BGTZ_BRANCH_OPCODE_X1
:
1777 dc
->jmp
.cond
= TCG_COND_GT
;
1780 case BLEZ_BRANCH_OPCODE_X1
:
1781 dc
->jmp
.cond
= TCG_COND_LE
;
1784 case BLTZ_BRANCH_OPCODE_X1
:
1785 dc
->jmp
.cond
= TCG_COND_LT
;
1788 case BLBC_BRANCH_OPCODE_X1
:
1789 dc
->jmp
.cond
= TCG_COND_EQ
;
1790 tcg_gen_andi_tl(dc
->jmp
.val1
, dc
->jmp
.val1
, 1);
1793 case BLBS_BRANCH_OPCODE_X1
:
1794 dc
->jmp
.cond
= TCG_COND_NE
;
1795 tcg_gen_andi_tl(dc
->jmp
.val1
, dc
->jmp
.val1
, 1);
1799 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1802 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1803 qemu_log("%s%s %s, " TARGET_FMT_lx
" <%s>",
1804 mnemonic
, ext
& 1 ? "" : "t",
1805 reg_names
[srca
], tgt
, lookup_symbol(tgt
));
1807 return TILEGX_EXCP_NONE
;
1810 static TileExcp
gen_jump_opcode_x1(DisasContext
*dc
, unsigned ext
, int off
)
1812 target_ulong tgt
= dc
->pc
+ off
* TILEGX_BUNDLE_SIZE_IN_BYTES
;
1813 const char *mnemonic
= "j";
1815 /* The extension field is 1 bit, therefore we only have JAL and J. */
1816 if (ext
== JAL_JUMP_OPCODE_X1
) {
1817 tcg_gen_movi_tl(dest_gr(dc
, TILEGX_R_LR
),
1818 dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
1821 dc
->jmp
.cond
= TCG_COND_ALWAYS
;
1822 dc
->jmp
.dest
= tcg_const_tl(tgt
);
1824 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1825 qemu_log("%s " TARGET_FMT_lx
" <%s>",
1826 mnemonic
, tgt
, lookup_symbol(tgt
));
1828 return TILEGX_EXCP_NONE
;
1834 void (*get
)(TCGv
, TCGv_ptr
);
1835 void (*put
)(TCGv_ptr
, TCGv
);
1838 static const TileSPR
*find_spr(unsigned spr
)
1840 /* Allow the compiler to construct the binary search tree. */
1841 #define D(N, O, G, P) \
1842 case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
1846 offsetof(CPUTLGState
, spregs
[TILEGX_SPR_CMPEXCH
]), 0, 0)
1847 D(INTERRUPT_CRITICAL_SECTION
,
1848 offsetof(CPUTLGState
, spregs
[TILEGX_SPR_CRITICAL_SEC
]), 0, 0)
1850 offsetof(CPUTLGState
, spregs
[TILEGX_SPR_SIM_CONTROL
]), 0, 0)
1855 qemu_log_mask(LOG_UNIMP
, "UNIMP SPR %u\n", spr
);
1859 static TileExcp
gen_mtspr_x1(DisasContext
*dc
, unsigned spr
, unsigned srca
)
1861 const TileSPR
*def
= find_spr(spr
);
1865 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "mtspr spr[%u], %s", spr
, reg_names
[srca
]);
1866 return TILEGX_EXCP_OPCODE_UNKNOWN
;
1869 tsrca
= load_gr(dc
, srca
);
1871 def
->put(cpu_env
, tsrca
);
1873 tcg_gen_st_tl(tsrca
, cpu_env
, def
->offset
);
1875 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "mtspr %s, %s", def
->name
, reg_names
[srca
]);
1876 return TILEGX_EXCP_NONE
;
1879 static TileExcp
gen_mfspr_x1(DisasContext
*dc
, unsigned dest
, unsigned spr
)
1881 const TileSPR
*def
= find_spr(spr
);
1885 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "mtspr %s, spr[%u]", reg_names
[dest
], spr
);
1886 return TILEGX_EXCP_OPCODE_UNKNOWN
;
1889 tdest
= dest_gr(dc
, dest
);
1891 def
->get(tdest
, cpu_env
);
1893 tcg_gen_ld_tl(tdest
, cpu_env
, def
->offset
);
1895 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "mfspr %s, %s", reg_names
[dest
], def
->name
);
1896 return TILEGX_EXCP_NONE
;
1899 static TileExcp
decode_y0(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1901 unsigned opc
= get_Opcode_Y0(bundle
);
1902 unsigned ext
= get_RRROpcodeExtension_Y0(bundle
);
1903 unsigned dest
= get_Dest_Y0(bundle
);
1904 unsigned srca
= get_SrcA_Y0(bundle
);
1909 case RRR_1_OPCODE_Y0
:
1910 if (ext
== UNARY_RRR_1_OPCODE_Y0
) {
1911 ext
= get_UnaryOpcodeExtension_Y0(bundle
);
1912 return gen_rr_opcode(dc
, OE(opc
, ext
, Y0
), dest
, srca
);
1915 case RRR_0_OPCODE_Y0
:
1916 case RRR_2_OPCODE_Y0
:
1917 case RRR_3_OPCODE_Y0
:
1918 case RRR_4_OPCODE_Y0
:
1919 case RRR_5_OPCODE_Y0
:
1920 case RRR_6_OPCODE_Y0
:
1921 case RRR_7_OPCODE_Y0
:
1922 case RRR_8_OPCODE_Y0
:
1923 case RRR_9_OPCODE_Y0
:
1924 srcb
= get_SrcB_Y0(bundle
);
1925 return gen_rrr_opcode(dc
, OE(opc
, ext
, Y0
), dest
, srca
, srcb
);
1927 case SHIFT_OPCODE_Y0
:
1928 ext
= get_ShiftOpcodeExtension_Y0(bundle
);
1929 imm
= get_ShAmt_Y0(bundle
);
1930 return gen_rri_opcode(dc
, OE(opc
, ext
, Y0
), dest
, srca
, imm
);
1932 case ADDI_OPCODE_Y0
:
1933 case ADDXI_OPCODE_Y0
:
1934 case ANDI_OPCODE_Y0
:
1935 case CMPEQI_OPCODE_Y0
:
1936 case CMPLTSI_OPCODE_Y0
:
1937 imm
= (int8_t)get_Imm8_Y0(bundle
);
1938 return gen_rri_opcode(dc
, OE(opc
, 0, Y0
), dest
, srca
, imm
);
1941 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1945 static TileExcp
decode_y1(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1947 unsigned opc
= get_Opcode_Y1(bundle
);
1948 unsigned ext
= get_RRROpcodeExtension_Y1(bundle
);
1949 unsigned dest
= get_Dest_Y1(bundle
);
1950 unsigned srca
= get_SrcA_Y1(bundle
);
1954 switch (get_Opcode_Y1(bundle
)) {
1955 case RRR_1_OPCODE_Y1
:
1956 if (ext
== UNARY_RRR_1_OPCODE_Y0
) {
1957 ext
= get_UnaryOpcodeExtension_Y1(bundle
);
1958 return gen_rr_opcode(dc
, OE(opc
, ext
, Y1
), dest
, srca
);
1961 case RRR_0_OPCODE_Y1
:
1962 case RRR_2_OPCODE_Y1
:
1963 case RRR_3_OPCODE_Y1
:
1964 case RRR_4_OPCODE_Y1
:
1965 case RRR_5_OPCODE_Y1
:
1966 case RRR_6_OPCODE_Y1
:
1967 case RRR_7_OPCODE_Y1
:
1968 srcb
= get_SrcB_Y1(bundle
);
1969 return gen_rrr_opcode(dc
, OE(opc
, ext
, Y1
), dest
, srca
, srcb
);
1971 case SHIFT_OPCODE_Y1
:
1972 ext
= get_ShiftOpcodeExtension_Y1(bundle
);
1973 imm
= get_ShAmt_Y1(bundle
);
1974 return gen_rri_opcode(dc
, OE(opc
, ext
, Y1
), dest
, srca
, imm
);
1976 case ADDI_OPCODE_Y1
:
1977 case ADDXI_OPCODE_Y1
:
1978 case ANDI_OPCODE_Y1
:
1979 case CMPEQI_OPCODE_Y1
:
1980 case CMPLTSI_OPCODE_Y1
:
1981 imm
= (int8_t)get_Imm8_Y1(bundle
);
1982 return gen_rri_opcode(dc
, OE(opc
, 0, Y1
), dest
, srca
, imm
);
1985 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
1989 static TileExcp
decode_y2(DisasContext
*dc
, tilegx_bundle_bits bundle
)
1991 unsigned mode
= get_Mode(bundle
);
1992 unsigned opc
= get_Opcode_Y2(bundle
);
1993 unsigned srca
= get_SrcA_Y2(bundle
);
1994 unsigned srcbdest
= get_SrcBDest_Y2(bundle
);
1995 const char *mnemonic
;
1998 switch (OEY2(opc
, mode
)) {
1999 case OEY2(LD1S_OPCODE_Y2
, MODE_OPCODE_YA2
):
2003 case OEY2(LD1U_OPCODE_Y2
, MODE_OPCODE_YA2
):
2007 case OEY2(LD2S_OPCODE_Y2
, MODE_OPCODE_YA2
):
2011 case OEY2(LD2U_OPCODE_Y2
, MODE_OPCODE_YA2
):
2015 case OEY2(LD4S_OPCODE_Y2
, MODE_OPCODE_YB2
):
2019 case OEY2(LD4U_OPCODE_Y2
, MODE_OPCODE_YB2
):
2023 case OEY2(LD_OPCODE_Y2
, MODE_OPCODE_YB2
):
2027 tcg_gen_qemu_ld_tl(dest_gr(dc
, srcbdest
), load_gr(dc
, srca
),
2029 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "%s %s, %s", mnemonic
,
2030 reg_names
[srcbdest
], reg_names
[srca
]);
2031 return TILEGX_EXCP_NONE
;
2033 case OEY2(ST1_OPCODE_Y2
, MODE_OPCODE_YC2
):
2034 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_UB
, "st1");
2035 case OEY2(ST2_OPCODE_Y2
, MODE_OPCODE_YC2
):
2036 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_TEUW
, "st2");
2037 case OEY2(ST4_OPCODE_Y2
, MODE_OPCODE_YC2
):
2038 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_TEUL
, "st4");
2039 case OEY2(ST_OPCODE_Y2
, MODE_OPCODE_YC2
):
2040 return gen_st_opcode(dc
, 0, srca
, srcbdest
, MO_TEQ
, "st");
2043 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
2047 static TileExcp
decode_x0(DisasContext
*dc
, tilegx_bundle_bits bundle
)
2049 unsigned opc
= get_Opcode_X0(bundle
);
2050 unsigned dest
= get_Dest_X0(bundle
);
2051 unsigned srca
= get_SrcA_X0(bundle
);
2052 unsigned ext
, srcb
, bfs
, bfe
;
2056 case RRR_0_OPCODE_X0
:
2057 ext
= get_RRROpcodeExtension_X0(bundle
);
2058 if (ext
== UNARY_RRR_0_OPCODE_X0
) {
2059 ext
= get_UnaryOpcodeExtension_X0(bundle
);
2060 return gen_rr_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
);
2062 srcb
= get_SrcB_X0(bundle
);
2063 return gen_rrr_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
, srcb
);
2065 case SHIFT_OPCODE_X0
:
2066 ext
= get_ShiftOpcodeExtension_X0(bundle
);
2067 imm
= get_ShAmt_X0(bundle
);
2068 return gen_rri_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
, imm
);
2070 case IMM8_OPCODE_X0
:
2071 ext
= get_Imm8OpcodeExtension_X0(bundle
);
2072 imm
= (int8_t)get_Imm8_X0(bundle
);
2073 return gen_rri_opcode(dc
, OE(opc
, ext
, X0
), dest
, srca
, imm
);
2076 ext
= get_BFOpcodeExtension_X0(bundle
);
2077 bfs
= get_BFStart_X0(bundle
);
2078 bfe
= get_BFEnd_X0(bundle
);
2079 return gen_bf_opcode_x0(dc
, ext
, dest
, srca
, bfs
, bfe
);
2081 case ADDLI_OPCODE_X0
:
2082 case SHL16INSLI_OPCODE_X0
:
2083 case ADDXLI_OPCODE_X0
:
2084 imm
= (int16_t)get_Imm16_X0(bundle
);
2085 return gen_rri_opcode(dc
, OE(opc
, 0, X0
), dest
, srca
, imm
);
2088 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
2092 static TileExcp
decode_x1(DisasContext
*dc
, tilegx_bundle_bits bundle
)
2094 unsigned opc
= get_Opcode_X1(bundle
);
2095 unsigned dest
= get_Dest_X1(bundle
);
2096 unsigned srca
= get_SrcA_X1(bundle
);
2101 case RRR_0_OPCODE_X1
:
2102 ext
= get_RRROpcodeExtension_X1(bundle
);
2103 srcb
= get_SrcB_X1(bundle
);
2105 case UNARY_RRR_0_OPCODE_X1
:
2106 ext
= get_UnaryOpcodeExtension_X1(bundle
);
2107 return gen_rr_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
);
2108 case ST1_RRR_0_OPCODE_X1
:
2109 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_UB
, "st1");
2110 case ST2_RRR_0_OPCODE_X1
:
2111 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUW
, "st2");
2112 case ST4_RRR_0_OPCODE_X1
:
2113 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUL
, "st4");
2114 case STNT1_RRR_0_OPCODE_X1
:
2115 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_UB
, "stnt1");
2116 case STNT2_RRR_0_OPCODE_X1
:
2117 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUW
, "stnt2");
2118 case STNT4_RRR_0_OPCODE_X1
:
2119 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEUL
, "stnt4");
2120 case STNT_RRR_0_OPCODE_X1
:
2121 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEQ
, "stnt");
2122 case ST_RRR_0_OPCODE_X1
:
2123 return gen_st_opcode(dc
, dest
, srca
, srcb
, MO_TEQ
, "st");
2125 return gen_rrr_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
, srcb
);
2127 case SHIFT_OPCODE_X1
:
2128 ext
= get_ShiftOpcodeExtension_X1(bundle
);
2129 imm
= get_ShAmt_X1(bundle
);
2130 return gen_rri_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
, imm
);
2132 case IMM8_OPCODE_X1
:
2133 ext
= get_Imm8OpcodeExtension_X1(bundle
);
2134 imm
= (int8_t)get_Dest_Imm8_X1(bundle
);
2135 srcb
= get_SrcB_X1(bundle
);
2137 case ST1_ADD_IMM8_OPCODE_X1
:
2138 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_UB
, "st1_add");
2139 case ST2_ADD_IMM8_OPCODE_X1
:
2140 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_TEUW
, "st2_add");
2141 case ST4_ADD_IMM8_OPCODE_X1
:
2142 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_TEUL
, "st4_add");
2143 case STNT1_ADD_IMM8_OPCODE_X1
:
2144 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_UB
, "stnt1_add");
2145 case STNT2_ADD_IMM8_OPCODE_X1
:
2146 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_TEUW
, "stnt2_add");
2147 case STNT4_ADD_IMM8_OPCODE_X1
:
2148 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_TEUL
, "stnt4_add");
2149 case STNT_ADD_IMM8_OPCODE_X1
:
2150 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_TEQ
, "stnt_add");
2151 case ST_ADD_IMM8_OPCODE_X1
:
2152 return gen_st_add_opcode(dc
, srca
, srcb
, imm
, MO_TEQ
, "st_add");
2153 case MFSPR_IMM8_OPCODE_X1
:
2154 return gen_mfspr_x1(dc
, dest
, get_MF_Imm14_X1(bundle
));
2155 case MTSPR_IMM8_OPCODE_X1
:
2156 return gen_mtspr_x1(dc
, get_MT_Imm14_X1(bundle
), srca
);
2158 imm
= (int8_t)get_Imm8_X1(bundle
);
2159 return gen_rri_opcode(dc
, OE(opc
, ext
, X1
), dest
, srca
, imm
);
2161 case BRANCH_OPCODE_X1
:
2162 ext
= get_BrType_X1(bundle
);
2163 imm
= sextract32(get_BrOff_X1(bundle
), 0, 17);
2164 return gen_branch_opcode_x1(dc
, ext
, srca
, imm
);
2166 case JUMP_OPCODE_X1
:
2167 ext
= get_JumpOpcodeExtension_X1(bundle
);
2168 imm
= sextract32(get_JumpOff_X1(bundle
), 0, 27);
2169 return gen_jump_opcode_x1(dc
, ext
, imm
);
2171 case ADDLI_OPCODE_X1
:
2172 case SHL16INSLI_OPCODE_X1
:
2173 case ADDXLI_OPCODE_X1
:
2174 imm
= (int16_t)get_Imm16_X1(bundle
);
2175 return gen_rri_opcode(dc
, OE(opc
, 0, X1
), dest
, srca
, imm
);
2178 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED
;
2182 static void notice_excp(DisasContext
*dc
, uint64_t bundle
,
2183 const char *type
, TileExcp excp
)
2185 if (likely(excp
== TILEGX_EXCP_NONE
)) {
2188 gen_exception(dc
, excp
);
2189 if (excp
== TILEGX_EXCP_OPCODE_UNIMPLEMENTED
) {
2190 qemu_log_mask(LOG_UNIMP
, "UNIMP %s, [" FMT64X
"]\n", type
, bundle
);
2194 static void translate_one_bundle(DisasContext
*dc
, uint64_t bundle
)
2198 for (i
= 0; i
< ARRAY_SIZE(dc
->wb
); i
++) {
2199 DisasContextTemp
*wb
= &dc
->wb
[i
];
2200 wb
->reg
= TILEGX_R_NOREG
;
2201 TCGV_UNUSED_I64(wb
->val
);
2205 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2206 tcg_gen_debug_insn_start(dc
->pc
);
2209 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " %" PRIx64
": { ", dc
->pc
);
2210 if (get_Mode(bundle
)) {
2211 notice_excp(dc
, bundle
, "y0", decode_y0(dc
, bundle
));
2212 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " ; ");
2213 notice_excp(dc
, bundle
, "y1", decode_y1(dc
, bundle
));
2214 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " ; ");
2215 notice_excp(dc
, bundle
, "y2", decode_y2(dc
, bundle
));
2217 notice_excp(dc
, bundle
, "x0", decode_x0(dc
, bundle
));
2218 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " ; ");
2219 notice_excp(dc
, bundle
, "x1", decode_x1(dc
, bundle
));
2221 qemu_log_mask(CPU_LOG_TB_IN_ASM
, " }\n");
2223 for (i
= dc
->num_wb
- 1; i
>= 0; --i
) {
2224 DisasContextTemp
*wb
= &dc
->wb
[i
];
2225 if (wb
->reg
< TILEGX_R_COUNT
) {
2226 tcg_gen_mov_i64(cpu_regs
[wb
->reg
], wb
->val
);
2228 tcg_temp_free_i64(wb
->val
);
2231 if (dc
->jmp
.cond
!= TCG_COND_NEVER
) {
2232 if (dc
->jmp
.cond
== TCG_COND_ALWAYS
) {
2233 tcg_gen_mov_i64(cpu_pc
, dc
->jmp
.dest
);
2235 TCGv next
= tcg_const_i64(dc
->pc
+ TILEGX_BUNDLE_SIZE_IN_BYTES
);
2236 tcg_gen_movcond_i64(dc
->jmp
.cond
, cpu_pc
,
2237 dc
->jmp
.val1
, load_zero(dc
),
2238 dc
->jmp
.dest
, next
);
2239 tcg_temp_free_i64(dc
->jmp
.val1
);
2240 tcg_temp_free_i64(next
);
2242 tcg_temp_free_i64(dc
->jmp
.dest
);
2245 } else if (dc
->atomic_excp
!= TILEGX_EXCP_NONE
) {
2246 gen_exception(dc
, dc
->atomic_excp
);
2250 static inline void gen_intermediate_code_internal(TileGXCPU
*cpu
,
2251 TranslationBlock
*tb
,
2255 DisasContext
*dc
= &ctx
;
2256 CPUState
*cs
= CPU(cpu
);
2257 CPUTLGState
*env
= &cpu
->env
;
2258 uint64_t pc_start
= tb
->pc
;
2259 uint64_t next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2262 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2266 dc
->exit_tb
= false;
2267 dc
->atomic_excp
= TILEGX_EXCP_NONE
;
2268 dc
->jmp
.cond
= TCG_COND_NEVER
;
2269 TCGV_UNUSED_I64(dc
->jmp
.dest
);
2270 TCGV_UNUSED_I64(dc
->jmp
.val1
);
2271 TCGV_UNUSED_I64(dc
->zero
);
2273 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
2274 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2277 max_insns
= CF_COUNT_MASK
;
2279 if (cs
->singlestep_enabled
|| singlestep
) {
2286 j
= tcg_op_buf_count();
2290 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
2293 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
2294 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
2295 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
2297 translate_one_bundle(dc
, cpu_ldq_data(env
, dc
->pc
));
2300 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
2303 dc
->pc
+= TILEGX_BUNDLE_SIZE_IN_BYTES
;
2304 if (++num_insns
>= max_insns
2305 || dc
->pc
>= next_page_start
2306 || tcg_op_buf_full()) {
2307 /* Ending the TB due to TB size or page boundary. Set PC. */
2308 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
2314 gen_tb_end(tb
, num_insns
);
2316 j
= tcg_op_buf_count();
2319 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
2322 tb
->size
= dc
->pc
- pc_start
;
2323 tb
->icount
= num_insns
;
2326 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "\n");
2329 void gen_intermediate_code(CPUTLGState
*env
, struct TranslationBlock
*tb
)
2331 gen_intermediate_code_internal(tilegx_env_get_cpu(env
), tb
, false);
2334 void gen_intermediate_code_pc(CPUTLGState
*env
, struct TranslationBlock
*tb
)
2336 gen_intermediate_code_internal(tilegx_env_get_cpu(env
), tb
, true);
2339 void restore_state_to_opc(CPUTLGState
*env
, TranslationBlock
*tb
, int pc_pos
)
2341 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];
2344 void tilegx_tcg_init(void)
2348 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
2349 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUTLGState
, pc
), "pc");
2350 for (i
= 0; i
< TILEGX_R_COUNT
; i
++) {
2351 cpu_regs
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
2352 offsetof(CPUTLGState
, regs
[i
]),