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git.proxmox.com Git - mirror_qemu.git/blob - target-unicore32/cpu.h
2 * UniCore32 virtual CPU header
4 * Copyright (C) 2010-2011 GUAN Xue-tao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef __CPU_UC32_H__
11 #define __CPU_UC32_H__
13 #define TARGET_LONG_BITS 32
14 #define TARGET_PAGE_BITS 12
16 #define TARGET_PHYS_ADDR_SPACE_BITS 32
17 #define TARGET_VIRT_ADDR_SPACE_BITS 32
19 #define ELF_MACHINE EM_UNICORE32
21 #define CPUState struct CPUUniCore32State
24 #include "qemu-common.h"
26 #include "softfloat.h"
28 #define NB_MMU_MODES 2
30 typedef struct CPUUniCore32State
{
31 /* Regs for current mode. */
33 /* Frequently accessed ASR bits are stored separately for efficiently.
34 This contains all the other bits. Use asr_{read,write} to access
36 uint32_t uncached_asr
;
39 /* Banked registers. */
40 uint32_t banked_bsr
[6];
41 uint32_t banked_r29
[6];
42 uint32_t banked_r30
[6];
44 /* asr flag cache for faster execution */
45 uint32_t CF
; /* 0 or 1 */
46 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
47 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
48 uint32_t ZF
; /* Z set if zero. */
50 /* System control coprocessor (cp0) */
53 uint32_t c0_cachetype
;
54 uint32_t c1_sys
; /* System control register. */
55 uint32_t c2_base
; /* MMU translation table base. */
56 uint32_t c3_faultstatus
; /* Fault status registers. */
57 uint32_t c4_faultaddr
; /* Fault address registers. */
58 uint32_t c5_cacheop
; /* Cache operation registers. */
59 uint32_t c6_tlbop
; /* TLB operation registers. */
62 /* UniCore-F64 coprocessor state. */
66 float_status fp_status
;
71 /* Internal CPU feature flags. */
77 #define ASR_MODE_USER (0x10)
78 #define ASR_MODE_INTR (0x12)
79 #define ASR_MODE_PRIV (0x13)
80 #define ASR_MODE_TRAP (0x17)
81 #define ASR_MODE_EXTN (0x1b)
82 #define ASR_MODE_SUSR (0x1f)
83 #define ASR_I (1 << 7)
84 #define ASR_V (1 << 28)
85 #define ASR_C (1 << 29)
86 #define ASR_Z (1 << 30)
87 #define ASR_N (1 << 31)
88 #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
89 #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
91 #define UC32_EXCP_PRIV (ASR_MODE_PRIV)
92 #define UC32_EXCP_TRAP (ASR_MODE_TRAP)
94 /* Return the current ASR value. */
95 target_ulong
cpu_asr_read(CPUState
*env1
);
96 /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
97 void cpu_asr_write(CPUState
*env1
, target_ulong val
, target_ulong mask
);
99 /* UniCore-F64 system registers. */
100 #define UC32_UCF64_FPSCR (31)
101 #define UCF64_FPSCR_MASK (0x27ffffff)
102 #define UCF64_FPSCR_RND_MASK (0x7)
103 #define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
104 #define UCF64_FPSCR_TRAPEN_MASK (0x7f)
105 #define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
106 #define UCF64_FPSCR_FLAG_MASK (0x3ff)
107 #define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
108 #define UCF64_FPSCR_FLAG_ZERO (1 << 17)
109 #define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
110 #define UCF64_FPSCR_FLAG_INVALID (1 << 19)
111 #define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
112 #define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
113 #define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
114 #define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
115 #define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
116 #define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
117 #define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
119 #define UC32_HWCAP_CMOV 4 /* 1 << 2 */
120 #define UC32_HWCAP_UCF64 8 /* 1 << 3 */
122 #define UC32_CPUID(env) (env->cp0.c0_cpuid)
123 #define UC32_CPUID_UCV2 0x40010863
124 #define UC32_CPUID_ANY 0xffffffff
126 #define cpu_init uc32_cpu_init
127 #define cpu_exec uc32_cpu_exec
128 #define cpu_signal_handler uc32_cpu_signal_handler
129 #define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault
131 CPUState
*uc32_cpu_init(const char *cpu_model
);
132 int uc32_cpu_exec(CPUState
*s
);
133 int uc32_cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
);
134 int uc32_cpu_handle_mmu_fault(CPUState
*env
, target_ulong address
, int rw
,
137 #define CPU_SAVE_VERSION 2
139 /* MMU modes definitions */
140 #define MMU_MODE0_SUFFIX _kernel
141 #define MMU_MODE1_SUFFIX _user
142 #define MMU_USER_IDX 1
143 static inline int cpu_mmu_index(CPUState
*env
)
145 return (env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
? 1 : 0;
148 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
151 env
->regs
[29] = newsp
;
156 static inline void cpu_set_tls(CPUState
*env
, target_ulong newtls
)
158 env
->regs
[16] = newtls
;
162 #include "exec-all.h"
164 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)
166 env
->regs
[31] = tb
->pc
;
169 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
170 target_ulong
*cs_base
, int *flags
)
175 if ((env
->uncached_asr
& ASR_M
) != ASR_MODE_USER
) {
180 void uc32_translate_init(void);
181 void do_interrupt(CPUState
*);
182 void switch_mode(CPUUniCore32State
*, int);
184 static inline bool cpu_has_work(CPUState
*env
)
186 return env
->interrupt_request
&
187 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_EXITTB
);
190 #endif /* __CPU_UC32_H__ */