target-unicore32/helper.c

   1 /*
   2  * Copyright (C) 2010-2011 GUAN Xue-tao
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Contributions from 2012-04-01 on are considered under GPL version 2,
   9  * or (at your option) any later version.
  10  */
  11
  12 #include "cpu.h"
  13 #include "gdbstub.h"
  14 #include "helper.h"
  15 #include "host-utils.h"
  16
  17 static inline void set_feature(CPUUniCore32State *env, int feature)
  18 {
  19     env->features |= feature;
  20 }
  21
  22 struct uc32_cpu_t {
  23     uint32_t id;
  24     const char *name;
  25 };
  26
  27 static const struct uc32_cpu_t uc32_cpu_names[] = {
  28     { UC32_CPUID_UCV2, "UniCore-II"},
  29     { UC32_CPUID_ANY, "any"},
  30     { 0, NULL}
  31 };
  32
  33 /* return 0 if not found */
  34 static uint32_t uc32_cpu_find_by_name(const char *name)
  35 {
  36     int i;
  37     uint32_t id;
  38
  39     id = 0;
  40     for (i = 0; uc32_cpu_names[i].name; i++) {
  41         if (strcmp(name, uc32_cpu_names[i].name) == 0) {
  42             id = uc32_cpu_names[i].id;
  43             break;
  44         }
  45     }
  46     return id;
  47 }
  48
  49 CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
  50 {
  51     CPUUniCore32State *env;
  52     uint32_t id;
  53     static int inited = 1;
  54
  55     env = g_malloc0(sizeof(CPUUniCore32State));
  56     cpu_exec_init(env);
  57
  58     id = uc32_cpu_find_by_name(cpu_model);
  59     switch (id) {
  60     case UC32_CPUID_UCV2:
  61         set_feature(env, UC32_HWCAP_CMOV);
  62         set_feature(env, UC32_HWCAP_UCF64);
  63         env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
  64         env->cp0.c0_cachetype = 0x1dd20d2;
  65         env->cp0.c1_sys = 0x00090078;
  66         break;
  67     case UC32_CPUID_ANY: /* For userspace emulation.  */
  68         set_feature(env, UC32_HWCAP_CMOV);
  69         set_feature(env, UC32_HWCAP_UCF64);
  70         break;
  71     default:
  72         cpu_abort(env, "Bad CPU ID: %x\n", id);
  73     }
  74
  75     env->cpu_model_str = cpu_model;
  76     env->cp0.c0_cpuid = id;
  77     env->uncached_asr = ASR_MODE_USER;
  78     env->regs[31] = 0;
  79
  80     if (inited) {
  81         inited = 0;
  82         uc32_translate_init();
  83     }
  84
  85     tlb_flush(env, 1);
  86     qemu_init_vcpu(env);
  87     return env;
  88 }
  89
  90 uint32_t HELPER(clo)(uint32_t x)
  91 {
  92     return clo32(x);
  93 }
  94
  95 uint32_t HELPER(clz)(uint32_t x)
  96 {
  97     return clz32(x);
  98 }
  99
 100 void do_interrupt(CPUUniCore32State *env)
 101 {
 102     env->exception_index = -1;
 103 }
 104
 105 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
 106                               int mmu_idx)
 107 {
 108     env->exception_index = UC32_EXCP_TRAP;
 109     env->cp0.c4_faultaddr = address;
 110     return 1;
 111 }
 112
 113 /* These should probably raise undefined insn exceptions.  */
 114 void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
 115 {
 116     int op1 = (insn >> 8) & 0xf;
 117     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
 118     return;
 119 }
 120
 121 uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
 122 {
 123     int op1 = (insn >> 8) & 0xf;
 124     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
 125     return 0;
 126 }
 127
 128 void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
 129 {
 130     cpu_abort(env, "cp0 insn %08x\n", insn);
 131 }
 132
 133 uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
 134 {
 135     cpu_abort(env, "cp0 insn %08x\n", insn);
 136     return 0;
 137 }
 138
 139 void switch_mode(CPUUniCore32State *env, int mode)
 140 {
 141     if (mode != ASR_MODE_USER) {
 142         cpu_abort(env, "Tried to switch out of user mode\n");
 143     }
 144 }
 145
 146 void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
 147 {
 148     cpu_abort(env, "banked r29 write\n");
 149 }
 150
 151 uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
 152 {
 153     cpu_abort(env, "banked r29 read\n");
 154     return 0;
 155 }
 156
 157 /* UniCore-F64 support.  We follow the convention used for F64 instrunctions:
 158    Single precition routines have a "s" suffix, double precision a
 159    "d" suffix.  */
 160
 161 /* Convert host exception flags to f64 form.  */
 162 static inline int ucf64_exceptbits_from_host(int host_bits)
 163 {
 164     int target_bits = 0;
 165
 166     if (host_bits & float_flag_invalid) {
 167         target_bits |= UCF64_FPSCR_FLAG_INVALID;
 168     }
 169     if (host_bits & float_flag_divbyzero) {
 170         target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
 171     }
 172     if (host_bits & float_flag_overflow) {
 173         target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
 174     }
 175     if (host_bits & float_flag_underflow) {
 176         target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
 177     }
 178     if (host_bits & float_flag_inexact) {
 179         target_bits |= UCF64_FPSCR_FLAG_INEXACT;
 180     }
 181     return target_bits;
 182 }
 183
 184 uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
 185 {
 186     int i;
 187     uint32_t fpscr;
 188
 189     fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
 190     i = get_float_exception_flags(&env->ucf64.fp_status);
 191     fpscr |= ucf64_exceptbits_from_host(i);
 192     return fpscr;
 193 }
 194
 195 /* Convert ucf64 exception flags to target form.  */
 196 static inline int ucf64_exceptbits_to_host(int target_bits)
 197 {
 198     int host_bits = 0;
 199
 200     if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
 201         host_bits |= float_flag_invalid;
 202     }
 203     if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
 204         host_bits |= float_flag_divbyzero;
 205     }
 206     if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
 207         host_bits |= float_flag_overflow;
 208     }
 209     if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
 210         host_bits |= float_flag_underflow;
 211     }
 212     if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
 213         host_bits |= float_flag_inexact;
 214     }
 215     return host_bits;
 216 }
 217
 218 void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
 219 {
 220     int i;
 221     uint32_t changed;
 222
 223     changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
 224     env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
 225
 226     changed ^= val;
 227     if (changed & (UCF64_FPSCR_RND_MASK)) {
 228         i = UCF64_FPSCR_RND(val);
 229         switch (i) {
 230         case 0:
 231             i = float_round_nearest_even;
 232             break;
 233         case 1:
 234             i = float_round_to_zero;
 235             break;
 236         case 2:
 237             i = float_round_up;
 238             break;
 239         case 3:
 240             i = float_round_down;
 241             break;
 242         default: /* 100 and 101 not implement */
 243             cpu_abort(env, "Unsupported UniCore-F64 round mode");
 244         }
 245         set_float_rounding_mode(i, &env->ucf64.fp_status);
 246     }
 247
 248     i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
 249     set_float_exception_flags(i, &env->ucf64.fp_status);
 250 }
 251
 252 float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
 253 {
 254     return float32_add(a, b, &env->ucf64.fp_status);
 255 }
 256
 257 float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
 258 {
 259     return float64_add(a, b, &env->ucf64.fp_status);
 260 }
 261
 262 float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
 263 {
 264     return float32_sub(a, b, &env->ucf64.fp_status);
 265 }
 266
 267 float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
 268 {
 269     return float64_sub(a, b, &env->ucf64.fp_status);
 270 }
 271
 272 float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
 273 {
 274     return float32_mul(a, b, &env->ucf64.fp_status);
 275 }
 276
 277 float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
 278 {
 279     return float64_mul(a, b, &env->ucf64.fp_status);
 280 }
 281
 282 float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
 283 {
 284     return float32_div(a, b, &env->ucf64.fp_status);
 285 }
 286
 287 float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
 288 {
 289     return float64_div(a, b, &env->ucf64.fp_status);
 290 }
 291
 292 float32 HELPER(ucf64_negs)(float32 a)
 293 {
 294     return float32_chs(a);
 295 }
 296
 297 float64 HELPER(ucf64_negd)(float64 a)
 298 {
 299     return float64_chs(a);
 300 }
 301
 302 float32 HELPER(ucf64_abss)(float32 a)
 303 {
 304     return float32_abs(a);
 305 }
 306
 307 float64 HELPER(ucf64_absd)(float64 a)
 308 {
 309     return float64_abs(a);
 310 }
 311
 312 /* XXX: check quiet/signaling case */
 313 void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
 314 {
 315     int flag;
 316     flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
 317     env->CF = 0;
 318     switch (c & 0x7) {
 319     case 0: /* F */
 320         break;
 321     case 1: /* UN */
 322         if (flag == 2) {
 323             env->CF = 1;
 324         }
 325         break;
 326     case 2: /* EQ */
 327         if (flag == 0) {
 328             env->CF = 1;
 329         }
 330         break;
 331     case 3: /* UEQ */
 332         if ((flag == 0) || (flag == 2)) {
 333             env->CF = 1;
 334         }
 335         break;
 336     case 4: /* OLT */
 337         if (flag == -1) {
 338             env->CF = 1;
 339         }
 340         break;
 341     case 5: /* ULT */
 342         if ((flag == -1) || (flag == 2)) {
 343             env->CF = 1;
 344         }
 345         break;
 346     case 6: /* OLE */
 347         if ((flag == -1) || (flag == 0)) {
 348             env->CF = 1;
 349         }
 350         break;
 351     case 7: /* ULE */
 352         if (flag != 1) {
 353             env->CF = 1;
 354         }
 355         break;
 356     }
 357     env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 358                     | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 359 }
 360
 361 void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
 362 {
 363     int flag;
 364     flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
 365     env->CF = 0;
 366     switch (c & 0x7) {
 367     case 0: /* F */
 368         break;
 369     case 1: /* UN */
 370         if (flag == 2) {
 371             env->CF = 1;
 372         }
 373         break;
 374     case 2: /* EQ */
 375         if (flag == 0) {
 376             env->CF = 1;
 377         }
 378         break;
 379     case 3: /* UEQ */
 380         if ((flag == 0) || (flag == 2)) {
 381             env->CF = 1;
 382         }
 383         break;
 384     case 4: /* OLT */
 385         if (flag == -1) {
 386             env->CF = 1;
 387         }
 388         break;
 389     case 5: /* ULT */
 390         if ((flag == -1) || (flag == 2)) {
 391             env->CF = 1;
 392         }
 393         break;
 394     case 6: /* OLE */
 395         if ((flag == -1) || (flag == 0)) {
 396             env->CF = 1;
 397         }
 398         break;
 399     case 7: /* ULE */
 400         if (flag != 1) {
 401             env->CF = 1;
 402         }
 403         break;
 404     }
 405     env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 406                     | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 407 }
 408
 409 /* Helper routines to perform bitwise copies between float and int.  */
 410 static inline float32 ucf64_itos(uint32_t i)
 411 {
 412     union {
 413         uint32_t i;
 414         float32 s;
 415     } v;
 416
 417     v.i = i;
 418     return v.s;
 419 }
 420
 421 static inline uint32_t ucf64_stoi(float32 s)
 422 {
 423     union {
 424         uint32_t i;
 425         float32 s;
 426     } v;
 427
 428     v.s = s;
 429     return v.i;
 430 }
 431
 432 static inline float64 ucf64_itod(uint64_t i)
 433 {
 434     union {
 435         uint64_t i;
 436         float64 d;
 437     } v;
 438
 439     v.i = i;
 440     return v.d;
 441 }
 442
 443 static inline uint64_t ucf64_dtoi(float64 d)
 444 {
 445     union {
 446         uint64_t i;
 447         float64 d;
 448     } v;
 449
 450     v.d = d;
 451     return v.i;
 452 }
 453
 454 /* Integer to float conversion.  */
 455 float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
 456 {
 457     return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
 458 }
 459
 460 float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
 461 {
 462     return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
 463 }
 464
 465 /* Float to integer conversion.  */
 466 float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
 467 {
 468     return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
 469 }
 470
 471 float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
 472 {
 473     return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
 474 }
 475
 476 /* floating point conversion */
 477 float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
 478 {
 479     return float32_to_float64(x, &env->ucf64.fp_status);
 480 }
 481
 482 float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
 483 {
 484     return float64_to_float32(x, &env->ucf64.fp_status);
 485 }