2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
34 #define CPUState struct CPUXtensaState
37 #include "qemu-common.h"
40 #define TARGET_HAS_ICE 1
42 #define NB_MMU_MODES 4
44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
46 #define TARGET_PAGE_BITS 12
49 /* Additional instructions */
50 XTENSA_OPTION_CODE_DENSITY
,
52 XTENSA_OPTION_EXTENDED_L32R
,
53 XTENSA_OPTION_16_BIT_IMUL
,
54 XTENSA_OPTION_32_BIT_IMUL
,
55 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
56 XTENSA_OPTION_32_BIT_IDIV
,
58 XTENSA_OPTION_MISC_OP_NSA
,
59 XTENSA_OPTION_MISC_OP_MINMAX
,
60 XTENSA_OPTION_MISC_OP_SEXT
,
61 XTENSA_OPTION_MISC_OP_CLAMPS
,
62 XTENSA_OPTION_COPROCESSOR
,
63 XTENSA_OPTION_BOOLEAN
,
64 XTENSA_OPTION_FP_COPROCESSOR
,
65 XTENSA_OPTION_MP_SYNCHRO
,
66 XTENSA_OPTION_CONDITIONAL_STORE
,
68 /* Interrupts and exceptions */
69 XTENSA_OPTION_EXCEPTION
,
70 XTENSA_OPTION_RELOCATABLE_VECTOR
,
71 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
72 XTENSA_OPTION_INTERRUPT
,
73 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
74 XTENSA_OPTION_TIMER_INTERRUPT
,
78 XTENSA_OPTION_ICACHE_TEST
,
79 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
81 XTENSA_OPTION_DCACHE_TEST
,
82 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
88 XTENSA_OPTION_HW_ALIGNMENT
,
89 XTENSA_OPTION_MEMORY_ECC_PARITY
,
91 /* Memory protection and translation */
92 XTENSA_OPTION_REGION_PROTECTION
,
93 XTENSA_OPTION_REGION_TRANSLATION
,
97 XTENSA_OPTION_WINDOWED_REGISTER
,
98 XTENSA_OPTION_PROCESSOR_INTERFACE
,
99 XTENSA_OPTION_MISC_SR
,
100 XTENSA_OPTION_THREAD_POINTER
,
101 XTENSA_OPTION_PROCESSOR_ID
,
103 XTENSA_OPTION_TRACE_PORT
,
151 #define PS_INTLEVEL 0xf
152 #define PS_INTLEVEL_SHIFT 0
158 #define PS_RING_SHIFT 6
161 #define PS_OWB_SHIFT 8
163 #define PS_CALLINC 0x30000
164 #define PS_CALLINC_SHIFT 16
165 #define PS_CALLINC_LEN 2
167 #define PS_WOE 0x40000
169 #define DEBUGCAUSE_IC 0x1
170 #define DEBUGCAUSE_IB 0x2
171 #define DEBUGCAUSE_DB 0x4
172 #define DEBUGCAUSE_BI 0x8
173 #define DEBUGCAUSE_BN 0x10
174 #define DEBUGCAUSE_DI 0x20
175 #define DEBUGCAUSE_DBNUM 0xf00
176 #define DEBUGCAUSE_DBNUM_SHIFT 8
179 #define MAX_NINTERRUPT 32
182 #define MAX_NCCOMPARE 3
183 #define MAX_TLB_WAY_SIZE 8
185 #define REGION_PAGE_MASK 0xe0000000
192 /* Dynamic vectors */
193 EXC_WINDOW_OVERFLOW4
,
194 EXC_WINDOW_UNDERFLOW4
,
195 EXC_WINDOW_OVERFLOW8
,
196 EXC_WINDOW_UNDERFLOW8
,
197 EXC_WINDOW_OVERFLOW12
,
198 EXC_WINDOW_UNDERFLOW12
,
208 ILLEGAL_INSTRUCTION_CAUSE
= 0,
210 INSTRUCTION_FETCH_ERROR_CAUSE
,
211 LOAD_STORE_ERROR_CAUSE
,
212 LEVEL1_INTERRUPT_CAUSE
,
214 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
215 PRIVILEGED_CAUSE
= 8,
216 LOAD_STORE_ALIGNMENT_CAUSE
,
218 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
219 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
220 INSTR_PIF_ADDR_ERROR_CAUSE
,
221 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
224 INST_TLB_MULTI_HIT_CAUSE
,
225 INST_FETCH_PRIVILEGE_CAUSE
,
226 INST_FETCH_PROHIBITED_CAUSE
= 20,
227 LOAD_STORE_TLB_MISS_CAUSE
= 24,
228 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
229 LOAD_STORE_PRIVILEGE_CAUSE
,
230 LOAD_PROHIBITED_CAUSE
= 28,
231 STORE_PROHIBITED_CAUSE
,
233 COPROCESSOR0_DISABLED
= 32,
247 typedef struct xtensa_tlb_entry
{
255 typedef struct xtensa_tlb
{
257 const unsigned way_size
[10];
259 unsigned nrefillentries
;
262 typedef struct XtensaGdbReg
{
268 typedef struct XtensaGdbRegmap
{
271 /* PC + a + ar + sr + ur */
272 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
275 typedef struct XtensaConfig
{
278 XtensaGdbRegmap gdb_regmap
;
283 uint32_t exception_vector
[EXC_MAX
];
286 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
287 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
288 uint32_t inttype_mask
[INTTYPE_MAX
];
291 interrupt_type inttype
;
292 } interrupt
[MAX_NINTERRUPT
];
294 uint32_t timerint
[MAX_NCCOMPARE
];
296 unsigned extint
[MAX_NINTERRUPT
];
298 unsigned debug_level
;
302 uint32_t clock_freq_khz
;
308 typedef struct XtensaConfigList
{
309 const XtensaConfig
*config
;
310 struct XtensaConfigList
*next
;
313 typedef struct CPUXtensaState
{
314 const XtensaConfig
*config
;
319 uint32_t phys_regs
[MAX_NAREG
];
321 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
322 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
323 unsigned autorefill_idx
;
325 int pending_irq_level
; /* level of last raised IRQ */
327 QEMUTimer
*ccompare_timer
;
328 uint32_t wake_ccount
;
336 #define cpu_init cpu_xtensa_init
337 #define cpu_exec cpu_xtensa_exec
338 #define cpu_gen_code cpu_xtensa_gen_code
339 #define cpu_signal_handler cpu_xtensa_signal_handler
340 #define cpu_list xtensa_cpu_list
342 CPUXtensaState
*cpu_xtensa_init(const char *cpu_model
);
343 void xtensa_translate_init(void);
344 int cpu_xtensa_exec(CPUXtensaState
*s
);
345 void xtensa_register_core(XtensaConfigList
*node
);
346 void do_interrupt(CPUXtensaState
*s
);
347 void check_interrupts(CPUXtensaState
*s
);
348 void xtensa_irq_init(CPUState
*env
);
349 void *xtensa_get_extint(CPUState
*env
, unsigned extint
);
350 void xtensa_advance_ccount(CPUState
*env
, uint32_t d
);
351 void xtensa_timer_irq(CPUState
*env
, uint32_t id
, uint32_t active
);
352 void xtensa_rearm_ccompare_timer(CPUState
*env
);
353 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
354 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
355 void xtensa_sync_window_from_phys(CPUState
*env
);
356 void xtensa_sync_phys_from_window(CPUState
*env
);
357 uint32_t xtensa_tlb_get_addr_mask(const CPUState
*env
, bool dtlb
, uint32_t way
);
358 void split_tlb_entry_spec_way(const CPUState
*env
, uint32_t v
, bool dtlb
,
359 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
360 int xtensa_tlb_lookup(const CPUState
*env
, uint32_t addr
, bool dtlb
,
361 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
362 void xtensa_tlb_set_entry(CPUState
*env
, bool dtlb
,
363 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
364 int xtensa_get_physical_addr(CPUState
*env
,
365 uint32_t vaddr
, int is_write
, int mmu_idx
,
366 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
367 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUState
*env
);
370 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
372 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
375 return (config
->options
& opt
) != 0;
378 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
380 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
383 static inline int xtensa_get_cintlevel(const CPUState
*env
)
385 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
386 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
387 level
= env
->config
->excm_level
;
392 static inline int xtensa_get_ring(const CPUState
*env
)
394 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
395 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
401 static inline int xtensa_get_cring(const CPUState
*env
)
403 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
404 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
405 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
411 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUState
*env
,
412 bool dtlb
, unsigned wi
, unsigned ei
)
419 /* MMU modes definitions */
420 #define MMU_MODE0_SUFFIX _ring0
421 #define MMU_MODE1_SUFFIX _ring1
422 #define MMU_MODE2_SUFFIX _ring2
423 #define MMU_MODE3_SUFFIX _ring3
425 static inline int cpu_mmu_index(CPUState
*env
)
427 return xtensa_get_cring(env
);
430 #define XTENSA_TBFLAG_RING_MASK 0x3
431 #define XTENSA_TBFLAG_EXCM 0x4
432 #define XTENSA_TBFLAG_LITBASE 0x8
433 #define XTENSA_TBFLAG_DEBUG 0x10
434 #define XTENSA_TBFLAG_ICOUNT 0x20
436 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
437 target_ulong
*cs_base
, int *flags
)
442 *flags
|= xtensa_get_ring(env
);
443 if (env
->sregs
[PS
] & PS_EXCM
) {
444 *flags
|= XTENSA_TBFLAG_EXCM
;
446 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
447 (env
->sregs
[LITBASE
] & 1)) {
448 *flags
|= XTENSA_TBFLAG_LITBASE
;
450 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
451 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
452 *flags
|= XTENSA_TBFLAG_DEBUG
;
454 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
455 *flags
|= XTENSA_TBFLAG_ICOUNT
;
461 #include "exec-all.h"
463 static inline int cpu_has_work(CPUState
*env
)
465 return env
->pending_irq_level
;
468 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)