target-xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef CPU_XTENSA_H
  29 #define CPU_XTENSA_H
  30
  31 #define TARGET_LONG_BITS 32
  32 #define ELF_MACHINE EM_XTENSA
  33
  34 #define CPUState struct CPUXtensaState
  35
  36 #include "config.h"
  37 #include "qemu-common.h"
  38 #include "cpu-defs.h"
  39
  40 #define TARGET_HAS_ICE 1
  41
  42 #define NB_MMU_MODES 4
  43
  44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  46 #define TARGET_PAGE_BITS 12
  47
  48 enum {
  49     /* Additional instructions */
  50     XTENSA_OPTION_CODE_DENSITY,
  51     XTENSA_OPTION_LOOP,
  52     XTENSA_OPTION_EXTENDED_L32R,
  53     XTENSA_OPTION_16_BIT_IMUL,
  54     XTENSA_OPTION_32_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IDIV,
  56     XTENSA_OPTION_MAC16,
  57     XTENSA_OPTION_MISC_OP,
  58     XTENSA_OPTION_COPROCESSOR,
  59     XTENSA_OPTION_BOOLEAN,
  60     XTENSA_OPTION_FP_COPROCESSOR,
  61     XTENSA_OPTION_MP_SYNCHRO,
  62     XTENSA_OPTION_CONDITIONAL_STORE,
  63
  64     /* Interrupts and exceptions */
  65     XTENSA_OPTION_EXCEPTION,
  66     XTENSA_OPTION_RELOCATABLE_VECTOR,
  67     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  68     XTENSA_OPTION_INTERRUPT,
  69     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  70     XTENSA_OPTION_TIMER_INTERRUPT,
  71
  72     /* Local memory */
  73     XTENSA_OPTION_ICACHE,
  74     XTENSA_OPTION_ICACHE_TEST,
  75     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  76     XTENSA_OPTION_DCACHE,
  77     XTENSA_OPTION_DCACHE_TEST,
  78     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  79     XTENSA_OPTION_IRAM,
  80     XTENSA_OPTION_IROM,
  81     XTENSA_OPTION_DRAM,
  82     XTENSA_OPTION_DROM,
  83     XTENSA_OPTION_XLMI,
  84     XTENSA_OPTION_HW_ALIGNMENT,
  85     XTENSA_OPTION_MEMORY_ECC_PARITY,
  86
  87     /* Memory protection and translation */
  88     XTENSA_OPTION_REGION_PROTECTION,
  89     XTENSA_OPTION_REGION_TRANSLATION,
  90     XTENSA_OPTION_MMU,
  91
  92     /* Other */
  93     XTENSA_OPTION_WINDOWED_REGISTER,
  94     XTENSA_OPTION_PROCESSOR_INTERFACE,
  95     XTENSA_OPTION_MISC_SR,
  96     XTENSA_OPTION_THREAD_POINTER,
  97     XTENSA_OPTION_PROCESSOR_ID,
  98     XTENSA_OPTION_DEBUG,
  99     XTENSA_OPTION_TRACE_PORT,
 100 };
 101
 102 enum {
 103     THREADPTR = 231,
 104     FCR = 232,
 105     FSR = 233,
 106 };
 107
 108 enum {
 109     SAR = 3,
 110     SCOMPARE1 = 12,
 111     EPC1 = 177,
 112     DEPC = 192,
 113     EXCSAVE1 = 209,
 114     PS = 230,
 115     EXCCAUSE = 232,
 116     EXCVADDR = 238,
 117 };
 118
 119 #define PS_INTLEVEL 0xf
 120 #define PS_INTLEVEL_SHIFT 0
 121
 122 #define PS_EXCM 0x10
 123 #define PS_UM 0x20
 124
 125 #define PS_RING 0xc0
 126 #define PS_RING_SHIFT 6
 127
 128 #define PS_OWB 0xf00
 129 #define PS_OWB_SHIFT 8
 130
 131 #define PS_CALLINC 0x30000
 132 #define PS_CALLINC_SHIFT 16
 133 #define PS_CALLINC_LEN 2
 134
 135 #define PS_WOE 0x40000
 136
 137 enum {
 138     /* Static vectors */
 139     EXC_RESET,
 140     EXC_MEMORY_ERROR,
 141
 142     /* Dynamic vectors */
 143     EXC_WINDOW_OVERFLOW4,
 144     EXC_WINDOW_UNDERFLOW4,
 145     EXC_WINDOW_OVERFLOW8,
 146     EXC_WINDOW_UNDERFLOW8,
 147     EXC_WINDOW_OVERFLOW12,
 148     EXC_WINDOW_UNDERFLOW12,
 149     EXC_IRQ,
 150     EXC_KERNEL,
 151     EXC_USER,
 152     EXC_DOUBLE,
 153     EXC_MAX
 154 };
 155
 156 enum {
 157     ILLEGAL_INSTRUCTION_CAUSE = 0,
 158     SYSCALL_CAUSE,
 159     INSTRUCTION_FETCH_ERROR_CAUSE,
 160     LOAD_STORE_ERROR_CAUSE,
 161     LEVEL1_INTERRUPT_CAUSE,
 162     ALLOCA_CAUSE,
 163     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 164     PRIVILEGED_CAUSE = 8,
 165     LOAD_STORE_ALIGNMENT_CAUSE,
 166
 167     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 168     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 169     INSTR_PIF_ADDR_ERROR_CAUSE,
 170     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 171
 172     INST_TLB_MISS_CAUSE,
 173     INST_TLB_MULTI_HIT_CAUSE,
 174     INST_FETCH_PRIVILEGE_CAUSE,
 175     INST_FETCH_PROHIBITED_CAUSE = 20,
 176     LOAD_STORE_TLB_MISS_CAUSE = 24,
 177     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 178     LOAD_STORE_PRIVILEGE_CAUSE,
 179     LOAD_PROHIBITED_CAUSE = 28,
 180     STORE_PROHIBITED_CAUSE,
 181
 182     COPROCESSOR0_DISABLED = 32,
 183 };
 184
 185 typedef struct XtensaConfig {
 186     const char *name;
 187     uint64_t options;
 188     int excm_level;
 189     int ndepc;
 190     uint32_t exception_vector[EXC_MAX];
 191 } XtensaConfig;
 192
 193 typedef struct CPUXtensaState {
 194     const XtensaConfig *config;
 195     uint32_t regs[16];
 196     uint32_t pc;
 197     uint32_t sregs[256];
 198     uint32_t uregs[256];
 199
 200     int exception_taken;
 201
 202     CPU_COMMON
 203 } CPUXtensaState;
 204
 205 #define cpu_init cpu_xtensa_init
 206 #define cpu_exec cpu_xtensa_exec
 207 #define cpu_gen_code cpu_xtensa_gen_code
 208 #define cpu_signal_handler cpu_xtensa_signal_handler
 209 #define cpu_list xtensa_cpu_list
 210
 211 CPUXtensaState *cpu_xtensa_init(const char *cpu_model);
 212 void xtensa_translate_init(void);
 213 int cpu_xtensa_exec(CPUXtensaState *s);
 214 void do_interrupt(CPUXtensaState *s);
 215 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 216 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 217
 218 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 219
 220 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 221 {
 222     return (config->options & XTENSA_OPTION_BIT(opt)) != 0;
 223 }
 224
 225 static inline int xtensa_get_cintlevel(const CPUState *env)
 226 {
 227     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 228     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 229         level = env->config->excm_level;
 230     }
 231     return level;
 232 }
 233
 234 static inline int xtensa_get_ring(const CPUState *env)
 235 {
 236     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 237         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 238     } else {
 239         return 0;
 240     }
 241 }
 242
 243 static inline int xtensa_get_cring(const CPUState *env)
 244 {
 245     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 246             (env->sregs[PS] & PS_EXCM) == 0) {
 247         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 248     } else {
 249         return 0;
 250     }
 251 }
 252
 253 /* MMU modes definitions */
 254 #define MMU_MODE0_SUFFIX _ring0
 255 #define MMU_MODE1_SUFFIX _ring1
 256 #define MMU_MODE2_SUFFIX _ring2
 257 #define MMU_MODE3_SUFFIX _ring3
 258
 259 static inline int cpu_mmu_index(CPUState *env)
 260 {
 261     return xtensa_get_cring(env);
 262 }
 263
 264 #define XTENSA_TBFLAG_RING_MASK 0x3
 265 #define XTENSA_TBFLAG_EXCM 0x4
 266
 267 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 268         target_ulong *cs_base, int *flags)
 269 {
 270     *pc = env->pc;
 271     *cs_base = 0;
 272     *flags = 0;
 273     *flags |= xtensa_get_ring(env);
 274     if (env->sregs[PS] & PS_EXCM) {
 275         *flags |= XTENSA_TBFLAG_EXCM;
 276     }
 277 }
 278
 279 #include "cpu-all.h"
 280 #include "exec-all.h"
 281
 282 static inline int cpu_has_work(CPUState *env)
 283 {
 284     return 1;
 285 }
 286
 287 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 288 {
 289     env->pc = tb->pc;
 290 }
 291
 292 #endif