2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
34 #define CPUArchState struct CPUXtensaState
37 #include "qemu-common.h"
39 #include "fpu/softfloat.h"
41 #define TARGET_HAS_ICE 1
43 #define NB_MMU_MODES 4
45 #define TARGET_PHYS_ADDR_SPACE_BITS 32
46 #define TARGET_VIRT_ADDR_SPACE_BITS 32
47 #define TARGET_PAGE_BITS 12
50 /* Additional instructions */
51 XTENSA_OPTION_CODE_DENSITY
,
53 XTENSA_OPTION_EXTENDED_L32R
,
54 XTENSA_OPTION_16_BIT_IMUL
,
55 XTENSA_OPTION_32_BIT_IMUL
,
56 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
57 XTENSA_OPTION_32_BIT_IDIV
,
59 XTENSA_OPTION_MISC_OP_NSA
,
60 XTENSA_OPTION_MISC_OP_MINMAX
,
61 XTENSA_OPTION_MISC_OP_SEXT
,
62 XTENSA_OPTION_MISC_OP_CLAMPS
,
63 XTENSA_OPTION_COPROCESSOR
,
64 XTENSA_OPTION_BOOLEAN
,
65 XTENSA_OPTION_FP_COPROCESSOR
,
66 XTENSA_OPTION_MP_SYNCHRO
,
67 XTENSA_OPTION_CONDITIONAL_STORE
,
68 XTENSA_OPTION_ATOMCTL
,
70 /* Interrupts and exceptions */
71 XTENSA_OPTION_EXCEPTION
,
72 XTENSA_OPTION_RELOCATABLE_VECTOR
,
73 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
74 XTENSA_OPTION_INTERRUPT
,
75 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
76 XTENSA_OPTION_TIMER_INTERRUPT
,
80 XTENSA_OPTION_ICACHE_TEST
,
81 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
83 XTENSA_OPTION_DCACHE_TEST
,
84 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
90 XTENSA_OPTION_HW_ALIGNMENT
,
91 XTENSA_OPTION_MEMORY_ECC_PARITY
,
93 /* Memory protection and translation */
94 XTENSA_OPTION_REGION_PROTECTION
,
95 XTENSA_OPTION_REGION_TRANSLATION
,
99 XTENSA_OPTION_WINDOWED_REGISTER
,
100 XTENSA_OPTION_PROCESSOR_INTERFACE
,
101 XTENSA_OPTION_MISC_SR
,
102 XTENSA_OPTION_THREAD_POINTER
,
103 XTENSA_OPTION_PROCESSOR_ID
,
105 XTENSA_OPTION_TRACE_PORT
,
156 #define PS_INTLEVEL 0xf
157 #define PS_INTLEVEL_SHIFT 0
163 #define PS_RING_SHIFT 6
166 #define PS_OWB_SHIFT 8
168 #define PS_CALLINC 0x30000
169 #define PS_CALLINC_SHIFT 16
170 #define PS_CALLINC_LEN 2
172 #define PS_WOE 0x40000
174 #define DEBUGCAUSE_IC 0x1
175 #define DEBUGCAUSE_IB 0x2
176 #define DEBUGCAUSE_DB 0x4
177 #define DEBUGCAUSE_BI 0x8
178 #define DEBUGCAUSE_BN 0x10
179 #define DEBUGCAUSE_DI 0x20
180 #define DEBUGCAUSE_DBNUM 0xf00
181 #define DEBUGCAUSE_DBNUM_SHIFT 8
183 #define DBREAKC_SB 0x80000000
184 #define DBREAKC_LB 0x40000000
185 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
186 #define DBREAKC_MASK 0x3f
189 #define MAX_NINTERRUPT 32
192 #define MAX_NCCOMPARE 3
193 #define MAX_TLB_WAY_SIZE 8
194 #define MAX_NDBREAK 2
196 #define REGION_PAGE_MASK 0xe0000000
198 #define PAGE_CACHE_MASK 0x700
199 #define PAGE_CACHE_SHIFT 8
200 #define PAGE_CACHE_INVALID 0x000
201 #define PAGE_CACHE_BYPASS 0x100
202 #define PAGE_CACHE_WT 0x200
203 #define PAGE_CACHE_WB 0x400
204 #define PAGE_CACHE_ISOLATE 0x600
211 /* Dynamic vectors */
212 EXC_WINDOW_OVERFLOW4
,
213 EXC_WINDOW_UNDERFLOW4
,
214 EXC_WINDOW_OVERFLOW8
,
215 EXC_WINDOW_UNDERFLOW8
,
216 EXC_WINDOW_OVERFLOW12
,
217 EXC_WINDOW_UNDERFLOW12
,
227 ILLEGAL_INSTRUCTION_CAUSE
= 0,
229 INSTRUCTION_FETCH_ERROR_CAUSE
,
230 LOAD_STORE_ERROR_CAUSE
,
231 LEVEL1_INTERRUPT_CAUSE
,
233 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
234 PRIVILEGED_CAUSE
= 8,
235 LOAD_STORE_ALIGNMENT_CAUSE
,
237 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
238 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
239 INSTR_PIF_ADDR_ERROR_CAUSE
,
240 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
243 INST_TLB_MULTI_HIT_CAUSE
,
244 INST_FETCH_PRIVILEGE_CAUSE
,
245 INST_FETCH_PROHIBITED_CAUSE
= 20,
246 LOAD_STORE_TLB_MISS_CAUSE
= 24,
247 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
248 LOAD_STORE_PRIVILEGE_CAUSE
,
249 LOAD_PROHIBITED_CAUSE
= 28,
250 STORE_PROHIBITED_CAUSE
,
252 COPROCESSOR0_DISABLED
= 32,
266 typedef struct xtensa_tlb_entry
{
274 typedef struct xtensa_tlb
{
276 const unsigned way_size
[10];
278 unsigned nrefillentries
;
281 typedef struct XtensaGdbReg
{
287 typedef struct XtensaGdbRegmap
{
290 /* PC + a + ar + sr + ur */
291 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
294 typedef struct XtensaConfig
{
297 XtensaGdbRegmap gdb_regmap
;
302 uint32_t exception_vector
[EXC_MAX
];
305 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
306 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
307 uint32_t inttype_mask
[INTTYPE_MAX
];
310 interrupt_type inttype
;
311 } interrupt
[MAX_NINTERRUPT
];
313 uint32_t timerint
[MAX_NCCOMPARE
];
315 unsigned extint
[MAX_NINTERRUPT
];
317 unsigned debug_level
;
321 uint32_t clock_freq_khz
;
327 typedef struct XtensaConfigList
{
328 const XtensaConfig
*config
;
329 struct XtensaConfigList
*next
;
332 typedef struct CPUXtensaState
{
333 const XtensaConfig
*config
;
338 uint32_t phys_regs
[MAX_NAREG
];
340 float_status fp_status
;
342 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
343 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
344 unsigned autorefill_idx
;
346 int pending_irq_level
; /* level of last raised IRQ */
348 QEMUTimer
*ccompare_timer
;
349 uint32_t wake_ccount
;
354 /* Watchpoints for DBREAK registers */
355 CPUWatchpoint
*cpu_watchpoint
[MAX_NDBREAK
];
362 #define cpu_exec cpu_xtensa_exec
363 #define cpu_gen_code cpu_xtensa_gen_code
364 #define cpu_signal_handler cpu_xtensa_signal_handler
365 #define cpu_list xtensa_cpu_list
367 #ifdef TARGET_WORDS_BIGENDIAN
368 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
370 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
373 XtensaCPU
*cpu_xtensa_init(const char *cpu_model
);
375 static inline CPUXtensaState
*cpu_init(const char *cpu_model
)
377 XtensaCPU
*cpu
= cpu_xtensa_init(cpu_model
);
384 void xtensa_translate_init(void);
385 int cpu_xtensa_exec(CPUXtensaState
*s
);
386 void xtensa_register_core(XtensaConfigList
*node
);
387 void do_interrupt(CPUXtensaState
*s
);
388 void check_interrupts(CPUXtensaState
*s
);
389 void xtensa_irq_init(CPUXtensaState
*env
);
390 void *xtensa_get_extint(CPUXtensaState
*env
, unsigned extint
);
391 void xtensa_advance_ccount(CPUXtensaState
*env
, uint32_t d
);
392 void xtensa_timer_irq(CPUXtensaState
*env
, uint32_t id
, uint32_t active
);
393 void xtensa_rearm_ccompare_timer(CPUXtensaState
*env
);
394 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
395 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
396 void xtensa_sync_window_from_phys(CPUXtensaState
*env
);
397 void xtensa_sync_phys_from_window(CPUXtensaState
*env
);
398 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
);
399 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
400 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
401 int xtensa_tlb_lookup(const CPUXtensaState
*env
, uint32_t addr
, bool dtlb
,
402 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
403 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
404 xtensa_tlb_entry
*entry
, bool dtlb
,
405 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
406 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
407 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
408 int xtensa_get_physical_addr(CPUXtensaState
*env
, bool update_tlb
,
409 uint32_t vaddr
, int is_write
, int mmu_idx
,
410 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
411 void reset_mmu(CPUXtensaState
*env
);
412 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUXtensaState
*env
);
413 void debug_exception_env(CPUXtensaState
*new_env
, uint32_t cause
);
416 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
418 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
421 return (config
->options
& opt
) != 0;
424 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
426 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
429 static inline int xtensa_get_cintlevel(const CPUXtensaState
*env
)
431 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
432 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
433 level
= env
->config
->excm_level
;
438 static inline int xtensa_get_ring(const CPUXtensaState
*env
)
440 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
441 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
447 static inline int xtensa_get_cring(const CPUXtensaState
*env
)
449 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
450 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
451 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
457 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUXtensaState
*env
,
458 bool dtlb
, unsigned wi
, unsigned ei
)
465 /* MMU modes definitions */
466 #define MMU_MODE0_SUFFIX _ring0
467 #define MMU_MODE1_SUFFIX _ring1
468 #define MMU_MODE2_SUFFIX _ring2
469 #define MMU_MODE3_SUFFIX _ring3
471 static inline int cpu_mmu_index(CPUXtensaState
*env
)
473 return xtensa_get_cring(env
);
476 #define XTENSA_TBFLAG_RING_MASK 0x3
477 #define XTENSA_TBFLAG_EXCM 0x4
478 #define XTENSA_TBFLAG_LITBASE 0x8
479 #define XTENSA_TBFLAG_DEBUG 0x10
480 #define XTENSA_TBFLAG_ICOUNT 0x20
481 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
482 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
484 static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env
, target_ulong
*pc
,
485 target_ulong
*cs_base
, int *flags
)
490 *flags
|= xtensa_get_ring(env
);
491 if (env
->sregs
[PS
] & PS_EXCM
) {
492 *flags
|= XTENSA_TBFLAG_EXCM
;
494 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
495 (env
->sregs
[LITBASE
] & 1)) {
496 *flags
|= XTENSA_TBFLAG_LITBASE
;
498 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
499 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
500 *flags
|= XTENSA_TBFLAG_DEBUG
;
502 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
503 *flags
|= XTENSA_TBFLAG_ICOUNT
;
506 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_COPROCESSOR
)) {
507 *flags
|= env
->sregs
[CPENABLE
] << XTENSA_TBFLAG_CPENABLE_SHIFT
;
512 #include "exec-all.h"
514 static inline int cpu_has_work(CPUState
*cpu
)
516 CPUXtensaState
*env
= &XTENSA_CPU(cpu
)->env
;
518 return env
->pending_irq_level
;
521 static inline void cpu_pc_from_tb(CPUXtensaState
*env
, TranslationBlock
*tb
)