3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 typedef struct DisasContext
{
44 const XtensaConfig
*config
;
53 int singlestep_enabled
;
57 bool sar_m32_allocated
;
61 static TCGv_ptr cpu_env
;
62 static TCGv_i32 cpu_pc
;
63 static TCGv_i32 cpu_R
[16];
64 static TCGv_i32 cpu_SR
[256];
65 static TCGv_i32 cpu_UR
[256];
67 #include "gen-icount.h"
69 static const char * const sregnames
[256] = {
74 [SCOMPARE1
] = "SCOMPARE1",
75 [WINDOW_BASE
] = "WINDOW_BASE",
76 [WINDOW_START
] = "WINDOW_START",
79 [EXCSAVE1
] = "EXCSAVE1",
81 [EXCCAUSE
] = "EXCCAUSE",
82 [EXCVADDR
] = "EXCVADDR",
85 static const char * const uregnames
[256] = {
86 [THREADPTR
] = "THREADPTR",
91 void xtensa_translate_init(void)
93 static const char * const regnames
[] = {
94 "ar0", "ar1", "ar2", "ar3",
95 "ar4", "ar5", "ar6", "ar7",
96 "ar8", "ar9", "ar10", "ar11",
97 "ar12", "ar13", "ar14", "ar15",
101 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
102 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
103 offsetof(CPUState
, pc
), "pc");
105 for (i
= 0; i
< 16; i
++) {
106 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
107 offsetof(CPUState
, regs
[i
]),
111 for (i
= 0; i
< 256; ++i
) {
113 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
114 offsetof(CPUState
, sregs
[i
]),
119 for (i
= 0; i
< 256; ++i
) {
121 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
122 offsetof(CPUState
, uregs
[i
]),
130 static inline bool option_enabled(DisasContext
*dc
, int opt
)
132 return xtensa_option_enabled(dc
->config
, opt
);
135 static void init_sar_tracker(DisasContext
*dc
)
137 dc
->sar_5bit
= false;
138 dc
->sar_m32_5bit
= false;
139 dc
->sar_m32_allocated
= false;
142 static void reset_sar_tracker(DisasContext
*dc
)
144 if (dc
->sar_m32_allocated
) {
145 tcg_temp_free(dc
->sar_m32
);
149 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
151 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
152 if (dc
->sar_m32_5bit
) {
153 tcg_gen_discard_i32(dc
->sar_m32
);
156 dc
->sar_m32_5bit
= false;
159 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
161 TCGv_i32 tmp
= tcg_const_i32(32);
162 if (!dc
->sar_m32_allocated
) {
163 dc
->sar_m32
= tcg_temp_local_new_i32();
164 dc
->sar_m32_allocated
= true;
166 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
167 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
168 dc
->sar_5bit
= false;
169 dc
->sar_m32_5bit
= true;
173 static void gen_exception(int excp
)
175 TCGv_i32 tmp
= tcg_const_i32(excp
);
176 gen_helper_exception(tmp
);
180 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
182 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
183 TCGv_i32 tcause
= tcg_const_i32(cause
);
184 gen_helper_exception_cause(tpc
, tcause
);
186 tcg_temp_free(tcause
);
189 static void gen_check_privilege(DisasContext
*dc
)
192 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
196 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
198 tcg_gen_mov_i32(cpu_pc
, dest
);
199 if (dc
->singlestep_enabled
) {
200 gen_exception(EXCP_DEBUG
);
203 tcg_gen_goto_tb(slot
);
204 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
209 dc
->is_jmp
= DISAS_UPDATE
;
212 static void gen_jump(DisasContext
*dc
, TCGv dest
)
214 gen_jump_slot(dc
, dest
, -1);
217 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
219 TCGv_i32 tmp
= tcg_const_i32(dest
);
220 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
223 gen_jump_slot(dc
, tmp
, slot
);
227 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
230 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
232 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
233 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
234 tcg_temp_free(tcallinc
);
235 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
236 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
237 gen_jump_slot(dc
, dest
, slot
);
240 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
242 gen_callw_slot(dc
, callinc
, dest
, -1);
245 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
247 TCGv_i32 tmp
= tcg_const_i32(dest
);
248 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
251 gen_callw_slot(dc
, callinc
, tmp
, slot
);
255 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
257 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
258 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
259 dc
->next_pc
== dc
->lend
) {
260 int label
= gen_new_label();
262 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
263 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
264 gen_jumpi(dc
, dc
->lbeg
, slot
);
265 gen_set_label(label
);
266 gen_jumpi(dc
, dc
->next_pc
, -1);
272 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
274 if (!gen_check_loop_end(dc
, slot
)) {
275 gen_jumpi(dc
, dc
->next_pc
, slot
);
279 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
280 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
282 int label
= gen_new_label();
284 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
285 gen_jumpi_check_loop_end(dc
, 0);
286 gen_set_label(label
);
287 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
290 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
291 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
293 TCGv_i32 tmp
= tcg_const_i32(t1
);
294 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
298 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
300 static void (* const rsr_handler
[256])(DisasContext
*dc
,
301 TCGv_i32 d
, uint32_t sr
) = {
305 if (rsr_handler
[sr
]) {
306 rsr_handler
[sr
](dc
, d
, sr
);
308 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
311 qemu_log("RSR %d not implemented, ", sr
);
315 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
317 gen_helper_wsr_lbeg(s
);
320 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
322 gen_helper_wsr_lend(s
);
325 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
327 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
328 if (dc
->sar_m32_5bit
) {
329 tcg_gen_discard_i32(dc
->sar_m32
);
331 dc
->sar_5bit
= false;
332 dc
->sar_m32_5bit
= false;
335 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
337 gen_helper_wsr_windowbase(v
);
340 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
342 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
343 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
345 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
348 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
349 /* This can change mmu index, so exit tb */
350 gen_jumpi_check_loop_end(dc
, -1);
353 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
355 static void (* const wsr_handler
[256])(DisasContext
*dc
,
356 uint32_t sr
, TCGv_i32 v
) = {
357 [LBEG
] = gen_wsr_lbeg
,
358 [LEND
] = gen_wsr_lend
,
360 [WINDOW_BASE
] = gen_wsr_windowbase
,
365 if (wsr_handler
[sr
]) {
366 wsr_handler
[sr
](dc
, sr
, s
);
368 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
371 qemu_log("WSR %d not implemented, ", sr
);
375 static void disas_xtensa_insn(DisasContext
*dc
)
377 #define HAS_OPTION(opt) do { \
378 if (!option_enabled(dc, opt)) { \
379 qemu_log("Option %d is not enabled %s:%d\n", \
380 (opt), __FILE__, __LINE__); \
381 goto invalid_opcode; \
385 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
386 #define RESERVED() do { \
387 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
388 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
389 goto invalid_opcode; \
393 #ifdef TARGET_WORDS_BIGENDIAN
394 #define OP0 (((b0) & 0xf0) >> 4)
395 #define OP1 (((b2) & 0xf0) >> 4)
396 #define OP2 ((b2) & 0xf)
397 #define RRR_R ((b1) & 0xf)
398 #define RRR_S (((b1) & 0xf0) >> 4)
399 #define RRR_T ((b0) & 0xf)
401 #define OP0 (((b0) & 0xf))
402 #define OP1 (((b2) & 0xf))
403 #define OP2 (((b2) & 0xf0) >> 4)
404 #define RRR_R (((b1) & 0xf0) >> 4)
405 #define RRR_S (((b1) & 0xf))
406 #define RRR_T (((b0) & 0xf0) >> 4)
416 #define RRI8_IMM8 (b2)
417 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
419 #ifdef TARGET_WORDS_BIGENDIAN
420 #define RI16_IMM16 (((b1) << 8) | (b2))
422 #define RI16_IMM16 (((b2) << 8) | (b1))
425 #ifdef TARGET_WORDS_BIGENDIAN
426 #define CALL_N (((b0) & 0xc) >> 2)
427 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
429 #define CALL_N (((b0) & 0x30) >> 4)
430 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
432 #define CALL_OFFSET_SE \
433 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
435 #define CALLX_N CALL_N
436 #ifdef TARGET_WORDS_BIGENDIAN
437 #define CALLX_M ((b0) & 0x3)
439 #define CALLX_M (((b0) & 0xc0) >> 6)
441 #define CALLX_S RRR_S
443 #define BRI12_M CALLX_M
444 #define BRI12_S RRR_S
445 #ifdef TARGET_WORDS_BIGENDIAN
446 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
448 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
450 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
452 #define BRI8_M BRI12_M
453 #define BRI8_R RRI8_R
454 #define BRI8_S RRI8_S
455 #define BRI8_IMM8 RRI8_IMM8
456 #define BRI8_IMM8_SE RRI8_IMM8_SE
460 uint8_t b0
= ldub_code(dc
->pc
);
461 uint8_t b1
= ldub_code(dc
->pc
+ 1);
462 uint8_t b2
= ldub_code(dc
->pc
+ 2);
464 static const uint32_t B4CONST
[] = {
465 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
468 static const uint32_t B4CONSTU
[] = {
469 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
473 dc
->next_pc
= dc
->pc
+ 2;
474 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
476 dc
->next_pc
= dc
->pc
+ 3;
485 if ((RRR_R
& 0xc) == 0x8) {
486 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
493 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
504 gen_jump(dc
, cpu_R
[CALLX_S
]);
508 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
510 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
511 gen_helper_retw(tmp
, tmp
);
527 TCGv_i32 tmp
= tcg_temp_new_i32();
528 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
529 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
538 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
540 TCGv_i32 tmp
= tcg_temp_new_i32();
542 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
543 gen_callw(dc
, CALLX_N
, tmp
);
553 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
555 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
556 gen_helper_movsp(pc
);
557 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
577 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
589 default: /*reserved*/
598 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
601 gen_check_privilege(dc
);
602 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
603 gen_jump(dc
, cpu_SR
[EPC1
]);
611 gen_check_privilege(dc
);
613 dc
->config
->ndepc
? DEPC
: EPC1
]);
618 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
619 gen_check_privilege(dc
);
621 TCGv_i32 tmp
= tcg_const_i32(1);
624 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
625 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
628 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
629 cpu_SR
[WINDOW_START
], tmp
);
631 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
632 cpu_SR
[WINDOW_START
], tmp
);
635 gen_helper_restore_owb();
636 gen_jump(dc
, cpu_SR
[EPC1
]);
642 default: /*reserved*/
649 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
657 default: /*reserved*/
665 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
670 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
673 gen_exception_cause(dc
, SYSCALL_CAUSE
);
687 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
688 gen_check_privilege(dc
);
689 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
690 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
691 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
],
692 RRR_S
| ~PS_INTLEVEL
);
696 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
701 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
706 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
711 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
716 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
720 default: /*reserved*/
728 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
732 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
736 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
742 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
746 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
751 TCGv_i32 tmp
= tcg_temp_new_i32();
752 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
753 gen_right_shift_sar(dc
, tmp
);
760 TCGv_i32 tmp
= tcg_temp_new_i32();
761 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
762 gen_left_shift_sar(dc
, tmp
);
769 TCGv_i32 tmp
= tcg_const_i32(
770 RRR_S
| ((RRR_T
& 1) << 4));
771 gen_right_shift_sar(dc
, tmp
);
785 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
786 gen_check_privilege(dc
);
788 TCGv_i32 tmp
= tcg_const_i32(
789 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
790 gen_helper_rotw(tmp
);
796 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
797 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
801 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
802 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
805 default: /*reserved*/
818 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
823 int label
= gen_new_label();
824 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
826 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
827 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
828 gen_set_label(label
);
832 default: /*reserved*/
843 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
850 TCGv_i32 tmp
= tcg_temp_new_i32();
851 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
852 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
858 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
865 TCGv_i32 tmp
= tcg_temp_new_i32();
866 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
867 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
878 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
879 32 - (RRR_T
| ((OP2
& 1) << 4)));
884 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
885 RRR_S
| ((OP2
& 1) << 4));
889 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
894 TCGv_i32 tmp
= tcg_temp_new_i32();
896 gen_check_privilege(dc
);
898 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
899 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
900 gen_wsr(dc
, RSR_SR
, tmp
);
902 if (!sregnames
[RSR_SR
]) {
909 * Note: 64 bit ops are used here solely because SAR values
912 #define gen_shift_reg(cmd, reg) do { \
913 TCGv_i64 tmp = tcg_temp_new_i64(); \
914 tcg_gen_extu_i32_i64(tmp, reg); \
915 tcg_gen_##cmd##_i64(v, v, tmp); \
916 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
917 tcg_temp_free_i64(v); \
918 tcg_temp_free_i64(tmp); \
921 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
925 TCGv_i64 v
= tcg_temp_new_i64();
926 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
933 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
935 TCGv_i64 v
= tcg_temp_new_i64();
936 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
942 if (dc
->sar_m32_5bit
) {
943 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
945 TCGv_i64 v
= tcg_temp_new_i64();
946 TCGv_i32 s
= tcg_const_i32(32);
947 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
948 tcg_gen_andi_i32(s
, s
, 0x3f);
949 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
950 gen_shift_reg(shl
, s
);
957 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
959 TCGv_i64 v
= tcg_temp_new_i64();
960 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
968 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
970 TCGv_i32 v1
= tcg_temp_new_i32();
971 TCGv_i32 v2
= tcg_temp_new_i32();
972 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
973 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
974 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
981 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
983 TCGv_i32 v1
= tcg_temp_new_i32();
984 TCGv_i32 v2
= tcg_temp_new_i32();
985 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
986 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
987 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
993 default: /*reserved*/
1001 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1002 int label
= gen_new_label();
1003 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1004 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1005 gen_set_label(label
);
1010 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1011 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1016 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1018 TCGv_i64 r
= tcg_temp_new_i64();
1019 TCGv_i64 s
= tcg_temp_new_i64();
1020 TCGv_i64 t
= tcg_temp_new_i64();
1023 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1024 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1026 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1027 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1029 tcg_gen_mul_i64(r
, s
, t
);
1030 tcg_gen_shri_i64(r
, r
, 32);
1031 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1033 tcg_temp_free_i64(r
);
1034 tcg_temp_free_i64(s
);
1035 tcg_temp_free_i64(t
);
1040 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1046 int label1
= gen_new_label();
1047 int label2
= gen_new_label();
1049 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1051 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1053 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1054 OP2
== 13 ? 0x80000000 : 0);
1056 gen_set_label(label1
);
1058 tcg_gen_div_i32(cpu_R
[RRR_R
],
1059 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1061 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1062 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1064 gen_set_label(label2
);
1069 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1072 default: /*reserved*/
1082 gen_check_privilege(dc
);
1084 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1085 if (!sregnames
[RSR_SR
]) {
1092 gen_check_privilege(dc
);
1094 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1095 if (!sregnames
[RSR_SR
]) {
1101 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1103 int shift
= 24 - RRR_T
;
1106 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1107 } else if (shift
== 16) {
1108 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1110 TCGv_i32 tmp
= tcg_temp_new_i32();
1111 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1112 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1119 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1121 TCGv_i32 tmp1
= tcg_temp_new_i32();
1122 TCGv_i32 tmp2
= tcg_temp_new_i32();
1123 int label
= gen_new_label();
1125 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1126 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1127 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1128 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1129 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1131 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1132 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1133 0xffffffff >> (25 - RRR_T
));
1135 gen_set_label(label
);
1137 tcg_temp_free(tmp1
);
1138 tcg_temp_free(tmp2
);
1146 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1148 static const TCGCond cond
[] = {
1154 int label
= gen_new_label();
1156 if (RRR_R
!= RRR_T
) {
1157 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1158 tcg_gen_brcond_i32(cond
[OP2
- 4],
1159 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1160 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1162 tcg_gen_brcond_i32(cond
[OP2
- 4],
1163 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1164 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1166 gen_set_label(label
);
1175 static const TCGCond cond
[] = {
1181 int label
= gen_new_label();
1182 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1183 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1184 gen_set_label(label
);
1189 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1194 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1200 int st
= (RRR_S
<< 4) + RRR_T
;
1201 if (uregnames
[st
]) {
1202 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1204 qemu_log("RUR %d not implemented, ", st
);
1212 if (uregnames
[RSR_SR
]) {
1213 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
1215 qemu_log("WUR %d not implemented, ", RSR_SR
);
1227 int shiftimm
= RRR_S
| (OP1
<< 4);
1228 int maskimm
= (1 << (OP2
+ 1)) - 1;
1230 TCGv_i32 tmp
= tcg_temp_new_i32();
1231 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1232 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1246 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1253 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1254 gen_check_privilege(dc
);
1256 TCGv_i32 addr
= tcg_temp_new_i32();
1257 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1258 (0xffffffc0 | (RRR_R
<< 2)));
1259 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1260 tcg_temp_free(addr
);
1265 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1266 gen_check_privilege(dc
);
1268 TCGv_i32 addr
= tcg_temp_new_i32();
1269 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1270 (0xffffffc0 | (RRR_R
<< 2)));
1271 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1272 tcg_temp_free(addr
);
1283 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1288 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1292 default: /*reserved*/
1300 TCGv_i32 tmp
= tcg_const_i32(
1301 (0xfffc0000 | (RI16_IMM16
<< 2)) +
1302 ((dc
->pc
+ 3) & ~3));
1306 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
1312 #define gen_load_store(type, shift) do { \
1313 TCGv_i32 addr = tcg_temp_new_i32(); \
1314 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1315 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1316 tcg_temp_free(addr); \
1321 gen_load_store(ld8u
, 0);
1325 gen_load_store(ld16u
, 1);
1329 gen_load_store(ld32u
, 2);
1333 gen_load_store(st8
, 0);
1337 gen_load_store(st16
, 1);
1341 gen_load_store(st32
, 2);
1346 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1377 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1381 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1385 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1389 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1393 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1396 default: /*reserved*/
1404 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1410 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1414 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1418 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1421 default: /*reserved*/
1428 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1432 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1435 default: /*reserved*/
1442 gen_load_store(ld16s
, 1);
1446 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
1447 RRI8_IMM8
| (RRI8_S
<< 8) |
1448 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
1452 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1453 gen_load_store(ld32u
, 2); /*TODO acquire?*/
1457 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
1461 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
1464 case 14: /*S32C1Iy*/
1465 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1467 int label
= gen_new_label();
1468 TCGv_i32 tmp
= tcg_temp_local_new_i32();
1469 TCGv_i32 addr
= tcg_temp_local_new_i32();
1471 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
1472 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
1473 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
1474 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
1475 cpu_SR
[SCOMPARE1
], label
);
1477 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
1479 gen_set_label(label
);
1480 tcg_temp_free(addr
);
1486 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1487 gen_load_store(st32
, 2); /*TODO release?*/
1490 default: /*reserved*/
1495 #undef gen_load_store
1498 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1503 HAS_OPTION(XTENSA_OPTION_MAC16
);
1510 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1511 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1517 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1518 gen_callwi(dc
, CALL_N
,
1519 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1527 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
1532 static const TCGCond cond
[] = {
1533 TCG_COND_EQ
, /*BEQZ*/
1534 TCG_COND_NE
, /*BNEZ*/
1535 TCG_COND_LT
, /*BLTZ*/
1536 TCG_COND_GE
, /*BGEZ*/
1539 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
1540 4 + BRI12_IMM12_SE
);
1546 static const TCGCond cond
[] = {
1547 TCG_COND_EQ
, /*BEQI*/
1548 TCG_COND_NE
, /*BNEI*/
1549 TCG_COND_LT
, /*BLTI*/
1550 TCG_COND_GE
, /*BGEI*/
1553 gen_brcondi(dc
, cond
[BRI8_M
& 3],
1554 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
1561 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1563 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1564 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
1565 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
1566 gen_helper_entry(pc
, s
, imm
);
1576 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1581 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1587 case 10: /*LOOPGTZ*/
1588 HAS_OPTION(XTENSA_OPTION_LOOP
);
1590 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
1591 TCGv_i32 tmp
= tcg_const_i32(lend
);
1593 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
1594 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
1595 gen_wsr_lend(dc
, LEND
, tmp
);
1599 int label
= gen_new_label();
1600 tcg_gen_brcondi_i32(
1601 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
1602 cpu_R
[RRI8_S
], 0, label
);
1603 gen_jumpi(dc
, lend
, 1);
1604 gen_set_label(label
);
1607 gen_jumpi(dc
, dc
->next_pc
, 0);
1611 default: /*reserved*/
1620 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
1621 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
1631 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
1633 switch (RRI8_R
& 7) {
1634 case 0: /*BNONE*/ /*BANY*/
1636 TCGv_i32 tmp
= tcg_temp_new_i32();
1637 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
1638 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1643 case 1: /*BEQ*/ /*BNE*/
1644 case 2: /*BLT*/ /*BGE*/
1645 case 3: /*BLTU*/ /*BGEU*/
1647 static const TCGCond cond
[] = {
1653 [11] = TCG_COND_GEU
,
1655 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
1660 case 4: /*BALL*/ /*BNALL*/
1662 TCGv_i32 tmp
= tcg_temp_new_i32();
1663 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
1664 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
1670 case 5: /*BBC*/ /*BBS*/
1672 TCGv_i32 bit
= tcg_const_i32(1);
1673 TCGv_i32 tmp
= tcg_temp_new_i32();
1674 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
1675 tcg_gen_shl_i32(bit
, bit
, tmp
);
1676 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
1677 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1683 case 6: /*BBCI*/ /*BBSI*/
1686 TCGv_i32 tmp
= tcg_temp_new_i32();
1687 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
1688 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
1689 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1698 #define gen_narrow_load_store(type) do { \
1699 TCGv_i32 addr = tcg_temp_new_i32(); \
1700 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
1701 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
1702 tcg_temp_free(addr); \
1706 gen_narrow_load_store(ld32u
);
1710 gen_narrow_load_store(st32
);
1712 #undef gen_narrow_load_store
1715 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
1718 case 11: /*ADDI.Nn*/
1719 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
1723 if (RRRN_T
< 8) { /*MOVI.Nn*/
1724 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
1725 RRRN_R
| (RRRN_T
<< 4) |
1726 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
1727 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
1728 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
1730 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
1731 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
1738 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
1744 gen_jump(dc
, cpu_R
[0]);
1748 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1750 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
1751 gen_helper_retw(tmp
, tmp
);
1757 case 2: /*BREAK.Nn*/
1765 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1768 default: /*reserved*/
1774 default: /*reserved*/
1780 default: /*reserved*/
1785 gen_check_loop_end(dc
, 0);
1786 dc
->pc
= dc
->next_pc
;
1791 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
1792 dc
->pc
= dc
->next_pc
;
1796 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1800 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1801 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1802 if (bp
->pc
== dc
->pc
) {
1803 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1804 gen_exception(EXCP_DEBUG
);
1805 dc
->is_jmp
= DISAS_UPDATE
;
1811 static void gen_intermediate_code_internal(
1812 CPUState
*env
, TranslationBlock
*tb
, int search_pc
)
1817 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1818 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1819 uint32_t pc_start
= tb
->pc
;
1820 uint32_t next_page_start
=
1821 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1823 if (max_insns
== 0) {
1824 max_insns
= CF_COUNT_MASK
;
1827 dc
.config
= env
->config
;
1828 dc
.singlestep_enabled
= env
->singlestep_enabled
;
1831 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
1832 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
1833 dc
.lbeg
= env
->sregs
[LBEG
];
1834 dc
.lend
= env
->sregs
[LEND
];
1835 dc
.is_jmp
= DISAS_NEXT
;
1837 init_sar_tracker(&dc
);
1841 if (env
->singlestep_enabled
&& env
->exception_taken
) {
1842 env
->exception_taken
= 0;
1843 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1844 gen_exception(EXCP_DEBUG
);
1848 check_breakpoint(env
, &dc
);
1851 j
= gen_opc_ptr
- gen_opc_buf
;
1855 gen_opc_instr_start
[lj
++] = 0;
1858 gen_opc_pc
[lj
] = dc
.pc
;
1859 gen_opc_instr_start
[lj
] = 1;
1860 gen_opc_icount
[lj
] = insn_count
;
1863 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
1864 tcg_gen_debug_insn_start(dc
.pc
);
1867 disas_xtensa_insn(&dc
);
1869 if (env
->singlestep_enabled
) {
1870 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1871 gen_exception(EXCP_DEBUG
);
1874 } while (dc
.is_jmp
== DISAS_NEXT
&&
1875 insn_count
< max_insns
&&
1876 dc
.pc
< next_page_start
&&
1877 gen_opc_ptr
< gen_opc_end
);
1879 reset_sar_tracker(&dc
);
1881 if (dc
.is_jmp
== DISAS_NEXT
) {
1882 gen_jumpi(&dc
, dc
.pc
, 0);
1884 gen_icount_end(tb
, insn_count
);
1885 *gen_opc_ptr
= INDEX_op_end
;
1888 tb
->size
= dc
.pc
- pc_start
;
1889 tb
->icount
= insn_count
;
1893 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
1895 gen_intermediate_code_internal(env
, tb
, 0);
1898 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
1900 gen_intermediate_code_internal(env
, tb
, 1);
1903 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1908 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1910 for (i
= j
= 0; i
< 256; ++i
) {
1912 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
1913 (j
++ % 4) == 3 ? '\n' : ' ');
1917 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1919 for (i
= j
= 0; i
< 256; ++i
) {
1921 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
1922 (j
++ % 4) == 3 ? '\n' : ' ');
1926 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1928 for (i
= 0; i
< 16; ++i
) {
1929 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
1930 (i
% 4) == 3 ? '\n' : ' ');
1933 cpu_fprintf(f
, "\n");
1935 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1936 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
1937 (i
% 4) == 3 ? '\n' : ' ');
1941 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
1943 env
->pc
= gen_opc_pc
[pc_pos
];