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1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec-all.h"
35 #include "disas.h"
36 #include "tcg-op.h"
37 #include "qemu-log.h"
38 #include "sysemu.h"
39
40 #include "helpers.h"
41 #define GEN_HELPER 1
42 #include "helpers.h"
43
44 typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
49 int cring;
50 int ring;
51 uint32_t lbeg;
52 uint32_t lend;
53 TCGv_i32 litbase;
54 int is_jmp;
55 int singlestep_enabled;
56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
61
62 uint32_t ccount_delta;
63 unsigned used_window;
64 } DisasContext;
65
66 static TCGv_ptr cpu_env;
67 static TCGv_i32 cpu_pc;
68 static TCGv_i32 cpu_R[16];
69 static TCGv_i32 cpu_SR[256];
70 static TCGv_i32 cpu_UR[256];
71
72 #include "gen-icount.h"
73
74 static const char * const sregnames[256] = {
75 [LBEG] = "LBEG",
76 [LEND] = "LEND",
77 [LCOUNT] = "LCOUNT",
78 [SAR] = "SAR",
79 [LITBASE] = "LITBASE",
80 [SCOMPARE1] = "SCOMPARE1",
81 [WINDOW_BASE] = "WINDOW_BASE",
82 [WINDOW_START] = "WINDOW_START",
83 [EPC1] = "EPC1",
84 [EPC1 + 1] = "EPC2",
85 [EPC1 + 2] = "EPC3",
86 [EPC1 + 3] = "EPC4",
87 [EPC1 + 4] = "EPC5",
88 [EPC1 + 5] = "EPC6",
89 [EPC1 + 6] = "EPC7",
90 [DEPC] = "DEPC",
91 [EPS2] = "EPS2",
92 [EPS2 + 1] = "EPS3",
93 [EPS2 + 2] = "EPS4",
94 [EPS2 + 3] = "EPS5",
95 [EPS2 + 4] = "EPS6",
96 [EPS2 + 5] = "EPS7",
97 [EXCSAVE1] = "EXCSAVE1",
98 [EXCSAVE1 + 1] = "EXCSAVE2",
99 [EXCSAVE1 + 2] = "EXCSAVE3",
100 [EXCSAVE1 + 3] = "EXCSAVE4",
101 [EXCSAVE1 + 4] = "EXCSAVE5",
102 [EXCSAVE1 + 5] = "EXCSAVE6",
103 [EXCSAVE1 + 6] = "EXCSAVE7",
104 [INTSET] = "INTSET",
105 [INTCLEAR] = "INTCLEAR",
106 [INTENABLE] = "INTENABLE",
107 [PS] = "PS",
108 [EXCCAUSE] = "EXCCAUSE",
109 [CCOUNT] = "CCOUNT",
110 [EXCVADDR] = "EXCVADDR",
111 [CCOMPARE] = "CCOMPARE0",
112 [CCOMPARE + 1] = "CCOMPARE1",
113 [CCOMPARE + 2] = "CCOMPARE2",
114 };
115
116 static const char * const uregnames[256] = {
117 [THREADPTR] = "THREADPTR",
118 [FCR] = "FCR",
119 [FSR] = "FSR",
120 };
121
122 void xtensa_translate_init(void)
123 {
124 static const char * const regnames[] = {
125 "ar0", "ar1", "ar2", "ar3",
126 "ar4", "ar5", "ar6", "ar7",
127 "ar8", "ar9", "ar10", "ar11",
128 "ar12", "ar13", "ar14", "ar15",
129 };
130 int i;
131
132 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
133 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
134 offsetof(CPUState, pc), "pc");
135
136 for (i = 0; i < 16; i++) {
137 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
138 offsetof(CPUState, regs[i]),
139 regnames[i]);
140 }
141
142 for (i = 0; i < 256; ++i) {
143 if (sregnames[i]) {
144 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
145 offsetof(CPUState, sregs[i]),
146 sregnames[i]);
147 }
148 }
149
150 for (i = 0; i < 256; ++i) {
151 if (uregnames[i]) {
152 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
153 offsetof(CPUState, uregs[i]),
154 uregnames[i]);
155 }
156 }
157 #define GEN_HELPER 2
158 #include "helpers.h"
159 }
160
161 static inline bool option_enabled(DisasContext *dc, int opt)
162 {
163 return xtensa_option_enabled(dc->config, opt);
164 }
165
166 static void init_litbase(DisasContext *dc)
167 {
168 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
169 dc->litbase = tcg_temp_local_new_i32();
170 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
171 }
172 }
173
174 static void reset_litbase(DisasContext *dc)
175 {
176 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
177 tcg_temp_free(dc->litbase);
178 }
179 }
180
181 static void init_sar_tracker(DisasContext *dc)
182 {
183 dc->sar_5bit = false;
184 dc->sar_m32_5bit = false;
185 dc->sar_m32_allocated = false;
186 }
187
188 static void reset_sar_tracker(DisasContext *dc)
189 {
190 if (dc->sar_m32_allocated) {
191 tcg_temp_free(dc->sar_m32);
192 }
193 }
194
195 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
196 {
197 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
198 if (dc->sar_m32_5bit) {
199 tcg_gen_discard_i32(dc->sar_m32);
200 }
201 dc->sar_5bit = true;
202 dc->sar_m32_5bit = false;
203 }
204
205 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
206 {
207 TCGv_i32 tmp = tcg_const_i32(32);
208 if (!dc->sar_m32_allocated) {
209 dc->sar_m32 = tcg_temp_local_new_i32();
210 dc->sar_m32_allocated = true;
211 }
212 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
213 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
214 dc->sar_5bit = false;
215 dc->sar_m32_5bit = true;
216 tcg_temp_free(tmp);
217 }
218
219 static void gen_advance_ccount(DisasContext *dc)
220 {
221 if (dc->ccount_delta > 0) {
222 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
223 dc->ccount_delta = 0;
224 gen_helper_advance_ccount(tmp);
225 tcg_temp_free(tmp);
226 }
227 }
228
229 static void reset_used_window(DisasContext *dc)
230 {
231 dc->used_window = 0;
232 }
233
234 static void gen_exception(DisasContext *dc, int excp)
235 {
236 TCGv_i32 tmp = tcg_const_i32(excp);
237 gen_advance_ccount(dc);
238 gen_helper_exception(tmp);
239 tcg_temp_free(tmp);
240 }
241
242 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
243 {
244 TCGv_i32 tpc = tcg_const_i32(dc->pc);
245 TCGv_i32 tcause = tcg_const_i32(cause);
246 gen_advance_ccount(dc);
247 gen_helper_exception_cause(tpc, tcause);
248 tcg_temp_free(tpc);
249 tcg_temp_free(tcause);
250 }
251
252 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
253 TCGv_i32 vaddr)
254 {
255 TCGv_i32 tpc = tcg_const_i32(dc->pc);
256 TCGv_i32 tcause = tcg_const_i32(cause);
257 gen_advance_ccount(dc);
258 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
259 tcg_temp_free(tpc);
260 tcg_temp_free(tcause);
261 }
262
263 static void gen_check_privilege(DisasContext *dc)
264 {
265 if (dc->cring) {
266 gen_exception_cause(dc, PRIVILEGED_CAUSE);
267 }
268 }
269
270 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
271 {
272 tcg_gen_mov_i32(cpu_pc, dest);
273 if (dc->singlestep_enabled) {
274 gen_exception(dc, EXCP_DEBUG);
275 } else {
276 gen_advance_ccount(dc);
277 if (slot >= 0) {
278 tcg_gen_goto_tb(slot);
279 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
280 } else {
281 tcg_gen_exit_tb(0);
282 }
283 }
284 dc->is_jmp = DISAS_UPDATE;
285 }
286
287 static void gen_jump(DisasContext *dc, TCGv dest)
288 {
289 gen_jump_slot(dc, dest, -1);
290 }
291
292 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
293 {
294 TCGv_i32 tmp = tcg_const_i32(dest);
295 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
296 slot = -1;
297 }
298 gen_jump_slot(dc, tmp, slot);
299 tcg_temp_free(tmp);
300 }
301
302 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
303 int slot)
304 {
305 TCGv_i32 tcallinc = tcg_const_i32(callinc);
306
307 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
308 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
309 tcg_temp_free(tcallinc);
310 tcg_gen_movi_i32(cpu_R[callinc << 2],
311 (callinc << 30) | (dc->next_pc & 0x3fffffff));
312 gen_jump_slot(dc, dest, slot);
313 }
314
315 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
316 {
317 gen_callw_slot(dc, callinc, dest, -1);
318 }
319
320 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
321 {
322 TCGv_i32 tmp = tcg_const_i32(dest);
323 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
324 slot = -1;
325 }
326 gen_callw_slot(dc, callinc, tmp, slot);
327 tcg_temp_free(tmp);
328 }
329
330 static bool gen_check_loop_end(DisasContext *dc, int slot)
331 {
332 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
333 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
334 dc->next_pc == dc->lend) {
335 int label = gen_new_label();
336
337 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
338 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
339 gen_jumpi(dc, dc->lbeg, slot);
340 gen_set_label(label);
341 gen_jumpi(dc, dc->next_pc, -1);
342 return true;
343 }
344 return false;
345 }
346
347 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
348 {
349 if (!gen_check_loop_end(dc, slot)) {
350 gen_jumpi(dc, dc->next_pc, slot);
351 }
352 }
353
354 static void gen_brcond(DisasContext *dc, TCGCond cond,
355 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
356 {
357 int label = gen_new_label();
358
359 tcg_gen_brcond_i32(cond, t0, t1, label);
360 gen_jumpi_check_loop_end(dc, 0);
361 gen_set_label(label);
362 gen_jumpi(dc, dc->pc + offset, 1);
363 }
364
365 static void gen_brcondi(DisasContext *dc, TCGCond cond,
366 TCGv_i32 t0, uint32_t t1, uint32_t offset)
367 {
368 TCGv_i32 tmp = tcg_const_i32(t1);
369 gen_brcond(dc, cond, t0, tmp, offset);
370 tcg_temp_free(tmp);
371 }
372
373 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
374 {
375 gen_advance_ccount(dc);
376 tcg_gen_mov_i32(d, cpu_SR[sr]);
377 }
378
379 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
380 {
381 static void (* const rsr_handler[256])(DisasContext *dc,
382 TCGv_i32 d, uint32_t sr) = {
383 [CCOUNT] = gen_rsr_ccount,
384 };
385
386 if (sregnames[sr]) {
387 if (rsr_handler[sr]) {
388 rsr_handler[sr](dc, d, sr);
389 } else {
390 tcg_gen_mov_i32(d, cpu_SR[sr]);
391 }
392 } else {
393 qemu_log("RSR %d not implemented, ", sr);
394 }
395 }
396
397 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
398 {
399 gen_helper_wsr_lbeg(s);
400 }
401
402 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
403 {
404 gen_helper_wsr_lend(s);
405 }
406
407 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
408 {
409 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
410 if (dc->sar_m32_5bit) {
411 tcg_gen_discard_i32(dc->sar_m32);
412 }
413 dc->sar_5bit = false;
414 dc->sar_m32_5bit = false;
415 }
416
417 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
418 {
419 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
420 /* This can change tb->flags, so exit tb */
421 gen_jumpi_check_loop_end(dc, -1);
422 }
423
424 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
425 {
426 gen_helper_wsr_windowbase(v);
427 reset_used_window(dc);
428 }
429
430 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
431 {
432 tcg_gen_mov_i32(cpu_SR[sr], v);
433 reset_used_window(dc);
434 }
435
436 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
437 {
438 tcg_gen_andi_i32(cpu_SR[sr], v,
439 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
440 gen_helper_check_interrupts(cpu_env);
441 gen_jumpi_check_loop_end(dc, 0);
442 }
443
444 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
445 {
446 TCGv_i32 tmp = tcg_temp_new_i32();
447
448 tcg_gen_andi_i32(tmp, v,
449 dc->config->inttype_mask[INTTYPE_EDGE] |
450 dc->config->inttype_mask[INTTYPE_NMI] |
451 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
452 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
453 tcg_temp_free(tmp);
454 gen_helper_check_interrupts(cpu_env);
455 }
456
457 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
458 {
459 tcg_gen_mov_i32(cpu_SR[sr], v);
460 gen_helper_check_interrupts(cpu_env);
461 gen_jumpi_check_loop_end(dc, 0);
462 }
463
464 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
465 {
466 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
467 PS_UM | PS_EXCM | PS_INTLEVEL;
468
469 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
470 mask |= PS_RING;
471 }
472 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
473 reset_used_window(dc);
474 gen_helper_check_interrupts(cpu_env);
475 /* This can change mmu index and tb->flags, so exit tb */
476 gen_jumpi_check_loop_end(dc, -1);
477 }
478
479 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
480 {
481 uint32_t id = sr - CCOMPARE;
482 if (id < dc->config->nccompare) {
483 uint32_t int_bit = 1 << dc->config->timerint[id];
484 gen_advance_ccount(dc);
485 tcg_gen_mov_i32(cpu_SR[sr], v);
486 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
487 gen_helper_check_interrupts(cpu_env);
488 }
489 }
490
491 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
492 {
493 static void (* const wsr_handler[256])(DisasContext *dc,
494 uint32_t sr, TCGv_i32 v) = {
495 [LBEG] = gen_wsr_lbeg,
496 [LEND] = gen_wsr_lend,
497 [SAR] = gen_wsr_sar,
498 [LITBASE] = gen_wsr_litbase,
499 [WINDOW_BASE] = gen_wsr_windowbase,
500 [WINDOW_START] = gen_wsr_windowstart,
501 [INTSET] = gen_wsr_intset,
502 [INTCLEAR] = gen_wsr_intclear,
503 [INTENABLE] = gen_wsr_intenable,
504 [PS] = gen_wsr_ps,
505 [CCOMPARE] = gen_wsr_ccompare,
506 [CCOMPARE + 1] = gen_wsr_ccompare,
507 [CCOMPARE + 2] = gen_wsr_ccompare,
508 };
509
510 if (sregnames[sr]) {
511 if (wsr_handler[sr]) {
512 wsr_handler[sr](dc, sr, s);
513 } else {
514 tcg_gen_mov_i32(cpu_SR[sr], s);
515 }
516 } else {
517 qemu_log("WSR %d not implemented, ", sr);
518 }
519 }
520
521 static void gen_load_store_alignment(DisasContext *dc, int shift,
522 TCGv_i32 addr, bool no_hw_alignment)
523 {
524 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
525 tcg_gen_andi_i32(addr, addr, ~0 << shift);
526 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
527 no_hw_alignment) {
528 int label = gen_new_label();
529 TCGv_i32 tmp = tcg_temp_new_i32();
530 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
531 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
532 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
533 gen_set_label(label);
534 tcg_temp_free(tmp);
535 }
536 }
537
538 static void gen_waiti(DisasContext *dc, uint32_t imm4)
539 {
540 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
541 TCGv_i32 intlevel = tcg_const_i32(imm4);
542 gen_advance_ccount(dc);
543 gen_helper_waiti(pc, intlevel);
544 tcg_temp_free(pc);
545 tcg_temp_free(intlevel);
546 }
547
548 static void gen_window_check1(DisasContext *dc, unsigned r1)
549 {
550 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
551 return;
552 }
553 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
554 r1 / 4 > dc->used_window) {
555 TCGv_i32 pc = tcg_const_i32(dc->pc);
556 TCGv_i32 w = tcg_const_i32(r1 / 4);
557
558 dc->used_window = r1 / 4;
559 gen_advance_ccount(dc);
560 gen_helper_window_check(pc, w);
561
562 tcg_temp_free(w);
563 tcg_temp_free(pc);
564 }
565 }
566
567 static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
568 {
569 gen_window_check1(dc, r1 > r2 ? r1 : r2);
570 }
571
572 static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
573 unsigned r3)
574 {
575 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
576 }
577
578 static void disas_xtensa_insn(DisasContext *dc)
579 {
580 #define HAS_OPTION(opt) do { \
581 if (!option_enabled(dc, opt)) { \
582 qemu_log("Option %d is not enabled %s:%d\n", \
583 (opt), __FILE__, __LINE__); \
584 goto invalid_opcode; \
585 } \
586 } while (0)
587
588 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
589 #define RESERVED() do { \
590 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
591 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
592 goto invalid_opcode; \
593 } while (0)
594
595
596 #ifdef TARGET_WORDS_BIGENDIAN
597 #define OP0 (((b0) & 0xf0) >> 4)
598 #define OP1 (((b2) & 0xf0) >> 4)
599 #define OP2 ((b2) & 0xf)
600 #define RRR_R ((b1) & 0xf)
601 #define RRR_S (((b1) & 0xf0) >> 4)
602 #define RRR_T ((b0) & 0xf)
603 #else
604 #define OP0 (((b0) & 0xf))
605 #define OP1 (((b2) & 0xf))
606 #define OP2 (((b2) & 0xf0) >> 4)
607 #define RRR_R (((b1) & 0xf0) >> 4)
608 #define RRR_S (((b1) & 0xf))
609 #define RRR_T (((b0) & 0xf0) >> 4)
610 #endif
611
612 #define RRRN_R RRR_R
613 #define RRRN_S RRR_S
614 #define RRRN_T RRR_T
615
616 #define RRI8_R RRR_R
617 #define RRI8_S RRR_S
618 #define RRI8_T RRR_T
619 #define RRI8_IMM8 (b2)
620 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
621
622 #ifdef TARGET_WORDS_BIGENDIAN
623 #define RI16_IMM16 (((b1) << 8) | (b2))
624 #else
625 #define RI16_IMM16 (((b2) << 8) | (b1))
626 #endif
627
628 #ifdef TARGET_WORDS_BIGENDIAN
629 #define CALL_N (((b0) & 0xc) >> 2)
630 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
631 #else
632 #define CALL_N (((b0) & 0x30) >> 4)
633 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
634 #endif
635 #define CALL_OFFSET_SE \
636 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
637
638 #define CALLX_N CALL_N
639 #ifdef TARGET_WORDS_BIGENDIAN
640 #define CALLX_M ((b0) & 0x3)
641 #else
642 #define CALLX_M (((b0) & 0xc0) >> 6)
643 #endif
644 #define CALLX_S RRR_S
645
646 #define BRI12_M CALLX_M
647 #define BRI12_S RRR_S
648 #ifdef TARGET_WORDS_BIGENDIAN
649 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
650 #else
651 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
652 #endif
653 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
654
655 #define BRI8_M BRI12_M
656 #define BRI8_R RRI8_R
657 #define BRI8_S RRI8_S
658 #define BRI8_IMM8 RRI8_IMM8
659 #define BRI8_IMM8_SE RRI8_IMM8_SE
660
661 #define RSR_SR (b1)
662
663 uint8_t b0 = ldub_code(dc->pc);
664 uint8_t b1 = ldub_code(dc->pc + 1);
665 uint8_t b2 = ldub_code(dc->pc + 2);
666
667 static const uint32_t B4CONST[] = {
668 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
669 };
670
671 static const uint32_t B4CONSTU[] = {
672 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
673 };
674
675 if (OP0 >= 8) {
676 dc->next_pc = dc->pc + 2;
677 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
678 } else {
679 dc->next_pc = dc->pc + 3;
680 }
681
682 switch (OP0) {
683 case 0: /*QRST*/
684 switch (OP1) {
685 case 0: /*RST0*/
686 switch (OP2) {
687 case 0: /*ST0*/
688 if ((RRR_R & 0xc) == 0x8) {
689 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
690 }
691
692 switch (RRR_R) {
693 case 0: /*SNM0*/
694 switch (CALLX_M) {
695 case 0: /*ILL*/
696 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
697 break;
698
699 case 1: /*reserved*/
700 RESERVED();
701 break;
702
703 case 2: /*JR*/
704 switch (CALLX_N) {
705 case 0: /*RET*/
706 case 2: /*JX*/
707 gen_window_check1(dc, CALLX_S);
708 gen_jump(dc, cpu_R[CALLX_S]);
709 break;
710
711 case 1: /*RETWw*/
712 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
713 {
714 TCGv_i32 tmp = tcg_const_i32(dc->pc);
715 gen_advance_ccount(dc);
716 gen_helper_retw(tmp, tmp);
717 gen_jump(dc, tmp);
718 tcg_temp_free(tmp);
719 }
720 break;
721
722 case 3: /*reserved*/
723 RESERVED();
724 break;
725 }
726 break;
727
728 case 3: /*CALLX*/
729 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
730 switch (CALLX_N) {
731 case 0: /*CALLX0*/
732 {
733 TCGv_i32 tmp = tcg_temp_new_i32();
734 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
735 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
736 gen_jump(dc, tmp);
737 tcg_temp_free(tmp);
738 }
739 break;
740
741 case 1: /*CALLX4w*/
742 case 2: /*CALLX8w*/
743 case 3: /*CALLX12w*/
744 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
745 {
746 TCGv_i32 tmp = tcg_temp_new_i32();
747
748 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
749 gen_callw(dc, CALLX_N, tmp);
750 tcg_temp_free(tmp);
751 }
752 break;
753 }
754 break;
755 }
756 break;
757
758 case 1: /*MOVSPw*/
759 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
760 gen_window_check2(dc, RRR_T, RRR_S);
761 {
762 TCGv_i32 pc = tcg_const_i32(dc->pc);
763 gen_advance_ccount(dc);
764 gen_helper_movsp(pc);
765 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
766 tcg_temp_free(pc);
767 }
768 break;
769
770 case 2: /*SYNC*/
771 switch (RRR_T) {
772 case 0: /*ISYNC*/
773 break;
774
775 case 1: /*RSYNC*/
776 break;
777
778 case 2: /*ESYNC*/
779 break;
780
781 case 3: /*DSYNC*/
782 break;
783
784 case 8: /*EXCW*/
785 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
786 break;
787
788 case 12: /*MEMW*/
789 break;
790
791 case 13: /*EXTW*/
792 break;
793
794 case 15: /*NOP*/
795 break;
796
797 default: /*reserved*/
798 RESERVED();
799 break;
800 }
801 break;
802
803 case 3: /*RFEIx*/
804 switch (RRR_T) {
805 case 0: /*RFETx*/
806 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
807 switch (RRR_S) {
808 case 0: /*RFEx*/
809 gen_check_privilege(dc);
810 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
811 gen_helper_check_interrupts(cpu_env);
812 gen_jump(dc, cpu_SR[EPC1]);
813 break;
814
815 case 1: /*RFUEx*/
816 RESERVED();
817 break;
818
819 case 2: /*RFDEx*/
820 gen_check_privilege(dc);
821 gen_jump(dc, cpu_SR[
822 dc->config->ndepc ? DEPC : EPC1]);
823 break;
824
825 case 4: /*RFWOw*/
826 case 5: /*RFWUw*/
827 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
828 gen_check_privilege(dc);
829 {
830 TCGv_i32 tmp = tcg_const_i32(1);
831
832 tcg_gen_andi_i32(
833 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
834 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
835
836 if (RRR_S == 4) {
837 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
838 cpu_SR[WINDOW_START], tmp);
839 } else {
840 tcg_gen_or_i32(cpu_SR[WINDOW_START],
841 cpu_SR[WINDOW_START], tmp);
842 }
843
844 gen_helper_restore_owb();
845 gen_helper_check_interrupts(cpu_env);
846 gen_jump(dc, cpu_SR[EPC1]);
847
848 tcg_temp_free(tmp);
849 }
850 break;
851
852 default: /*reserved*/
853 RESERVED();
854 break;
855 }
856 break;
857
858 case 1: /*RFIx*/
859 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
860 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
861 gen_check_privilege(dc);
862 tcg_gen_mov_i32(cpu_SR[PS],
863 cpu_SR[EPS2 + RRR_S - 2]);
864 gen_helper_check_interrupts(cpu_env);
865 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
866 } else {
867 qemu_log("RFI %d is illegal\n", RRR_S);
868 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
869 }
870 break;
871
872 case 2: /*RFME*/
873 TBD();
874 break;
875
876 default: /*reserved*/
877 RESERVED();
878 break;
879
880 }
881 break;
882
883 case 4: /*BREAKx*/
884 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
885 TBD();
886 break;
887
888 case 5: /*SYSCALLx*/
889 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
890 switch (RRR_S) {
891 case 0: /*SYSCALLx*/
892 gen_exception_cause(dc, SYSCALL_CAUSE);
893 break;
894
895 case 1: /*SIMCALL*/
896 if (semihosting_enabled) {
897 gen_check_privilege(dc);
898 gen_helper_simcall(cpu_env);
899 } else {
900 qemu_log("SIMCALL but semihosting is disabled\n");
901 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
902 }
903 break;
904
905 default:
906 RESERVED();
907 break;
908 }
909 break;
910
911 case 6: /*RSILx*/
912 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
913 gen_check_privilege(dc);
914 gen_window_check1(dc, RRR_T);
915 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
916 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
917 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
918 gen_helper_check_interrupts(cpu_env);
919 gen_jumpi_check_loop_end(dc, 0);
920 break;
921
922 case 7: /*WAITIx*/
923 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
924 gen_check_privilege(dc);
925 gen_waiti(dc, RRR_S);
926 break;
927
928 case 8: /*ANY4p*/
929 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
930 TBD();
931 break;
932
933 case 9: /*ALL4p*/
934 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
935 TBD();
936 break;
937
938 case 10: /*ANY8p*/
939 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
940 TBD();
941 break;
942
943 case 11: /*ALL8p*/
944 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
945 TBD();
946 break;
947
948 default: /*reserved*/
949 RESERVED();
950 break;
951
952 }
953 break;
954
955 case 1: /*AND*/
956 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
957 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
958 break;
959
960 case 2: /*OR*/
961 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
962 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
963 break;
964
965 case 3: /*XOR*/
966 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
967 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
968 break;
969
970 case 4: /*ST1*/
971 switch (RRR_R) {
972 case 0: /*SSR*/
973 gen_window_check1(dc, RRR_S);
974 gen_right_shift_sar(dc, cpu_R[RRR_S]);
975 break;
976
977 case 1: /*SSL*/
978 gen_window_check1(dc, RRR_S);
979 gen_left_shift_sar(dc, cpu_R[RRR_S]);
980 break;
981
982 case 2: /*SSA8L*/
983 gen_window_check1(dc, RRR_S);
984 {
985 TCGv_i32 tmp = tcg_temp_new_i32();
986 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
987 gen_right_shift_sar(dc, tmp);
988 tcg_temp_free(tmp);
989 }
990 break;
991
992 case 3: /*SSA8B*/
993 gen_window_check1(dc, RRR_S);
994 {
995 TCGv_i32 tmp = tcg_temp_new_i32();
996 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
997 gen_left_shift_sar(dc, tmp);
998 tcg_temp_free(tmp);
999 }
1000 break;
1001
1002 case 4: /*SSAI*/
1003 {
1004 TCGv_i32 tmp = tcg_const_i32(
1005 RRR_S | ((RRR_T & 1) << 4));
1006 gen_right_shift_sar(dc, tmp);
1007 tcg_temp_free(tmp);
1008 }
1009 break;
1010
1011 case 6: /*RER*/
1012 TBD();
1013 break;
1014
1015 case 7: /*WER*/
1016 TBD();
1017 break;
1018
1019 case 8: /*ROTWw*/
1020 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1021 gen_check_privilege(dc);
1022 {
1023 TCGv_i32 tmp = tcg_const_i32(
1024 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1025 gen_helper_rotw(tmp);
1026 tcg_temp_free(tmp);
1027 reset_used_window(dc);
1028 }
1029 break;
1030
1031 case 14: /*NSAu*/
1032 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1033 gen_window_check2(dc, RRR_S, RRR_T);
1034 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1035 break;
1036
1037 case 15: /*NSAUu*/
1038 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1039 gen_window_check2(dc, RRR_S, RRR_T);
1040 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1041 break;
1042
1043 default: /*reserved*/
1044 RESERVED();
1045 break;
1046 }
1047 break;
1048
1049 case 5: /*TLB*/
1050 TBD();
1051 break;
1052
1053 case 6: /*RT0*/
1054 gen_window_check2(dc, RRR_R, RRR_T);
1055 switch (RRR_S) {
1056 case 0: /*NEG*/
1057 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1058 break;
1059
1060 case 1: /*ABS*/
1061 {
1062 int label = gen_new_label();
1063 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1064 tcg_gen_brcondi_i32(
1065 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1066 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1067 gen_set_label(label);
1068 }
1069 break;
1070
1071 default: /*reserved*/
1072 RESERVED();
1073 break;
1074 }
1075 break;
1076
1077 case 7: /*reserved*/
1078 RESERVED();
1079 break;
1080
1081 case 8: /*ADD*/
1082 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1083 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1084 break;
1085
1086 case 9: /*ADD**/
1087 case 10:
1088 case 11:
1089 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1090 {
1091 TCGv_i32 tmp = tcg_temp_new_i32();
1092 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1093 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1094 tcg_temp_free(tmp);
1095 }
1096 break;
1097
1098 case 12: /*SUB*/
1099 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1100 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1101 break;
1102
1103 case 13: /*SUB**/
1104 case 14:
1105 case 15:
1106 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1107 {
1108 TCGv_i32 tmp = tcg_temp_new_i32();
1109 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1110 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1111 tcg_temp_free(tmp);
1112 }
1113 break;
1114 }
1115 break;
1116
1117 case 1: /*RST1*/
1118 switch (OP2) {
1119 case 0: /*SLLI*/
1120 case 1:
1121 gen_window_check2(dc, RRR_R, RRR_S);
1122 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1123 32 - (RRR_T | ((OP2 & 1) << 4)));
1124 break;
1125
1126 case 2: /*SRAI*/
1127 case 3:
1128 gen_window_check2(dc, RRR_R, RRR_T);
1129 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1130 RRR_S | ((OP2 & 1) << 4));
1131 break;
1132
1133 case 4: /*SRLI*/
1134 gen_window_check2(dc, RRR_R, RRR_T);
1135 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1136 break;
1137
1138 case 6: /*XSR*/
1139 {
1140 TCGv_i32 tmp = tcg_temp_new_i32();
1141 if (RSR_SR >= 64) {
1142 gen_check_privilege(dc);
1143 }
1144 gen_window_check1(dc, RRR_T);
1145 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1146 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1147 gen_wsr(dc, RSR_SR, tmp);
1148 tcg_temp_free(tmp);
1149 if (!sregnames[RSR_SR]) {
1150 TBD();
1151 }
1152 }
1153 break;
1154
1155 /*
1156 * Note: 64 bit ops are used here solely because SAR values
1157 * have range 0..63
1158 */
1159 #define gen_shift_reg(cmd, reg) do { \
1160 TCGv_i64 tmp = tcg_temp_new_i64(); \
1161 tcg_gen_extu_i32_i64(tmp, reg); \
1162 tcg_gen_##cmd##_i64(v, v, tmp); \
1163 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1164 tcg_temp_free_i64(v); \
1165 tcg_temp_free_i64(tmp); \
1166 } while (0)
1167
1168 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1169
1170 case 8: /*SRC*/
1171 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1172 {
1173 TCGv_i64 v = tcg_temp_new_i64();
1174 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1175 gen_shift(shr);
1176 }
1177 break;
1178
1179 case 9: /*SRL*/
1180 gen_window_check2(dc, RRR_R, RRR_T);
1181 if (dc->sar_5bit) {
1182 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1183 } else {
1184 TCGv_i64 v = tcg_temp_new_i64();
1185 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1186 gen_shift(shr);
1187 }
1188 break;
1189
1190 case 10: /*SLL*/
1191 gen_window_check2(dc, RRR_R, RRR_S);
1192 if (dc->sar_m32_5bit) {
1193 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1194 } else {
1195 TCGv_i64 v = tcg_temp_new_i64();
1196 TCGv_i32 s = tcg_const_i32(32);
1197 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1198 tcg_gen_andi_i32(s, s, 0x3f);
1199 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1200 gen_shift_reg(shl, s);
1201 tcg_temp_free(s);
1202 }
1203 break;
1204
1205 case 11: /*SRA*/
1206 gen_window_check2(dc, RRR_R, RRR_T);
1207 if (dc->sar_5bit) {
1208 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1209 } else {
1210 TCGv_i64 v = tcg_temp_new_i64();
1211 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1212 gen_shift(sar);
1213 }
1214 break;
1215 #undef gen_shift
1216 #undef gen_shift_reg
1217
1218 case 12: /*MUL16U*/
1219 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1220 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1221 {
1222 TCGv_i32 v1 = tcg_temp_new_i32();
1223 TCGv_i32 v2 = tcg_temp_new_i32();
1224 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1225 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1226 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1227 tcg_temp_free(v2);
1228 tcg_temp_free(v1);
1229 }
1230 break;
1231
1232 case 13: /*MUL16S*/
1233 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1234 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1235 {
1236 TCGv_i32 v1 = tcg_temp_new_i32();
1237 TCGv_i32 v2 = tcg_temp_new_i32();
1238 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1239 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1240 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1241 tcg_temp_free(v2);
1242 tcg_temp_free(v1);
1243 }
1244 break;
1245
1246 default: /*reserved*/
1247 RESERVED();
1248 break;
1249 }
1250 break;
1251
1252 case 2: /*RST2*/
1253 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1254
1255 if (OP2 >= 12) {
1256 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1257 int label = gen_new_label();
1258 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1259 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1260 gen_set_label(label);
1261 }
1262
1263 switch (OP2) {
1264 case 8: /*MULLi*/
1265 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1266 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1267 break;
1268
1269 case 10: /*MULUHi*/
1270 case 11: /*MULSHi*/
1271 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1272 {
1273 TCGv_i64 r = tcg_temp_new_i64();
1274 TCGv_i64 s = tcg_temp_new_i64();
1275 TCGv_i64 t = tcg_temp_new_i64();
1276
1277 if (OP2 == 10) {
1278 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1279 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1280 } else {
1281 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1282 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1283 }
1284 tcg_gen_mul_i64(r, s, t);
1285 tcg_gen_shri_i64(r, r, 32);
1286 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1287
1288 tcg_temp_free_i64(r);
1289 tcg_temp_free_i64(s);
1290 tcg_temp_free_i64(t);
1291 }
1292 break;
1293
1294 case 12: /*QUOUi*/
1295 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1296 break;
1297
1298 case 13: /*QUOSi*/
1299 case 15: /*REMSi*/
1300 {
1301 int label1 = gen_new_label();
1302 int label2 = gen_new_label();
1303
1304 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1305 label1);
1306 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1307 label1);
1308 tcg_gen_movi_i32(cpu_R[RRR_R],
1309 OP2 == 13 ? 0x80000000 : 0);
1310 tcg_gen_br(label2);
1311 gen_set_label(label1);
1312 if (OP2 == 13) {
1313 tcg_gen_div_i32(cpu_R[RRR_R],
1314 cpu_R[RRR_S], cpu_R[RRR_T]);
1315 } else {
1316 tcg_gen_rem_i32(cpu_R[RRR_R],
1317 cpu_R[RRR_S], cpu_R[RRR_T]);
1318 }
1319 gen_set_label(label2);
1320 }
1321 break;
1322
1323 case 14: /*REMUi*/
1324 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1325 break;
1326
1327 default: /*reserved*/
1328 RESERVED();
1329 break;
1330 }
1331 break;
1332
1333 case 3: /*RST3*/
1334 switch (OP2) {
1335 case 0: /*RSR*/
1336 if (RSR_SR >= 64) {
1337 gen_check_privilege(dc);
1338 }
1339 gen_window_check1(dc, RRR_T);
1340 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1341 if (!sregnames[RSR_SR]) {
1342 TBD();
1343 }
1344 break;
1345
1346 case 1: /*WSR*/
1347 if (RSR_SR >= 64) {
1348 gen_check_privilege(dc);
1349 }
1350 gen_window_check1(dc, RRR_T);
1351 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1352 if (!sregnames[RSR_SR]) {
1353 TBD();
1354 }
1355 break;
1356
1357 case 2: /*SEXTu*/
1358 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1359 gen_window_check2(dc, RRR_R, RRR_S);
1360 {
1361 int shift = 24 - RRR_T;
1362
1363 if (shift == 24) {
1364 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1365 } else if (shift == 16) {
1366 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1367 } else {
1368 TCGv_i32 tmp = tcg_temp_new_i32();
1369 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1370 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1371 tcg_temp_free(tmp);
1372 }
1373 }
1374 break;
1375
1376 case 3: /*CLAMPSu*/
1377 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1378 gen_window_check2(dc, RRR_R, RRR_S);
1379 {
1380 TCGv_i32 tmp1 = tcg_temp_new_i32();
1381 TCGv_i32 tmp2 = tcg_temp_new_i32();
1382 int label = gen_new_label();
1383
1384 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1385 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1386 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1387 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1388 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1389
1390 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1391 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1392 0xffffffff >> (25 - RRR_T));
1393
1394 gen_set_label(label);
1395
1396 tcg_temp_free(tmp1);
1397 tcg_temp_free(tmp2);
1398 }
1399 break;
1400
1401 case 4: /*MINu*/
1402 case 5: /*MAXu*/
1403 case 6: /*MINUu*/
1404 case 7: /*MAXUu*/
1405 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1406 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1407 {
1408 static const TCGCond cond[] = {
1409 TCG_COND_LE,
1410 TCG_COND_GE,
1411 TCG_COND_LEU,
1412 TCG_COND_GEU
1413 };
1414 int label = gen_new_label();
1415
1416 if (RRR_R != RRR_T) {
1417 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1418 tcg_gen_brcond_i32(cond[OP2 - 4],
1419 cpu_R[RRR_S], cpu_R[RRR_T], label);
1420 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1421 } else {
1422 tcg_gen_brcond_i32(cond[OP2 - 4],
1423 cpu_R[RRR_T], cpu_R[RRR_S], label);
1424 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1425 }
1426 gen_set_label(label);
1427 }
1428 break;
1429
1430 case 8: /*MOVEQZ*/
1431 case 9: /*MOVNEZ*/
1432 case 10: /*MOVLTZ*/
1433 case 11: /*MOVGEZ*/
1434 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1435 {
1436 static const TCGCond cond[] = {
1437 TCG_COND_NE,
1438 TCG_COND_EQ,
1439 TCG_COND_GE,
1440 TCG_COND_LT
1441 };
1442 int label = gen_new_label();
1443 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1444 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1445 gen_set_label(label);
1446 }
1447 break;
1448
1449 case 12: /*MOVFp*/
1450 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1451 TBD();
1452 break;
1453
1454 case 13: /*MOVTp*/
1455 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1456 TBD();
1457 break;
1458
1459 case 14: /*RUR*/
1460 gen_window_check1(dc, RRR_R);
1461 {
1462 int st = (RRR_S << 4) + RRR_T;
1463 if (uregnames[st]) {
1464 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1465 } else {
1466 qemu_log("RUR %d not implemented, ", st);
1467 TBD();
1468 }
1469 }
1470 break;
1471
1472 case 15: /*WUR*/
1473 gen_window_check1(dc, RRR_T);
1474 {
1475 if (uregnames[RSR_SR]) {
1476 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1477 } else {
1478 qemu_log("WUR %d not implemented, ", RSR_SR);
1479 TBD();
1480 }
1481 }
1482 break;
1483
1484 }
1485 break;
1486
1487 case 4: /*EXTUI*/
1488 case 5:
1489 gen_window_check2(dc, RRR_R, RRR_T);
1490 {
1491 int shiftimm = RRR_S | (OP1 << 4);
1492 int maskimm = (1 << (OP2 + 1)) - 1;
1493
1494 TCGv_i32 tmp = tcg_temp_new_i32();
1495 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1496 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1497 tcg_temp_free(tmp);
1498 }
1499 break;
1500
1501 case 6: /*CUST0*/
1502 RESERVED();
1503 break;
1504
1505 case 7: /*CUST1*/
1506 RESERVED();
1507 break;
1508
1509 case 8: /*LSCXp*/
1510 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
1511 TBD();
1512 break;
1513
1514 case 9: /*LSC4*/
1515 gen_window_check2(dc, RRR_S, RRR_T);
1516 switch (OP2) {
1517 case 0: /*L32E*/
1518 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1519 gen_check_privilege(dc);
1520 {
1521 TCGv_i32 addr = tcg_temp_new_i32();
1522 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1523 (0xffffffc0 | (RRR_R << 2)));
1524 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1525 tcg_temp_free(addr);
1526 }
1527 break;
1528
1529 case 4: /*S32E*/
1530 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1531 gen_check_privilege(dc);
1532 {
1533 TCGv_i32 addr = tcg_temp_new_i32();
1534 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1535 (0xffffffc0 | (RRR_R << 2)));
1536 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1537 tcg_temp_free(addr);
1538 }
1539 break;
1540
1541 default:
1542 RESERVED();
1543 break;
1544 }
1545 break;
1546
1547 case 10: /*FP0*/
1548 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1549 TBD();
1550 break;
1551
1552 case 11: /*FP1*/
1553 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1554 TBD();
1555 break;
1556
1557 default: /*reserved*/
1558 RESERVED();
1559 break;
1560 }
1561 break;
1562
1563 case 1: /*L32R*/
1564 gen_window_check1(dc, RRR_T);
1565 {
1566 TCGv_i32 tmp = tcg_const_i32(
1567 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1568 0 : ((dc->pc + 3) & ~3)) +
1569 (0xfffc0000 | (RI16_IMM16 << 2)));
1570
1571 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1572 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1573 }
1574 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
1575 tcg_temp_free(tmp);
1576 }
1577 break;
1578
1579 case 2: /*LSAI*/
1580 #define gen_load_store(type, shift) do { \
1581 TCGv_i32 addr = tcg_temp_new_i32(); \
1582 gen_window_check2(dc, RRI8_S, RRI8_T); \
1583 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1584 if (shift) { \
1585 gen_load_store_alignment(dc, shift, addr, false); \
1586 } \
1587 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1588 tcg_temp_free(addr); \
1589 } while (0)
1590
1591 switch (RRI8_R) {
1592 case 0: /*L8UI*/
1593 gen_load_store(ld8u, 0);
1594 break;
1595
1596 case 1: /*L16UI*/
1597 gen_load_store(ld16u, 1);
1598 break;
1599
1600 case 2: /*L32I*/
1601 gen_load_store(ld32u, 2);
1602 break;
1603
1604 case 4: /*S8I*/
1605 gen_load_store(st8, 0);
1606 break;
1607
1608 case 5: /*S16I*/
1609 gen_load_store(st16, 1);
1610 break;
1611
1612 case 6: /*S32I*/
1613 gen_load_store(st32, 2);
1614 break;
1615
1616 case 7: /*CACHEc*/
1617 if (RRI8_T < 8) {
1618 HAS_OPTION(XTENSA_OPTION_DCACHE);
1619 }
1620
1621 switch (RRI8_T) {
1622 case 0: /*DPFRc*/
1623 break;
1624
1625 case 1: /*DPFWc*/
1626 break;
1627
1628 case 2: /*DPFROc*/
1629 break;
1630
1631 case 3: /*DPFWOc*/
1632 break;
1633
1634 case 4: /*DHWBc*/
1635 break;
1636
1637 case 5: /*DHWBIc*/
1638 break;
1639
1640 case 6: /*DHIc*/
1641 break;
1642
1643 case 7: /*DIIc*/
1644 break;
1645
1646 case 8: /*DCEc*/
1647 switch (OP1) {
1648 case 0: /*DPFLl*/
1649 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1650 break;
1651
1652 case 2: /*DHUl*/
1653 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1654 break;
1655
1656 case 3: /*DIUl*/
1657 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1658 break;
1659
1660 case 4: /*DIWBc*/
1661 HAS_OPTION(XTENSA_OPTION_DCACHE);
1662 break;
1663
1664 case 5: /*DIWBIc*/
1665 HAS_OPTION(XTENSA_OPTION_DCACHE);
1666 break;
1667
1668 default: /*reserved*/
1669 RESERVED();
1670 break;
1671
1672 }
1673 break;
1674
1675 case 12: /*IPFc*/
1676 HAS_OPTION(XTENSA_OPTION_ICACHE);
1677 break;
1678
1679 case 13: /*ICEc*/
1680 switch (OP1) {
1681 case 0: /*IPFLl*/
1682 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1683 break;
1684
1685 case 2: /*IHUl*/
1686 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1687 break;
1688
1689 case 3: /*IIUl*/
1690 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1691 break;
1692
1693 default: /*reserved*/
1694 RESERVED();
1695 break;
1696 }
1697 break;
1698
1699 case 14: /*IHIc*/
1700 HAS_OPTION(XTENSA_OPTION_ICACHE);
1701 break;
1702
1703 case 15: /*IIIc*/
1704 HAS_OPTION(XTENSA_OPTION_ICACHE);
1705 break;
1706
1707 default: /*reserved*/
1708 RESERVED();
1709 break;
1710 }
1711 break;
1712
1713 case 9: /*L16SI*/
1714 gen_load_store(ld16s, 1);
1715 break;
1716 #undef gen_load_store
1717
1718 case 10: /*MOVI*/
1719 gen_window_check1(dc, RRI8_T);
1720 tcg_gen_movi_i32(cpu_R[RRI8_T],
1721 RRI8_IMM8 | (RRI8_S << 8) |
1722 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1723 break;
1724
1725 #define gen_load_store_no_hw_align(type) do { \
1726 TCGv_i32 addr = tcg_temp_local_new_i32(); \
1727 gen_window_check2(dc, RRI8_S, RRI8_T); \
1728 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1729 gen_load_store_alignment(dc, 2, addr, true); \
1730 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1731 tcg_temp_free(addr); \
1732 } while (0)
1733
1734 case 11: /*L32AIy*/
1735 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1736 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
1737 break;
1738
1739 case 12: /*ADDI*/
1740 gen_window_check2(dc, RRI8_S, RRI8_T);
1741 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1742 break;
1743
1744 case 13: /*ADDMI*/
1745 gen_window_check2(dc, RRI8_S, RRI8_T);
1746 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1747 break;
1748
1749 case 14: /*S32C1Iy*/
1750 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1751 gen_window_check2(dc, RRI8_S, RRI8_T);
1752 {
1753 int label = gen_new_label();
1754 TCGv_i32 tmp = tcg_temp_local_new_i32();
1755 TCGv_i32 addr = tcg_temp_local_new_i32();
1756
1757 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1758 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
1759 gen_load_store_alignment(dc, 2, addr, true);
1760 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
1761 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1762 cpu_SR[SCOMPARE1], label);
1763
1764 tcg_gen_qemu_st32(tmp, addr, dc->cring);
1765
1766 gen_set_label(label);
1767 tcg_temp_free(addr);
1768 tcg_temp_free(tmp);
1769 }
1770 break;
1771
1772 case 15: /*S32RIy*/
1773 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1774 gen_load_store_no_hw_align(st32); /*TODO release?*/
1775 break;
1776 #undef gen_load_store_no_hw_align
1777
1778 default: /*reserved*/
1779 RESERVED();
1780 break;
1781 }
1782 break;
1783
1784 case 3: /*LSCIp*/
1785 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
1786 TBD();
1787 break;
1788
1789 case 4: /*MAC16d*/
1790 HAS_OPTION(XTENSA_OPTION_MAC16);
1791 TBD();
1792 break;
1793
1794 case 5: /*CALLN*/
1795 switch (CALL_N) {
1796 case 0: /*CALL0*/
1797 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1798 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1799 break;
1800
1801 case 1: /*CALL4w*/
1802 case 2: /*CALL8w*/
1803 case 3: /*CALL12w*/
1804 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1805 gen_window_check1(dc, CALL_N << 2);
1806 gen_callwi(dc, CALL_N,
1807 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1808 break;
1809 }
1810 break;
1811
1812 case 6: /*SI*/
1813 switch (CALL_N) {
1814 case 0: /*J*/
1815 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
1816 break;
1817
1818 case 1: /*BZ*/
1819 gen_window_check1(dc, BRI12_S);
1820 {
1821 static const TCGCond cond[] = {
1822 TCG_COND_EQ, /*BEQZ*/
1823 TCG_COND_NE, /*BNEZ*/
1824 TCG_COND_LT, /*BLTZ*/
1825 TCG_COND_GE, /*BGEZ*/
1826 };
1827
1828 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
1829 4 + BRI12_IMM12_SE);
1830 }
1831 break;
1832
1833 case 2: /*BI0*/
1834 gen_window_check1(dc, BRI8_S);
1835 {
1836 static const TCGCond cond[] = {
1837 TCG_COND_EQ, /*BEQI*/
1838 TCG_COND_NE, /*BNEI*/
1839 TCG_COND_LT, /*BLTI*/
1840 TCG_COND_GE, /*BGEI*/
1841 };
1842
1843 gen_brcondi(dc, cond[BRI8_M & 3],
1844 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
1845 }
1846 break;
1847
1848 case 3: /*BI1*/
1849 switch (BRI8_M) {
1850 case 0: /*ENTRYw*/
1851 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1852 {
1853 TCGv_i32 pc = tcg_const_i32(dc->pc);
1854 TCGv_i32 s = tcg_const_i32(BRI12_S);
1855 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
1856 gen_advance_ccount(dc);
1857 gen_helper_entry(pc, s, imm);
1858 tcg_temp_free(imm);
1859 tcg_temp_free(s);
1860 tcg_temp_free(pc);
1861 reset_used_window(dc);
1862 }
1863 break;
1864
1865 case 1: /*B1*/
1866 switch (BRI8_R) {
1867 case 0: /*BFp*/
1868 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1869 TBD();
1870 break;
1871
1872 case 1: /*BTp*/
1873 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1874 TBD();
1875 break;
1876
1877 case 8: /*LOOP*/
1878 case 9: /*LOOPNEZ*/
1879 case 10: /*LOOPGTZ*/
1880 HAS_OPTION(XTENSA_OPTION_LOOP);
1881 gen_window_check1(dc, RRI8_S);
1882 {
1883 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
1884 TCGv_i32 tmp = tcg_const_i32(lend);
1885
1886 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
1887 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
1888 gen_wsr_lend(dc, LEND, tmp);
1889 tcg_temp_free(tmp);
1890
1891 if (BRI8_R > 8) {
1892 int label = gen_new_label();
1893 tcg_gen_brcondi_i32(
1894 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
1895 cpu_R[RRI8_S], 0, label);
1896 gen_jumpi(dc, lend, 1);
1897 gen_set_label(label);
1898 }
1899
1900 gen_jumpi(dc, dc->next_pc, 0);
1901 }
1902 break;
1903
1904 default: /*reserved*/
1905 RESERVED();
1906 break;
1907
1908 }
1909 break;
1910
1911 case 2: /*BLTUI*/
1912 case 3: /*BGEUI*/
1913 gen_window_check1(dc, BRI8_S);
1914 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
1915 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
1916 break;
1917 }
1918 break;
1919
1920 }
1921 break;
1922
1923 case 7: /*B*/
1924 {
1925 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
1926
1927 switch (RRI8_R & 7) {
1928 case 0: /*BNONE*/ /*BANY*/
1929 gen_window_check2(dc, RRI8_S, RRI8_T);
1930 {
1931 TCGv_i32 tmp = tcg_temp_new_i32();
1932 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1933 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1934 tcg_temp_free(tmp);
1935 }
1936 break;
1937
1938 case 1: /*BEQ*/ /*BNE*/
1939 case 2: /*BLT*/ /*BGE*/
1940 case 3: /*BLTU*/ /*BGEU*/
1941 gen_window_check2(dc, RRI8_S, RRI8_T);
1942 {
1943 static const TCGCond cond[] = {
1944 [1] = TCG_COND_EQ,
1945 [2] = TCG_COND_LT,
1946 [3] = TCG_COND_LTU,
1947 [9] = TCG_COND_NE,
1948 [10] = TCG_COND_GE,
1949 [11] = TCG_COND_GEU,
1950 };
1951 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
1952 4 + RRI8_IMM8_SE);
1953 }
1954 break;
1955
1956 case 4: /*BALL*/ /*BNALL*/
1957 gen_window_check2(dc, RRI8_S, RRI8_T);
1958 {
1959 TCGv_i32 tmp = tcg_temp_new_i32();
1960 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1961 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
1962 4 + RRI8_IMM8_SE);
1963 tcg_temp_free(tmp);
1964 }
1965 break;
1966
1967 case 5: /*BBC*/ /*BBS*/
1968 gen_window_check2(dc, RRI8_S, RRI8_T);
1969 {
1970 TCGv_i32 bit = tcg_const_i32(1);
1971 TCGv_i32 tmp = tcg_temp_new_i32();
1972 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
1973 tcg_gen_shl_i32(bit, bit, tmp);
1974 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
1975 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1976 tcg_temp_free(tmp);
1977 tcg_temp_free(bit);
1978 }
1979 break;
1980
1981 case 6: /*BBCI*/ /*BBSI*/
1982 case 7:
1983 gen_window_check1(dc, RRI8_S);
1984 {
1985 TCGv_i32 tmp = tcg_temp_new_i32();
1986 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
1987 1 << (((RRI8_R & 1) << 4) | RRI8_T));
1988 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1989 tcg_temp_free(tmp);
1990 }
1991 break;
1992
1993 }
1994 }
1995 break;
1996
1997 #define gen_narrow_load_store(type) do { \
1998 TCGv_i32 addr = tcg_temp_new_i32(); \
1999 gen_window_check2(dc, RRRN_S, RRRN_T); \
2000 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2001 gen_load_store_alignment(dc, 2, addr, false); \
2002 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2003 tcg_temp_free(addr); \
2004 } while (0)
2005
2006 case 8: /*L32I.Nn*/
2007 gen_narrow_load_store(ld32u);
2008 break;
2009
2010 case 9: /*S32I.Nn*/
2011 gen_narrow_load_store(st32);
2012 break;
2013 #undef gen_narrow_load_store
2014
2015 case 10: /*ADD.Nn*/
2016 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2017 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2018 break;
2019
2020 case 11: /*ADDI.Nn*/
2021 gen_window_check2(dc, RRRN_R, RRRN_S);
2022 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2023 break;
2024
2025 case 12: /*ST2n*/
2026 gen_window_check1(dc, RRRN_S);
2027 if (RRRN_T < 8) { /*MOVI.Nn*/
2028 tcg_gen_movi_i32(cpu_R[RRRN_S],
2029 RRRN_R | (RRRN_T << 4) |
2030 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2031 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2032 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2033
2034 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2035 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2036 }
2037 break;
2038
2039 case 13: /*ST3n*/
2040 switch (RRRN_R) {
2041 case 0: /*MOV.Nn*/
2042 gen_window_check2(dc, RRRN_S, RRRN_T);
2043 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2044 break;
2045
2046 case 15: /*S3*/
2047 switch (RRRN_T) {
2048 case 0: /*RET.Nn*/
2049 gen_jump(dc, cpu_R[0]);
2050 break;
2051
2052 case 1: /*RETW.Nn*/
2053 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2054 {
2055 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2056 gen_advance_ccount(dc);
2057 gen_helper_retw(tmp, tmp);
2058 gen_jump(dc, tmp);
2059 tcg_temp_free(tmp);
2060 }
2061 break;
2062
2063 case 2: /*BREAK.Nn*/
2064 TBD();
2065 break;
2066
2067 case 3: /*NOP.Nn*/
2068 break;
2069
2070 case 6: /*ILL.Nn*/
2071 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2072 break;
2073
2074 default: /*reserved*/
2075 RESERVED();
2076 break;
2077 }
2078 break;
2079
2080 default: /*reserved*/
2081 RESERVED();
2082 break;
2083 }
2084 break;
2085
2086 default: /*reserved*/
2087 RESERVED();
2088 break;
2089 }
2090
2091 gen_check_loop_end(dc, 0);
2092 dc->pc = dc->next_pc;
2093
2094 return;
2095
2096 invalid_opcode:
2097 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2098 dc->pc = dc->next_pc;
2099 #undef HAS_OPTION
2100 }
2101
2102 static void check_breakpoint(CPUState *env, DisasContext *dc)
2103 {
2104 CPUBreakpoint *bp;
2105
2106 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2107 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2108 if (bp->pc == dc->pc) {
2109 tcg_gen_movi_i32(cpu_pc, dc->pc);
2110 gen_exception(dc, EXCP_DEBUG);
2111 dc->is_jmp = DISAS_UPDATE;
2112 }
2113 }
2114 }
2115 }
2116
2117 static void gen_intermediate_code_internal(
2118 CPUState *env, TranslationBlock *tb, int search_pc)
2119 {
2120 DisasContext dc;
2121 int insn_count = 0;
2122 int j, lj = -1;
2123 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2124 int max_insns = tb->cflags & CF_COUNT_MASK;
2125 uint32_t pc_start = tb->pc;
2126 uint32_t next_page_start =
2127 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2128
2129 if (max_insns == 0) {
2130 max_insns = CF_COUNT_MASK;
2131 }
2132
2133 dc.config = env->config;
2134 dc.singlestep_enabled = env->singlestep_enabled;
2135 dc.tb = tb;
2136 dc.pc = pc_start;
2137 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2138 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
2139 dc.lbeg = env->sregs[LBEG];
2140 dc.lend = env->sregs[LEND];
2141 dc.is_jmp = DISAS_NEXT;
2142 dc.ccount_delta = 0;
2143
2144 init_litbase(&dc);
2145 init_sar_tracker(&dc);
2146 reset_used_window(&dc);
2147
2148 gen_icount_start();
2149
2150 if (env->singlestep_enabled && env->exception_taken) {
2151 env->exception_taken = 0;
2152 tcg_gen_movi_i32(cpu_pc, dc.pc);
2153 gen_exception(&dc, EXCP_DEBUG);
2154 }
2155
2156 do {
2157 check_breakpoint(env, &dc);
2158
2159 if (search_pc) {
2160 j = gen_opc_ptr - gen_opc_buf;
2161 if (lj < j) {
2162 lj++;
2163 while (lj < j) {
2164 gen_opc_instr_start[lj++] = 0;
2165 }
2166 }
2167 gen_opc_pc[lj] = dc.pc;
2168 gen_opc_instr_start[lj] = 1;
2169 gen_opc_icount[lj] = insn_count;
2170 }
2171
2172 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2173 tcg_gen_debug_insn_start(dc.pc);
2174 }
2175
2176 ++dc.ccount_delta;
2177
2178 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2179 gen_io_start();
2180 }
2181
2182 disas_xtensa_insn(&dc);
2183 ++insn_count;
2184 if (env->singlestep_enabled) {
2185 tcg_gen_movi_i32(cpu_pc, dc.pc);
2186 gen_exception(&dc, EXCP_DEBUG);
2187 break;
2188 }
2189 } while (dc.is_jmp == DISAS_NEXT &&
2190 insn_count < max_insns &&
2191 dc.pc < next_page_start &&
2192 gen_opc_ptr < gen_opc_end);
2193
2194 reset_litbase(&dc);
2195 reset_sar_tracker(&dc);
2196
2197 if (tb->cflags & CF_LAST_IO) {
2198 gen_io_end();
2199 }
2200
2201 if (dc.is_jmp == DISAS_NEXT) {
2202 gen_jumpi(&dc, dc.pc, 0);
2203 }
2204 gen_icount_end(tb, insn_count);
2205 *gen_opc_ptr = INDEX_op_end;
2206
2207 if (!search_pc) {
2208 tb->size = dc.pc - pc_start;
2209 tb->icount = insn_count;
2210 }
2211 }
2212
2213 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2214 {
2215 gen_intermediate_code_internal(env, tb, 0);
2216 }
2217
2218 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2219 {
2220 gen_intermediate_code_internal(env, tb, 1);
2221 }
2222
2223 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
2224 int flags)
2225 {
2226 int i, j;
2227
2228 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2229
2230 for (i = j = 0; i < 256; ++i) {
2231 if (sregnames[i]) {
2232 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2233 (j++ % 4) == 3 ? '\n' : ' ');
2234 }
2235 }
2236
2237 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2238
2239 for (i = j = 0; i < 256; ++i) {
2240 if (uregnames[i]) {
2241 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2242 (j++ % 4) == 3 ? '\n' : ' ');
2243 }
2244 }
2245
2246 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2247
2248 for (i = 0; i < 16; ++i) {
2249 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2250 (i % 4) == 3 ? '\n' : ' ');
2251 }
2252
2253 cpu_fprintf(f, "\n");
2254
2255 for (i = 0; i < env->config->nareg; ++i) {
2256 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2257 (i % 4) == 3 ? '\n' : ' ');
2258 }
2259 }
2260
2261 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
2262 {
2263 env->pc = gen_opc_pc[pc_pos];
2264 }
Qemu copy for testing