3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
72 static TCGv_ptr cpu_env
;
73 static TCGv_i32 cpu_pc
;
74 static TCGv_i32 cpu_R
[16];
75 static TCGv_i32 cpu_FR
[16];
76 static TCGv_i32 cpu_SR
[256];
77 static TCGv_i32 cpu_UR
[256];
79 #include "gen-icount.h"
81 static const char * const sregnames
[256] = {
87 [LITBASE
] = "LITBASE",
88 [SCOMPARE1
] = "SCOMPARE1",
95 [WINDOW_BASE
] = "WINDOW_BASE",
96 [WINDOW_START
] = "WINDOW_START",
97 [PTEVADDR
] = "PTEVADDR",
99 [ITLBCFG
] = "ITLBCFG",
100 [DTLBCFG
] = "DTLBCFG",
101 [IBREAKENABLE
] = "IBREAKENABLE",
102 [ATOMCTL
] = "ATOMCTL",
103 [IBREAKA
] = "IBREAKA0",
104 [IBREAKA
+ 1] = "IBREAKA1",
105 [DBREAKA
] = "DBREAKA0",
106 [DBREAKA
+ 1] = "DBREAKA1",
107 [DBREAKC
] = "DBREAKC0",
108 [DBREAKC
+ 1] = "DBREAKC1",
123 [EXCSAVE1
] = "EXCSAVE1",
124 [EXCSAVE1
+ 1] = "EXCSAVE2",
125 [EXCSAVE1
+ 2] = "EXCSAVE3",
126 [EXCSAVE1
+ 3] = "EXCSAVE4",
127 [EXCSAVE1
+ 4] = "EXCSAVE5",
128 [EXCSAVE1
+ 5] = "EXCSAVE6",
129 [EXCSAVE1
+ 6] = "EXCSAVE7",
130 [CPENABLE
] = "CPENABLE",
132 [INTCLEAR
] = "INTCLEAR",
133 [INTENABLE
] = "INTENABLE",
135 [VECBASE
] = "VECBASE",
136 [EXCCAUSE
] = "EXCCAUSE",
137 [DEBUGCAUSE
] = "DEBUGCAUSE",
141 [ICOUNTLEVEL
] = "ICOUNTLEVEL",
142 [EXCVADDR
] = "EXCVADDR",
143 [CCOMPARE
] = "CCOMPARE0",
144 [CCOMPARE
+ 1] = "CCOMPARE1",
145 [CCOMPARE
+ 2] = "CCOMPARE2",
148 static const char * const uregnames
[256] = {
149 [THREADPTR
] = "THREADPTR",
154 void xtensa_translate_init(void)
156 static const char * const regnames
[] = {
157 "ar0", "ar1", "ar2", "ar3",
158 "ar4", "ar5", "ar6", "ar7",
159 "ar8", "ar9", "ar10", "ar11",
160 "ar12", "ar13", "ar14", "ar15",
162 static const char * const fregnames
[] = {
163 "f0", "f1", "f2", "f3",
164 "f4", "f5", "f6", "f7",
165 "f8", "f9", "f10", "f11",
166 "f12", "f13", "f14", "f15",
170 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
171 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
172 offsetof(CPUXtensaState
, pc
), "pc");
174 for (i
= 0; i
< 16; i
++) {
175 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
176 offsetof(CPUXtensaState
, regs
[i
]),
180 for (i
= 0; i
< 16; i
++) {
181 cpu_FR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
182 offsetof(CPUXtensaState
, fregs
[i
]),
186 for (i
= 0; i
< 256; ++i
) {
188 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
189 offsetof(CPUXtensaState
, sregs
[i
]),
194 for (i
= 0; i
< 256; ++i
) {
196 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
197 offsetof(CPUXtensaState
, uregs
[i
]),
205 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
207 return xtensa_option_bits_enabled(dc
->config
, opt
);
210 static inline bool option_enabled(DisasContext
*dc
, int opt
)
212 return xtensa_option_enabled(dc
->config
, opt
);
215 static void init_litbase(DisasContext
*dc
)
217 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
218 dc
->litbase
= tcg_temp_local_new_i32();
219 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
223 static void reset_litbase(DisasContext
*dc
)
225 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
226 tcg_temp_free(dc
->litbase
);
230 static void init_sar_tracker(DisasContext
*dc
)
232 dc
->sar_5bit
= false;
233 dc
->sar_m32_5bit
= false;
234 dc
->sar_m32_allocated
= false;
237 static void reset_sar_tracker(DisasContext
*dc
)
239 if (dc
->sar_m32_allocated
) {
240 tcg_temp_free(dc
->sar_m32
);
244 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
246 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
247 if (dc
->sar_m32_5bit
) {
248 tcg_gen_discard_i32(dc
->sar_m32
);
251 dc
->sar_m32_5bit
= false;
254 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
256 TCGv_i32 tmp
= tcg_const_i32(32);
257 if (!dc
->sar_m32_allocated
) {
258 dc
->sar_m32
= tcg_temp_local_new_i32();
259 dc
->sar_m32_allocated
= true;
261 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
262 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
263 dc
->sar_5bit
= false;
264 dc
->sar_m32_5bit
= true;
268 static void gen_advance_ccount(DisasContext
*dc
)
270 if (dc
->ccount_delta
> 0) {
271 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
272 dc
->ccount_delta
= 0;
273 gen_helper_advance_ccount(cpu_env
, tmp
);
278 static void reset_used_window(DisasContext
*dc
)
283 static void gen_exception(DisasContext
*dc
, int excp
)
285 TCGv_i32 tmp
= tcg_const_i32(excp
);
286 gen_advance_ccount(dc
);
287 gen_helper_exception(cpu_env
, tmp
);
291 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
293 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
294 TCGv_i32 tcause
= tcg_const_i32(cause
);
295 gen_advance_ccount(dc
);
296 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
298 tcg_temp_free(tcause
);
299 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
300 cause
== SYSCALL_CAUSE
) {
301 dc
->is_jmp
= DISAS_UPDATE
;
305 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
308 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
309 TCGv_i32 tcause
= tcg_const_i32(cause
);
310 gen_advance_ccount(dc
);
311 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
313 tcg_temp_free(tcause
);
316 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
318 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
319 TCGv_i32 tcause
= tcg_const_i32(cause
);
320 gen_advance_ccount(dc
);
321 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
323 tcg_temp_free(tcause
);
324 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
325 dc
->is_jmp
= DISAS_UPDATE
;
329 static void gen_check_privilege(DisasContext
*dc
)
332 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
333 dc
->is_jmp
= DISAS_UPDATE
;
337 static void gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
339 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
340 !(dc
->cpenable
& (1 << cp
))) {
341 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
342 dc
->is_jmp
= DISAS_UPDATE
;
346 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
348 tcg_gen_mov_i32(cpu_pc
, dest
);
349 gen_advance_ccount(dc
);
351 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
353 if (dc
->singlestep_enabled
) {
354 gen_exception(dc
, EXCP_DEBUG
);
357 tcg_gen_goto_tb(slot
);
358 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
363 dc
->is_jmp
= DISAS_UPDATE
;
366 static void gen_jump(DisasContext
*dc
, TCGv dest
)
368 gen_jump_slot(dc
, dest
, -1);
371 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
373 TCGv_i32 tmp
= tcg_const_i32(dest
);
374 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
377 gen_jump_slot(dc
, tmp
, slot
);
381 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
384 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
386 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
387 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
388 tcg_temp_free(tcallinc
);
389 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
390 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
391 gen_jump_slot(dc
, dest
, slot
);
394 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
396 gen_callw_slot(dc
, callinc
, dest
, -1);
399 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
401 TCGv_i32 tmp
= tcg_const_i32(dest
);
402 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
405 gen_callw_slot(dc
, callinc
, tmp
, slot
);
409 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
411 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
412 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
413 dc
->next_pc
== dc
->lend
) {
414 int label
= gen_new_label();
416 gen_advance_ccount(dc
);
417 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
418 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
419 gen_jumpi(dc
, dc
->lbeg
, slot
);
420 gen_set_label(label
);
421 gen_jumpi(dc
, dc
->next_pc
, -1);
427 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
429 if (!gen_check_loop_end(dc
, slot
)) {
430 gen_jumpi(dc
, dc
->next_pc
, slot
);
434 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
435 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
437 int label
= gen_new_label();
439 gen_advance_ccount(dc
);
440 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
441 gen_jumpi_check_loop_end(dc
, 0);
442 gen_set_label(label
);
443 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
446 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
447 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
449 TCGv_i32 tmp
= tcg_const_i32(t1
);
450 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
454 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
456 gen_advance_ccount(dc
);
457 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
460 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
462 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
463 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
464 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
467 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
469 static void (* const rsr_handler
[256])(DisasContext
*dc
,
470 TCGv_i32 d
, uint32_t sr
) = {
471 [CCOUNT
] = gen_rsr_ccount
,
472 [PTEVADDR
] = gen_rsr_ptevaddr
,
476 if (rsr_handler
[sr
]) {
477 rsr_handler
[sr
](dc
, d
, sr
);
479 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
482 qemu_log("RSR %d not implemented, ", sr
);
486 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
488 gen_helper_wsr_lbeg(cpu_env
, s
);
489 gen_jumpi_check_loop_end(dc
, 0);
492 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
494 gen_helper_wsr_lend(cpu_env
, s
);
495 gen_jumpi_check_loop_end(dc
, 0);
498 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
500 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
501 if (dc
->sar_m32_5bit
) {
502 tcg_gen_discard_i32(dc
->sar_m32
);
504 dc
->sar_5bit
= false;
505 dc
->sar_m32_5bit
= false;
508 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
510 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
513 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
515 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
516 /* This can change tb->flags, so exit tb */
517 gen_jumpi_check_loop_end(dc
, -1);
520 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
522 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
525 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
527 gen_helper_wsr_windowbase(cpu_env
, v
);
528 reset_used_window(dc
);
531 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
533 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
534 reset_used_window(dc
);
537 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
539 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
542 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
544 gen_helper_wsr_rasid(cpu_env
, v
);
545 /* This can change tb->flags, so exit tb */
546 gen_jumpi_check_loop_end(dc
, -1);
549 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
551 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
554 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
556 gen_helper_wsr_ibreakenable(cpu_env
, v
);
557 gen_jumpi_check_loop_end(dc
, 0);
560 static void gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
562 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
565 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
567 unsigned id
= sr
- IBREAKA
;
569 if (id
< dc
->config
->nibreak
) {
570 TCGv_i32 tmp
= tcg_const_i32(id
);
571 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
573 gen_jumpi_check_loop_end(dc
, 0);
577 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
579 unsigned id
= sr
- DBREAKA
;
581 if (id
< dc
->config
->ndbreak
) {
582 TCGv_i32 tmp
= tcg_const_i32(id
);
583 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
588 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
590 unsigned id
= sr
- DBREAKC
;
592 if (id
< dc
->config
->ndbreak
) {
593 TCGv_i32 tmp
= tcg_const_i32(id
);
594 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
599 static void gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
601 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc
, -1);
606 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
608 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
609 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
610 gen_helper_check_interrupts(cpu_env
);
611 gen_jumpi_check_loop_end(dc
, 0);
614 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
616 TCGv_i32 tmp
= tcg_temp_new_i32();
618 tcg_gen_andi_i32(tmp
, v
,
619 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
620 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
621 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
622 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
624 gen_helper_check_interrupts(cpu_env
);
627 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
629 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
630 gen_helper_check_interrupts(cpu_env
);
631 gen_jumpi_check_loop_end(dc
, 0);
634 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
636 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
637 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
639 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
642 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
643 reset_used_window(dc
);
644 gen_helper_check_interrupts(cpu_env
);
645 /* This can change mmu index and tb->flags, so exit tb */
646 gen_jumpi_check_loop_end(dc
, -1);
649 static void gen_wsr_debugcause(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
653 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
657 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
660 tcg_gen_mov_i32(dc
->next_icount
, v
);
662 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
666 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
668 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
669 /* This can change tb->flags, so exit tb */
670 gen_jumpi_check_loop_end(dc
, -1);
673 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
675 uint32_t id
= sr
- CCOMPARE
;
676 if (id
< dc
->config
->nccompare
) {
677 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
678 gen_advance_ccount(dc
);
679 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
680 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
681 gen_helper_check_interrupts(cpu_env
);
685 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
687 static void (* const wsr_handler
[256])(DisasContext
*dc
,
688 uint32_t sr
, TCGv_i32 v
) = {
689 [LBEG
] = gen_wsr_lbeg
,
690 [LEND
] = gen_wsr_lend
,
693 [LITBASE
] = gen_wsr_litbase
,
694 [ACCHI
] = gen_wsr_acchi
,
695 [WINDOW_BASE
] = gen_wsr_windowbase
,
696 [WINDOW_START
] = gen_wsr_windowstart
,
697 [PTEVADDR
] = gen_wsr_ptevaddr
,
698 [RASID
] = gen_wsr_rasid
,
699 [ITLBCFG
] = gen_wsr_tlbcfg
,
700 [DTLBCFG
] = gen_wsr_tlbcfg
,
701 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
702 [ATOMCTL
] = gen_wsr_atomctl
,
703 [IBREAKA
] = gen_wsr_ibreaka
,
704 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
705 [DBREAKA
] = gen_wsr_dbreaka
,
706 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
707 [DBREAKC
] = gen_wsr_dbreakc
,
708 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
709 [CPENABLE
] = gen_wsr_cpenable
,
710 [INTSET
] = gen_wsr_intset
,
711 [INTCLEAR
] = gen_wsr_intclear
,
712 [INTENABLE
] = gen_wsr_intenable
,
714 [DEBUGCAUSE
] = gen_wsr_debugcause
,
715 [PRID
] = gen_wsr_prid
,
716 [ICOUNT
] = gen_wsr_icount
,
717 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
718 [CCOMPARE
] = gen_wsr_ccompare
,
719 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
720 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
724 if (wsr_handler
[sr
]) {
725 wsr_handler
[sr
](dc
, sr
, s
);
727 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
730 qemu_log("WSR %d not implemented, ", sr
);
734 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
738 gen_helper_wur_fcr(cpu_env
, s
);
742 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
746 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
751 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
752 TCGv_i32 addr
, bool no_hw_alignment
)
754 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
755 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
756 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
758 int label
= gen_new_label();
759 TCGv_i32 tmp
= tcg_temp_new_i32();
760 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
761 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
762 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
763 gen_set_label(label
);
768 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
770 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
771 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
772 gen_advance_ccount(dc
);
773 gen_helper_waiti(cpu_env
, pc
, intlevel
);
775 tcg_temp_free(intlevel
);
778 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
780 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
783 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
784 r1
/ 4 > dc
->used_window
) {
785 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
786 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
788 dc
->used_window
= r1
/ 4;
789 gen_advance_ccount(dc
);
790 gen_helper_window_check(cpu_env
, pc
, w
);
797 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
799 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
802 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
805 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
808 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
810 TCGv_i32 m
= tcg_temp_new_i32();
813 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
815 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
820 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
822 #define HAS_OPTION_BITS(opt) do { \
823 if (!option_bits_enabled(dc, opt)) { \
824 qemu_log("Option is not enabled %s:%d\n", \
825 __FILE__, __LINE__); \
826 goto invalid_opcode; \
830 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
832 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
833 #define RESERVED() do { \
834 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
835 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
836 goto invalid_opcode; \
840 #ifdef TARGET_WORDS_BIGENDIAN
841 #define OP0 (((b0) & 0xf0) >> 4)
842 #define OP1 (((b2) & 0xf0) >> 4)
843 #define OP2 ((b2) & 0xf)
844 #define RRR_R ((b1) & 0xf)
845 #define RRR_S (((b1) & 0xf0) >> 4)
846 #define RRR_T ((b0) & 0xf)
848 #define OP0 (((b0) & 0xf))
849 #define OP1 (((b2) & 0xf))
850 #define OP2 (((b2) & 0xf0) >> 4)
851 #define RRR_R (((b1) & 0xf0) >> 4)
852 #define RRR_S (((b1) & 0xf))
853 #define RRR_T (((b0) & 0xf0) >> 4)
855 #define RRR_X ((RRR_R & 0x4) >> 2)
856 #define RRR_Y ((RRR_T & 0x4) >> 2)
857 #define RRR_W (RRR_R & 0x3)
866 #define RRI8_IMM8 (b2)
867 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
869 #ifdef TARGET_WORDS_BIGENDIAN
870 #define RI16_IMM16 (((b1) << 8) | (b2))
872 #define RI16_IMM16 (((b2) << 8) | (b1))
875 #ifdef TARGET_WORDS_BIGENDIAN
876 #define CALL_N (((b0) & 0xc) >> 2)
877 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
879 #define CALL_N (((b0) & 0x30) >> 4)
880 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
882 #define CALL_OFFSET_SE \
883 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
885 #define CALLX_N CALL_N
886 #ifdef TARGET_WORDS_BIGENDIAN
887 #define CALLX_M ((b0) & 0x3)
889 #define CALLX_M (((b0) & 0xc0) >> 6)
891 #define CALLX_S RRR_S
893 #define BRI12_M CALLX_M
894 #define BRI12_S RRR_S
895 #ifdef TARGET_WORDS_BIGENDIAN
896 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
898 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
900 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
902 #define BRI8_M BRI12_M
903 #define BRI8_R RRI8_R
904 #define BRI8_S RRI8_S
905 #define BRI8_IMM8 RRI8_IMM8
906 #define BRI8_IMM8_SE RRI8_IMM8_SE
910 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
911 uint8_t b1
= cpu_ldub_code(env
, dc
->pc
+ 1);
914 static const uint32_t B4CONST
[] = {
915 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
918 static const uint32_t B4CONSTU
[] = {
919 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
923 dc
->next_pc
= dc
->pc
+ 2;
924 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
926 dc
->next_pc
= dc
->pc
+ 3;
927 b2
= cpu_ldub_code(env
, dc
->pc
+ 2);
936 if ((RRR_R
& 0xc) == 0x8) {
937 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
944 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
955 gen_window_check1(dc
, CALLX_S
);
956 gen_jump(dc
, cpu_R
[CALLX_S
]);
960 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
962 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
963 gen_advance_ccount(dc
);
964 gen_helper_retw(tmp
, cpu_env
, tmp
);
977 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
981 TCGv_i32 tmp
= tcg_temp_new_i32();
982 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
983 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
992 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
994 TCGv_i32 tmp
= tcg_temp_new_i32();
996 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
997 gen_callw(dc
, CALLX_N
, tmp
);
1007 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1008 gen_window_check2(dc
, RRR_T
, RRR_S
);
1010 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1011 gen_advance_ccount(dc
);
1012 gen_helper_movsp(cpu_env
, pc
);
1013 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1033 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1045 default: /*reserved*/
1054 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1057 gen_check_privilege(dc
);
1058 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1059 gen_helper_check_interrupts(cpu_env
);
1060 gen_jump(dc
, cpu_SR
[EPC1
]);
1068 gen_check_privilege(dc
);
1069 gen_jump(dc
, cpu_SR
[
1070 dc
->config
->ndepc
? DEPC
: EPC1
]);
1075 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1076 gen_check_privilege(dc
);
1078 TCGv_i32 tmp
= tcg_const_i32(1);
1081 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1082 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1085 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1086 cpu_SR
[WINDOW_START
], tmp
);
1088 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1089 cpu_SR
[WINDOW_START
], tmp
);
1092 gen_helper_restore_owb(cpu_env
);
1093 gen_helper_check_interrupts(cpu_env
);
1094 gen_jump(dc
, cpu_SR
[EPC1
]);
1100 default: /*reserved*/
1107 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1108 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1109 gen_check_privilege(dc
);
1110 tcg_gen_mov_i32(cpu_SR
[PS
],
1111 cpu_SR
[EPS2
+ RRR_S
- 2]);
1112 gen_helper_check_interrupts(cpu_env
);
1113 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1115 qemu_log("RFI %d is illegal\n", RRR_S
);
1116 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1124 default: /*reserved*/
1132 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1134 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1138 case 5: /*SYSCALLx*/
1139 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1141 case 0: /*SYSCALLx*/
1142 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1146 if (semihosting_enabled
) {
1147 gen_check_privilege(dc
);
1148 gen_helper_simcall(cpu_env
);
1150 qemu_log("SIMCALL but semihosting is disabled\n");
1151 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1162 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1163 gen_check_privilege(dc
);
1164 gen_window_check1(dc
, RRR_T
);
1165 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1166 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1167 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1168 gen_helper_check_interrupts(cpu_env
);
1169 gen_jumpi_check_loop_end(dc
, 0);
1173 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1174 gen_check_privilege(dc
);
1175 gen_waiti(dc
, RRR_S
);
1182 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1184 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1185 TCGv_i32 mask
= tcg_const_i32(
1186 ((1 << shift
) - 1) << RRR_S
);
1187 TCGv_i32 tmp
= tcg_temp_new_i32();
1189 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1190 if (RRR_R
& 1) { /*ALL*/
1191 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1193 tcg_gen_add_i32(tmp
, tmp
, mask
);
1195 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1196 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1198 tcg_temp_free(mask
);
1203 default: /*reserved*/
1211 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1212 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1216 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1217 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1221 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1222 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1228 gen_window_check1(dc
, RRR_S
);
1229 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1233 gen_window_check1(dc
, RRR_S
);
1234 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1238 gen_window_check1(dc
, RRR_S
);
1240 TCGv_i32 tmp
= tcg_temp_new_i32();
1241 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1242 gen_right_shift_sar(dc
, tmp
);
1248 gen_window_check1(dc
, RRR_S
);
1250 TCGv_i32 tmp
= tcg_temp_new_i32();
1251 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1252 gen_left_shift_sar(dc
, tmp
);
1259 TCGv_i32 tmp
= tcg_const_i32(
1260 RRR_S
| ((RRR_T
& 1) << 4));
1261 gen_right_shift_sar(dc
, tmp
);
1275 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1276 gen_check_privilege(dc
);
1278 TCGv_i32 tmp
= tcg_const_i32(
1279 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1280 gen_helper_rotw(cpu_env
, tmp
);
1282 reset_used_window(dc
);
1287 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1288 gen_window_check2(dc
, RRR_S
, RRR_T
);
1289 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1293 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1294 gen_window_check2(dc
, RRR_S
, RRR_T
);
1295 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1298 default: /*reserved*/
1306 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1307 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1308 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1309 gen_check_privilege(dc
);
1310 gen_window_check2(dc
, RRR_S
, RRR_T
);
1312 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1314 switch (RRR_R
& 7) {
1315 case 3: /*RITLB0*/ /*RDTLB0*/
1316 gen_helper_rtlb0(cpu_R
[RRR_T
],
1317 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1320 case 4: /*IITLB*/ /*IDTLB*/
1321 gen_helper_itlb(cpu_env
, cpu_R
[RRR_S
], dtlb
);
1322 /* This could change memory mapping, so exit tb */
1323 gen_jumpi_check_loop_end(dc
, -1);
1326 case 5: /*PITLB*/ /*PDTLB*/
1327 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1328 gen_helper_ptlb(cpu_R
[RRR_T
],
1329 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1332 case 6: /*WITLB*/ /*WDTLB*/
1334 cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1335 /* This could change memory mapping, so exit tb */
1336 gen_jumpi_check_loop_end(dc
, -1);
1339 case 7: /*RITLB1*/ /*RDTLB1*/
1340 gen_helper_rtlb1(cpu_R
[RRR_T
],
1341 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1345 tcg_temp_free(dtlb
);
1349 tcg_temp_free(dtlb
);
1354 gen_window_check2(dc
, RRR_R
, RRR_T
);
1357 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1362 int label
= gen_new_label();
1363 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1364 tcg_gen_brcondi_i32(
1365 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1366 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1367 gen_set_label(label
);
1371 default: /*reserved*/
1377 case 7: /*reserved*/
1382 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1383 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1389 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1391 TCGv_i32 tmp
= tcg_temp_new_i32();
1392 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1393 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1399 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1400 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1406 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1408 TCGv_i32 tmp
= tcg_temp_new_i32();
1409 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1410 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1421 gen_window_check2(dc
, RRR_R
, RRR_S
);
1422 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1423 32 - (RRR_T
| ((OP2
& 1) << 4)));
1428 gen_window_check2(dc
, RRR_R
, RRR_T
);
1429 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1430 RRR_S
| ((OP2
& 1) << 4));
1434 gen_window_check2(dc
, RRR_R
, RRR_T
);
1435 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1440 TCGv_i32 tmp
= tcg_temp_new_i32();
1442 gen_check_privilege(dc
);
1444 gen_window_check1(dc
, RRR_T
);
1445 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1446 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1447 gen_wsr(dc
, RSR_SR
, tmp
);
1449 if (!sregnames
[RSR_SR
]) {
1456 * Note: 64 bit ops are used here solely because SAR values
1459 #define gen_shift_reg(cmd, reg) do { \
1460 TCGv_i64 tmp = tcg_temp_new_i64(); \
1461 tcg_gen_extu_i32_i64(tmp, reg); \
1462 tcg_gen_##cmd##_i64(v, v, tmp); \
1463 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1464 tcg_temp_free_i64(v); \
1465 tcg_temp_free_i64(tmp); \
1468 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1471 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1473 TCGv_i64 v
= tcg_temp_new_i64();
1474 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1480 gen_window_check2(dc
, RRR_R
, RRR_T
);
1482 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1484 TCGv_i64 v
= tcg_temp_new_i64();
1485 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1491 gen_window_check2(dc
, RRR_R
, RRR_S
);
1492 if (dc
->sar_m32_5bit
) {
1493 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1495 TCGv_i64 v
= tcg_temp_new_i64();
1496 TCGv_i32 s
= tcg_const_i32(32);
1497 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1498 tcg_gen_andi_i32(s
, s
, 0x3f);
1499 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1500 gen_shift_reg(shl
, s
);
1506 gen_window_check2(dc
, RRR_R
, RRR_T
);
1508 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1510 TCGv_i64 v
= tcg_temp_new_i64();
1511 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1516 #undef gen_shift_reg
1519 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1520 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1522 TCGv_i32 v1
= tcg_temp_new_i32();
1523 TCGv_i32 v2
= tcg_temp_new_i32();
1524 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1525 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1526 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1533 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1534 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1536 TCGv_i32 v1
= tcg_temp_new_i32();
1537 TCGv_i32 v2
= tcg_temp_new_i32();
1538 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1539 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1540 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1546 default: /*reserved*/
1554 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1558 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1559 int label
= gen_new_label();
1560 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1561 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1562 gen_set_label(label
);
1566 #define BOOLEAN_LOGIC(fn, r, s, t) \
1568 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1569 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1570 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1572 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1573 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1574 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1575 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1576 tcg_temp_free(tmp1); \
1577 tcg_temp_free(tmp2); \
1581 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1585 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1589 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1593 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1597 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1600 #undef BOOLEAN_LOGIC
1603 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1604 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1609 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1611 TCGv_i64 r
= tcg_temp_new_i64();
1612 TCGv_i64 s
= tcg_temp_new_i64();
1613 TCGv_i64 t
= tcg_temp_new_i64();
1616 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1617 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1619 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1620 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1622 tcg_gen_mul_i64(r
, s
, t
);
1623 tcg_gen_shri_i64(r
, r
, 32);
1624 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1626 tcg_temp_free_i64(r
);
1627 tcg_temp_free_i64(s
);
1628 tcg_temp_free_i64(t
);
1633 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1639 int label1
= gen_new_label();
1640 int label2
= gen_new_label();
1642 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1644 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1646 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1647 OP2
== 13 ? 0x80000000 : 0);
1649 gen_set_label(label1
);
1651 tcg_gen_div_i32(cpu_R
[RRR_R
],
1652 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1654 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1655 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1657 gen_set_label(label2
);
1662 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1665 default: /*reserved*/
1675 gen_check_privilege(dc
);
1677 gen_window_check1(dc
, RRR_T
);
1678 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1679 if (!sregnames
[RSR_SR
]) {
1686 gen_check_privilege(dc
);
1688 gen_window_check1(dc
, RRR_T
);
1689 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1690 if (!sregnames
[RSR_SR
]) {
1696 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1697 gen_window_check2(dc
, RRR_R
, RRR_S
);
1699 int shift
= 24 - RRR_T
;
1702 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1703 } else if (shift
== 16) {
1704 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1706 TCGv_i32 tmp
= tcg_temp_new_i32();
1707 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1708 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1715 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1716 gen_window_check2(dc
, RRR_R
, RRR_S
);
1718 TCGv_i32 tmp1
= tcg_temp_new_i32();
1719 TCGv_i32 tmp2
= tcg_temp_new_i32();
1720 int label
= gen_new_label();
1722 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1723 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1724 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1725 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1726 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1728 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1729 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1730 0xffffffff >> (25 - RRR_T
));
1732 gen_set_label(label
);
1734 tcg_temp_free(tmp1
);
1735 tcg_temp_free(tmp2
);
1743 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1744 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1746 static const TCGCond cond
[] = {
1752 int label
= gen_new_label();
1754 if (RRR_R
!= RRR_T
) {
1755 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1756 tcg_gen_brcond_i32(cond
[OP2
- 4],
1757 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1758 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1760 tcg_gen_brcond_i32(cond
[OP2
- 4],
1761 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1762 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1764 gen_set_label(label
);
1772 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1774 static const TCGCond cond
[] = {
1780 int label
= gen_new_label();
1781 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1782 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1783 gen_set_label(label
);
1789 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1790 gen_window_check2(dc
, RRR_R
, RRR_S
);
1792 int label
= gen_new_label();
1793 TCGv_i32 tmp
= tcg_temp_new_i32();
1795 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1796 tcg_gen_brcondi_i32(
1797 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1799 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1800 gen_set_label(label
);
1806 gen_window_check1(dc
, RRR_R
);
1808 int st
= (RRR_S
<< 4) + RRR_T
;
1809 if (uregnames
[st
]) {
1810 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1812 qemu_log("RUR %d not implemented, ", st
);
1819 gen_window_check1(dc
, RRR_T
);
1820 if (uregnames
[RSR_SR
]) {
1821 gen_wur(RSR_SR
, cpu_R
[RRR_T
]);
1823 qemu_log("WUR %d not implemented, ", RSR_SR
);
1833 gen_window_check2(dc
, RRR_R
, RRR_T
);
1835 int shiftimm
= RRR_S
| ((OP1
& 1) << 4);
1836 int maskimm
= (1 << (OP2
+ 1)) - 1;
1838 TCGv_i32 tmp
= tcg_temp_new_i32();
1839 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1840 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1859 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1860 gen_window_check2(dc
, RRR_S
, RRR_T
);
1861 gen_check_cpenable(dc
, 0);
1863 TCGv_i32 addr
= tcg_temp_new_i32();
1864 tcg_gen_add_i32(addr
, cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1865 gen_load_store_alignment(dc
, 2, addr
, false);
1867 tcg_gen_qemu_st32(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1869 tcg_gen_qemu_ld32u(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1872 tcg_gen_mov_i32(cpu_R
[RRR_S
], addr
);
1874 tcg_temp_free(addr
);
1878 default: /*reserved*/
1885 gen_window_check2(dc
, RRR_S
, RRR_T
);
1888 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1889 gen_check_privilege(dc
);
1891 TCGv_i32 addr
= tcg_temp_new_i32();
1892 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1893 (0xffffffc0 | (RRR_R
<< 2)));
1894 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1895 tcg_temp_free(addr
);
1900 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1901 gen_check_privilege(dc
);
1903 TCGv_i32 addr
= tcg_temp_new_i32();
1904 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1905 (0xffffffc0 | (RRR_R
<< 2)));
1906 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1907 tcg_temp_free(addr
);
1918 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1921 gen_check_cpenable(dc
, 0);
1922 gen_helper_add_s(cpu_FR
[RRR_R
], cpu_env
,
1923 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1927 gen_check_cpenable(dc
, 0);
1928 gen_helper_sub_s(cpu_FR
[RRR_R
], cpu_env
,
1929 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1933 gen_check_cpenable(dc
, 0);
1934 gen_helper_mul_s(cpu_FR
[RRR_R
], cpu_env
,
1935 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1939 gen_check_cpenable(dc
, 0);
1940 gen_helper_madd_s(cpu_FR
[RRR_R
], cpu_env
,
1941 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1945 gen_check_cpenable(dc
, 0);
1946 gen_helper_msub_s(cpu_FR
[RRR_R
], cpu_env
,
1947 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1950 case 8: /*ROUND.Sf*/
1951 case 9: /*TRUNC.Sf*/
1952 case 10: /*FLOOR.Sf*/
1953 case 11: /*CEIL.Sf*/
1954 case 14: /*UTRUNC.Sf*/
1955 gen_window_check1(dc
, RRR_R
);
1956 gen_check_cpenable(dc
, 0);
1958 static const unsigned rounding_mode_const
[] = {
1959 float_round_nearest_even
,
1960 float_round_to_zero
,
1963 [6] = float_round_to_zero
,
1965 TCGv_i32 rounding_mode
= tcg_const_i32(
1966 rounding_mode_const
[OP2
& 7]);
1967 TCGv_i32 scale
= tcg_const_i32(RRR_T
);
1970 gen_helper_ftoui(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1971 rounding_mode
, scale
);
1973 gen_helper_ftoi(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1974 rounding_mode
, scale
);
1977 tcg_temp_free(rounding_mode
);
1978 tcg_temp_free(scale
);
1982 case 12: /*FLOAT.Sf*/
1983 case 13: /*UFLOAT.Sf*/
1984 gen_window_check1(dc
, RRR_S
);
1985 gen_check_cpenable(dc
, 0);
1987 TCGv_i32 scale
= tcg_const_i32(-RRR_T
);
1990 gen_helper_uitof(cpu_FR
[RRR_R
], cpu_env
,
1991 cpu_R
[RRR_S
], scale
);
1993 gen_helper_itof(cpu_FR
[RRR_R
], cpu_env
,
1994 cpu_R
[RRR_S
], scale
);
1996 tcg_temp_free(scale
);
2003 gen_check_cpenable(dc
, 0);
2004 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2008 gen_check_cpenable(dc
, 0);
2009 gen_helper_abs_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2013 gen_window_check1(dc
, RRR_R
);
2014 gen_check_cpenable(dc
, 0);
2015 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_FR
[RRR_S
]);
2019 gen_window_check1(dc
, RRR_S
);
2020 gen_check_cpenable(dc
, 0);
2021 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_R
[RRR_S
]);
2025 gen_check_cpenable(dc
, 0);
2026 gen_helper_neg_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2029 default: /*reserved*/
2035 default: /*reserved*/
2042 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2044 #define gen_compare(rel, br, a, b) \
2046 TCGv_i32 bit = tcg_const_i32(1 << br); \
2048 gen_check_cpenable(dc, 0); \
2049 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2050 tcg_temp_free(bit); \
2055 gen_compare(un_s
, RRR_R
, RRR_S
, RRR_T
);
2059 gen_compare(oeq_s
, RRR_R
, RRR_S
, RRR_T
);
2063 gen_compare(ueq_s
, RRR_R
, RRR_S
, RRR_T
);
2067 gen_compare(olt_s
, RRR_R
, RRR_S
, RRR_T
);
2071 gen_compare(ult_s
, RRR_R
, RRR_S
, RRR_T
);
2075 gen_compare(ole_s
, RRR_R
, RRR_S
, RRR_T
);
2079 gen_compare(ule_s
, RRR_R
, RRR_S
, RRR_T
);
2084 case 8: /*MOVEQZ.Sf*/
2085 case 9: /*MOVNEZ.Sf*/
2086 case 10: /*MOVLTZ.Sf*/
2087 case 11: /*MOVGEZ.Sf*/
2088 gen_window_check1(dc
, RRR_T
);
2089 gen_check_cpenable(dc
, 0);
2091 static const TCGCond cond
[] = {
2097 int label
= gen_new_label();
2098 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
2099 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2100 gen_set_label(label
);
2104 case 12: /*MOVF.Sf*/
2105 case 13: /*MOVT.Sf*/
2106 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2107 gen_check_cpenable(dc
, 0);
2109 int label
= gen_new_label();
2110 TCGv_i32 tmp
= tcg_temp_new_i32();
2112 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
2113 tcg_gen_brcondi_i32(
2114 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
2116 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2117 gen_set_label(label
);
2122 default: /*reserved*/
2128 default: /*reserved*/
2135 gen_window_check1(dc
, RRR_T
);
2137 TCGv_i32 tmp
= tcg_const_i32(
2138 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
2139 0 : ((dc
->pc
+ 3) & ~3)) +
2140 (0xfffc0000 | (RI16_IMM16
<< 2)));
2142 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
2143 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
2145 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
2151 #define gen_load_store(type, shift) do { \
2152 TCGv_i32 addr = tcg_temp_new_i32(); \
2153 gen_window_check2(dc, RRI8_S, RRI8_T); \
2154 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2156 gen_load_store_alignment(dc, shift, addr, false); \
2158 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2159 tcg_temp_free(addr); \
2164 gen_load_store(ld8u
, 0);
2168 gen_load_store(ld16u
, 1);
2172 gen_load_store(ld32u
, 2);
2176 gen_load_store(st8
, 0);
2180 gen_load_store(st16
, 1);
2184 gen_load_store(st32
, 2);
2189 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2220 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2224 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2228 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2232 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2236 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2239 default: /*reserved*/
2247 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2253 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2257 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2261 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2264 default: /*reserved*/
2271 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2275 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2278 default: /*reserved*/
2285 gen_load_store(ld16s
, 1);
2287 #undef gen_load_store
2290 gen_window_check1(dc
, RRI8_T
);
2291 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2292 RRI8_IMM8
| (RRI8_S
<< 8) |
2293 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2296 #define gen_load_store_no_hw_align(type) do { \
2297 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2298 gen_window_check2(dc, RRI8_S, RRI8_T); \
2299 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2300 gen_load_store_alignment(dc, 2, addr, true); \
2301 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2302 tcg_temp_free(addr); \
2306 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2307 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2311 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2312 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2316 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2317 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
2320 case 14: /*S32C1Iy*/
2321 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2322 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2324 int label
= gen_new_label();
2325 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2326 TCGv_i32 addr
= tcg_temp_local_new_i32();
2329 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2330 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2331 gen_load_store_alignment(dc
, 2, addr
, true);
2333 gen_advance_ccount(dc
);
2334 tpc
= tcg_const_i32(dc
->pc
);
2335 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2336 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2337 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2338 cpu_SR
[SCOMPARE1
], label
);
2340 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2342 gen_set_label(label
);
2344 tcg_temp_free(addr
);
2350 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2351 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2353 #undef gen_load_store_no_hw_align
2355 default: /*reserved*/
2367 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2368 gen_window_check1(dc
, RRI8_S
);
2369 gen_check_cpenable(dc
, 0);
2371 TCGv_i32 addr
= tcg_temp_new_i32();
2372 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2373 gen_load_store_alignment(dc
, 2, addr
, false);
2375 tcg_gen_qemu_st32(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2377 tcg_gen_qemu_ld32u(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2380 tcg_gen_mov_i32(cpu_R
[RRI8_S
], addr
);
2382 tcg_temp_free(addr
);
2386 default: /*reserved*/
2393 HAS_OPTION(XTENSA_OPTION_MAC16
);
2402 bool is_m1_sr
= (OP2
& 0x3) == 2;
2403 bool is_m2_sr
= (OP2
& 0xc) == 0;
2404 uint32_t ld_offset
= 0;
2411 case 0: /*MACI?/MACC?*/
2413 ld_offset
= (OP2
& 1) ? -4 : 4;
2415 if (OP2
>= 8) { /*MACI/MACC*/
2416 if (OP1
== 0) { /*LDINC/LDDEC*/
2421 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2426 case 2: /*MACD?/MACA?*/
2427 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2433 if (op
!= MAC16_NONE
) {
2435 gen_window_check1(dc
, RRR_S
);
2438 gen_window_check1(dc
, RRR_T
);
2443 TCGv_i32 vaddr
= tcg_temp_new_i32();
2444 TCGv_i32 mem32
= tcg_temp_new_i32();
2447 gen_window_check1(dc
, RRR_S
);
2448 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2449 gen_load_store_alignment(dc
, 2, vaddr
, false);
2450 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2452 if (op
!= MAC16_NONE
) {
2453 TCGv_i32 m1
= gen_mac16_m(
2454 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2455 OP1
& 1, op
== MAC16_UMUL
);
2456 TCGv_i32 m2
= gen_mac16_m(
2457 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2458 OP1
& 2, op
== MAC16_UMUL
);
2460 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2461 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2462 if (op
== MAC16_UMUL
) {
2463 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2465 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2468 TCGv_i32 res
= tcg_temp_new_i32();
2469 TCGv_i64 res64
= tcg_temp_new_i64();
2470 TCGv_i64 tmp
= tcg_temp_new_i64();
2472 tcg_gen_mul_i32(res
, m1
, m2
);
2473 tcg_gen_ext_i32_i64(res64
, res
);
2474 tcg_gen_concat_i32_i64(tmp
,
2475 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
]);
2476 if (op
== MAC16_MULA
) {
2477 tcg_gen_add_i64(tmp
, tmp
, res64
);
2479 tcg_gen_sub_i64(tmp
, tmp
, res64
);
2481 tcg_gen_trunc_i64_i32(cpu_SR
[ACCLO
], tmp
);
2482 tcg_gen_shri_i64(tmp
, tmp
, 32);
2483 tcg_gen_trunc_i64_i32(cpu_SR
[ACCHI
], tmp
);
2484 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2487 tcg_temp_free_i64(res64
);
2488 tcg_temp_free_i64(tmp
);
2494 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2495 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2497 tcg_temp_free(vaddr
);
2498 tcg_temp_free(mem32
);
2506 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2507 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2513 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2514 gen_window_check1(dc
, CALL_N
<< 2);
2515 gen_callwi(dc
, CALL_N
,
2516 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2524 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2528 gen_window_check1(dc
, BRI12_S
);
2530 static const TCGCond cond
[] = {
2531 TCG_COND_EQ
, /*BEQZ*/
2532 TCG_COND_NE
, /*BNEZ*/
2533 TCG_COND_LT
, /*BLTZ*/
2534 TCG_COND_GE
, /*BGEZ*/
2537 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2538 4 + BRI12_IMM12_SE
);
2543 gen_window_check1(dc
, BRI8_S
);
2545 static const TCGCond cond
[] = {
2546 TCG_COND_EQ
, /*BEQI*/
2547 TCG_COND_NE
, /*BNEI*/
2548 TCG_COND_LT
, /*BLTI*/
2549 TCG_COND_GE
, /*BGEI*/
2552 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2553 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2560 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2562 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2563 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2564 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2565 gen_advance_ccount(dc
);
2566 gen_helper_entry(cpu_env
, pc
, s
, imm
);
2570 reset_used_window(dc
);
2578 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2580 TCGv_i32 tmp
= tcg_temp_new_i32();
2581 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2583 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2584 tmp
, 0, 4 + RRI8_IMM8_SE
);
2591 case 10: /*LOOPGTZ*/
2592 HAS_OPTION(XTENSA_OPTION_LOOP
);
2593 gen_window_check1(dc
, RRI8_S
);
2595 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2596 TCGv_i32 tmp
= tcg_const_i32(lend
);
2598 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2599 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2600 gen_helper_wsr_lend(cpu_env
, tmp
);
2604 int label
= gen_new_label();
2605 tcg_gen_brcondi_i32(
2606 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2607 cpu_R
[RRI8_S
], 0, label
);
2608 gen_jumpi(dc
, lend
, 1);
2609 gen_set_label(label
);
2612 gen_jumpi(dc
, dc
->next_pc
, 0);
2616 default: /*reserved*/
2625 gen_window_check1(dc
, BRI8_S
);
2626 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2627 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2637 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2639 switch (RRI8_R
& 7) {
2640 case 0: /*BNONE*/ /*BANY*/
2641 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2643 TCGv_i32 tmp
= tcg_temp_new_i32();
2644 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2645 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2650 case 1: /*BEQ*/ /*BNE*/
2651 case 2: /*BLT*/ /*BGE*/
2652 case 3: /*BLTU*/ /*BGEU*/
2653 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2655 static const TCGCond cond
[] = {
2661 [11] = TCG_COND_GEU
,
2663 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2668 case 4: /*BALL*/ /*BNALL*/
2669 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2671 TCGv_i32 tmp
= tcg_temp_new_i32();
2672 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2673 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2679 case 5: /*BBC*/ /*BBS*/
2680 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2682 #ifdef TARGET_WORDS_BIGENDIAN
2683 TCGv_i32 bit
= tcg_const_i32(0x80000000);
2685 TCGv_i32 bit
= tcg_const_i32(0x00000001);
2687 TCGv_i32 tmp
= tcg_temp_new_i32();
2688 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2689 #ifdef TARGET_WORDS_BIGENDIAN
2690 tcg_gen_shr_i32(bit
, bit
, tmp
);
2692 tcg_gen_shl_i32(bit
, bit
, tmp
);
2694 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2695 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2701 case 6: /*BBCI*/ /*BBSI*/
2703 gen_window_check1(dc
, RRI8_S
);
2705 TCGv_i32 tmp
= tcg_temp_new_i32();
2706 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2707 #ifdef TARGET_WORDS_BIGENDIAN
2708 0x80000000 >> (((RRI8_R
& 1) << 4) | RRI8_T
));
2710 0x00000001 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2712 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2721 #define gen_narrow_load_store(type) do { \
2722 TCGv_i32 addr = tcg_temp_new_i32(); \
2723 gen_window_check2(dc, RRRN_S, RRRN_T); \
2724 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2725 gen_load_store_alignment(dc, 2, addr, false); \
2726 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2727 tcg_temp_free(addr); \
2731 gen_narrow_load_store(ld32u
);
2735 gen_narrow_load_store(st32
);
2737 #undef gen_narrow_load_store
2740 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2741 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2744 case 11: /*ADDI.Nn*/
2745 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2746 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2750 gen_window_check1(dc
, RRRN_S
);
2751 if (RRRN_T
< 8) { /*MOVI.Nn*/
2752 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2753 RRRN_R
| (RRRN_T
<< 4) |
2754 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2755 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2756 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2758 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2759 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2766 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2767 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2773 gen_jump(dc
, cpu_R
[0]);
2777 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2779 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2780 gen_advance_ccount(dc
);
2781 gen_helper_retw(tmp
, cpu_env
, tmp
);
2787 case 2: /*BREAK.Nn*/
2788 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2790 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2798 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2801 default: /*reserved*/
2807 default: /*reserved*/
2813 default: /*reserved*/
2818 if (dc
->is_jmp
== DISAS_NEXT
) {
2819 gen_check_loop_end(dc
, 0);
2821 dc
->pc
= dc
->next_pc
;
2826 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2827 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2831 static void check_breakpoint(CPUXtensaState
*env
, DisasContext
*dc
)
2835 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2836 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2837 if (bp
->pc
== dc
->pc
) {
2838 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2839 gen_exception(dc
, EXCP_DEBUG
);
2840 dc
->is_jmp
= DISAS_UPDATE
;
2846 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
2850 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
2851 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
2852 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
2853 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
2859 static void gen_intermediate_code_internal(
2860 CPUXtensaState
*env
, TranslationBlock
*tb
, int search_pc
)
2865 uint16_t *gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
2866 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2867 uint32_t pc_start
= tb
->pc
;
2868 uint32_t next_page_start
=
2869 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2871 if (max_insns
== 0) {
2872 max_insns
= CF_COUNT_MASK
;
2875 dc
.config
= env
->config
;
2876 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2879 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2880 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2881 dc
.lbeg
= env
->sregs
[LBEG
];
2882 dc
.lend
= env
->sregs
[LEND
];
2883 dc
.is_jmp
= DISAS_NEXT
;
2884 dc
.ccount_delta
= 0;
2885 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
2886 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
2887 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
2888 XTENSA_TBFLAG_CPENABLE_SHIFT
;
2891 init_sar_tracker(&dc
);
2892 reset_used_window(&dc
);
2894 dc
.next_icount
= tcg_temp_local_new_i32();
2899 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2900 env
->exception_taken
= 0;
2901 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2902 gen_exception(&dc
, EXCP_DEBUG
);
2906 check_breakpoint(env
, &dc
);
2909 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
2913 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
2916 tcg_ctx
.gen_opc_pc
[lj
] = dc
.pc
;
2917 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
2918 tcg_ctx
.gen_opc_icount
[lj
] = insn_count
;
2921 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2922 tcg_gen_debug_insn_start(dc
.pc
);
2927 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2932 int label
= gen_new_label();
2934 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
2935 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
2936 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
2938 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
2940 gen_set_label(label
);
2944 gen_ibreak_check(env
, &dc
);
2947 disas_xtensa_insn(env
, &dc
);
2950 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
2952 if (env
->singlestep_enabled
) {
2953 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2954 gen_exception(&dc
, EXCP_DEBUG
);
2957 } while (dc
.is_jmp
== DISAS_NEXT
&&
2958 insn_count
< max_insns
&&
2959 dc
.pc
< next_page_start
&&
2960 tcg_ctx
.gen_opc_ptr
< gen_opc_end
);
2963 reset_sar_tracker(&dc
);
2965 tcg_temp_free(dc
.next_icount
);
2968 if (tb
->cflags
& CF_LAST_IO
) {
2972 if (dc
.is_jmp
== DISAS_NEXT
) {
2973 gen_jumpi(&dc
, dc
.pc
, 0);
2975 gen_icount_end(tb
, insn_count
);
2976 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
2979 tb
->size
= dc
.pc
- pc_start
;
2980 tb
->icount
= insn_count
;
2984 void gen_intermediate_code(CPUXtensaState
*env
, TranslationBlock
*tb
)
2986 gen_intermediate_code_internal(env
, tb
, 0);
2989 void gen_intermediate_code_pc(CPUXtensaState
*env
, TranslationBlock
*tb
)
2991 gen_intermediate_code_internal(env
, tb
, 1);
2994 void cpu_dump_state(CPUXtensaState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
2999 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
3001 for (i
= j
= 0; i
< 256; ++i
) {
3003 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
3004 (j
++ % 4) == 3 ? '\n' : ' ');
3008 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3010 for (i
= j
= 0; i
< 256; ++i
) {
3012 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
3013 (j
++ % 4) == 3 ? '\n' : ' ');
3017 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3019 for (i
= 0; i
< 16; ++i
) {
3020 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
3021 (i
% 4) == 3 ? '\n' : ' ');
3024 cpu_fprintf(f
, "\n");
3026 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
3027 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
3028 (i
% 4) == 3 ? '\n' : ' ');
3031 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
3032 cpu_fprintf(f
, "\n");
3034 for (i
= 0; i
< 16; ++i
) {
3035 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
3036 float32_val(env
->fregs
[i
]),
3037 *(float *)&env
->fregs
[i
], (i
% 2) == 1 ? '\n' : ' ');
3042 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
, int pc_pos
)
3044 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];