3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
72 static TCGv_ptr cpu_env
;
73 static TCGv_i32 cpu_pc
;
74 static TCGv_i32 cpu_R
[16];
75 static TCGv_i32 cpu_FR
[16];
76 static TCGv_i32 cpu_SR
[256];
77 static TCGv_i32 cpu_UR
[256];
79 #include "gen-icount.h"
81 static const char * const sregnames
[256] = {
87 [LITBASE
] = "LITBASE",
88 [SCOMPARE1
] = "SCOMPARE1",
95 [WINDOW_BASE
] = "WINDOW_BASE",
96 [WINDOW_START
] = "WINDOW_START",
97 [PTEVADDR
] = "PTEVADDR",
99 [ITLBCFG
] = "ITLBCFG",
100 [DTLBCFG
] = "DTLBCFG",
101 [IBREAKENABLE
] = "IBREAKENABLE",
102 [CACHEATTR
] = "CACHEATTR",
103 [ATOMCTL
] = "ATOMCTL",
104 [IBREAKA
] = "IBREAKA0",
105 [IBREAKA
+ 1] = "IBREAKA1",
106 [DBREAKA
] = "DBREAKA0",
107 [DBREAKA
+ 1] = "DBREAKA1",
108 [DBREAKC
] = "DBREAKC0",
109 [DBREAKC
+ 1] = "DBREAKC1",
124 [EXCSAVE1
] = "EXCSAVE1",
125 [EXCSAVE1
+ 1] = "EXCSAVE2",
126 [EXCSAVE1
+ 2] = "EXCSAVE3",
127 [EXCSAVE1
+ 3] = "EXCSAVE4",
128 [EXCSAVE1
+ 4] = "EXCSAVE5",
129 [EXCSAVE1
+ 5] = "EXCSAVE6",
130 [EXCSAVE1
+ 6] = "EXCSAVE7",
131 [CPENABLE
] = "CPENABLE",
133 [INTCLEAR
] = "INTCLEAR",
134 [INTENABLE
] = "INTENABLE",
136 [VECBASE
] = "VECBASE",
137 [EXCCAUSE
] = "EXCCAUSE",
138 [DEBUGCAUSE
] = "DEBUGCAUSE",
142 [ICOUNTLEVEL
] = "ICOUNTLEVEL",
143 [EXCVADDR
] = "EXCVADDR",
144 [CCOMPARE
] = "CCOMPARE0",
145 [CCOMPARE
+ 1] = "CCOMPARE1",
146 [CCOMPARE
+ 2] = "CCOMPARE2",
149 static const char * const uregnames
[256] = {
150 [THREADPTR
] = "THREADPTR",
155 void xtensa_translate_init(void)
157 static const char * const regnames
[] = {
158 "ar0", "ar1", "ar2", "ar3",
159 "ar4", "ar5", "ar6", "ar7",
160 "ar8", "ar9", "ar10", "ar11",
161 "ar12", "ar13", "ar14", "ar15",
163 static const char * const fregnames
[] = {
164 "f0", "f1", "f2", "f3",
165 "f4", "f5", "f6", "f7",
166 "f8", "f9", "f10", "f11",
167 "f12", "f13", "f14", "f15",
171 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
172 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
173 offsetof(CPUXtensaState
, pc
), "pc");
175 for (i
= 0; i
< 16; i
++) {
176 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
177 offsetof(CPUXtensaState
, regs
[i
]),
181 for (i
= 0; i
< 16; i
++) {
182 cpu_FR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
183 offsetof(CPUXtensaState
, fregs
[i
]),
187 for (i
= 0; i
< 256; ++i
) {
189 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
190 offsetof(CPUXtensaState
, sregs
[i
]),
195 for (i
= 0; i
< 256; ++i
) {
197 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
198 offsetof(CPUXtensaState
, uregs
[i
]),
206 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
208 return xtensa_option_bits_enabled(dc
->config
, opt
);
211 static inline bool option_enabled(DisasContext
*dc
, int opt
)
213 return xtensa_option_enabled(dc
->config
, opt
);
216 static void init_litbase(DisasContext
*dc
)
218 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
219 dc
->litbase
= tcg_temp_local_new_i32();
220 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
224 static void reset_litbase(DisasContext
*dc
)
226 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
227 tcg_temp_free(dc
->litbase
);
231 static void init_sar_tracker(DisasContext
*dc
)
233 dc
->sar_5bit
= false;
234 dc
->sar_m32_5bit
= false;
235 dc
->sar_m32_allocated
= false;
238 static void reset_sar_tracker(DisasContext
*dc
)
240 if (dc
->sar_m32_allocated
) {
241 tcg_temp_free(dc
->sar_m32
);
245 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
247 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
248 if (dc
->sar_m32_5bit
) {
249 tcg_gen_discard_i32(dc
->sar_m32
);
252 dc
->sar_m32_5bit
= false;
255 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
257 TCGv_i32 tmp
= tcg_const_i32(32);
258 if (!dc
->sar_m32_allocated
) {
259 dc
->sar_m32
= tcg_temp_local_new_i32();
260 dc
->sar_m32_allocated
= true;
262 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
263 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
264 dc
->sar_5bit
= false;
265 dc
->sar_m32_5bit
= true;
269 static void gen_advance_ccount(DisasContext
*dc
)
271 if (dc
->ccount_delta
> 0) {
272 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
273 dc
->ccount_delta
= 0;
274 gen_helper_advance_ccount(cpu_env
, tmp
);
279 static void reset_used_window(DisasContext
*dc
)
284 static void gen_exception(DisasContext
*dc
, int excp
)
286 TCGv_i32 tmp
= tcg_const_i32(excp
);
287 gen_advance_ccount(dc
);
288 gen_helper_exception(cpu_env
, tmp
);
292 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
294 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
295 TCGv_i32 tcause
= tcg_const_i32(cause
);
296 gen_advance_ccount(dc
);
297 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
299 tcg_temp_free(tcause
);
300 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
301 cause
== SYSCALL_CAUSE
) {
302 dc
->is_jmp
= DISAS_UPDATE
;
306 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
309 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
310 TCGv_i32 tcause
= tcg_const_i32(cause
);
311 gen_advance_ccount(dc
);
312 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
314 tcg_temp_free(tcause
);
317 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
319 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
320 TCGv_i32 tcause
= tcg_const_i32(cause
);
321 gen_advance_ccount(dc
);
322 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
324 tcg_temp_free(tcause
);
325 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
326 dc
->is_jmp
= DISAS_UPDATE
;
330 static void gen_check_privilege(DisasContext
*dc
)
333 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
334 dc
->is_jmp
= DISAS_UPDATE
;
338 static void gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
340 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
341 !(dc
->cpenable
& (1 << cp
))) {
342 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
343 dc
->is_jmp
= DISAS_UPDATE
;
347 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
349 tcg_gen_mov_i32(cpu_pc
, dest
);
350 gen_advance_ccount(dc
);
352 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
354 if (dc
->singlestep_enabled
) {
355 gen_exception(dc
, EXCP_DEBUG
);
358 tcg_gen_goto_tb(slot
);
359 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
364 dc
->is_jmp
= DISAS_UPDATE
;
367 static void gen_jump(DisasContext
*dc
, TCGv dest
)
369 gen_jump_slot(dc
, dest
, -1);
372 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
374 TCGv_i32 tmp
= tcg_const_i32(dest
);
375 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
378 gen_jump_slot(dc
, tmp
, slot
);
382 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
385 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
387 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
388 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
389 tcg_temp_free(tcallinc
);
390 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
391 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
392 gen_jump_slot(dc
, dest
, slot
);
395 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
397 gen_callw_slot(dc
, callinc
, dest
, -1);
400 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
402 TCGv_i32 tmp
= tcg_const_i32(dest
);
403 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
406 gen_callw_slot(dc
, callinc
, tmp
, slot
);
410 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
412 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
413 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
414 dc
->next_pc
== dc
->lend
) {
415 int label
= gen_new_label();
417 gen_advance_ccount(dc
);
418 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
419 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
420 gen_jumpi(dc
, dc
->lbeg
, slot
);
421 gen_set_label(label
);
422 gen_jumpi(dc
, dc
->next_pc
, -1);
428 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
430 if (!gen_check_loop_end(dc
, slot
)) {
431 gen_jumpi(dc
, dc
->next_pc
, slot
);
435 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
436 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
438 int label
= gen_new_label();
440 gen_advance_ccount(dc
);
441 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
442 gen_jumpi_check_loop_end(dc
, 0);
443 gen_set_label(label
);
444 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
447 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
448 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
450 TCGv_i32 tmp
= tcg_const_i32(t1
);
451 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
455 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
457 gen_advance_ccount(dc
);
458 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
461 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
463 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
464 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
465 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
468 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
470 static void (* const rsr_handler
[256])(DisasContext
*dc
,
471 TCGv_i32 d
, uint32_t sr
) = {
472 [CCOUNT
] = gen_rsr_ccount
,
473 [PTEVADDR
] = gen_rsr_ptevaddr
,
477 if (rsr_handler
[sr
]) {
478 rsr_handler
[sr
](dc
, d
, sr
);
480 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
483 qemu_log("RSR %d not implemented, ", sr
);
487 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
489 gen_helper_wsr_lbeg(cpu_env
, s
);
490 gen_jumpi_check_loop_end(dc
, 0);
493 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
495 gen_helper_wsr_lend(cpu_env
, s
);
496 gen_jumpi_check_loop_end(dc
, 0);
499 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
501 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
502 if (dc
->sar_m32_5bit
) {
503 tcg_gen_discard_i32(dc
->sar_m32
);
505 dc
->sar_5bit
= false;
506 dc
->sar_m32_5bit
= false;
509 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
511 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
514 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
516 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
517 /* This can change tb->flags, so exit tb */
518 gen_jumpi_check_loop_end(dc
, -1);
521 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
523 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
526 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
528 gen_helper_wsr_windowbase(cpu_env
, v
);
529 reset_used_window(dc
);
532 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
534 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
535 reset_used_window(dc
);
538 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
540 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
543 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
545 gen_helper_wsr_rasid(cpu_env
, v
);
546 /* This can change tb->flags, so exit tb */
547 gen_jumpi_check_loop_end(dc
, -1);
550 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
552 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
555 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
557 gen_helper_wsr_ibreakenable(cpu_env
, v
);
558 gen_jumpi_check_loop_end(dc
, 0);
561 static void gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
563 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
566 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
568 unsigned id
= sr
- IBREAKA
;
570 if (id
< dc
->config
->nibreak
) {
571 TCGv_i32 tmp
= tcg_const_i32(id
);
572 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
574 gen_jumpi_check_loop_end(dc
, 0);
578 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
580 unsigned id
= sr
- DBREAKA
;
582 if (id
< dc
->config
->ndbreak
) {
583 TCGv_i32 tmp
= tcg_const_i32(id
);
584 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
589 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
591 unsigned id
= sr
- DBREAKC
;
593 if (id
< dc
->config
->ndbreak
) {
594 TCGv_i32 tmp
= tcg_const_i32(id
);
595 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
600 static void gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
602 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
603 /* This can change tb->flags, so exit tb */
604 gen_jumpi_check_loop_end(dc
, -1);
607 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
609 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
610 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
611 gen_helper_check_interrupts(cpu_env
);
612 gen_jumpi_check_loop_end(dc
, 0);
615 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
617 TCGv_i32 tmp
= tcg_temp_new_i32();
619 tcg_gen_andi_i32(tmp
, v
,
620 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
621 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
622 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
623 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
625 gen_helper_check_interrupts(cpu_env
);
628 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
630 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
631 gen_helper_check_interrupts(cpu_env
);
632 gen_jumpi_check_loop_end(dc
, 0);
635 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
637 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
638 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
640 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
643 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
644 reset_used_window(dc
);
645 gen_helper_check_interrupts(cpu_env
);
646 /* This can change mmu index and tb->flags, so exit tb */
647 gen_jumpi_check_loop_end(dc
, -1);
650 static void gen_wsr_debugcause(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
654 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
658 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
661 tcg_gen_mov_i32(dc
->next_icount
, v
);
663 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
667 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
669 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
670 /* This can change tb->flags, so exit tb */
671 gen_jumpi_check_loop_end(dc
, -1);
674 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
676 uint32_t id
= sr
- CCOMPARE
;
677 if (id
< dc
->config
->nccompare
) {
678 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
679 gen_advance_ccount(dc
);
680 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
681 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
682 gen_helper_check_interrupts(cpu_env
);
686 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
688 static void (* const wsr_handler
[256])(DisasContext
*dc
,
689 uint32_t sr
, TCGv_i32 v
) = {
690 [LBEG
] = gen_wsr_lbeg
,
691 [LEND
] = gen_wsr_lend
,
694 [LITBASE
] = gen_wsr_litbase
,
695 [ACCHI
] = gen_wsr_acchi
,
696 [WINDOW_BASE
] = gen_wsr_windowbase
,
697 [WINDOW_START
] = gen_wsr_windowstart
,
698 [PTEVADDR
] = gen_wsr_ptevaddr
,
699 [RASID
] = gen_wsr_rasid
,
700 [ITLBCFG
] = gen_wsr_tlbcfg
,
701 [DTLBCFG
] = gen_wsr_tlbcfg
,
702 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
703 [ATOMCTL
] = gen_wsr_atomctl
,
704 [IBREAKA
] = gen_wsr_ibreaka
,
705 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
706 [DBREAKA
] = gen_wsr_dbreaka
,
707 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
708 [DBREAKC
] = gen_wsr_dbreakc
,
709 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
710 [CPENABLE
] = gen_wsr_cpenable
,
711 [INTSET
] = gen_wsr_intset
,
712 [INTCLEAR
] = gen_wsr_intclear
,
713 [INTENABLE
] = gen_wsr_intenable
,
715 [DEBUGCAUSE
] = gen_wsr_debugcause
,
716 [PRID
] = gen_wsr_prid
,
717 [ICOUNT
] = gen_wsr_icount
,
718 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
719 [CCOMPARE
] = gen_wsr_ccompare
,
720 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
721 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
725 if (wsr_handler
[sr
]) {
726 wsr_handler
[sr
](dc
, sr
, s
);
728 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
731 qemu_log("WSR %d not implemented, ", sr
);
735 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
739 gen_helper_wur_fcr(cpu_env
, s
);
743 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
747 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
752 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
753 TCGv_i32 addr
, bool no_hw_alignment
)
755 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
756 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
757 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
759 int label
= gen_new_label();
760 TCGv_i32 tmp
= tcg_temp_new_i32();
761 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
762 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
763 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
764 gen_set_label(label
);
769 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
771 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
772 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
773 gen_advance_ccount(dc
);
774 gen_helper_waiti(cpu_env
, pc
, intlevel
);
776 tcg_temp_free(intlevel
);
779 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
781 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
784 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
785 r1
/ 4 > dc
->used_window
) {
786 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
787 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
789 dc
->used_window
= r1
/ 4;
790 gen_advance_ccount(dc
);
791 gen_helper_window_check(cpu_env
, pc
, w
);
798 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
800 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
803 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
806 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
809 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
811 TCGv_i32 m
= tcg_temp_new_i32();
814 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
816 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
821 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
823 #define HAS_OPTION_BITS(opt) do { \
824 if (!option_bits_enabled(dc, opt)) { \
825 qemu_log("Option is not enabled %s:%d\n", \
826 __FILE__, __LINE__); \
827 goto invalid_opcode; \
831 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
833 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
834 #define RESERVED() do { \
835 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
836 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
837 goto invalid_opcode; \
841 #ifdef TARGET_WORDS_BIGENDIAN
842 #define OP0 (((b0) & 0xf0) >> 4)
843 #define OP1 (((b2) & 0xf0) >> 4)
844 #define OP2 ((b2) & 0xf)
845 #define RRR_R ((b1) & 0xf)
846 #define RRR_S (((b1) & 0xf0) >> 4)
847 #define RRR_T ((b0) & 0xf)
849 #define OP0 (((b0) & 0xf))
850 #define OP1 (((b2) & 0xf))
851 #define OP2 (((b2) & 0xf0) >> 4)
852 #define RRR_R (((b1) & 0xf0) >> 4)
853 #define RRR_S (((b1) & 0xf))
854 #define RRR_T (((b0) & 0xf0) >> 4)
856 #define RRR_X ((RRR_R & 0x4) >> 2)
857 #define RRR_Y ((RRR_T & 0x4) >> 2)
858 #define RRR_W (RRR_R & 0x3)
867 #define RRI8_IMM8 (b2)
868 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
870 #ifdef TARGET_WORDS_BIGENDIAN
871 #define RI16_IMM16 (((b1) << 8) | (b2))
873 #define RI16_IMM16 (((b2) << 8) | (b1))
876 #ifdef TARGET_WORDS_BIGENDIAN
877 #define CALL_N (((b0) & 0xc) >> 2)
878 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
880 #define CALL_N (((b0) & 0x30) >> 4)
881 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
883 #define CALL_OFFSET_SE \
884 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
886 #define CALLX_N CALL_N
887 #ifdef TARGET_WORDS_BIGENDIAN
888 #define CALLX_M ((b0) & 0x3)
890 #define CALLX_M (((b0) & 0xc0) >> 6)
892 #define CALLX_S RRR_S
894 #define BRI12_M CALLX_M
895 #define BRI12_S RRR_S
896 #ifdef TARGET_WORDS_BIGENDIAN
897 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
899 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
901 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
903 #define BRI8_M BRI12_M
904 #define BRI8_R RRI8_R
905 #define BRI8_S RRI8_S
906 #define BRI8_IMM8 RRI8_IMM8
907 #define BRI8_IMM8_SE RRI8_IMM8_SE
911 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
912 uint8_t b1
= cpu_ldub_code(env
, dc
->pc
+ 1);
915 static const uint32_t B4CONST
[] = {
916 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
919 static const uint32_t B4CONSTU
[] = {
920 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
924 dc
->next_pc
= dc
->pc
+ 2;
925 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
927 dc
->next_pc
= dc
->pc
+ 3;
928 b2
= cpu_ldub_code(env
, dc
->pc
+ 2);
937 if ((RRR_R
& 0xc) == 0x8) {
938 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
945 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
956 gen_window_check1(dc
, CALLX_S
);
957 gen_jump(dc
, cpu_R
[CALLX_S
]);
961 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
963 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
964 gen_advance_ccount(dc
);
965 gen_helper_retw(tmp
, cpu_env
, tmp
);
978 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
982 TCGv_i32 tmp
= tcg_temp_new_i32();
983 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
984 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
993 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
995 TCGv_i32 tmp
= tcg_temp_new_i32();
997 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
998 gen_callw(dc
, CALLX_N
, tmp
);
1008 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1009 gen_window_check2(dc
, RRR_T
, RRR_S
);
1011 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1012 gen_advance_ccount(dc
);
1013 gen_helper_movsp(cpu_env
, pc
);
1014 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1034 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1046 default: /*reserved*/
1055 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1058 gen_check_privilege(dc
);
1059 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1060 gen_helper_check_interrupts(cpu_env
);
1061 gen_jump(dc
, cpu_SR
[EPC1
]);
1069 gen_check_privilege(dc
);
1070 gen_jump(dc
, cpu_SR
[
1071 dc
->config
->ndepc
? DEPC
: EPC1
]);
1076 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1077 gen_check_privilege(dc
);
1079 TCGv_i32 tmp
= tcg_const_i32(1);
1082 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1083 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1086 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1087 cpu_SR
[WINDOW_START
], tmp
);
1089 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1090 cpu_SR
[WINDOW_START
], tmp
);
1093 gen_helper_restore_owb(cpu_env
);
1094 gen_helper_check_interrupts(cpu_env
);
1095 gen_jump(dc
, cpu_SR
[EPC1
]);
1101 default: /*reserved*/
1108 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1109 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1110 gen_check_privilege(dc
);
1111 tcg_gen_mov_i32(cpu_SR
[PS
],
1112 cpu_SR
[EPS2
+ RRR_S
- 2]);
1113 gen_helper_check_interrupts(cpu_env
);
1114 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1116 qemu_log("RFI %d is illegal\n", RRR_S
);
1117 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1125 default: /*reserved*/
1133 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1135 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1139 case 5: /*SYSCALLx*/
1140 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1142 case 0: /*SYSCALLx*/
1143 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1147 if (semihosting_enabled
) {
1148 gen_check_privilege(dc
);
1149 gen_helper_simcall(cpu_env
);
1151 qemu_log("SIMCALL but semihosting is disabled\n");
1152 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1163 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1164 gen_check_privilege(dc
);
1165 gen_window_check1(dc
, RRR_T
);
1166 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1167 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1168 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1169 gen_helper_check_interrupts(cpu_env
);
1170 gen_jumpi_check_loop_end(dc
, 0);
1174 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1175 gen_check_privilege(dc
);
1176 gen_waiti(dc
, RRR_S
);
1183 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1185 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1186 TCGv_i32 mask
= tcg_const_i32(
1187 ((1 << shift
) - 1) << RRR_S
);
1188 TCGv_i32 tmp
= tcg_temp_new_i32();
1190 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1191 if (RRR_R
& 1) { /*ALL*/
1192 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1194 tcg_gen_add_i32(tmp
, tmp
, mask
);
1196 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1197 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1199 tcg_temp_free(mask
);
1204 default: /*reserved*/
1212 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1213 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1217 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1218 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1222 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1223 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1229 gen_window_check1(dc
, RRR_S
);
1230 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1234 gen_window_check1(dc
, RRR_S
);
1235 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1239 gen_window_check1(dc
, RRR_S
);
1241 TCGv_i32 tmp
= tcg_temp_new_i32();
1242 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1243 gen_right_shift_sar(dc
, tmp
);
1249 gen_window_check1(dc
, RRR_S
);
1251 TCGv_i32 tmp
= tcg_temp_new_i32();
1252 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1253 gen_left_shift_sar(dc
, tmp
);
1260 TCGv_i32 tmp
= tcg_const_i32(
1261 RRR_S
| ((RRR_T
& 1) << 4));
1262 gen_right_shift_sar(dc
, tmp
);
1276 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1277 gen_check_privilege(dc
);
1279 TCGv_i32 tmp
= tcg_const_i32(
1280 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1281 gen_helper_rotw(cpu_env
, tmp
);
1283 reset_used_window(dc
);
1288 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1289 gen_window_check2(dc
, RRR_S
, RRR_T
);
1290 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1294 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1295 gen_window_check2(dc
, RRR_S
, RRR_T
);
1296 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1299 default: /*reserved*/
1307 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1308 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1309 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1310 gen_check_privilege(dc
);
1311 gen_window_check2(dc
, RRR_S
, RRR_T
);
1313 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1315 switch (RRR_R
& 7) {
1316 case 3: /*RITLB0*/ /*RDTLB0*/
1317 gen_helper_rtlb0(cpu_R
[RRR_T
],
1318 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1321 case 4: /*IITLB*/ /*IDTLB*/
1322 gen_helper_itlb(cpu_env
, cpu_R
[RRR_S
], dtlb
);
1323 /* This could change memory mapping, so exit tb */
1324 gen_jumpi_check_loop_end(dc
, -1);
1327 case 5: /*PITLB*/ /*PDTLB*/
1328 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1329 gen_helper_ptlb(cpu_R
[RRR_T
],
1330 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1333 case 6: /*WITLB*/ /*WDTLB*/
1335 cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1336 /* This could change memory mapping, so exit tb */
1337 gen_jumpi_check_loop_end(dc
, -1);
1340 case 7: /*RITLB1*/ /*RDTLB1*/
1341 gen_helper_rtlb1(cpu_R
[RRR_T
],
1342 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1346 tcg_temp_free(dtlb
);
1350 tcg_temp_free(dtlb
);
1355 gen_window_check2(dc
, RRR_R
, RRR_T
);
1358 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1363 int label
= gen_new_label();
1364 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1365 tcg_gen_brcondi_i32(
1366 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1367 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1368 gen_set_label(label
);
1372 default: /*reserved*/
1378 case 7: /*reserved*/
1383 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1384 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1390 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1392 TCGv_i32 tmp
= tcg_temp_new_i32();
1393 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1394 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1400 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1401 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1407 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1409 TCGv_i32 tmp
= tcg_temp_new_i32();
1410 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1411 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1422 gen_window_check2(dc
, RRR_R
, RRR_S
);
1423 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1424 32 - (RRR_T
| ((OP2
& 1) << 4)));
1429 gen_window_check2(dc
, RRR_R
, RRR_T
);
1430 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1431 RRR_S
| ((OP2
& 1) << 4));
1435 gen_window_check2(dc
, RRR_R
, RRR_T
);
1436 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1441 TCGv_i32 tmp
= tcg_temp_new_i32();
1443 gen_check_privilege(dc
);
1445 gen_window_check1(dc
, RRR_T
);
1446 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1447 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1448 gen_wsr(dc
, RSR_SR
, tmp
);
1450 if (!sregnames
[RSR_SR
]) {
1457 * Note: 64 bit ops are used here solely because SAR values
1460 #define gen_shift_reg(cmd, reg) do { \
1461 TCGv_i64 tmp = tcg_temp_new_i64(); \
1462 tcg_gen_extu_i32_i64(tmp, reg); \
1463 tcg_gen_##cmd##_i64(v, v, tmp); \
1464 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1465 tcg_temp_free_i64(v); \
1466 tcg_temp_free_i64(tmp); \
1469 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1472 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1474 TCGv_i64 v
= tcg_temp_new_i64();
1475 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1481 gen_window_check2(dc
, RRR_R
, RRR_T
);
1483 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1485 TCGv_i64 v
= tcg_temp_new_i64();
1486 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1492 gen_window_check2(dc
, RRR_R
, RRR_S
);
1493 if (dc
->sar_m32_5bit
) {
1494 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1496 TCGv_i64 v
= tcg_temp_new_i64();
1497 TCGv_i32 s
= tcg_const_i32(32);
1498 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1499 tcg_gen_andi_i32(s
, s
, 0x3f);
1500 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1501 gen_shift_reg(shl
, s
);
1507 gen_window_check2(dc
, RRR_R
, RRR_T
);
1509 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1511 TCGv_i64 v
= tcg_temp_new_i64();
1512 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1517 #undef gen_shift_reg
1520 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1521 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1523 TCGv_i32 v1
= tcg_temp_new_i32();
1524 TCGv_i32 v2
= tcg_temp_new_i32();
1525 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1526 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1527 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1534 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1535 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1537 TCGv_i32 v1
= tcg_temp_new_i32();
1538 TCGv_i32 v2
= tcg_temp_new_i32();
1539 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1540 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1541 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1547 default: /*reserved*/
1555 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1559 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1560 int label
= gen_new_label();
1561 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1562 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1563 gen_set_label(label
);
1567 #define BOOLEAN_LOGIC(fn, r, s, t) \
1569 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1570 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1571 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1573 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1574 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1575 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1576 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1577 tcg_temp_free(tmp1); \
1578 tcg_temp_free(tmp2); \
1582 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1586 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1590 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1594 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1598 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1601 #undef BOOLEAN_LOGIC
1604 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1605 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1610 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1612 TCGv_i64 r
= tcg_temp_new_i64();
1613 TCGv_i64 s
= tcg_temp_new_i64();
1614 TCGv_i64 t
= tcg_temp_new_i64();
1617 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1618 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1620 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1621 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1623 tcg_gen_mul_i64(r
, s
, t
);
1624 tcg_gen_shri_i64(r
, r
, 32);
1625 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1627 tcg_temp_free_i64(r
);
1628 tcg_temp_free_i64(s
);
1629 tcg_temp_free_i64(t
);
1634 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1640 int label1
= gen_new_label();
1641 int label2
= gen_new_label();
1643 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1645 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1647 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1648 OP2
== 13 ? 0x80000000 : 0);
1650 gen_set_label(label1
);
1652 tcg_gen_div_i32(cpu_R
[RRR_R
],
1653 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1655 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1656 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1658 gen_set_label(label2
);
1663 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1666 default: /*reserved*/
1676 gen_check_privilege(dc
);
1678 gen_window_check1(dc
, RRR_T
);
1679 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1680 if (!sregnames
[RSR_SR
]) {
1687 gen_check_privilege(dc
);
1689 gen_window_check1(dc
, RRR_T
);
1690 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1691 if (!sregnames
[RSR_SR
]) {
1697 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1698 gen_window_check2(dc
, RRR_R
, RRR_S
);
1700 int shift
= 24 - RRR_T
;
1703 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1704 } else if (shift
== 16) {
1705 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1707 TCGv_i32 tmp
= tcg_temp_new_i32();
1708 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1709 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1716 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1717 gen_window_check2(dc
, RRR_R
, RRR_S
);
1719 TCGv_i32 tmp1
= tcg_temp_new_i32();
1720 TCGv_i32 tmp2
= tcg_temp_new_i32();
1721 int label
= gen_new_label();
1723 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1724 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1725 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1726 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1727 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1729 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1730 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1731 0xffffffff >> (25 - RRR_T
));
1733 gen_set_label(label
);
1735 tcg_temp_free(tmp1
);
1736 tcg_temp_free(tmp2
);
1744 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1745 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1747 static const TCGCond cond
[] = {
1753 int label
= gen_new_label();
1755 if (RRR_R
!= RRR_T
) {
1756 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1757 tcg_gen_brcond_i32(cond
[OP2
- 4],
1758 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1759 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1761 tcg_gen_brcond_i32(cond
[OP2
- 4],
1762 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1763 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1765 gen_set_label(label
);
1773 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1775 static const TCGCond cond
[] = {
1781 int label
= gen_new_label();
1782 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1783 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1784 gen_set_label(label
);
1790 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1791 gen_window_check2(dc
, RRR_R
, RRR_S
);
1793 int label
= gen_new_label();
1794 TCGv_i32 tmp
= tcg_temp_new_i32();
1796 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1797 tcg_gen_brcondi_i32(
1798 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1800 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1801 gen_set_label(label
);
1807 gen_window_check1(dc
, RRR_R
);
1809 int st
= (RRR_S
<< 4) + RRR_T
;
1810 if (uregnames
[st
]) {
1811 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1813 qemu_log("RUR %d not implemented, ", st
);
1820 gen_window_check1(dc
, RRR_T
);
1821 if (uregnames
[RSR_SR
]) {
1822 gen_wur(RSR_SR
, cpu_R
[RRR_T
]);
1824 qemu_log("WUR %d not implemented, ", RSR_SR
);
1834 gen_window_check2(dc
, RRR_R
, RRR_T
);
1836 int shiftimm
= RRR_S
| ((OP1
& 1) << 4);
1837 int maskimm
= (1 << (OP2
+ 1)) - 1;
1839 TCGv_i32 tmp
= tcg_temp_new_i32();
1840 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1841 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1860 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1861 gen_window_check2(dc
, RRR_S
, RRR_T
);
1862 gen_check_cpenable(dc
, 0);
1864 TCGv_i32 addr
= tcg_temp_new_i32();
1865 tcg_gen_add_i32(addr
, cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1866 gen_load_store_alignment(dc
, 2, addr
, false);
1868 tcg_gen_qemu_st32(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1870 tcg_gen_qemu_ld32u(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1873 tcg_gen_mov_i32(cpu_R
[RRR_S
], addr
);
1875 tcg_temp_free(addr
);
1879 default: /*reserved*/
1886 gen_window_check2(dc
, RRR_S
, RRR_T
);
1889 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1890 gen_check_privilege(dc
);
1892 TCGv_i32 addr
= tcg_temp_new_i32();
1893 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1894 (0xffffffc0 | (RRR_R
<< 2)));
1895 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1896 tcg_temp_free(addr
);
1901 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1902 gen_check_privilege(dc
);
1904 TCGv_i32 addr
= tcg_temp_new_i32();
1905 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1906 (0xffffffc0 | (RRR_R
<< 2)));
1907 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1908 tcg_temp_free(addr
);
1919 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1922 gen_check_cpenable(dc
, 0);
1923 gen_helper_add_s(cpu_FR
[RRR_R
], cpu_env
,
1924 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1928 gen_check_cpenable(dc
, 0);
1929 gen_helper_sub_s(cpu_FR
[RRR_R
], cpu_env
,
1930 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1934 gen_check_cpenable(dc
, 0);
1935 gen_helper_mul_s(cpu_FR
[RRR_R
], cpu_env
,
1936 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1940 gen_check_cpenable(dc
, 0);
1941 gen_helper_madd_s(cpu_FR
[RRR_R
], cpu_env
,
1942 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1946 gen_check_cpenable(dc
, 0);
1947 gen_helper_msub_s(cpu_FR
[RRR_R
], cpu_env
,
1948 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1951 case 8: /*ROUND.Sf*/
1952 case 9: /*TRUNC.Sf*/
1953 case 10: /*FLOOR.Sf*/
1954 case 11: /*CEIL.Sf*/
1955 case 14: /*UTRUNC.Sf*/
1956 gen_window_check1(dc
, RRR_R
);
1957 gen_check_cpenable(dc
, 0);
1959 static const unsigned rounding_mode_const
[] = {
1960 float_round_nearest_even
,
1961 float_round_to_zero
,
1964 [6] = float_round_to_zero
,
1966 TCGv_i32 rounding_mode
= tcg_const_i32(
1967 rounding_mode_const
[OP2
& 7]);
1968 TCGv_i32 scale
= tcg_const_i32(RRR_T
);
1971 gen_helper_ftoui(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1972 rounding_mode
, scale
);
1974 gen_helper_ftoi(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1975 rounding_mode
, scale
);
1978 tcg_temp_free(rounding_mode
);
1979 tcg_temp_free(scale
);
1983 case 12: /*FLOAT.Sf*/
1984 case 13: /*UFLOAT.Sf*/
1985 gen_window_check1(dc
, RRR_S
);
1986 gen_check_cpenable(dc
, 0);
1988 TCGv_i32 scale
= tcg_const_i32(-RRR_T
);
1991 gen_helper_uitof(cpu_FR
[RRR_R
], cpu_env
,
1992 cpu_R
[RRR_S
], scale
);
1994 gen_helper_itof(cpu_FR
[RRR_R
], cpu_env
,
1995 cpu_R
[RRR_S
], scale
);
1997 tcg_temp_free(scale
);
2004 gen_check_cpenable(dc
, 0);
2005 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2009 gen_check_cpenable(dc
, 0);
2010 gen_helper_abs_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2014 gen_window_check1(dc
, RRR_R
);
2015 gen_check_cpenable(dc
, 0);
2016 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_FR
[RRR_S
]);
2020 gen_window_check1(dc
, RRR_S
);
2021 gen_check_cpenable(dc
, 0);
2022 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_R
[RRR_S
]);
2026 gen_check_cpenable(dc
, 0);
2027 gen_helper_neg_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2030 default: /*reserved*/
2036 default: /*reserved*/
2043 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2045 #define gen_compare(rel, br, a, b) \
2047 TCGv_i32 bit = tcg_const_i32(1 << br); \
2049 gen_check_cpenable(dc, 0); \
2050 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2051 tcg_temp_free(bit); \
2056 gen_compare(un_s
, RRR_R
, RRR_S
, RRR_T
);
2060 gen_compare(oeq_s
, RRR_R
, RRR_S
, RRR_T
);
2064 gen_compare(ueq_s
, RRR_R
, RRR_S
, RRR_T
);
2068 gen_compare(olt_s
, RRR_R
, RRR_S
, RRR_T
);
2072 gen_compare(ult_s
, RRR_R
, RRR_S
, RRR_T
);
2076 gen_compare(ole_s
, RRR_R
, RRR_S
, RRR_T
);
2080 gen_compare(ule_s
, RRR_R
, RRR_S
, RRR_T
);
2085 case 8: /*MOVEQZ.Sf*/
2086 case 9: /*MOVNEZ.Sf*/
2087 case 10: /*MOVLTZ.Sf*/
2088 case 11: /*MOVGEZ.Sf*/
2089 gen_window_check1(dc
, RRR_T
);
2090 gen_check_cpenable(dc
, 0);
2092 static const TCGCond cond
[] = {
2098 int label
= gen_new_label();
2099 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
2100 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2101 gen_set_label(label
);
2105 case 12: /*MOVF.Sf*/
2106 case 13: /*MOVT.Sf*/
2107 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2108 gen_check_cpenable(dc
, 0);
2110 int label
= gen_new_label();
2111 TCGv_i32 tmp
= tcg_temp_new_i32();
2113 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
2114 tcg_gen_brcondi_i32(
2115 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
2117 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2118 gen_set_label(label
);
2123 default: /*reserved*/
2129 default: /*reserved*/
2136 gen_window_check1(dc
, RRR_T
);
2138 TCGv_i32 tmp
= tcg_const_i32(
2139 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
2140 0 : ((dc
->pc
+ 3) & ~3)) +
2141 (0xfffc0000 | (RI16_IMM16
<< 2)));
2143 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
2144 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
2146 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
2152 #define gen_load_store(type, shift) do { \
2153 TCGv_i32 addr = tcg_temp_new_i32(); \
2154 gen_window_check2(dc, RRI8_S, RRI8_T); \
2155 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2157 gen_load_store_alignment(dc, shift, addr, false); \
2159 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2160 tcg_temp_free(addr); \
2165 gen_load_store(ld8u
, 0);
2169 gen_load_store(ld16u
, 1);
2173 gen_load_store(ld32u
, 2);
2177 gen_load_store(st8
, 0);
2181 gen_load_store(st16
, 1);
2185 gen_load_store(st32
, 2);
2190 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2221 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2225 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2229 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2233 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2237 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2240 default: /*reserved*/
2248 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2254 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2258 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2262 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2265 default: /*reserved*/
2272 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2276 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2279 default: /*reserved*/
2286 gen_load_store(ld16s
, 1);
2288 #undef gen_load_store
2291 gen_window_check1(dc
, RRI8_T
);
2292 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2293 RRI8_IMM8
| (RRI8_S
<< 8) |
2294 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2297 #define gen_load_store_no_hw_align(type) do { \
2298 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2299 gen_window_check2(dc, RRI8_S, RRI8_T); \
2300 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2301 gen_load_store_alignment(dc, 2, addr, true); \
2302 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2303 tcg_temp_free(addr); \
2307 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2308 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2312 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2313 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2317 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2318 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
2321 case 14: /*S32C1Iy*/
2322 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2323 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2325 int label
= gen_new_label();
2326 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2327 TCGv_i32 addr
= tcg_temp_local_new_i32();
2330 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2331 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2332 gen_load_store_alignment(dc
, 2, addr
, true);
2334 gen_advance_ccount(dc
);
2335 tpc
= tcg_const_i32(dc
->pc
);
2336 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2337 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2338 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2339 cpu_SR
[SCOMPARE1
], label
);
2341 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2343 gen_set_label(label
);
2345 tcg_temp_free(addr
);
2351 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2352 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2354 #undef gen_load_store_no_hw_align
2356 default: /*reserved*/
2368 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2369 gen_window_check1(dc
, RRI8_S
);
2370 gen_check_cpenable(dc
, 0);
2372 TCGv_i32 addr
= tcg_temp_new_i32();
2373 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2374 gen_load_store_alignment(dc
, 2, addr
, false);
2376 tcg_gen_qemu_st32(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2378 tcg_gen_qemu_ld32u(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2381 tcg_gen_mov_i32(cpu_R
[RRI8_S
], addr
);
2383 tcg_temp_free(addr
);
2387 default: /*reserved*/
2394 HAS_OPTION(XTENSA_OPTION_MAC16
);
2403 bool is_m1_sr
= (OP2
& 0x3) == 2;
2404 bool is_m2_sr
= (OP2
& 0xc) == 0;
2405 uint32_t ld_offset
= 0;
2412 case 0: /*MACI?/MACC?*/
2414 ld_offset
= (OP2
& 1) ? -4 : 4;
2416 if (OP2
>= 8) { /*MACI/MACC*/
2417 if (OP1
== 0) { /*LDINC/LDDEC*/
2422 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2427 case 2: /*MACD?/MACA?*/
2428 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2434 if (op
!= MAC16_NONE
) {
2436 gen_window_check1(dc
, RRR_S
);
2439 gen_window_check1(dc
, RRR_T
);
2444 TCGv_i32 vaddr
= tcg_temp_new_i32();
2445 TCGv_i32 mem32
= tcg_temp_new_i32();
2448 gen_window_check1(dc
, RRR_S
);
2449 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2450 gen_load_store_alignment(dc
, 2, vaddr
, false);
2451 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2453 if (op
!= MAC16_NONE
) {
2454 TCGv_i32 m1
= gen_mac16_m(
2455 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2456 OP1
& 1, op
== MAC16_UMUL
);
2457 TCGv_i32 m2
= gen_mac16_m(
2458 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2459 OP1
& 2, op
== MAC16_UMUL
);
2461 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2462 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2463 if (op
== MAC16_UMUL
) {
2464 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2466 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2469 TCGv_i32 res
= tcg_temp_new_i32();
2470 TCGv_i64 res64
= tcg_temp_new_i64();
2471 TCGv_i64 tmp
= tcg_temp_new_i64();
2473 tcg_gen_mul_i32(res
, m1
, m2
);
2474 tcg_gen_ext_i32_i64(res64
, res
);
2475 tcg_gen_concat_i32_i64(tmp
,
2476 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
]);
2477 if (op
== MAC16_MULA
) {
2478 tcg_gen_add_i64(tmp
, tmp
, res64
);
2480 tcg_gen_sub_i64(tmp
, tmp
, res64
);
2482 tcg_gen_trunc_i64_i32(cpu_SR
[ACCLO
], tmp
);
2483 tcg_gen_shri_i64(tmp
, tmp
, 32);
2484 tcg_gen_trunc_i64_i32(cpu_SR
[ACCHI
], tmp
);
2485 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2488 tcg_temp_free_i64(res64
);
2489 tcg_temp_free_i64(tmp
);
2495 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2496 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2498 tcg_temp_free(vaddr
);
2499 tcg_temp_free(mem32
);
2507 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2508 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2514 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2515 gen_window_check1(dc
, CALL_N
<< 2);
2516 gen_callwi(dc
, CALL_N
,
2517 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2525 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2529 gen_window_check1(dc
, BRI12_S
);
2531 static const TCGCond cond
[] = {
2532 TCG_COND_EQ
, /*BEQZ*/
2533 TCG_COND_NE
, /*BNEZ*/
2534 TCG_COND_LT
, /*BLTZ*/
2535 TCG_COND_GE
, /*BGEZ*/
2538 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2539 4 + BRI12_IMM12_SE
);
2544 gen_window_check1(dc
, BRI8_S
);
2546 static const TCGCond cond
[] = {
2547 TCG_COND_EQ
, /*BEQI*/
2548 TCG_COND_NE
, /*BNEI*/
2549 TCG_COND_LT
, /*BLTI*/
2550 TCG_COND_GE
, /*BGEI*/
2553 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2554 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2561 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2563 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2564 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2565 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2566 gen_advance_ccount(dc
);
2567 gen_helper_entry(cpu_env
, pc
, s
, imm
);
2571 reset_used_window(dc
);
2579 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2581 TCGv_i32 tmp
= tcg_temp_new_i32();
2582 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2584 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2585 tmp
, 0, 4 + RRI8_IMM8_SE
);
2592 case 10: /*LOOPGTZ*/
2593 HAS_OPTION(XTENSA_OPTION_LOOP
);
2594 gen_window_check1(dc
, RRI8_S
);
2596 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2597 TCGv_i32 tmp
= tcg_const_i32(lend
);
2599 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2600 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2601 gen_helper_wsr_lend(cpu_env
, tmp
);
2605 int label
= gen_new_label();
2606 tcg_gen_brcondi_i32(
2607 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2608 cpu_R
[RRI8_S
], 0, label
);
2609 gen_jumpi(dc
, lend
, 1);
2610 gen_set_label(label
);
2613 gen_jumpi(dc
, dc
->next_pc
, 0);
2617 default: /*reserved*/
2626 gen_window_check1(dc
, BRI8_S
);
2627 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2628 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2638 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2640 switch (RRI8_R
& 7) {
2641 case 0: /*BNONE*/ /*BANY*/
2642 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2644 TCGv_i32 tmp
= tcg_temp_new_i32();
2645 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2646 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2651 case 1: /*BEQ*/ /*BNE*/
2652 case 2: /*BLT*/ /*BGE*/
2653 case 3: /*BLTU*/ /*BGEU*/
2654 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2656 static const TCGCond cond
[] = {
2662 [11] = TCG_COND_GEU
,
2664 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2669 case 4: /*BALL*/ /*BNALL*/
2670 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2672 TCGv_i32 tmp
= tcg_temp_new_i32();
2673 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2674 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2680 case 5: /*BBC*/ /*BBS*/
2681 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2683 #ifdef TARGET_WORDS_BIGENDIAN
2684 TCGv_i32 bit
= tcg_const_i32(0x80000000);
2686 TCGv_i32 bit
= tcg_const_i32(0x00000001);
2688 TCGv_i32 tmp
= tcg_temp_new_i32();
2689 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2690 #ifdef TARGET_WORDS_BIGENDIAN
2691 tcg_gen_shr_i32(bit
, bit
, tmp
);
2693 tcg_gen_shl_i32(bit
, bit
, tmp
);
2695 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2696 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2702 case 6: /*BBCI*/ /*BBSI*/
2704 gen_window_check1(dc
, RRI8_S
);
2706 TCGv_i32 tmp
= tcg_temp_new_i32();
2707 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2708 #ifdef TARGET_WORDS_BIGENDIAN
2709 0x80000000 >> (((RRI8_R
& 1) << 4) | RRI8_T
));
2711 0x00000001 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2713 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2722 #define gen_narrow_load_store(type) do { \
2723 TCGv_i32 addr = tcg_temp_new_i32(); \
2724 gen_window_check2(dc, RRRN_S, RRRN_T); \
2725 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2726 gen_load_store_alignment(dc, 2, addr, false); \
2727 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2728 tcg_temp_free(addr); \
2732 gen_narrow_load_store(ld32u
);
2736 gen_narrow_load_store(st32
);
2738 #undef gen_narrow_load_store
2741 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2742 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2745 case 11: /*ADDI.Nn*/
2746 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2747 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2751 gen_window_check1(dc
, RRRN_S
);
2752 if (RRRN_T
< 8) { /*MOVI.Nn*/
2753 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2754 RRRN_R
| (RRRN_T
<< 4) |
2755 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2756 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2757 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2759 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2760 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2767 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2768 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2774 gen_jump(dc
, cpu_R
[0]);
2778 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2780 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2781 gen_advance_ccount(dc
);
2782 gen_helper_retw(tmp
, cpu_env
, tmp
);
2788 case 2: /*BREAK.Nn*/
2789 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2791 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2799 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2802 default: /*reserved*/
2808 default: /*reserved*/
2814 default: /*reserved*/
2819 if (dc
->is_jmp
== DISAS_NEXT
) {
2820 gen_check_loop_end(dc
, 0);
2822 dc
->pc
= dc
->next_pc
;
2827 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2828 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2832 static void check_breakpoint(CPUXtensaState
*env
, DisasContext
*dc
)
2836 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2837 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2838 if (bp
->pc
== dc
->pc
) {
2839 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2840 gen_exception(dc
, EXCP_DEBUG
);
2841 dc
->is_jmp
= DISAS_UPDATE
;
2847 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
2851 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
2852 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
2853 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
2854 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
2860 static void gen_intermediate_code_internal(
2861 CPUXtensaState
*env
, TranslationBlock
*tb
, int search_pc
)
2866 uint16_t *gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
2867 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2868 uint32_t pc_start
= tb
->pc
;
2869 uint32_t next_page_start
=
2870 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2872 if (max_insns
== 0) {
2873 max_insns
= CF_COUNT_MASK
;
2876 dc
.config
= env
->config
;
2877 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2880 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2881 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2882 dc
.lbeg
= env
->sregs
[LBEG
];
2883 dc
.lend
= env
->sregs
[LEND
];
2884 dc
.is_jmp
= DISAS_NEXT
;
2885 dc
.ccount_delta
= 0;
2886 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
2887 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
2888 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
2889 XTENSA_TBFLAG_CPENABLE_SHIFT
;
2892 init_sar_tracker(&dc
);
2893 reset_used_window(&dc
);
2895 dc
.next_icount
= tcg_temp_local_new_i32();
2900 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2901 env
->exception_taken
= 0;
2902 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2903 gen_exception(&dc
, EXCP_DEBUG
);
2907 check_breakpoint(env
, &dc
);
2910 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
2914 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
2917 tcg_ctx
.gen_opc_pc
[lj
] = dc
.pc
;
2918 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
2919 tcg_ctx
.gen_opc_icount
[lj
] = insn_count
;
2922 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2923 tcg_gen_debug_insn_start(dc
.pc
);
2928 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2933 int label
= gen_new_label();
2935 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
2936 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
2937 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
2939 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
2941 gen_set_label(label
);
2945 gen_ibreak_check(env
, &dc
);
2948 disas_xtensa_insn(env
, &dc
);
2951 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
2953 if (env
->singlestep_enabled
) {
2954 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2955 gen_exception(&dc
, EXCP_DEBUG
);
2958 } while (dc
.is_jmp
== DISAS_NEXT
&&
2959 insn_count
< max_insns
&&
2960 dc
.pc
< next_page_start
&&
2961 tcg_ctx
.gen_opc_ptr
< gen_opc_end
);
2964 reset_sar_tracker(&dc
);
2966 tcg_temp_free(dc
.next_icount
);
2969 if (tb
->cflags
& CF_LAST_IO
) {
2973 if (dc
.is_jmp
== DISAS_NEXT
) {
2974 gen_jumpi(&dc
, dc
.pc
, 0);
2976 gen_icount_end(tb
, insn_count
);
2977 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
2980 tb
->size
= dc
.pc
- pc_start
;
2981 tb
->icount
= insn_count
;
2985 void gen_intermediate_code(CPUXtensaState
*env
, TranslationBlock
*tb
)
2987 gen_intermediate_code_internal(env
, tb
, 0);
2990 void gen_intermediate_code_pc(CPUXtensaState
*env
, TranslationBlock
*tb
)
2992 gen_intermediate_code_internal(env
, tb
, 1);
2995 void cpu_dump_state(CPUXtensaState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
3000 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
3002 for (i
= j
= 0; i
< 256; ++i
) {
3004 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
3005 (j
++ % 4) == 3 ? '\n' : ' ');
3009 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3011 for (i
= j
= 0; i
< 256; ++i
) {
3013 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
3014 (j
++ % 4) == 3 ? '\n' : ' ');
3018 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3020 for (i
= 0; i
< 16; ++i
) {
3021 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
3022 (i
% 4) == 3 ? '\n' : ' ');
3025 cpu_fprintf(f
, "\n");
3027 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
3028 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
3029 (i
% 4) == 3 ? '\n' : ' ');
3032 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
3033 cpu_fprintf(f
, "\n");
3035 for (i
= 0; i
< 16; ++i
) {
3036 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
3037 float32_val(env
->fregs
[i
]),
3038 *(float *)&env
->fregs
[i
], (i
% 2) == 1 ? '\n' : ' ');
3043 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
, int pc_pos
)
3045 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];