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target-xtensa: implement depbits instruction
[mirror_qemu.git] / target-xtensa / translate.c
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41
42 #include "exec/helper-proto.h"
43 #include "exec/helper-gen.h"
44
45 #include "trace-tcg.h"
46
47
48 typedef struct DisasContext {
49 const XtensaConfig *config;
50 TranslationBlock *tb;
51 uint32_t pc;
52 uint32_t next_pc;
53 int cring;
54 int ring;
55 uint32_t lbeg;
56 uint32_t lend;
57 TCGv_i32 litbase;
58 int is_jmp;
59 int singlestep_enabled;
60
61 bool sar_5bit;
62 bool sar_m32_5bit;
63 bool sar_m32_allocated;
64 TCGv_i32 sar_m32;
65
66 uint32_t ccount_delta;
67 unsigned window;
68
69 bool debug;
70 bool icount;
71 TCGv_i32 next_icount;
72
73 unsigned cpenable;
74 } DisasContext;
75
76 static TCGv_ptr cpu_env;
77 static TCGv_i32 cpu_pc;
78 static TCGv_i32 cpu_R[16];
79 static TCGv_i32 cpu_FR[16];
80 static TCGv_i32 cpu_SR[256];
81 static TCGv_i32 cpu_UR[256];
82
83 #include "exec/gen-icount.h"
84
85 typedef struct XtensaReg {
86 const char *name;
87 uint64_t opt_bits;
88 enum {
89 SR_R = 1,
90 SR_W = 2,
91 SR_X = 4,
92 SR_RW = 3,
93 SR_RWX = 7,
94 } access;
95 } XtensaReg;
96
97 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
98 .name = (regname), \
99 .opt_bits = XTENSA_OPTION_BIT(opt), \
100 .access = (acc), \
101 }
102
103 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
104
105 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
106 .name = (regname), \
107 .opt_bits = (opt), \
108 .access = (acc), \
109 }
110
111 #define XTENSA_REG_BITS(regname, opt) \
112 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
113
114 static const XtensaReg sregnames[256] = {
115 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
116 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
117 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
118 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
119 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
120 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
121 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
122 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
123 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
124 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
125 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
126 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
127 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
128 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
129 [WINDOW_START] = XTENSA_REG("WINDOW_START",
130 XTENSA_OPTION_WINDOWED_REGISTER),
131 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
132 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
133 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
134 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
135 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
136 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
137 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
138 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
139 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
140 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
141 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
142 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
143 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
144 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
145 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
146 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
153 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
159 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
160 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
161 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
162 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
163 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
164 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
165 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
167 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
169 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
171 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
173 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
174 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
175 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
176 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
177 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
178 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
179 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
180 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
181 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
182 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
183 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
184 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
185 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
186 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
187 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
188 XTENSA_OPTION_TIMER_INTERRUPT),
189 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
190 XTENSA_OPTION_TIMER_INTERRUPT),
191 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
192 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
193 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
194 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
195 };
196
197 static const XtensaReg uregnames[256] = {
198 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
199 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
200 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
201 };
202
203 void xtensa_translate_init(void)
204 {
205 static const char * const regnames[] = {
206 "ar0", "ar1", "ar2", "ar3",
207 "ar4", "ar5", "ar6", "ar7",
208 "ar8", "ar9", "ar10", "ar11",
209 "ar12", "ar13", "ar14", "ar15",
210 };
211 static const char * const fregnames[] = {
212 "f0", "f1", "f2", "f3",
213 "f4", "f5", "f6", "f7",
214 "f8", "f9", "f10", "f11",
215 "f12", "f13", "f14", "f15",
216 };
217 int i;
218
219 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
220 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
221 offsetof(CPUXtensaState, pc), "pc");
222
223 for (i = 0; i < 16; i++) {
224 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
225 offsetof(CPUXtensaState, regs[i]),
226 regnames[i]);
227 }
228
229 for (i = 0; i < 16; i++) {
230 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
231 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
232 fregnames[i]);
233 }
234
235 for (i = 0; i < 256; ++i) {
236 if (sregnames[i].name) {
237 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
238 offsetof(CPUXtensaState, sregs[i]),
239 sregnames[i].name);
240 }
241 }
242
243 for (i = 0; i < 256; ++i) {
244 if (uregnames[i].name) {
245 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
246 offsetof(CPUXtensaState, uregs[i]),
247 uregnames[i].name);
248 }
249 }
250 }
251
252 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
253 {
254 return xtensa_option_bits_enabled(dc->config, opt);
255 }
256
257 static inline bool option_enabled(DisasContext *dc, int opt)
258 {
259 return xtensa_option_enabled(dc->config, opt);
260 }
261
262 static void init_litbase(DisasContext *dc)
263 {
264 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
265 dc->litbase = tcg_temp_local_new_i32();
266 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
267 }
268 }
269
270 static void reset_litbase(DisasContext *dc)
271 {
272 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
273 tcg_temp_free(dc->litbase);
274 }
275 }
276
277 static void init_sar_tracker(DisasContext *dc)
278 {
279 dc->sar_5bit = false;
280 dc->sar_m32_5bit = false;
281 dc->sar_m32_allocated = false;
282 }
283
284 static void reset_sar_tracker(DisasContext *dc)
285 {
286 if (dc->sar_m32_allocated) {
287 tcg_temp_free(dc->sar_m32);
288 }
289 }
290
291 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
292 {
293 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
294 if (dc->sar_m32_5bit) {
295 tcg_gen_discard_i32(dc->sar_m32);
296 }
297 dc->sar_5bit = true;
298 dc->sar_m32_5bit = false;
299 }
300
301 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
302 {
303 TCGv_i32 tmp = tcg_const_i32(32);
304 if (!dc->sar_m32_allocated) {
305 dc->sar_m32 = tcg_temp_local_new_i32();
306 dc->sar_m32_allocated = true;
307 }
308 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
309 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
310 dc->sar_5bit = false;
311 dc->sar_m32_5bit = true;
312 tcg_temp_free(tmp);
313 }
314
315 static void gen_advance_ccount(DisasContext *dc)
316 {
317 if (dc->ccount_delta > 0) {
318 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
319 gen_helper_advance_ccount(cpu_env, tmp);
320 tcg_temp_free(tmp);
321 }
322 dc->ccount_delta = 0;
323 }
324
325 static void gen_exception(DisasContext *dc, int excp)
326 {
327 TCGv_i32 tmp = tcg_const_i32(excp);
328 gen_advance_ccount(dc);
329 gen_helper_exception(cpu_env, tmp);
330 tcg_temp_free(tmp);
331 }
332
333 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
334 {
335 TCGv_i32 tpc = tcg_const_i32(dc->pc);
336 TCGv_i32 tcause = tcg_const_i32(cause);
337 gen_advance_ccount(dc);
338 gen_helper_exception_cause(cpu_env, tpc, tcause);
339 tcg_temp_free(tpc);
340 tcg_temp_free(tcause);
341 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
342 cause == SYSCALL_CAUSE) {
343 dc->is_jmp = DISAS_UPDATE;
344 }
345 }
346
347 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
348 TCGv_i32 vaddr)
349 {
350 TCGv_i32 tpc = tcg_const_i32(dc->pc);
351 TCGv_i32 tcause = tcg_const_i32(cause);
352 gen_advance_ccount(dc);
353 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
354 tcg_temp_free(tpc);
355 tcg_temp_free(tcause);
356 }
357
358 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
359 {
360 TCGv_i32 tpc = tcg_const_i32(dc->pc);
361 TCGv_i32 tcause = tcg_const_i32(cause);
362 gen_advance_ccount(dc);
363 gen_helper_debug_exception(cpu_env, tpc, tcause);
364 tcg_temp_free(tpc);
365 tcg_temp_free(tcause);
366 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
367 dc->is_jmp = DISAS_UPDATE;
368 }
369 }
370
371 static bool gen_check_privilege(DisasContext *dc)
372 {
373 if (dc->cring) {
374 gen_exception_cause(dc, PRIVILEGED_CAUSE);
375 dc->is_jmp = DISAS_UPDATE;
376 return false;
377 }
378 return true;
379 }
380
381 static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
382 {
383 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
384 !(dc->cpenable & (1 << cp))) {
385 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
386 dc->is_jmp = DISAS_UPDATE;
387 return false;
388 }
389 return true;
390 }
391
392 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
393 {
394 tcg_gen_mov_i32(cpu_pc, dest);
395 gen_advance_ccount(dc);
396 if (dc->icount) {
397 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
398 }
399 if (dc->singlestep_enabled) {
400 gen_exception(dc, EXCP_DEBUG);
401 } else {
402 if (slot >= 0) {
403 tcg_gen_goto_tb(slot);
404 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
405 } else {
406 tcg_gen_exit_tb(0);
407 }
408 }
409 dc->is_jmp = DISAS_UPDATE;
410 }
411
412 static void gen_jump(DisasContext *dc, TCGv dest)
413 {
414 gen_jump_slot(dc, dest, -1);
415 }
416
417 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
418 {
419 TCGv_i32 tmp = tcg_const_i32(dest);
420 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
421 slot = -1;
422 }
423 gen_jump_slot(dc, tmp, slot);
424 tcg_temp_free(tmp);
425 }
426
427 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
428 int slot)
429 {
430 TCGv_i32 tcallinc = tcg_const_i32(callinc);
431
432 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
433 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
434 tcg_temp_free(tcallinc);
435 tcg_gen_movi_i32(cpu_R[callinc << 2],
436 (callinc << 30) | (dc->next_pc & 0x3fffffff));
437 gen_jump_slot(dc, dest, slot);
438 }
439
440 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
441 {
442 gen_callw_slot(dc, callinc, dest, -1);
443 }
444
445 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
446 {
447 TCGv_i32 tmp = tcg_const_i32(dest);
448 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
449 slot = -1;
450 }
451 gen_callw_slot(dc, callinc, tmp, slot);
452 tcg_temp_free(tmp);
453 }
454
455 static bool gen_check_loop_end(DisasContext *dc, int slot)
456 {
457 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
458 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
459 dc->next_pc == dc->lend) {
460 TCGLabel *label = gen_new_label();
461
462 gen_advance_ccount(dc);
463 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
464 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
465 gen_jumpi(dc, dc->lbeg, slot);
466 gen_set_label(label);
467 gen_jumpi(dc, dc->next_pc, -1);
468 return true;
469 }
470 return false;
471 }
472
473 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
474 {
475 if (!gen_check_loop_end(dc, slot)) {
476 gen_jumpi(dc, dc->next_pc, slot);
477 }
478 }
479
480 static void gen_brcond(DisasContext *dc, TCGCond cond,
481 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
482 {
483 TCGLabel *label = gen_new_label();
484
485 gen_advance_ccount(dc);
486 tcg_gen_brcond_i32(cond, t0, t1, label);
487 gen_jumpi_check_loop_end(dc, 0);
488 gen_set_label(label);
489 gen_jumpi(dc, dc->pc + offset, 1);
490 }
491
492 static void gen_brcondi(DisasContext *dc, TCGCond cond,
493 TCGv_i32 t0, uint32_t t1, uint32_t offset)
494 {
495 TCGv_i32 tmp = tcg_const_i32(t1);
496 gen_brcond(dc, cond, t0, tmp, offset);
497 tcg_temp_free(tmp);
498 }
499
500 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
501 {
502 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
503 if (sregnames[sr].name) {
504 qemu_log("SR %s is not configured\n", sregnames[sr].name);
505 } else {
506 qemu_log("SR %d is not implemented\n", sr);
507 }
508 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
509 return false;
510 } else if (!(sregnames[sr].access & access)) {
511 static const char * const access_text[] = {
512 [SR_R] = "rsr",
513 [SR_W] = "wsr",
514 [SR_X] = "xsr",
515 };
516 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
517 qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
518 access_text[access]);
519 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
520 return false;
521 }
522 return true;
523 }
524
525 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
526 {
527 gen_advance_ccount(dc);
528 tcg_gen_mov_i32(d, cpu_SR[sr]);
529 }
530
531 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
532 {
533 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
534 tcg_gen_or_i32(d, d, cpu_SR[sr]);
535 tcg_gen_andi_i32(d, d, 0xfffffffc);
536 }
537
538 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
539 {
540 static void (* const rsr_handler[256])(DisasContext *dc,
541 TCGv_i32 d, uint32_t sr) = {
542 [CCOUNT] = gen_rsr_ccount,
543 [PTEVADDR] = gen_rsr_ptevaddr,
544 };
545
546 if (rsr_handler[sr]) {
547 rsr_handler[sr](dc, d, sr);
548 } else {
549 tcg_gen_mov_i32(d, cpu_SR[sr]);
550 }
551 }
552
553 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
554 {
555 gen_helper_wsr_lbeg(cpu_env, s);
556 gen_jumpi_check_loop_end(dc, 0);
557 }
558
559 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
560 {
561 gen_helper_wsr_lend(cpu_env, s);
562 gen_jumpi_check_loop_end(dc, 0);
563 }
564
565 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
566 {
567 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
568 if (dc->sar_m32_5bit) {
569 tcg_gen_discard_i32(dc->sar_m32);
570 }
571 dc->sar_5bit = false;
572 dc->sar_m32_5bit = false;
573 }
574
575 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
576 {
577 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
578 }
579
580 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
581 {
582 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
583 /* This can change tb->flags, so exit tb */
584 gen_jumpi_check_loop_end(dc, -1);
585 }
586
587 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
588 {
589 tcg_gen_ext8s_i32(cpu_SR[sr], s);
590 }
591
592 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
593 {
594 gen_helper_wsr_windowbase(cpu_env, v);
595 /* This can change tb->flags, so exit tb */
596 gen_jumpi_check_loop_end(dc, -1);
597 }
598
599 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
600 {
601 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc, -1);
604 }
605
606 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
607 {
608 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
609 }
610
611 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
612 {
613 gen_helper_wsr_rasid(cpu_env, v);
614 /* This can change tb->flags, so exit tb */
615 gen_jumpi_check_loop_end(dc, -1);
616 }
617
618 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
619 {
620 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
621 }
622
623 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
624 {
625 gen_helper_wsr_ibreakenable(cpu_env, v);
626 gen_jumpi_check_loop_end(dc, 0);
627 }
628
629 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630 {
631 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
632 }
633
634 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
635 {
636 unsigned id = sr - IBREAKA;
637
638 if (id < dc->config->nibreak) {
639 TCGv_i32 tmp = tcg_const_i32(id);
640 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
641 tcg_temp_free(tmp);
642 gen_jumpi_check_loop_end(dc, 0);
643 }
644 }
645
646 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
647 {
648 unsigned id = sr - DBREAKA;
649
650 if (id < dc->config->ndbreak) {
651 TCGv_i32 tmp = tcg_const_i32(id);
652 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
653 tcg_temp_free(tmp);
654 }
655 }
656
657 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
658 {
659 unsigned id = sr - DBREAKC;
660
661 if (id < dc->config->ndbreak) {
662 TCGv_i32 tmp = tcg_const_i32(id);
663 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
664 tcg_temp_free(tmp);
665 }
666 }
667
668 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
669 {
670 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
671 /* This can change tb->flags, so exit tb */
672 gen_jumpi_check_loop_end(dc, -1);
673 }
674
675 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
676 {
677 tcg_gen_andi_i32(cpu_SR[sr], v,
678 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
679 gen_helper_check_interrupts(cpu_env);
680 gen_jumpi_check_loop_end(dc, 0);
681 }
682
683 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
684 {
685 TCGv_i32 tmp = tcg_temp_new_i32();
686
687 tcg_gen_andi_i32(tmp, v,
688 dc->config->inttype_mask[INTTYPE_EDGE] |
689 dc->config->inttype_mask[INTTYPE_NMI] |
690 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
691 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
692 tcg_temp_free(tmp);
693 gen_helper_check_interrupts(cpu_env);
694 }
695
696 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
697 {
698 tcg_gen_mov_i32(cpu_SR[sr], v);
699 gen_helper_check_interrupts(cpu_env);
700 gen_jumpi_check_loop_end(dc, 0);
701 }
702
703 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
704 {
705 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
706 PS_UM | PS_EXCM | PS_INTLEVEL;
707
708 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
709 mask |= PS_RING;
710 }
711 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
712 gen_helper_check_interrupts(cpu_env);
713 /* This can change mmu index and tb->flags, so exit tb */
714 gen_jumpi_check_loop_end(dc, -1);
715 }
716
717 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
718 {
719 if (dc->icount) {
720 tcg_gen_mov_i32(dc->next_icount, v);
721 } else {
722 tcg_gen_mov_i32(cpu_SR[sr], v);
723 }
724 }
725
726 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
727 {
728 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
729 /* This can change tb->flags, so exit tb */
730 gen_jumpi_check_loop_end(dc, -1);
731 }
732
733 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
734 {
735 uint32_t id = sr - CCOMPARE;
736 if (id < dc->config->nccompare) {
737 uint32_t int_bit = 1 << dc->config->timerint[id];
738 gen_advance_ccount(dc);
739 tcg_gen_mov_i32(cpu_SR[sr], v);
740 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
741 gen_helper_check_interrupts(cpu_env);
742 }
743 }
744
745 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
746 {
747 static void (* const wsr_handler[256])(DisasContext *dc,
748 uint32_t sr, TCGv_i32 v) = {
749 [LBEG] = gen_wsr_lbeg,
750 [LEND] = gen_wsr_lend,
751 [SAR] = gen_wsr_sar,
752 [BR] = gen_wsr_br,
753 [LITBASE] = gen_wsr_litbase,
754 [ACCHI] = gen_wsr_acchi,
755 [WINDOW_BASE] = gen_wsr_windowbase,
756 [WINDOW_START] = gen_wsr_windowstart,
757 [PTEVADDR] = gen_wsr_ptevaddr,
758 [RASID] = gen_wsr_rasid,
759 [ITLBCFG] = gen_wsr_tlbcfg,
760 [DTLBCFG] = gen_wsr_tlbcfg,
761 [IBREAKENABLE] = gen_wsr_ibreakenable,
762 [ATOMCTL] = gen_wsr_atomctl,
763 [IBREAKA] = gen_wsr_ibreaka,
764 [IBREAKA + 1] = gen_wsr_ibreaka,
765 [DBREAKA] = gen_wsr_dbreaka,
766 [DBREAKA + 1] = gen_wsr_dbreaka,
767 [DBREAKC] = gen_wsr_dbreakc,
768 [DBREAKC + 1] = gen_wsr_dbreakc,
769 [CPENABLE] = gen_wsr_cpenable,
770 [INTSET] = gen_wsr_intset,
771 [INTCLEAR] = gen_wsr_intclear,
772 [INTENABLE] = gen_wsr_intenable,
773 [PS] = gen_wsr_ps,
774 [ICOUNT] = gen_wsr_icount,
775 [ICOUNTLEVEL] = gen_wsr_icountlevel,
776 [CCOMPARE] = gen_wsr_ccompare,
777 [CCOMPARE + 1] = gen_wsr_ccompare,
778 [CCOMPARE + 2] = gen_wsr_ccompare,
779 };
780
781 if (wsr_handler[sr]) {
782 wsr_handler[sr](dc, sr, s);
783 } else {
784 tcg_gen_mov_i32(cpu_SR[sr], s);
785 }
786 }
787
788 static void gen_wur(uint32_t ur, TCGv_i32 s)
789 {
790 switch (ur) {
791 case FCR:
792 gen_helper_wur_fcr(cpu_env, s);
793 break;
794
795 case FSR:
796 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
797 break;
798
799 default:
800 tcg_gen_mov_i32(cpu_UR[ur], s);
801 break;
802 }
803 }
804
805 static void gen_load_store_alignment(DisasContext *dc, int shift,
806 TCGv_i32 addr, bool no_hw_alignment)
807 {
808 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
809 tcg_gen_andi_i32(addr, addr, ~0 << shift);
810 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
811 no_hw_alignment) {
812 TCGLabel *label = gen_new_label();
813 TCGv_i32 tmp = tcg_temp_new_i32();
814 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
815 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
816 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
817 gen_set_label(label);
818 tcg_temp_free(tmp);
819 }
820 }
821
822 static void gen_waiti(DisasContext *dc, uint32_t imm4)
823 {
824 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
825 TCGv_i32 intlevel = tcg_const_i32(imm4);
826 gen_advance_ccount(dc);
827 gen_helper_waiti(cpu_env, pc, intlevel);
828 tcg_temp_free(pc);
829 tcg_temp_free(intlevel);
830 }
831
832 static bool gen_window_check1(DisasContext *dc, unsigned r1)
833 {
834 if (r1 / 4 > dc->window) {
835 TCGv_i32 pc = tcg_const_i32(dc->pc);
836 TCGv_i32 w = tcg_const_i32(r1 / 4);
837
838 gen_advance_ccount(dc);
839 gen_helper_window_check(cpu_env, pc, w);
840 dc->is_jmp = DISAS_UPDATE;
841 return false;
842 }
843 return true;
844 }
845
846 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
847 {
848 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
849 }
850
851 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
852 unsigned r3)
853 {
854 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
855 }
856
857 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
858 {
859 TCGv_i32 m = tcg_temp_new_i32();
860
861 if (hi) {
862 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
863 } else {
864 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
865 }
866 return m;
867 }
868
869 static inline unsigned xtensa_op0_insn_len(unsigned op0)
870 {
871 return op0 >= 8 ? 2 : 3;
872 }
873
874 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
875 {
876 #define HAS_OPTION_BITS(opt) do { \
877 if (!option_bits_enabled(dc, opt)) { \
878 qemu_log("Option is not enabled %s:%d\n", \
879 __FILE__, __LINE__); \
880 goto invalid_opcode; \
881 } \
882 } while (0)
883
884 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
885
886 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
887 #define RESERVED() do { \
888 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
889 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
890 goto invalid_opcode; \
891 } while (0)
892
893
894 #ifdef TARGET_WORDS_BIGENDIAN
895 #define OP0 (((b0) & 0xf0) >> 4)
896 #define OP1 (((b2) & 0xf0) >> 4)
897 #define OP2 ((b2) & 0xf)
898 #define RRR_R ((b1) & 0xf)
899 #define RRR_S (((b1) & 0xf0) >> 4)
900 #define RRR_T ((b0) & 0xf)
901 #else
902 #define OP0 (((b0) & 0xf))
903 #define OP1 (((b2) & 0xf))
904 #define OP2 (((b2) & 0xf0) >> 4)
905 #define RRR_R (((b1) & 0xf0) >> 4)
906 #define RRR_S (((b1) & 0xf))
907 #define RRR_T (((b0) & 0xf0) >> 4)
908 #endif
909 #define RRR_X ((RRR_R & 0x4) >> 2)
910 #define RRR_Y ((RRR_T & 0x4) >> 2)
911 #define RRR_W (RRR_R & 0x3)
912
913 #define RRRN_R RRR_R
914 #define RRRN_S RRR_S
915 #define RRRN_T RRR_T
916
917 #define RRI4_R RRR_R
918 #define RRI4_S RRR_S
919 #define RRI4_T RRR_T
920 #ifdef TARGET_WORDS_BIGENDIAN
921 #define RRI4_IMM4 ((b2) & 0xf)
922 #else
923 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
924 #endif
925
926 #define RRI8_R RRR_R
927 #define RRI8_S RRR_S
928 #define RRI8_T RRR_T
929 #define RRI8_IMM8 (b2)
930 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
931
932 #ifdef TARGET_WORDS_BIGENDIAN
933 #define RI16_IMM16 (((b1) << 8) | (b2))
934 #else
935 #define RI16_IMM16 (((b2) << 8) | (b1))
936 #endif
937
938 #ifdef TARGET_WORDS_BIGENDIAN
939 #define CALL_N (((b0) & 0xc) >> 2)
940 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
941 #else
942 #define CALL_N (((b0) & 0x30) >> 4)
943 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
944 #endif
945 #define CALL_OFFSET_SE \
946 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
947
948 #define CALLX_N CALL_N
949 #ifdef TARGET_WORDS_BIGENDIAN
950 #define CALLX_M ((b0) & 0x3)
951 #else
952 #define CALLX_M (((b0) & 0xc0) >> 6)
953 #endif
954 #define CALLX_S RRR_S
955
956 #define BRI12_M CALLX_M
957 #define BRI12_S RRR_S
958 #ifdef TARGET_WORDS_BIGENDIAN
959 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
960 #else
961 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
962 #endif
963 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
964
965 #define BRI8_M BRI12_M
966 #define BRI8_R RRI8_R
967 #define BRI8_S RRI8_S
968 #define BRI8_IMM8 RRI8_IMM8
969 #define BRI8_IMM8_SE RRI8_IMM8_SE
970
971 #define RSR_SR (b1)
972
973 uint8_t b0 = cpu_ldub_code(env, dc->pc);
974 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
975 uint8_t b2 = 0;
976 unsigned len = xtensa_op0_insn_len(OP0);
977
978 static const uint32_t B4CONST[] = {
979 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
980 };
981
982 static const uint32_t B4CONSTU[] = {
983 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
984 };
985
986 switch (len) {
987 case 2:
988 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
989 break;
990
991 case 3:
992 b2 = cpu_ldub_code(env, dc->pc + 2);
993 break;
994
995 default:
996 RESERVED();
997 }
998 dc->next_pc = dc->pc + len;
999
1000 switch (OP0) {
1001 case 0: /*QRST*/
1002 switch (OP1) {
1003 case 0: /*RST0*/
1004 switch (OP2) {
1005 case 0: /*ST0*/
1006 if ((RRR_R & 0xc) == 0x8) {
1007 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1008 }
1009
1010 switch (RRR_R) {
1011 case 0: /*SNM0*/
1012 switch (CALLX_M) {
1013 case 0: /*ILL*/
1014 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1015 break;
1016
1017 case 1: /*reserved*/
1018 RESERVED();
1019 break;
1020
1021 case 2: /*JR*/
1022 switch (CALLX_N) {
1023 case 0: /*RET*/
1024 case 2: /*JX*/
1025 if (gen_window_check1(dc, CALLX_S)) {
1026 gen_jump(dc, cpu_R[CALLX_S]);
1027 }
1028 break;
1029
1030 case 1: /*RETWw*/
1031 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1032 {
1033 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1034 gen_advance_ccount(dc);
1035 gen_helper_retw(tmp, cpu_env, tmp);
1036 gen_jump(dc, tmp);
1037 tcg_temp_free(tmp);
1038 }
1039 break;
1040
1041 case 3: /*reserved*/
1042 RESERVED();
1043 break;
1044 }
1045 break;
1046
1047 case 3: /*CALLX*/
1048 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1049 break;
1050 }
1051 switch (CALLX_N) {
1052 case 0: /*CALLX0*/
1053 {
1054 TCGv_i32 tmp = tcg_temp_new_i32();
1055 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1056 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1057 gen_jump(dc, tmp);
1058 tcg_temp_free(tmp);
1059 }
1060 break;
1061
1062 case 1: /*CALLX4w*/
1063 case 2: /*CALLX8w*/
1064 case 3: /*CALLX12w*/
1065 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1066 {
1067 TCGv_i32 tmp = tcg_temp_new_i32();
1068
1069 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1070 gen_callw(dc, CALLX_N, tmp);
1071 tcg_temp_free(tmp);
1072 }
1073 break;
1074 }
1075 break;
1076 }
1077 break;
1078
1079 case 1: /*MOVSPw*/
1080 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1081 if (gen_window_check2(dc, RRR_T, RRR_S)) {
1082 TCGv_i32 pc = tcg_const_i32(dc->pc);
1083 gen_advance_ccount(dc);
1084 gen_helper_movsp(cpu_env, pc);
1085 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1086 tcg_temp_free(pc);
1087 }
1088 break;
1089
1090 case 2: /*SYNC*/
1091 switch (RRR_T) {
1092 case 0: /*ISYNC*/
1093 break;
1094
1095 case 1: /*RSYNC*/
1096 break;
1097
1098 case 2: /*ESYNC*/
1099 break;
1100
1101 case 3: /*DSYNC*/
1102 break;
1103
1104 case 8: /*EXCW*/
1105 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1106 break;
1107
1108 case 12: /*MEMW*/
1109 break;
1110
1111 case 13: /*EXTW*/
1112 break;
1113
1114 case 15: /*NOP*/
1115 break;
1116
1117 default: /*reserved*/
1118 RESERVED();
1119 break;
1120 }
1121 break;
1122
1123 case 3: /*RFEIx*/
1124 switch (RRR_T) {
1125 case 0: /*RFETx*/
1126 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1127 switch (RRR_S) {
1128 case 0: /*RFEx*/
1129 if (gen_check_privilege(dc)) {
1130 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1131 gen_helper_check_interrupts(cpu_env);
1132 gen_jump(dc, cpu_SR[EPC1]);
1133 }
1134 break;
1135
1136 case 1: /*RFUEx*/
1137 RESERVED();
1138 break;
1139
1140 case 2: /*RFDEx*/
1141 if (gen_check_privilege(dc)) {
1142 gen_jump(dc, cpu_SR[
1143 dc->config->ndepc ? DEPC : EPC1]);
1144 }
1145 break;
1146
1147 case 4: /*RFWOw*/
1148 case 5: /*RFWUw*/
1149 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1150 if (gen_check_privilege(dc)) {
1151 TCGv_i32 tmp = tcg_const_i32(1);
1152
1153 tcg_gen_andi_i32(
1154 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1155 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1156
1157 if (RRR_S == 4) {
1158 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1159 cpu_SR[WINDOW_START], tmp);
1160 } else {
1161 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1162 cpu_SR[WINDOW_START], tmp);
1163 }
1164
1165 gen_helper_restore_owb(cpu_env);
1166 gen_helper_check_interrupts(cpu_env);
1167 gen_jump(dc, cpu_SR[EPC1]);
1168
1169 tcg_temp_free(tmp);
1170 }
1171 break;
1172
1173 default: /*reserved*/
1174 RESERVED();
1175 break;
1176 }
1177 break;
1178
1179 case 1: /*RFIx*/
1180 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1181 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1182 if (gen_check_privilege(dc)) {
1183 tcg_gen_mov_i32(cpu_SR[PS],
1184 cpu_SR[EPS2 + RRR_S - 2]);
1185 gen_helper_check_interrupts(cpu_env);
1186 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1187 }
1188 } else {
1189 qemu_log("RFI %d is illegal\n", RRR_S);
1190 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1191 }
1192 break;
1193
1194 case 2: /*RFME*/
1195 TBD();
1196 break;
1197
1198 default: /*reserved*/
1199 RESERVED();
1200 break;
1201
1202 }
1203 break;
1204
1205 case 4: /*BREAKx*/
1206 HAS_OPTION(XTENSA_OPTION_DEBUG);
1207 if (dc->debug) {
1208 gen_debug_exception(dc, DEBUGCAUSE_BI);
1209 }
1210 break;
1211
1212 case 5: /*SYSCALLx*/
1213 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1214 switch (RRR_S) {
1215 case 0: /*SYSCALLx*/
1216 gen_exception_cause(dc, SYSCALL_CAUSE);
1217 break;
1218
1219 case 1: /*SIMCALL*/
1220 if (semihosting_enabled()) {
1221 if (gen_check_privilege(dc)) {
1222 gen_helper_simcall(cpu_env);
1223 }
1224 } else {
1225 qemu_log("SIMCALL but semihosting is disabled\n");
1226 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1227 }
1228 break;
1229
1230 default:
1231 RESERVED();
1232 break;
1233 }
1234 break;
1235
1236 case 6: /*RSILx*/
1237 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1238 if (gen_check_privilege(dc) &&
1239 gen_window_check1(dc, RRR_T)) {
1240 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1241 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1242 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1243 gen_helper_check_interrupts(cpu_env);
1244 gen_jumpi_check_loop_end(dc, 0);
1245 }
1246 break;
1247
1248 case 7: /*WAITIx*/
1249 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1250 if (gen_check_privilege(dc)) {
1251 gen_waiti(dc, RRR_S);
1252 }
1253 break;
1254
1255 case 8: /*ANY4p*/
1256 case 9: /*ALL4p*/
1257 case 10: /*ANY8p*/
1258 case 11: /*ALL8p*/
1259 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1260 {
1261 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1262 TCGv_i32 mask = tcg_const_i32(
1263 ((1 << shift) - 1) << RRR_S);
1264 TCGv_i32 tmp = tcg_temp_new_i32();
1265
1266 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1267 if (RRR_R & 1) { /*ALL*/
1268 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1269 } else { /*ANY*/
1270 tcg_gen_add_i32(tmp, tmp, mask);
1271 }
1272 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1273 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1274 tmp, RRR_T, 1);
1275 tcg_temp_free(mask);
1276 tcg_temp_free(tmp);
1277 }
1278 break;
1279
1280 default: /*reserved*/
1281 RESERVED();
1282 break;
1283
1284 }
1285 break;
1286
1287 case 1: /*AND*/
1288 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1289 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1290 }
1291 break;
1292
1293 case 2: /*OR*/
1294 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1295 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1296 }
1297 break;
1298
1299 case 3: /*XOR*/
1300 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1301 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1302 }
1303 break;
1304
1305 case 4: /*ST1*/
1306 switch (RRR_R) {
1307 case 0: /*SSR*/
1308 if (gen_window_check1(dc, RRR_S)) {
1309 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1310 }
1311 break;
1312
1313 case 1: /*SSL*/
1314 if (gen_window_check1(dc, RRR_S)) {
1315 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1316 }
1317 break;
1318
1319 case 2: /*SSA8L*/
1320 if (gen_window_check1(dc, RRR_S)) {
1321 TCGv_i32 tmp = tcg_temp_new_i32();
1322 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1323 gen_right_shift_sar(dc, tmp);
1324 tcg_temp_free(tmp);
1325 }
1326 break;
1327
1328 case 3: /*SSA8B*/
1329 if (gen_window_check1(dc, RRR_S)) {
1330 TCGv_i32 tmp = tcg_temp_new_i32();
1331 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1332 gen_left_shift_sar(dc, tmp);
1333 tcg_temp_free(tmp);
1334 }
1335 break;
1336
1337 case 4: /*SSAI*/
1338 {
1339 TCGv_i32 tmp = tcg_const_i32(
1340 RRR_S | ((RRR_T & 1) << 4));
1341 gen_right_shift_sar(dc, tmp);
1342 tcg_temp_free(tmp);
1343 }
1344 break;
1345
1346 case 6: /*RER*/
1347 TBD();
1348 break;
1349
1350 case 7: /*WER*/
1351 TBD();
1352 break;
1353
1354 case 8: /*ROTWw*/
1355 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1356 if (gen_check_privilege(dc)) {
1357 TCGv_i32 tmp = tcg_const_i32(
1358 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1359 gen_helper_rotw(cpu_env, tmp);
1360 tcg_temp_free(tmp);
1361 /* This can change tb->flags, so exit tb */
1362 gen_jumpi_check_loop_end(dc, -1);
1363 }
1364 break;
1365
1366 case 14: /*NSAu*/
1367 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1368 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1369 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1370 }
1371 break;
1372
1373 case 15: /*NSAUu*/
1374 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1375 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1376 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1377 }
1378 break;
1379
1380 default: /*reserved*/
1381 RESERVED();
1382 break;
1383 }
1384 break;
1385
1386 case 5: /*TLB*/
1387 HAS_OPTION_BITS(
1388 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1389 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1390 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1391 if (gen_check_privilege(dc) &&
1392 gen_window_check2(dc, RRR_S, RRR_T)) {
1393 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1394
1395 switch (RRR_R & 7) {
1396 case 3: /*RITLB0*/ /*RDTLB0*/
1397 gen_helper_rtlb0(cpu_R[RRR_T],
1398 cpu_env, cpu_R[RRR_S], dtlb);
1399 break;
1400
1401 case 4: /*IITLB*/ /*IDTLB*/
1402 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1403 /* This could change memory mapping, so exit tb */
1404 gen_jumpi_check_loop_end(dc, -1);
1405 break;
1406
1407 case 5: /*PITLB*/ /*PDTLB*/
1408 tcg_gen_movi_i32(cpu_pc, dc->pc);
1409 gen_helper_ptlb(cpu_R[RRR_T],
1410 cpu_env, cpu_R[RRR_S], dtlb);
1411 break;
1412
1413 case 6: /*WITLB*/ /*WDTLB*/
1414 gen_helper_wtlb(
1415 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1416 /* This could change memory mapping, so exit tb */
1417 gen_jumpi_check_loop_end(dc, -1);
1418 break;
1419
1420 case 7: /*RITLB1*/ /*RDTLB1*/
1421 gen_helper_rtlb1(cpu_R[RRR_T],
1422 cpu_env, cpu_R[RRR_S], dtlb);
1423 break;
1424
1425 default:
1426 tcg_temp_free(dtlb);
1427 RESERVED();
1428 break;
1429 }
1430 tcg_temp_free(dtlb);
1431 }
1432 break;
1433
1434 case 6: /*RT0*/
1435 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1436 break;
1437 }
1438 switch (RRR_S) {
1439 case 0: /*NEG*/
1440 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1441 break;
1442
1443 case 1: /*ABS*/
1444 {
1445 TCGv_i32 zero = tcg_const_i32(0);
1446 TCGv_i32 neg = tcg_temp_new_i32();
1447
1448 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1449 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1450 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1451 tcg_temp_free(neg);
1452 tcg_temp_free(zero);
1453 }
1454 break;
1455
1456 default: /*reserved*/
1457 RESERVED();
1458 break;
1459 }
1460 break;
1461
1462 case 7: /*reserved*/
1463 RESERVED();
1464 break;
1465
1466 case 8: /*ADD*/
1467 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1468 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1469 }
1470 break;
1471
1472 case 9: /*ADD**/
1473 case 10:
1474 case 11:
1475 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1476 TCGv_i32 tmp = tcg_temp_new_i32();
1477 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1478 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1479 tcg_temp_free(tmp);
1480 }
1481 break;
1482
1483 case 12: /*SUB*/
1484 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1485 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1486 }
1487 break;
1488
1489 case 13: /*SUB**/
1490 case 14:
1491 case 15:
1492 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1493 TCGv_i32 tmp = tcg_temp_new_i32();
1494 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1495 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1496 tcg_temp_free(tmp);
1497 }
1498 break;
1499 }
1500 break;
1501
1502 case 1: /*RST1*/
1503 switch (OP2) {
1504 case 0: /*SLLI*/
1505 case 1:
1506 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1507 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1508 32 - (RRR_T | ((OP2 & 1) << 4)));
1509 }
1510 break;
1511
1512 case 2: /*SRAI*/
1513 case 3:
1514 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1515 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1516 RRR_S | ((OP2 & 1) << 4));
1517 }
1518 break;
1519
1520 case 4: /*SRLI*/
1521 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1522 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1523 }
1524 break;
1525
1526 case 6: /*XSR*/
1527 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1528 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1529 gen_window_check1(dc, RRR_T)) {
1530 TCGv_i32 tmp = tcg_temp_new_i32();
1531
1532 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1533 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1534 gen_wsr(dc, RSR_SR, tmp);
1535 tcg_temp_free(tmp);
1536 }
1537 break;
1538
1539 /*
1540 * Note: 64 bit ops are used here solely because SAR values
1541 * have range 0..63
1542 */
1543 #define gen_shift_reg(cmd, reg) do { \
1544 TCGv_i64 tmp = tcg_temp_new_i64(); \
1545 tcg_gen_extu_i32_i64(tmp, reg); \
1546 tcg_gen_##cmd##_i64(v, v, tmp); \
1547 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
1548 tcg_temp_free_i64(v); \
1549 tcg_temp_free_i64(tmp); \
1550 } while (0)
1551
1552 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1553
1554 case 8: /*SRC*/
1555 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1556 TCGv_i64 v = tcg_temp_new_i64();
1557 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1558 gen_shift(shr);
1559 }
1560 break;
1561
1562 case 9: /*SRL*/
1563 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1564 break;
1565 }
1566 if (dc->sar_5bit) {
1567 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1568 } else {
1569 TCGv_i64 v = tcg_temp_new_i64();
1570 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1571 gen_shift(shr);
1572 }
1573 break;
1574
1575 case 10: /*SLL*/
1576 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1577 break;
1578 }
1579 if (dc->sar_m32_5bit) {
1580 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1581 } else {
1582 TCGv_i64 v = tcg_temp_new_i64();
1583 TCGv_i32 s = tcg_const_i32(32);
1584 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1585 tcg_gen_andi_i32(s, s, 0x3f);
1586 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1587 gen_shift_reg(shl, s);
1588 tcg_temp_free(s);
1589 }
1590 break;
1591
1592 case 11: /*SRA*/
1593 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1594 break;
1595 }
1596 if (dc->sar_5bit) {
1597 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1598 } else {
1599 TCGv_i64 v = tcg_temp_new_i64();
1600 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1601 gen_shift(sar);
1602 }
1603 break;
1604 #undef gen_shift
1605 #undef gen_shift_reg
1606
1607 case 12: /*MUL16U*/
1608 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1609 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1610 TCGv_i32 v1 = tcg_temp_new_i32();
1611 TCGv_i32 v2 = tcg_temp_new_i32();
1612 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1613 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1614 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1615 tcg_temp_free(v2);
1616 tcg_temp_free(v1);
1617 }
1618 break;
1619
1620 case 13: /*MUL16S*/
1621 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1622 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1623 TCGv_i32 v1 = tcg_temp_new_i32();
1624 TCGv_i32 v2 = tcg_temp_new_i32();
1625 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1626 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1627 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1628 tcg_temp_free(v2);
1629 tcg_temp_free(v1);
1630 }
1631 break;
1632
1633 default: /*reserved*/
1634 RESERVED();
1635 break;
1636 }
1637 break;
1638
1639 case 2: /*RST2*/
1640 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1641 break;
1642 }
1643
1644 if (OP2 >= 12) {
1645 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1646 TCGLabel *label = gen_new_label();
1647 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1648 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1649 gen_set_label(label);
1650 }
1651
1652 switch (OP2) {
1653 #define BOOLEAN_LOGIC(fn, r, s, t) \
1654 do { \
1655 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1656 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1657 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1658 \
1659 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1660 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1661 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1662 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1663 tcg_temp_free(tmp1); \
1664 tcg_temp_free(tmp2); \
1665 } while (0)
1666
1667 case 0: /*ANDBp*/
1668 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1669 break;
1670
1671 case 1: /*ANDBCp*/
1672 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1673 break;
1674
1675 case 2: /*ORBp*/
1676 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1677 break;
1678
1679 case 3: /*ORBCp*/
1680 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1681 break;
1682
1683 case 4: /*XORBp*/
1684 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1685 break;
1686
1687 #undef BOOLEAN_LOGIC
1688
1689 case 8: /*MULLi*/
1690 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1691 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1692 break;
1693
1694 case 10: /*MULUHi*/
1695 case 11: /*MULSHi*/
1696 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1697 {
1698 TCGv lo = tcg_temp_new();
1699
1700 if (OP2 == 10) {
1701 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1702 cpu_R[RRR_S], cpu_R[RRR_T]);
1703 } else {
1704 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1705 cpu_R[RRR_S], cpu_R[RRR_T]);
1706 }
1707 tcg_temp_free(lo);
1708 }
1709 break;
1710
1711 case 12: /*QUOUi*/
1712 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1713 break;
1714
1715 case 13: /*QUOSi*/
1716 case 15: /*REMSi*/
1717 {
1718 TCGLabel *label1 = gen_new_label();
1719 TCGLabel *label2 = gen_new_label();
1720
1721 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1722 label1);
1723 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1724 label1);
1725 tcg_gen_movi_i32(cpu_R[RRR_R],
1726 OP2 == 13 ? 0x80000000 : 0);
1727 tcg_gen_br(label2);
1728 gen_set_label(label1);
1729 if (OP2 == 13) {
1730 tcg_gen_div_i32(cpu_R[RRR_R],
1731 cpu_R[RRR_S], cpu_R[RRR_T]);
1732 } else {
1733 tcg_gen_rem_i32(cpu_R[RRR_R],
1734 cpu_R[RRR_S], cpu_R[RRR_T]);
1735 }
1736 gen_set_label(label2);
1737 }
1738 break;
1739
1740 case 14: /*REMUi*/
1741 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1742 break;
1743
1744 default: /*reserved*/
1745 RESERVED();
1746 break;
1747 }
1748 break;
1749
1750 case 3: /*RST3*/
1751 switch (OP2) {
1752 case 0: /*RSR*/
1753 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1754 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1755 gen_window_check1(dc, RRR_T)) {
1756 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1757 }
1758 break;
1759
1760 case 1: /*WSR*/
1761 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1762 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1763 gen_window_check1(dc, RRR_T)) {
1764 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1765 }
1766 break;
1767
1768 case 2: /*SEXTu*/
1769 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1770 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1771 int shift = 24 - RRR_T;
1772
1773 if (shift == 24) {
1774 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1775 } else if (shift == 16) {
1776 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1777 } else {
1778 TCGv_i32 tmp = tcg_temp_new_i32();
1779 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1780 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1781 tcg_temp_free(tmp);
1782 }
1783 }
1784 break;
1785
1786 case 3: /*CLAMPSu*/
1787 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1788 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1789 TCGv_i32 tmp1 = tcg_temp_new_i32();
1790 TCGv_i32 tmp2 = tcg_temp_new_i32();
1791 TCGv_i32 zero = tcg_const_i32(0);
1792
1793 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1794 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1795 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1796
1797 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1798 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1799
1800 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1801 cpu_R[RRR_S], tmp1);
1802 tcg_temp_free(tmp1);
1803 tcg_temp_free(tmp2);
1804 tcg_temp_free(zero);
1805 }
1806 break;
1807
1808 case 4: /*MINu*/
1809 case 5: /*MAXu*/
1810 case 6: /*MINUu*/
1811 case 7: /*MAXUu*/
1812 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1813 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1814 static const TCGCond cond[] = {
1815 TCG_COND_LE,
1816 TCG_COND_GE,
1817 TCG_COND_LEU,
1818 TCG_COND_GEU
1819 };
1820 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1821 cpu_R[RRR_S], cpu_R[RRR_T],
1822 cpu_R[RRR_S], cpu_R[RRR_T]);
1823 }
1824 break;
1825
1826 case 8: /*MOVEQZ*/
1827 case 9: /*MOVNEZ*/
1828 case 10: /*MOVLTZ*/
1829 case 11: /*MOVGEZ*/
1830 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1831 static const TCGCond cond[] = {
1832 TCG_COND_EQ,
1833 TCG_COND_NE,
1834 TCG_COND_LT,
1835 TCG_COND_GE,
1836 };
1837 TCGv_i32 zero = tcg_const_i32(0);
1838
1839 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1840 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1841 tcg_temp_free(zero);
1842 }
1843 break;
1844
1845 case 12: /*MOVFp*/
1846 case 13: /*MOVTp*/
1847 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1848 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1849 TCGv_i32 zero = tcg_const_i32(0);
1850 TCGv_i32 tmp = tcg_temp_new_i32();
1851
1852 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1853 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1854 cpu_R[RRR_R], tmp, zero,
1855 cpu_R[RRR_S], cpu_R[RRR_R]);
1856
1857 tcg_temp_free(tmp);
1858 tcg_temp_free(zero);
1859 }
1860 break;
1861
1862 case 14: /*RUR*/
1863 if (gen_window_check1(dc, RRR_R)) {
1864 int st = (RRR_S << 4) + RRR_T;
1865 if (uregnames[st].name) {
1866 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1867 } else {
1868 qemu_log("RUR %d not implemented, ", st);
1869 TBD();
1870 }
1871 }
1872 break;
1873
1874 case 15: /*WUR*/
1875 if (gen_window_check1(dc, RRR_T)) {
1876 if (uregnames[RSR_SR].name) {
1877 gen_wur(RSR_SR, cpu_R[RRR_T]);
1878 } else {
1879 qemu_log("WUR %d not implemented, ", RSR_SR);
1880 TBD();
1881 }
1882 }
1883 break;
1884
1885 }
1886 break;
1887
1888 case 4: /*EXTUI*/
1889 case 5:
1890 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1891 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1892 int maskimm = (1 << (OP2 + 1)) - 1;
1893
1894 TCGv_i32 tmp = tcg_temp_new_i32();
1895 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1896 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1897 tcg_temp_free(tmp);
1898 }
1899 break;
1900
1901 case 6: /*CUST0*/
1902 RESERVED();
1903 break;
1904
1905 case 7: /*CUST1*/
1906 RESERVED();
1907 break;
1908
1909 case 8: /*LSCXp*/
1910 switch (OP2) {
1911 case 0: /*LSXf*/
1912 case 1: /*LSXUf*/
1913 case 4: /*SSXf*/
1914 case 5: /*SSXUf*/
1915 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1916 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1917 gen_check_cpenable(dc, 0)) {
1918 TCGv_i32 addr = tcg_temp_new_i32();
1919 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1920 gen_load_store_alignment(dc, 2, addr, false);
1921 if (OP2 & 0x4) {
1922 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1923 } else {
1924 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1925 }
1926 if (OP2 & 0x1) {
1927 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1928 }
1929 tcg_temp_free(addr);
1930 }
1931 break;
1932
1933 default: /*reserved*/
1934 RESERVED();
1935 break;
1936 }
1937 break;
1938
1939 case 9: /*LSC4*/
1940 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1941 break;
1942 }
1943 switch (OP2) {
1944 case 0: /*L32E*/
1945 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1946 if (gen_check_privilege(dc) &&
1947 gen_window_check2(dc, RRR_S, RRR_T)) {
1948 TCGv_i32 addr = tcg_temp_new_i32();
1949 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1950 (0xffffffc0 | (RRR_R << 2)));
1951 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1952 tcg_temp_free(addr);
1953 }
1954 break;
1955
1956 case 4: /*S32E*/
1957 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1958 if (gen_check_privilege(dc) &&
1959 gen_window_check2(dc, RRR_S, RRR_T)) {
1960 TCGv_i32 addr = tcg_temp_new_i32();
1961 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1962 (0xffffffc0 | (RRR_R << 2)));
1963 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1964 tcg_temp_free(addr);
1965 }
1966 break;
1967
1968 default:
1969 RESERVED();
1970 break;
1971 }
1972 break;
1973
1974 case 10: /*FP0*/
1975 /*DEPBITS*/
1976 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
1977 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1978 break;
1979 }
1980 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
1981 OP2, RRR_R + 1);
1982 break;
1983 }
1984
1985 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1986 switch (OP2) {
1987 case 0: /*ADD.Sf*/
1988 if (gen_check_cpenable(dc, 0)) {
1989 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1990 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1991 }
1992 break;
1993
1994 case 1: /*SUB.Sf*/
1995 if (gen_check_cpenable(dc, 0)) {
1996 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1997 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1998 }
1999 break;
2000
2001 case 2: /*MUL.Sf*/
2002 if (gen_check_cpenable(dc, 0)) {
2003 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2004 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2005 }
2006 break;
2007
2008 case 4: /*MADD.Sf*/
2009 if (gen_check_cpenable(dc, 0)) {
2010 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2011 cpu_FR[RRR_R], cpu_FR[RRR_S],
2012 cpu_FR[RRR_T]);
2013 }
2014 break;
2015
2016 case 5: /*MSUB.Sf*/
2017 if (gen_check_cpenable(dc, 0)) {
2018 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2019 cpu_FR[RRR_R], cpu_FR[RRR_S],
2020 cpu_FR[RRR_T]);
2021 }
2022 break;
2023
2024 case 8: /*ROUND.Sf*/
2025 case 9: /*TRUNC.Sf*/
2026 case 10: /*FLOOR.Sf*/
2027 case 11: /*CEIL.Sf*/
2028 case 14: /*UTRUNC.Sf*/
2029 if (gen_window_check1(dc, RRR_R) &&
2030 gen_check_cpenable(dc, 0)) {
2031 static const unsigned rounding_mode_const[] = {
2032 float_round_nearest_even,
2033 float_round_to_zero,
2034 float_round_down,
2035 float_round_up,
2036 [6] = float_round_to_zero,
2037 };
2038 TCGv_i32 rounding_mode = tcg_const_i32(
2039 rounding_mode_const[OP2 & 7]);
2040 TCGv_i32 scale = tcg_const_i32(RRR_T);
2041
2042 if (OP2 == 14) {
2043 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2044 rounding_mode, scale);
2045 } else {
2046 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2047 rounding_mode, scale);
2048 }
2049
2050 tcg_temp_free(rounding_mode);
2051 tcg_temp_free(scale);
2052 }
2053 break;
2054
2055 case 12: /*FLOAT.Sf*/
2056 case 13: /*UFLOAT.Sf*/
2057 if (gen_window_check1(dc, RRR_S) &&
2058 gen_check_cpenable(dc, 0)) {
2059 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2060
2061 if (OP2 == 13) {
2062 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2063 cpu_R[RRR_S], scale);
2064 } else {
2065 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2066 cpu_R[RRR_S], scale);
2067 }
2068 tcg_temp_free(scale);
2069 }
2070 break;
2071
2072 case 15: /*FP1OP*/
2073 switch (RRR_T) {
2074 case 0: /*MOV.Sf*/
2075 if (gen_check_cpenable(dc, 0)) {
2076 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2077 }
2078 break;
2079
2080 case 1: /*ABS.Sf*/
2081 if (gen_check_cpenable(dc, 0)) {
2082 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2083 }
2084 break;
2085
2086 case 4: /*RFRf*/
2087 if (gen_window_check1(dc, RRR_R) &&
2088 gen_check_cpenable(dc, 0)) {
2089 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2090 }
2091 break;
2092
2093 case 5: /*WFRf*/
2094 if (gen_window_check1(dc, RRR_S) &&
2095 gen_check_cpenable(dc, 0)) {
2096 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2097 }
2098 break;
2099
2100 case 6: /*NEG.Sf*/
2101 if (gen_check_cpenable(dc, 0)) {
2102 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2103 }
2104 break;
2105
2106 default: /*reserved*/
2107 RESERVED();
2108 break;
2109 }
2110 break;
2111
2112 default: /*reserved*/
2113 RESERVED();
2114 break;
2115 }
2116 break;
2117
2118 case 11: /*FP1*/
2119 /*DEPBITS*/
2120 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2121 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2122 break;
2123 }
2124 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2125 OP2 + 16, RRR_R + 1);
2126 break;
2127 }
2128
2129 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2130
2131 #define gen_compare(rel, br, a, b) \
2132 do { \
2133 if (gen_check_cpenable(dc, 0)) { \
2134 TCGv_i32 bit = tcg_const_i32(1 << br); \
2135 \
2136 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2137 tcg_temp_free(bit); \
2138 } \
2139 } while (0)
2140
2141 switch (OP2) {
2142 case 1: /*UN.Sf*/
2143 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2144 break;
2145
2146 case 2: /*OEQ.Sf*/
2147 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2148 break;
2149
2150 case 3: /*UEQ.Sf*/
2151 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2152 break;
2153
2154 case 4: /*OLT.Sf*/
2155 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2156 break;
2157
2158 case 5: /*ULT.Sf*/
2159 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2160 break;
2161
2162 case 6: /*OLE.Sf*/
2163 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2164 break;
2165
2166 case 7: /*ULE.Sf*/
2167 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2168 break;
2169
2170 #undef gen_compare
2171
2172 case 8: /*MOVEQZ.Sf*/
2173 case 9: /*MOVNEZ.Sf*/
2174 case 10: /*MOVLTZ.Sf*/
2175 case 11: /*MOVGEZ.Sf*/
2176 if (gen_window_check1(dc, RRR_T) &&
2177 gen_check_cpenable(dc, 0)) {
2178 static const TCGCond cond[] = {
2179 TCG_COND_EQ,
2180 TCG_COND_NE,
2181 TCG_COND_LT,
2182 TCG_COND_GE,
2183 };
2184 TCGv_i32 zero = tcg_const_i32(0);
2185
2186 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2187 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2188 tcg_temp_free(zero);
2189 }
2190 break;
2191
2192 case 12: /*MOVF.Sf*/
2193 case 13: /*MOVT.Sf*/
2194 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2195 if (gen_check_cpenable(dc, 0)) {
2196 TCGv_i32 zero = tcg_const_i32(0);
2197 TCGv_i32 tmp = tcg_temp_new_i32();
2198
2199 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2200 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2201 cpu_FR[RRR_R], tmp, zero,
2202 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2203
2204 tcg_temp_free(tmp);
2205 tcg_temp_free(zero);
2206 }
2207 break;
2208
2209 default: /*reserved*/
2210 RESERVED();
2211 break;
2212 }
2213 break;
2214
2215 default: /*reserved*/
2216 RESERVED();
2217 break;
2218 }
2219 break;
2220
2221 case 1: /*L32R*/
2222 if (gen_window_check1(dc, RRR_T)) {
2223 TCGv_i32 tmp = tcg_const_i32(
2224 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2225 0 : ((dc->pc + 3) & ~3)) +
2226 (0xfffc0000 | (RI16_IMM16 << 2)));
2227
2228 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2229 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2230 }
2231 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2232 tcg_temp_free(tmp);
2233 }
2234 break;
2235
2236 case 2: /*LSAI*/
2237 #define gen_load_store(type, shift) do { \
2238 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2239 TCGv_i32 addr = tcg_temp_new_i32(); \
2240 \
2241 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2242 if (shift) { \
2243 gen_load_store_alignment(dc, shift, addr, false); \
2244 } \
2245 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2246 tcg_temp_free(addr); \
2247 } \
2248 } while (0)
2249
2250 switch (RRI8_R) {
2251 case 0: /*L8UI*/
2252 gen_load_store(ld8u, 0);
2253 break;
2254
2255 case 1: /*L16UI*/
2256 gen_load_store(ld16u, 1);
2257 break;
2258
2259 case 2: /*L32I*/
2260 gen_load_store(ld32u, 2);
2261 break;
2262
2263 case 4: /*S8I*/
2264 gen_load_store(st8, 0);
2265 break;
2266
2267 case 5: /*S16I*/
2268 gen_load_store(st16, 1);
2269 break;
2270
2271 case 6: /*S32I*/
2272 gen_load_store(st32, 2);
2273 break;
2274
2275 #define gen_dcache_hit_test(w, shift) do { \
2276 if (gen_window_check1(dc, RRI##w##_S)) { \
2277 TCGv_i32 addr = tcg_temp_new_i32(); \
2278 TCGv_i32 res = tcg_temp_new_i32(); \
2279 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2280 RRI##w##_IMM##w << shift); \
2281 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2282 tcg_temp_free(addr); \
2283 tcg_temp_free(res); \
2284 } \
2285 } while (0)
2286
2287 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2288 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2289
2290 case 7: /*CACHEc*/
2291 if (RRI8_T < 8) {
2292 HAS_OPTION(XTENSA_OPTION_DCACHE);
2293 }
2294
2295 switch (RRI8_T) {
2296 case 0: /*DPFRc*/
2297 gen_window_check1(dc, RRI8_S);
2298 break;
2299
2300 case 1: /*DPFWc*/
2301 gen_window_check1(dc, RRI8_S);
2302 break;
2303
2304 case 2: /*DPFROc*/
2305 gen_window_check1(dc, RRI8_S);
2306 break;
2307
2308 case 3: /*DPFWOc*/
2309 gen_window_check1(dc, RRI8_S);
2310 break;
2311
2312 case 4: /*DHWBc*/
2313 gen_dcache_hit_test8();
2314 break;
2315
2316 case 5: /*DHWBIc*/
2317 gen_dcache_hit_test8();
2318 break;
2319
2320 case 6: /*DHIc*/
2321 if (gen_check_privilege(dc)) {
2322 gen_dcache_hit_test8();
2323 }
2324 break;
2325
2326 case 7: /*DIIc*/
2327 if (gen_check_privilege(dc)) {
2328 gen_window_check1(dc, RRI8_S);
2329 }
2330 break;
2331
2332 case 8: /*DCEc*/
2333 switch (OP1) {
2334 case 0: /*DPFLl*/
2335 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2336 if (gen_check_privilege(dc)) {
2337 gen_dcache_hit_test4();
2338 }
2339 break;
2340
2341 case 2: /*DHUl*/
2342 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2343 if (gen_check_privilege(dc)) {
2344 gen_dcache_hit_test4();
2345 }
2346 break;
2347
2348 case 3: /*DIUl*/
2349 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2350 if (gen_check_privilege(dc)) {
2351 gen_window_check1(dc, RRI4_S);
2352 }
2353 break;
2354
2355 case 4: /*DIWBc*/
2356 HAS_OPTION(XTENSA_OPTION_DCACHE);
2357 if (gen_check_privilege(dc)) {
2358 gen_window_check1(dc, RRI4_S);
2359 }
2360 break;
2361
2362 case 5: /*DIWBIc*/
2363 HAS_OPTION(XTENSA_OPTION_DCACHE);
2364 if (gen_check_privilege(dc)) {
2365 gen_window_check1(dc, RRI4_S);
2366 }
2367 break;
2368
2369 default: /*reserved*/
2370 RESERVED();
2371 break;
2372
2373 }
2374 break;
2375
2376 #undef gen_dcache_hit_test
2377 #undef gen_dcache_hit_test4
2378 #undef gen_dcache_hit_test8
2379
2380 #define gen_icache_hit_test(w, shift) do { \
2381 if (gen_window_check1(dc, RRI##w##_S)) { \
2382 TCGv_i32 addr = tcg_temp_new_i32(); \
2383 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2384 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2385 RRI##w##_IMM##w << shift); \
2386 gen_helper_itlb_hit_test(cpu_env, addr); \
2387 tcg_temp_free(addr); \
2388 }\
2389 } while (0)
2390
2391 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2392 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2393
2394 case 12: /*IPFc*/
2395 HAS_OPTION(XTENSA_OPTION_ICACHE);
2396 gen_window_check1(dc, RRI8_S);
2397 break;
2398
2399 case 13: /*ICEc*/
2400 switch (OP1) {
2401 case 0: /*IPFLl*/
2402 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2403 if (gen_check_privilege(dc)) {
2404 gen_icache_hit_test4();
2405 }
2406 break;
2407
2408 case 2: /*IHUl*/
2409 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2410 if (gen_check_privilege(dc)) {
2411 gen_icache_hit_test4();
2412 }
2413 break;
2414
2415 case 3: /*IIUl*/
2416 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2417 if (gen_check_privilege(dc)) {
2418 gen_window_check1(dc, RRI4_S);
2419 }
2420 break;
2421
2422 default: /*reserved*/
2423 RESERVED();
2424 break;
2425 }
2426 break;
2427
2428 case 14: /*IHIc*/
2429 HAS_OPTION(XTENSA_OPTION_ICACHE);
2430 gen_icache_hit_test8();
2431 break;
2432
2433 case 15: /*IIIc*/
2434 HAS_OPTION(XTENSA_OPTION_ICACHE);
2435 if (gen_check_privilege(dc)) {
2436 gen_window_check1(dc, RRI8_S);
2437 }
2438 break;
2439
2440 default: /*reserved*/
2441 RESERVED();
2442 break;
2443 }
2444 break;
2445
2446 #undef gen_icache_hit_test
2447 #undef gen_icache_hit_test4
2448 #undef gen_icache_hit_test8
2449
2450 case 9: /*L16SI*/
2451 gen_load_store(ld16s, 1);
2452 break;
2453 #undef gen_load_store
2454
2455 case 10: /*MOVI*/
2456 if (gen_window_check1(dc, RRI8_T)) {
2457 tcg_gen_movi_i32(cpu_R[RRI8_T],
2458 RRI8_IMM8 | (RRI8_S << 8) |
2459 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2460 }
2461 break;
2462
2463 #define gen_load_store_no_hw_align(type) do { \
2464 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2465 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2466 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2467 gen_load_store_alignment(dc, 2, addr, true); \
2468 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2469 tcg_temp_free(addr); \
2470 } \
2471 } while (0)
2472
2473 case 11: /*L32AIy*/
2474 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2475 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2476 break;
2477
2478 case 12: /*ADDI*/
2479 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2480 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2481 }
2482 break;
2483
2484 case 13: /*ADDMI*/
2485 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2486 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2487 RRI8_IMM8_SE << 8);
2488 }
2489 break;
2490
2491 case 14: /*S32C1Iy*/
2492 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2493 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2494 TCGLabel *label = gen_new_label();
2495 TCGv_i32 tmp = tcg_temp_local_new_i32();
2496 TCGv_i32 addr = tcg_temp_local_new_i32();
2497 TCGv_i32 tpc;
2498
2499 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2500 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2501 gen_load_store_alignment(dc, 2, addr, true);
2502
2503 gen_advance_ccount(dc);
2504 tpc = tcg_const_i32(dc->pc);
2505 gen_helper_check_atomctl(cpu_env, tpc, addr);
2506 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2507 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2508 cpu_SR[SCOMPARE1], label);
2509
2510 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2511
2512 gen_set_label(label);
2513 tcg_temp_free(tpc);
2514 tcg_temp_free(addr);
2515 tcg_temp_free(tmp);
2516 }
2517 break;
2518
2519 case 15: /*S32RIy*/
2520 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2521 gen_load_store_no_hw_align(st32); /*TODO release?*/
2522 break;
2523 #undef gen_load_store_no_hw_align
2524
2525 default: /*reserved*/
2526 RESERVED();
2527 break;
2528 }
2529 break;
2530
2531 case 3: /*LSCIp*/
2532 switch (RRI8_R) {
2533 case 0: /*LSIf*/
2534 case 4: /*SSIf*/
2535 case 8: /*LSIUf*/
2536 case 12: /*SSIUf*/
2537 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2538 if (gen_window_check1(dc, RRI8_S) &&
2539 gen_check_cpenable(dc, 0)) {
2540 TCGv_i32 addr = tcg_temp_new_i32();
2541 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2542 gen_load_store_alignment(dc, 2, addr, false);
2543 if (RRI8_R & 0x4) {
2544 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2545 } else {
2546 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2547 }
2548 if (RRI8_R & 0x8) {
2549 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2550 }
2551 tcg_temp_free(addr);
2552 }
2553 break;
2554
2555 default: /*reserved*/
2556 RESERVED();
2557 break;
2558 }
2559 break;
2560
2561 case 4: /*MAC16d*/
2562 HAS_OPTION(XTENSA_OPTION_MAC16);
2563 {
2564 enum {
2565 MAC16_UMUL = 0x0,
2566 MAC16_MUL = 0x4,
2567 MAC16_MULA = 0x8,
2568 MAC16_MULS = 0xc,
2569 MAC16_NONE = 0xf,
2570 } op = OP1 & 0xc;
2571 bool is_m1_sr = (OP2 & 0x3) == 2;
2572 bool is_m2_sr = (OP2 & 0xc) == 0;
2573 uint32_t ld_offset = 0;
2574
2575 if (OP2 > 9) {
2576 RESERVED();
2577 }
2578
2579 switch (OP2 & 2) {
2580 case 0: /*MACI?/MACC?*/
2581 is_m1_sr = true;
2582 ld_offset = (OP2 & 1) ? -4 : 4;
2583
2584 if (OP2 >= 8) { /*MACI/MACC*/
2585 if (OP1 == 0) { /*LDINC/LDDEC*/
2586 op = MAC16_NONE;
2587 } else {
2588 RESERVED();
2589 }
2590 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2591 RESERVED();
2592 }
2593 break;
2594
2595 case 2: /*MACD?/MACA?*/
2596 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2597 RESERVED();
2598 }
2599 break;
2600 }
2601
2602 if (op != MAC16_NONE) {
2603 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2604 break;
2605 }
2606 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2607 break;
2608 }
2609 }
2610
2611 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2612 break;
2613 }
2614
2615 {
2616 TCGv_i32 vaddr = tcg_temp_new_i32();
2617 TCGv_i32 mem32 = tcg_temp_new_i32();
2618
2619 if (ld_offset) {
2620 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2621 gen_load_store_alignment(dc, 2, vaddr, false);
2622 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2623 }
2624 if (op != MAC16_NONE) {
2625 TCGv_i32 m1 = gen_mac16_m(
2626 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2627 OP1 & 1, op == MAC16_UMUL);
2628 TCGv_i32 m2 = gen_mac16_m(
2629 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2630 OP1 & 2, op == MAC16_UMUL);
2631
2632 if (op == MAC16_MUL || op == MAC16_UMUL) {
2633 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2634 if (op == MAC16_UMUL) {
2635 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2636 } else {
2637 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2638 }
2639 } else {
2640 TCGv_i32 lo = tcg_temp_new_i32();
2641 TCGv_i32 hi = tcg_temp_new_i32();
2642
2643 tcg_gen_mul_i32(lo, m1, m2);
2644 tcg_gen_sari_i32(hi, lo, 31);
2645 if (op == MAC16_MULA) {
2646 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2647 cpu_SR[ACCLO], cpu_SR[ACCHI],
2648 lo, hi);
2649 } else {
2650 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2651 cpu_SR[ACCLO], cpu_SR[ACCHI],
2652 lo, hi);
2653 }
2654 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2655
2656 tcg_temp_free_i32(lo);
2657 tcg_temp_free_i32(hi);
2658 }
2659 tcg_temp_free(m1);
2660 tcg_temp_free(m2);
2661 }
2662 if (ld_offset) {
2663 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2664 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2665 }
2666 tcg_temp_free(vaddr);
2667 tcg_temp_free(mem32);
2668 }
2669 }
2670 break;
2671
2672 case 5: /*CALLN*/
2673 switch (CALL_N) {
2674 case 0: /*CALL0*/
2675 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2676 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2677 break;
2678
2679 case 1: /*CALL4w*/
2680 case 2: /*CALL8w*/
2681 case 3: /*CALL12w*/
2682 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2683 if (gen_window_check1(dc, CALL_N << 2)) {
2684 gen_callwi(dc, CALL_N,
2685 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2686 }
2687 break;
2688 }
2689 break;
2690
2691 case 6: /*SI*/
2692 switch (CALL_N) {
2693 case 0: /*J*/
2694 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2695 break;
2696
2697 case 1: /*BZ*/
2698 if (gen_window_check1(dc, BRI12_S)) {
2699 static const TCGCond cond[] = {
2700 TCG_COND_EQ, /*BEQZ*/
2701 TCG_COND_NE, /*BNEZ*/
2702 TCG_COND_LT, /*BLTZ*/
2703 TCG_COND_GE, /*BGEZ*/
2704 };
2705
2706 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2707 4 + BRI12_IMM12_SE);
2708 }
2709 break;
2710
2711 case 2: /*BI0*/
2712 if (gen_window_check1(dc, BRI8_S)) {
2713 static const TCGCond cond[] = {
2714 TCG_COND_EQ, /*BEQI*/
2715 TCG_COND_NE, /*BNEI*/
2716 TCG_COND_LT, /*BLTI*/
2717 TCG_COND_GE, /*BGEI*/
2718 };
2719
2720 gen_brcondi(dc, cond[BRI8_M & 3],
2721 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2722 }
2723 break;
2724
2725 case 3: /*BI1*/
2726 switch (BRI8_M) {
2727 case 0: /*ENTRYw*/
2728 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2729 {
2730 TCGv_i32 pc = tcg_const_i32(dc->pc);
2731 TCGv_i32 s = tcg_const_i32(BRI12_S);
2732 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2733 gen_advance_ccount(dc);
2734 gen_helper_entry(cpu_env, pc, s, imm);
2735 tcg_temp_free(imm);
2736 tcg_temp_free(s);
2737 tcg_temp_free(pc);
2738 /* This can change tb->flags, so exit tb */
2739 gen_jumpi_check_loop_end(dc, -1);
2740 }
2741 break;
2742
2743 case 1: /*B1*/
2744 switch (BRI8_R) {
2745 case 0: /*BFp*/
2746 case 1: /*BTp*/
2747 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2748 {
2749 TCGv_i32 tmp = tcg_temp_new_i32();
2750 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2751 gen_brcondi(dc,
2752 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2753 tmp, 0, 4 + RRI8_IMM8_SE);
2754 tcg_temp_free(tmp);
2755 }
2756 break;
2757
2758 case 8: /*LOOP*/
2759 case 9: /*LOOPNEZ*/
2760 case 10: /*LOOPGTZ*/
2761 HAS_OPTION(XTENSA_OPTION_LOOP);
2762 if (gen_window_check1(dc, RRI8_S)) {
2763 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2764 TCGv_i32 tmp = tcg_const_i32(lend);
2765
2766 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2767 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2768 gen_helper_wsr_lend(cpu_env, tmp);
2769 tcg_temp_free(tmp);
2770
2771 if (BRI8_R > 8) {
2772 TCGLabel *label = gen_new_label();
2773 tcg_gen_brcondi_i32(
2774 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2775 cpu_R[RRI8_S], 0, label);
2776 gen_jumpi(dc, lend, 1);
2777 gen_set_label(label);
2778 }
2779
2780 gen_jumpi(dc, dc->next_pc, 0);
2781 }
2782 break;
2783
2784 default: /*reserved*/
2785 RESERVED();
2786 break;
2787
2788 }
2789 break;
2790
2791 case 2: /*BLTUI*/
2792 case 3: /*BGEUI*/
2793 if (gen_window_check1(dc, BRI8_S)) {
2794 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2795 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2796 4 + BRI8_IMM8_SE);
2797 }
2798 break;
2799 }
2800 break;
2801
2802 }
2803 break;
2804
2805 case 7: /*B*/
2806 {
2807 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2808
2809 switch (RRI8_R & 7) {
2810 case 0: /*BNONE*/ /*BANY*/
2811 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2812 TCGv_i32 tmp = tcg_temp_new_i32();
2813 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2814 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2815 tcg_temp_free(tmp);
2816 }
2817 break;
2818
2819 case 1: /*BEQ*/ /*BNE*/
2820 case 2: /*BLT*/ /*BGE*/
2821 case 3: /*BLTU*/ /*BGEU*/
2822 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2823 static const TCGCond cond[] = {
2824 [1] = TCG_COND_EQ,
2825 [2] = TCG_COND_LT,
2826 [3] = TCG_COND_LTU,
2827 [9] = TCG_COND_NE,
2828 [10] = TCG_COND_GE,
2829 [11] = TCG_COND_GEU,
2830 };
2831 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2832 4 + RRI8_IMM8_SE);
2833 }
2834 break;
2835
2836 case 4: /*BALL*/ /*BNALL*/
2837 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2838 TCGv_i32 tmp = tcg_temp_new_i32();
2839 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2840 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2841 4 + RRI8_IMM8_SE);
2842 tcg_temp_free(tmp);
2843 }
2844 break;
2845
2846 case 5: /*BBC*/ /*BBS*/
2847 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2848 #ifdef TARGET_WORDS_BIGENDIAN
2849 TCGv_i32 bit = tcg_const_i32(0x80000000);
2850 #else
2851 TCGv_i32 bit = tcg_const_i32(0x00000001);
2852 #endif
2853 TCGv_i32 tmp = tcg_temp_new_i32();
2854 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2855 #ifdef TARGET_WORDS_BIGENDIAN
2856 tcg_gen_shr_i32(bit, bit, tmp);
2857 #else
2858 tcg_gen_shl_i32(bit, bit, tmp);
2859 #endif
2860 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2861 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2862 tcg_temp_free(tmp);
2863 tcg_temp_free(bit);
2864 }
2865 break;
2866
2867 case 6: /*BBCI*/ /*BBSI*/
2868 case 7:
2869 if (gen_window_check1(dc, RRI8_S)) {
2870 TCGv_i32 tmp = tcg_temp_new_i32();
2871 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2872 #ifdef TARGET_WORDS_BIGENDIAN
2873 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2874 #else
2875 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2876 #endif
2877 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2878 tcg_temp_free(tmp);
2879 }
2880 break;
2881
2882 }
2883 }
2884 break;
2885
2886 #define gen_narrow_load_store(type) do { \
2887 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2888 TCGv_i32 addr = tcg_temp_new_i32(); \
2889 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2890 gen_load_store_alignment(dc, 2, addr, false); \
2891 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2892 tcg_temp_free(addr); \
2893 } \
2894 } while (0)
2895
2896 case 8: /*L32I.Nn*/
2897 gen_narrow_load_store(ld32u);
2898 break;
2899
2900 case 9: /*S32I.Nn*/
2901 gen_narrow_load_store(st32);
2902 break;
2903 #undef gen_narrow_load_store
2904
2905 case 10: /*ADD.Nn*/
2906 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2907 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2908 }
2909 break;
2910
2911 case 11: /*ADDI.Nn*/
2912 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2913 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2914 RRRN_T ? RRRN_T : -1);
2915 }
2916 break;
2917
2918 case 12: /*ST2n*/
2919 if (!gen_window_check1(dc, RRRN_S)) {
2920 break;
2921 }
2922 if (RRRN_T < 8) { /*MOVI.Nn*/
2923 tcg_gen_movi_i32(cpu_R[RRRN_S],
2924 RRRN_R | (RRRN_T << 4) |
2925 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2926 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2927 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2928
2929 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2930 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2931 }
2932 break;
2933
2934 case 13: /*ST3n*/
2935 switch (RRRN_R) {
2936 case 0: /*MOV.Nn*/
2937 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
2938 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2939 }
2940 break;
2941
2942 case 15: /*S3*/
2943 switch (RRRN_T) {
2944 case 0: /*RET.Nn*/
2945 gen_jump(dc, cpu_R[0]);
2946 break;
2947
2948 case 1: /*RETW.Nn*/
2949 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2950 {
2951 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2952 gen_advance_ccount(dc);
2953 gen_helper_retw(tmp, cpu_env, tmp);
2954 gen_jump(dc, tmp);
2955 tcg_temp_free(tmp);
2956 }
2957 break;
2958
2959 case 2: /*BREAK.Nn*/
2960 HAS_OPTION(XTENSA_OPTION_DEBUG);
2961 if (dc->debug) {
2962 gen_debug_exception(dc, DEBUGCAUSE_BN);
2963 }
2964 break;
2965
2966 case 3: /*NOP.Nn*/
2967 break;
2968
2969 case 6: /*ILL.Nn*/
2970 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2971 break;
2972
2973 default: /*reserved*/
2974 RESERVED();
2975 break;
2976 }
2977 break;
2978
2979 default: /*reserved*/
2980 RESERVED();
2981 break;
2982 }
2983 break;
2984
2985 default: /*reserved*/
2986 RESERVED();
2987 break;
2988 }
2989
2990 if (dc->is_jmp == DISAS_NEXT) {
2991 gen_check_loop_end(dc, 0);
2992 }
2993 dc->pc = dc->next_pc;
2994
2995 return;
2996
2997 invalid_opcode:
2998 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2999 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
3000 #undef HAS_OPTION
3001 }
3002
3003 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3004 {
3005 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3006 return xtensa_op0_insn_len(OP0);
3007 }
3008
3009 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
3010 {
3011 unsigned i;
3012
3013 for (i = 0; i < dc->config->nibreak; ++i) {
3014 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3015 env->sregs[IBREAKA + i] == dc->pc) {
3016 gen_debug_exception(dc, DEBUGCAUSE_IB);
3017 break;
3018 }
3019 }
3020 }
3021
3022 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3023 {
3024 XtensaCPU *cpu = xtensa_env_get_cpu(env);
3025 CPUState *cs = CPU(cpu);
3026 DisasContext dc;
3027 int insn_count = 0;
3028 int max_insns = tb->cflags & CF_COUNT_MASK;
3029 uint32_t pc_start = tb->pc;
3030 uint32_t next_page_start =
3031 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3032
3033 if (max_insns == 0) {
3034 max_insns = CF_COUNT_MASK;
3035 }
3036 if (max_insns > TCG_MAX_INSNS) {
3037 max_insns = TCG_MAX_INSNS;
3038 }
3039
3040 dc.config = env->config;
3041 dc.singlestep_enabled = cs->singlestep_enabled;
3042 dc.tb = tb;
3043 dc.pc = pc_start;
3044 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3045 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3046 dc.lbeg = env->sregs[LBEG];
3047 dc.lend = env->sregs[LEND];
3048 dc.is_jmp = DISAS_NEXT;
3049 dc.ccount_delta = 0;
3050 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3051 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3052 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3053 XTENSA_TBFLAG_CPENABLE_SHIFT;
3054 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3055 XTENSA_TBFLAG_WINDOW_SHIFT);
3056
3057 init_litbase(&dc);
3058 init_sar_tracker(&dc);
3059 if (dc.icount) {
3060 dc.next_icount = tcg_temp_local_new_i32();
3061 }
3062
3063 gen_tb_start(tb);
3064
3065 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3066 tcg_gen_movi_i32(cpu_pc, dc.pc);
3067 gen_exception(&dc, EXCP_DEBUG);
3068 }
3069
3070 do {
3071 tcg_gen_insn_start(dc.pc);
3072 ++insn_count;
3073
3074 ++dc.ccount_delta;
3075
3076 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3077 tcg_gen_movi_i32(cpu_pc, dc.pc);
3078 gen_exception(&dc, EXCP_DEBUG);
3079 dc.is_jmp = DISAS_UPDATE;
3080 break;
3081 }
3082
3083 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
3084 gen_io_start();
3085 }
3086
3087 if (dc.icount) {
3088 TCGLabel *label = gen_new_label();
3089
3090 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3091 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3092 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3093 if (dc.debug) {
3094 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3095 }
3096 gen_set_label(label);
3097 }
3098
3099 if (dc.debug) {
3100 gen_ibreak_check(env, &dc);
3101 }
3102
3103 disas_xtensa_insn(env, &dc);
3104 if (dc.icount) {
3105 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3106 }
3107 if (cs->singlestep_enabled) {
3108 tcg_gen_movi_i32(cpu_pc, dc.pc);
3109 gen_exception(&dc, EXCP_DEBUG);
3110 break;
3111 }
3112 } while (dc.is_jmp == DISAS_NEXT &&
3113 insn_count < max_insns &&
3114 dc.pc < next_page_start &&
3115 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
3116 !tcg_op_buf_full());
3117
3118 reset_litbase(&dc);
3119 reset_sar_tracker(&dc);
3120 if (dc.icount) {
3121 tcg_temp_free(dc.next_icount);
3122 }
3123
3124 if (tb->cflags & CF_LAST_IO) {
3125 gen_io_end();
3126 }
3127
3128 if (dc.is_jmp == DISAS_NEXT) {
3129 gen_jumpi(&dc, dc.pc, 0);
3130 }
3131 gen_tb_end(tb, insn_count);
3132
3133 #ifdef DEBUG_DISAS
3134 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3135 qemu_log("----------------\n");
3136 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3137 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
3138 qemu_log("\n");
3139 }
3140 #endif
3141 tb->size = dc.pc - pc_start;
3142 tb->icount = insn_count;
3143 }
3144
3145 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3146 fprintf_function cpu_fprintf, int flags)
3147 {
3148 XtensaCPU *cpu = XTENSA_CPU(cs);
3149 CPUXtensaState *env = &cpu->env;
3150 int i, j;
3151
3152 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3153
3154 for (i = j = 0; i < 256; ++i) {
3155 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3156 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3157 (j++ % 4) == 3 ? '\n' : ' ');
3158 }
3159 }
3160
3161 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3162
3163 for (i = j = 0; i < 256; ++i) {
3164 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3165 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3166 (j++ % 4) == 3 ? '\n' : ' ');
3167 }
3168 }
3169
3170 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3171
3172 for (i = 0; i < 16; ++i) {
3173 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3174 (i % 4) == 3 ? '\n' : ' ');
3175 }
3176
3177 cpu_fprintf(f, "\n");
3178
3179 for (i = 0; i < env->config->nareg; ++i) {
3180 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3181 (i % 4) == 3 ? '\n' : ' ');
3182 }
3183
3184 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3185 cpu_fprintf(f, "\n");
3186
3187 for (i = 0; i < 16; ++i) {
3188 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3189 float32_val(env->fregs[i].f32[FP_F32_LOW]),
3190 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
3191 (i % 2) == 1 ? '\n' : ' ');
3192 }
3193 }
3194 }
3195
3196 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
3197 target_ulong *data)
3198 {
3199 env->pc = data[0];
3200 }
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