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target-xtensa: implement LSCX and LSCI groups
[mirror_qemu.git] / target-xtensa / translate.c
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec-all.h"
35 #include "disas.h"
36 #include "tcg-op.h"
37 #include "qemu-log.h"
38 #include "sysemu.h"
39
40 #include "helper.h"
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
49 int cring;
50 int ring;
51 uint32_t lbeg;
52 uint32_t lend;
53 TCGv_i32 litbase;
54 int is_jmp;
55 int singlestep_enabled;
56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
61
62 uint32_t ccount_delta;
63 unsigned used_window;
64
65 bool debug;
66 bool icount;
67 TCGv_i32 next_icount;
68 } DisasContext;
69
70 static TCGv_ptr cpu_env;
71 static TCGv_i32 cpu_pc;
72 static TCGv_i32 cpu_R[16];
73 static TCGv_i32 cpu_FR[16];
74 static TCGv_i32 cpu_SR[256];
75 static TCGv_i32 cpu_UR[256];
76
77 #include "gen-icount.h"
78
79 static const char * const sregnames[256] = {
80 [LBEG] = "LBEG",
81 [LEND] = "LEND",
82 [LCOUNT] = "LCOUNT",
83 [SAR] = "SAR",
84 [BR] = "BR",
85 [LITBASE] = "LITBASE",
86 [SCOMPARE1] = "SCOMPARE1",
87 [ACCLO] = "ACCLO",
88 [ACCHI] = "ACCHI",
89 [MR] = "MR0",
90 [MR + 1] = "MR1",
91 [MR + 2] = "MR2",
92 [MR + 3] = "MR3",
93 [WINDOW_BASE] = "WINDOW_BASE",
94 [WINDOW_START] = "WINDOW_START",
95 [PTEVADDR] = "PTEVADDR",
96 [RASID] = "RASID",
97 [ITLBCFG] = "ITLBCFG",
98 [DTLBCFG] = "DTLBCFG",
99 [IBREAKENABLE] = "IBREAKENABLE",
100 [IBREAKA] = "IBREAKA0",
101 [IBREAKA + 1] = "IBREAKA1",
102 [DBREAKA] = "DBREAKA0",
103 [DBREAKA + 1] = "DBREAKA1",
104 [DBREAKC] = "DBREAKC0",
105 [DBREAKC + 1] = "DBREAKC1",
106 [EPC1] = "EPC1",
107 [EPC1 + 1] = "EPC2",
108 [EPC1 + 2] = "EPC3",
109 [EPC1 + 3] = "EPC4",
110 [EPC1 + 4] = "EPC5",
111 [EPC1 + 5] = "EPC6",
112 [EPC1 + 6] = "EPC7",
113 [DEPC] = "DEPC",
114 [EPS2] = "EPS2",
115 [EPS2 + 1] = "EPS3",
116 [EPS2 + 2] = "EPS4",
117 [EPS2 + 3] = "EPS5",
118 [EPS2 + 4] = "EPS6",
119 [EPS2 + 5] = "EPS7",
120 [EXCSAVE1] = "EXCSAVE1",
121 [EXCSAVE1 + 1] = "EXCSAVE2",
122 [EXCSAVE1 + 2] = "EXCSAVE3",
123 [EXCSAVE1 + 3] = "EXCSAVE4",
124 [EXCSAVE1 + 4] = "EXCSAVE5",
125 [EXCSAVE1 + 5] = "EXCSAVE6",
126 [EXCSAVE1 + 6] = "EXCSAVE7",
127 [CPENABLE] = "CPENABLE",
128 [INTSET] = "INTSET",
129 [INTCLEAR] = "INTCLEAR",
130 [INTENABLE] = "INTENABLE",
131 [PS] = "PS",
132 [VECBASE] = "VECBASE",
133 [EXCCAUSE] = "EXCCAUSE",
134 [DEBUGCAUSE] = "DEBUGCAUSE",
135 [CCOUNT] = "CCOUNT",
136 [PRID] = "PRID",
137 [ICOUNT] = "ICOUNT",
138 [ICOUNTLEVEL] = "ICOUNTLEVEL",
139 [EXCVADDR] = "EXCVADDR",
140 [CCOMPARE] = "CCOMPARE0",
141 [CCOMPARE + 1] = "CCOMPARE1",
142 [CCOMPARE + 2] = "CCOMPARE2",
143 };
144
145 static const char * const uregnames[256] = {
146 [THREADPTR] = "THREADPTR",
147 [FCR] = "FCR",
148 [FSR] = "FSR",
149 };
150
151 void xtensa_translate_init(void)
152 {
153 static const char * const regnames[] = {
154 "ar0", "ar1", "ar2", "ar3",
155 "ar4", "ar5", "ar6", "ar7",
156 "ar8", "ar9", "ar10", "ar11",
157 "ar12", "ar13", "ar14", "ar15",
158 };
159 static const char * const fregnames[] = {
160 "f0", "f1", "f2", "f3",
161 "f4", "f5", "f6", "f7",
162 "f8", "f9", "f10", "f11",
163 "f12", "f13", "f14", "f15",
164 };
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
169 offsetof(CPUXtensaState, pc), "pc");
170
171 for (i = 0; i < 16; i++) {
172 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
173 offsetof(CPUXtensaState, regs[i]),
174 regnames[i]);
175 }
176
177 for (i = 0; i < 16; i++) {
178 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
179 offsetof(CPUXtensaState, fregs[i]),
180 fregnames[i]);
181 }
182
183 for (i = 0; i < 256; ++i) {
184 if (sregnames[i]) {
185 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
186 offsetof(CPUXtensaState, sregs[i]),
187 sregnames[i]);
188 }
189 }
190
191 for (i = 0; i < 256; ++i) {
192 if (uregnames[i]) {
193 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
194 offsetof(CPUXtensaState, uregs[i]),
195 uregnames[i]);
196 }
197 }
198 #define GEN_HELPER 2
199 #include "helper.h"
200 }
201
202 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
203 {
204 return xtensa_option_bits_enabled(dc->config, opt);
205 }
206
207 static inline bool option_enabled(DisasContext *dc, int opt)
208 {
209 return xtensa_option_enabled(dc->config, opt);
210 }
211
212 static void init_litbase(DisasContext *dc)
213 {
214 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
215 dc->litbase = tcg_temp_local_new_i32();
216 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
217 }
218 }
219
220 static void reset_litbase(DisasContext *dc)
221 {
222 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
223 tcg_temp_free(dc->litbase);
224 }
225 }
226
227 static void init_sar_tracker(DisasContext *dc)
228 {
229 dc->sar_5bit = false;
230 dc->sar_m32_5bit = false;
231 dc->sar_m32_allocated = false;
232 }
233
234 static void reset_sar_tracker(DisasContext *dc)
235 {
236 if (dc->sar_m32_allocated) {
237 tcg_temp_free(dc->sar_m32);
238 }
239 }
240
241 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
242 {
243 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
244 if (dc->sar_m32_5bit) {
245 tcg_gen_discard_i32(dc->sar_m32);
246 }
247 dc->sar_5bit = true;
248 dc->sar_m32_5bit = false;
249 }
250
251 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
252 {
253 TCGv_i32 tmp = tcg_const_i32(32);
254 if (!dc->sar_m32_allocated) {
255 dc->sar_m32 = tcg_temp_local_new_i32();
256 dc->sar_m32_allocated = true;
257 }
258 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
259 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
260 dc->sar_5bit = false;
261 dc->sar_m32_5bit = true;
262 tcg_temp_free(tmp);
263 }
264
265 static void gen_advance_ccount(DisasContext *dc)
266 {
267 if (dc->ccount_delta > 0) {
268 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
269 dc->ccount_delta = 0;
270 gen_helper_advance_ccount(cpu_env, tmp);
271 tcg_temp_free(tmp);
272 }
273 }
274
275 static void reset_used_window(DisasContext *dc)
276 {
277 dc->used_window = 0;
278 }
279
280 static void gen_exception(DisasContext *dc, int excp)
281 {
282 TCGv_i32 tmp = tcg_const_i32(excp);
283 gen_advance_ccount(dc);
284 gen_helper_exception(cpu_env, tmp);
285 tcg_temp_free(tmp);
286 }
287
288 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
289 {
290 TCGv_i32 tpc = tcg_const_i32(dc->pc);
291 TCGv_i32 tcause = tcg_const_i32(cause);
292 gen_advance_ccount(dc);
293 gen_helper_exception_cause(cpu_env, tpc, tcause);
294 tcg_temp_free(tpc);
295 tcg_temp_free(tcause);
296 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
297 cause == SYSCALL_CAUSE) {
298 dc->is_jmp = DISAS_UPDATE;
299 }
300 }
301
302 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
303 TCGv_i32 vaddr)
304 {
305 TCGv_i32 tpc = tcg_const_i32(dc->pc);
306 TCGv_i32 tcause = tcg_const_i32(cause);
307 gen_advance_ccount(dc);
308 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
309 tcg_temp_free(tpc);
310 tcg_temp_free(tcause);
311 }
312
313 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
314 {
315 TCGv_i32 tpc = tcg_const_i32(dc->pc);
316 TCGv_i32 tcause = tcg_const_i32(cause);
317 gen_advance_ccount(dc);
318 gen_helper_debug_exception(cpu_env, tpc, tcause);
319 tcg_temp_free(tpc);
320 tcg_temp_free(tcause);
321 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
322 dc->is_jmp = DISAS_UPDATE;
323 }
324 }
325
326 static void gen_check_privilege(DisasContext *dc)
327 {
328 if (dc->cring) {
329 gen_exception_cause(dc, PRIVILEGED_CAUSE);
330 dc->is_jmp = DISAS_UPDATE;
331 }
332 }
333
334 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
335 {
336 tcg_gen_mov_i32(cpu_pc, dest);
337 gen_advance_ccount(dc);
338 if (dc->icount) {
339 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
340 }
341 if (dc->singlestep_enabled) {
342 gen_exception(dc, EXCP_DEBUG);
343 } else {
344 if (slot >= 0) {
345 tcg_gen_goto_tb(slot);
346 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
347 } else {
348 tcg_gen_exit_tb(0);
349 }
350 }
351 dc->is_jmp = DISAS_UPDATE;
352 }
353
354 static void gen_jump(DisasContext *dc, TCGv dest)
355 {
356 gen_jump_slot(dc, dest, -1);
357 }
358
359 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
360 {
361 TCGv_i32 tmp = tcg_const_i32(dest);
362 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
363 slot = -1;
364 }
365 gen_jump_slot(dc, tmp, slot);
366 tcg_temp_free(tmp);
367 }
368
369 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
370 int slot)
371 {
372 TCGv_i32 tcallinc = tcg_const_i32(callinc);
373
374 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
375 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
376 tcg_temp_free(tcallinc);
377 tcg_gen_movi_i32(cpu_R[callinc << 2],
378 (callinc << 30) | (dc->next_pc & 0x3fffffff));
379 gen_jump_slot(dc, dest, slot);
380 }
381
382 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
383 {
384 gen_callw_slot(dc, callinc, dest, -1);
385 }
386
387 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
388 {
389 TCGv_i32 tmp = tcg_const_i32(dest);
390 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
391 slot = -1;
392 }
393 gen_callw_slot(dc, callinc, tmp, slot);
394 tcg_temp_free(tmp);
395 }
396
397 static bool gen_check_loop_end(DisasContext *dc, int slot)
398 {
399 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
400 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
401 dc->next_pc == dc->lend) {
402 int label = gen_new_label();
403
404 gen_advance_ccount(dc);
405 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
406 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
407 gen_jumpi(dc, dc->lbeg, slot);
408 gen_set_label(label);
409 gen_jumpi(dc, dc->next_pc, -1);
410 return true;
411 }
412 return false;
413 }
414
415 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
416 {
417 if (!gen_check_loop_end(dc, slot)) {
418 gen_jumpi(dc, dc->next_pc, slot);
419 }
420 }
421
422 static void gen_brcond(DisasContext *dc, TCGCond cond,
423 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
424 {
425 int label = gen_new_label();
426
427 gen_advance_ccount(dc);
428 tcg_gen_brcond_i32(cond, t0, t1, label);
429 gen_jumpi_check_loop_end(dc, 0);
430 gen_set_label(label);
431 gen_jumpi(dc, dc->pc + offset, 1);
432 }
433
434 static void gen_brcondi(DisasContext *dc, TCGCond cond,
435 TCGv_i32 t0, uint32_t t1, uint32_t offset)
436 {
437 TCGv_i32 tmp = tcg_const_i32(t1);
438 gen_brcond(dc, cond, t0, tmp, offset);
439 tcg_temp_free(tmp);
440 }
441
442 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
443 {
444 gen_advance_ccount(dc);
445 tcg_gen_mov_i32(d, cpu_SR[sr]);
446 }
447
448 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
449 {
450 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
451 tcg_gen_or_i32(d, d, cpu_SR[sr]);
452 tcg_gen_andi_i32(d, d, 0xfffffffc);
453 }
454
455 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
456 {
457 static void (* const rsr_handler[256])(DisasContext *dc,
458 TCGv_i32 d, uint32_t sr) = {
459 [CCOUNT] = gen_rsr_ccount,
460 [PTEVADDR] = gen_rsr_ptevaddr,
461 };
462
463 if (sregnames[sr]) {
464 if (rsr_handler[sr]) {
465 rsr_handler[sr](dc, d, sr);
466 } else {
467 tcg_gen_mov_i32(d, cpu_SR[sr]);
468 }
469 } else {
470 qemu_log("RSR %d not implemented, ", sr);
471 }
472 }
473
474 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
475 {
476 gen_helper_wsr_lbeg(cpu_env, s);
477 gen_jumpi_check_loop_end(dc, 0);
478 }
479
480 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
481 {
482 gen_helper_wsr_lend(cpu_env, s);
483 gen_jumpi_check_loop_end(dc, 0);
484 }
485
486 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
487 {
488 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
489 if (dc->sar_m32_5bit) {
490 tcg_gen_discard_i32(dc->sar_m32);
491 }
492 dc->sar_5bit = false;
493 dc->sar_m32_5bit = false;
494 }
495
496 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
497 {
498 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
499 }
500
501 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
502 {
503 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
504 /* This can change tb->flags, so exit tb */
505 gen_jumpi_check_loop_end(dc, -1);
506 }
507
508 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
509 {
510 tcg_gen_ext8s_i32(cpu_SR[sr], s);
511 }
512
513 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
514 {
515 gen_helper_wsr_windowbase(cpu_env, v);
516 reset_used_window(dc);
517 }
518
519 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
520 {
521 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
522 reset_used_window(dc);
523 }
524
525 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
526 {
527 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
528 }
529
530 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
531 {
532 gen_helper_wsr_rasid(cpu_env, v);
533 /* This can change tb->flags, so exit tb */
534 gen_jumpi_check_loop_end(dc, -1);
535 }
536
537 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
538 {
539 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
540 }
541
542 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
543 {
544 gen_helper_wsr_ibreakenable(cpu_env, v);
545 gen_jumpi_check_loop_end(dc, 0);
546 }
547
548 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
549 {
550 unsigned id = sr - IBREAKA;
551
552 if (id < dc->config->nibreak) {
553 TCGv_i32 tmp = tcg_const_i32(id);
554 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
555 tcg_temp_free(tmp);
556 gen_jumpi_check_loop_end(dc, 0);
557 }
558 }
559
560 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
561 {
562 unsigned id = sr - DBREAKA;
563
564 if (id < dc->config->ndbreak) {
565 TCGv_i32 tmp = tcg_const_i32(id);
566 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
567 tcg_temp_free(tmp);
568 }
569 }
570
571 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
572 {
573 unsigned id = sr - DBREAKC;
574
575 if (id < dc->config->ndbreak) {
576 TCGv_i32 tmp = tcg_const_i32(id);
577 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
578 tcg_temp_free(tmp);
579 }
580 }
581
582 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
583 {
584 tcg_gen_andi_i32(cpu_SR[sr], v,
585 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
586 gen_helper_check_interrupts(cpu_env);
587 gen_jumpi_check_loop_end(dc, 0);
588 }
589
590 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
591 {
592 TCGv_i32 tmp = tcg_temp_new_i32();
593
594 tcg_gen_andi_i32(tmp, v,
595 dc->config->inttype_mask[INTTYPE_EDGE] |
596 dc->config->inttype_mask[INTTYPE_NMI] |
597 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
598 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
599 tcg_temp_free(tmp);
600 gen_helper_check_interrupts(cpu_env);
601 }
602
603 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
604 {
605 tcg_gen_mov_i32(cpu_SR[sr], v);
606 gen_helper_check_interrupts(cpu_env);
607 gen_jumpi_check_loop_end(dc, 0);
608 }
609
610 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
611 {
612 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
613 PS_UM | PS_EXCM | PS_INTLEVEL;
614
615 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
616 mask |= PS_RING;
617 }
618 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
619 reset_used_window(dc);
620 gen_helper_check_interrupts(cpu_env);
621 /* This can change mmu index and tb->flags, so exit tb */
622 gen_jumpi_check_loop_end(dc, -1);
623 }
624
625 static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
626 {
627 }
628
629 static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630 {
631 }
632
633 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
634 {
635 if (dc->icount) {
636 tcg_gen_mov_i32(dc->next_icount, v);
637 } else {
638 tcg_gen_mov_i32(cpu_SR[sr], v);
639 }
640 }
641
642 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
643 {
644 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
645 /* This can change tb->flags, so exit tb */
646 gen_jumpi_check_loop_end(dc, -1);
647 }
648
649 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
650 {
651 uint32_t id = sr - CCOMPARE;
652 if (id < dc->config->nccompare) {
653 uint32_t int_bit = 1 << dc->config->timerint[id];
654 gen_advance_ccount(dc);
655 tcg_gen_mov_i32(cpu_SR[sr], v);
656 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
657 gen_helper_check_interrupts(cpu_env);
658 }
659 }
660
661 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
662 {
663 static void (* const wsr_handler[256])(DisasContext *dc,
664 uint32_t sr, TCGv_i32 v) = {
665 [LBEG] = gen_wsr_lbeg,
666 [LEND] = gen_wsr_lend,
667 [SAR] = gen_wsr_sar,
668 [BR] = gen_wsr_br,
669 [LITBASE] = gen_wsr_litbase,
670 [ACCHI] = gen_wsr_acchi,
671 [WINDOW_BASE] = gen_wsr_windowbase,
672 [WINDOW_START] = gen_wsr_windowstart,
673 [PTEVADDR] = gen_wsr_ptevaddr,
674 [RASID] = gen_wsr_rasid,
675 [ITLBCFG] = gen_wsr_tlbcfg,
676 [DTLBCFG] = gen_wsr_tlbcfg,
677 [IBREAKENABLE] = gen_wsr_ibreakenable,
678 [IBREAKA] = gen_wsr_ibreaka,
679 [IBREAKA + 1] = gen_wsr_ibreaka,
680 [DBREAKA] = gen_wsr_dbreaka,
681 [DBREAKA + 1] = gen_wsr_dbreaka,
682 [DBREAKC] = gen_wsr_dbreakc,
683 [DBREAKC + 1] = gen_wsr_dbreakc,
684 [INTSET] = gen_wsr_intset,
685 [INTCLEAR] = gen_wsr_intclear,
686 [INTENABLE] = gen_wsr_intenable,
687 [PS] = gen_wsr_ps,
688 [DEBUGCAUSE] = gen_wsr_debugcause,
689 [PRID] = gen_wsr_prid,
690 [ICOUNT] = gen_wsr_icount,
691 [ICOUNTLEVEL] = gen_wsr_icountlevel,
692 [CCOMPARE] = gen_wsr_ccompare,
693 [CCOMPARE + 1] = gen_wsr_ccompare,
694 [CCOMPARE + 2] = gen_wsr_ccompare,
695 };
696
697 if (sregnames[sr]) {
698 if (wsr_handler[sr]) {
699 wsr_handler[sr](dc, sr, s);
700 } else {
701 tcg_gen_mov_i32(cpu_SR[sr], s);
702 }
703 } else {
704 qemu_log("WSR %d not implemented, ", sr);
705 }
706 }
707
708 static void gen_wur(uint32_t ur, TCGv_i32 s)
709 {
710 switch (ur) {
711 case FCR:
712 gen_helper_wur_fcr(cpu_env, s);
713 break;
714
715 case FSR:
716 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
717 break;
718
719 default:
720 tcg_gen_mov_i32(cpu_UR[ur], s);
721 break;
722 }
723 }
724
725 static void gen_load_store_alignment(DisasContext *dc, int shift,
726 TCGv_i32 addr, bool no_hw_alignment)
727 {
728 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
729 tcg_gen_andi_i32(addr, addr, ~0 << shift);
730 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
731 no_hw_alignment) {
732 int label = gen_new_label();
733 TCGv_i32 tmp = tcg_temp_new_i32();
734 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
735 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
736 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
737 gen_set_label(label);
738 tcg_temp_free(tmp);
739 }
740 }
741
742 static void gen_waiti(DisasContext *dc, uint32_t imm4)
743 {
744 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
745 TCGv_i32 intlevel = tcg_const_i32(imm4);
746 gen_advance_ccount(dc);
747 gen_helper_waiti(cpu_env, pc, intlevel);
748 tcg_temp_free(pc);
749 tcg_temp_free(intlevel);
750 }
751
752 static void gen_window_check1(DisasContext *dc, unsigned r1)
753 {
754 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
755 return;
756 }
757 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
758 r1 / 4 > dc->used_window) {
759 TCGv_i32 pc = tcg_const_i32(dc->pc);
760 TCGv_i32 w = tcg_const_i32(r1 / 4);
761
762 dc->used_window = r1 / 4;
763 gen_advance_ccount(dc);
764 gen_helper_window_check(cpu_env, pc, w);
765
766 tcg_temp_free(w);
767 tcg_temp_free(pc);
768 }
769 }
770
771 static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
772 {
773 gen_window_check1(dc, r1 > r2 ? r1 : r2);
774 }
775
776 static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
777 unsigned r3)
778 {
779 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
780 }
781
782 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
783 {
784 TCGv_i32 m = tcg_temp_new_i32();
785
786 if (hi) {
787 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
788 } else {
789 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
790 }
791 return m;
792 }
793
794 static void disas_xtensa_insn(DisasContext *dc)
795 {
796 #define HAS_OPTION_BITS(opt) do { \
797 if (!option_bits_enabled(dc, opt)) { \
798 qemu_log("Option is not enabled %s:%d\n", \
799 __FILE__, __LINE__); \
800 goto invalid_opcode; \
801 } \
802 } while (0)
803
804 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
805
806 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
807 #define RESERVED() do { \
808 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
809 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
810 goto invalid_opcode; \
811 } while (0)
812
813
814 #ifdef TARGET_WORDS_BIGENDIAN
815 #define OP0 (((b0) & 0xf0) >> 4)
816 #define OP1 (((b2) & 0xf0) >> 4)
817 #define OP2 ((b2) & 0xf)
818 #define RRR_R ((b1) & 0xf)
819 #define RRR_S (((b1) & 0xf0) >> 4)
820 #define RRR_T ((b0) & 0xf)
821 #else
822 #define OP0 (((b0) & 0xf))
823 #define OP1 (((b2) & 0xf))
824 #define OP2 (((b2) & 0xf0) >> 4)
825 #define RRR_R (((b1) & 0xf0) >> 4)
826 #define RRR_S (((b1) & 0xf))
827 #define RRR_T (((b0) & 0xf0) >> 4)
828 #endif
829 #define RRR_X ((RRR_R & 0x4) >> 2)
830 #define RRR_Y ((RRR_T & 0x4) >> 2)
831 #define RRR_W (RRR_R & 0x3)
832
833 #define RRRN_R RRR_R
834 #define RRRN_S RRR_S
835 #define RRRN_T RRR_T
836
837 #define RRI8_R RRR_R
838 #define RRI8_S RRR_S
839 #define RRI8_T RRR_T
840 #define RRI8_IMM8 (b2)
841 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
842
843 #ifdef TARGET_WORDS_BIGENDIAN
844 #define RI16_IMM16 (((b1) << 8) | (b2))
845 #else
846 #define RI16_IMM16 (((b2) << 8) | (b1))
847 #endif
848
849 #ifdef TARGET_WORDS_BIGENDIAN
850 #define CALL_N (((b0) & 0xc) >> 2)
851 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
852 #else
853 #define CALL_N (((b0) & 0x30) >> 4)
854 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
855 #endif
856 #define CALL_OFFSET_SE \
857 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
858
859 #define CALLX_N CALL_N
860 #ifdef TARGET_WORDS_BIGENDIAN
861 #define CALLX_M ((b0) & 0x3)
862 #else
863 #define CALLX_M (((b0) & 0xc0) >> 6)
864 #endif
865 #define CALLX_S RRR_S
866
867 #define BRI12_M CALLX_M
868 #define BRI12_S RRR_S
869 #ifdef TARGET_WORDS_BIGENDIAN
870 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
871 #else
872 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
873 #endif
874 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
875
876 #define BRI8_M BRI12_M
877 #define BRI8_R RRI8_R
878 #define BRI8_S RRI8_S
879 #define BRI8_IMM8 RRI8_IMM8
880 #define BRI8_IMM8_SE RRI8_IMM8_SE
881
882 #define RSR_SR (b1)
883
884 uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc);
885 uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1);
886 uint8_t b2 = 0;
887
888 static const uint32_t B4CONST[] = {
889 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
890 };
891
892 static const uint32_t B4CONSTU[] = {
893 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
894 };
895
896 if (OP0 >= 8) {
897 dc->next_pc = dc->pc + 2;
898 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
899 } else {
900 dc->next_pc = dc->pc + 3;
901 b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2);
902 }
903
904 switch (OP0) {
905 case 0: /*QRST*/
906 switch (OP1) {
907 case 0: /*RST0*/
908 switch (OP2) {
909 case 0: /*ST0*/
910 if ((RRR_R & 0xc) == 0x8) {
911 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
912 }
913
914 switch (RRR_R) {
915 case 0: /*SNM0*/
916 switch (CALLX_M) {
917 case 0: /*ILL*/
918 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
919 break;
920
921 case 1: /*reserved*/
922 RESERVED();
923 break;
924
925 case 2: /*JR*/
926 switch (CALLX_N) {
927 case 0: /*RET*/
928 case 2: /*JX*/
929 gen_window_check1(dc, CALLX_S);
930 gen_jump(dc, cpu_R[CALLX_S]);
931 break;
932
933 case 1: /*RETWw*/
934 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
935 {
936 TCGv_i32 tmp = tcg_const_i32(dc->pc);
937 gen_advance_ccount(dc);
938 gen_helper_retw(tmp, cpu_env, tmp);
939 gen_jump(dc, tmp);
940 tcg_temp_free(tmp);
941 }
942 break;
943
944 case 3: /*reserved*/
945 RESERVED();
946 break;
947 }
948 break;
949
950 case 3: /*CALLX*/
951 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
952 switch (CALLX_N) {
953 case 0: /*CALLX0*/
954 {
955 TCGv_i32 tmp = tcg_temp_new_i32();
956 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
957 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
958 gen_jump(dc, tmp);
959 tcg_temp_free(tmp);
960 }
961 break;
962
963 case 1: /*CALLX4w*/
964 case 2: /*CALLX8w*/
965 case 3: /*CALLX12w*/
966 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
967 {
968 TCGv_i32 tmp = tcg_temp_new_i32();
969
970 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
971 gen_callw(dc, CALLX_N, tmp);
972 tcg_temp_free(tmp);
973 }
974 break;
975 }
976 break;
977 }
978 break;
979
980 case 1: /*MOVSPw*/
981 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
982 gen_window_check2(dc, RRR_T, RRR_S);
983 {
984 TCGv_i32 pc = tcg_const_i32(dc->pc);
985 gen_advance_ccount(dc);
986 gen_helper_movsp(cpu_env, pc);
987 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
988 tcg_temp_free(pc);
989 }
990 break;
991
992 case 2: /*SYNC*/
993 switch (RRR_T) {
994 case 0: /*ISYNC*/
995 break;
996
997 case 1: /*RSYNC*/
998 break;
999
1000 case 2: /*ESYNC*/
1001 break;
1002
1003 case 3: /*DSYNC*/
1004 break;
1005
1006 case 8: /*EXCW*/
1007 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1008 break;
1009
1010 case 12: /*MEMW*/
1011 break;
1012
1013 case 13: /*EXTW*/
1014 break;
1015
1016 case 15: /*NOP*/
1017 break;
1018
1019 default: /*reserved*/
1020 RESERVED();
1021 break;
1022 }
1023 break;
1024
1025 case 3: /*RFEIx*/
1026 switch (RRR_T) {
1027 case 0: /*RFETx*/
1028 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1029 switch (RRR_S) {
1030 case 0: /*RFEx*/
1031 gen_check_privilege(dc);
1032 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1033 gen_helper_check_interrupts(cpu_env);
1034 gen_jump(dc, cpu_SR[EPC1]);
1035 break;
1036
1037 case 1: /*RFUEx*/
1038 RESERVED();
1039 break;
1040
1041 case 2: /*RFDEx*/
1042 gen_check_privilege(dc);
1043 gen_jump(dc, cpu_SR[
1044 dc->config->ndepc ? DEPC : EPC1]);
1045 break;
1046
1047 case 4: /*RFWOw*/
1048 case 5: /*RFWUw*/
1049 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1050 gen_check_privilege(dc);
1051 {
1052 TCGv_i32 tmp = tcg_const_i32(1);
1053
1054 tcg_gen_andi_i32(
1055 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1056 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1057
1058 if (RRR_S == 4) {
1059 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1060 cpu_SR[WINDOW_START], tmp);
1061 } else {
1062 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1063 cpu_SR[WINDOW_START], tmp);
1064 }
1065
1066 gen_helper_restore_owb(cpu_env);
1067 gen_helper_check_interrupts(cpu_env);
1068 gen_jump(dc, cpu_SR[EPC1]);
1069
1070 tcg_temp_free(tmp);
1071 }
1072 break;
1073
1074 default: /*reserved*/
1075 RESERVED();
1076 break;
1077 }
1078 break;
1079
1080 case 1: /*RFIx*/
1081 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1082 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1083 gen_check_privilege(dc);
1084 tcg_gen_mov_i32(cpu_SR[PS],
1085 cpu_SR[EPS2 + RRR_S - 2]);
1086 gen_helper_check_interrupts(cpu_env);
1087 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1088 } else {
1089 qemu_log("RFI %d is illegal\n", RRR_S);
1090 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1091 }
1092 break;
1093
1094 case 2: /*RFME*/
1095 TBD();
1096 break;
1097
1098 default: /*reserved*/
1099 RESERVED();
1100 break;
1101
1102 }
1103 break;
1104
1105 case 4: /*BREAKx*/
1106 HAS_OPTION(XTENSA_OPTION_DEBUG);
1107 if (dc->debug) {
1108 gen_debug_exception(dc, DEBUGCAUSE_BI);
1109 }
1110 break;
1111
1112 case 5: /*SYSCALLx*/
1113 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1114 switch (RRR_S) {
1115 case 0: /*SYSCALLx*/
1116 gen_exception_cause(dc, SYSCALL_CAUSE);
1117 break;
1118
1119 case 1: /*SIMCALL*/
1120 if (semihosting_enabled) {
1121 gen_check_privilege(dc);
1122 gen_helper_simcall(cpu_env);
1123 } else {
1124 qemu_log("SIMCALL but semihosting is disabled\n");
1125 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1126 }
1127 break;
1128
1129 default:
1130 RESERVED();
1131 break;
1132 }
1133 break;
1134
1135 case 6: /*RSILx*/
1136 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1137 gen_check_privilege(dc);
1138 gen_window_check1(dc, RRR_T);
1139 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1140 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1141 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1142 gen_helper_check_interrupts(cpu_env);
1143 gen_jumpi_check_loop_end(dc, 0);
1144 break;
1145
1146 case 7: /*WAITIx*/
1147 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1148 gen_check_privilege(dc);
1149 gen_waiti(dc, RRR_S);
1150 break;
1151
1152 case 8: /*ANY4p*/
1153 case 9: /*ALL4p*/
1154 case 10: /*ANY8p*/
1155 case 11: /*ALL8p*/
1156 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1157 {
1158 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1159 TCGv_i32 mask = tcg_const_i32(
1160 ((1 << shift) - 1) << RRR_S);
1161 TCGv_i32 tmp = tcg_temp_new_i32();
1162
1163 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1164 if (RRR_R & 1) { /*ALL*/
1165 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1166 } else { /*ANY*/
1167 tcg_gen_add_i32(tmp, tmp, mask);
1168 }
1169 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1170 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1171 tmp, RRR_T, 1);
1172 tcg_temp_free(mask);
1173 tcg_temp_free(tmp);
1174 }
1175 break;
1176
1177 default: /*reserved*/
1178 RESERVED();
1179 break;
1180
1181 }
1182 break;
1183
1184 case 1: /*AND*/
1185 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1186 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1187 break;
1188
1189 case 2: /*OR*/
1190 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1191 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1192 break;
1193
1194 case 3: /*XOR*/
1195 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1196 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1197 break;
1198
1199 case 4: /*ST1*/
1200 switch (RRR_R) {
1201 case 0: /*SSR*/
1202 gen_window_check1(dc, RRR_S);
1203 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1204 break;
1205
1206 case 1: /*SSL*/
1207 gen_window_check1(dc, RRR_S);
1208 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1209 break;
1210
1211 case 2: /*SSA8L*/
1212 gen_window_check1(dc, RRR_S);
1213 {
1214 TCGv_i32 tmp = tcg_temp_new_i32();
1215 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1216 gen_right_shift_sar(dc, tmp);
1217 tcg_temp_free(tmp);
1218 }
1219 break;
1220
1221 case 3: /*SSA8B*/
1222 gen_window_check1(dc, RRR_S);
1223 {
1224 TCGv_i32 tmp = tcg_temp_new_i32();
1225 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1226 gen_left_shift_sar(dc, tmp);
1227 tcg_temp_free(tmp);
1228 }
1229 break;
1230
1231 case 4: /*SSAI*/
1232 {
1233 TCGv_i32 tmp = tcg_const_i32(
1234 RRR_S | ((RRR_T & 1) << 4));
1235 gen_right_shift_sar(dc, tmp);
1236 tcg_temp_free(tmp);
1237 }
1238 break;
1239
1240 case 6: /*RER*/
1241 TBD();
1242 break;
1243
1244 case 7: /*WER*/
1245 TBD();
1246 break;
1247
1248 case 8: /*ROTWw*/
1249 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1250 gen_check_privilege(dc);
1251 {
1252 TCGv_i32 tmp = tcg_const_i32(
1253 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1254 gen_helper_rotw(cpu_env, tmp);
1255 tcg_temp_free(tmp);
1256 reset_used_window(dc);
1257 }
1258 break;
1259
1260 case 14: /*NSAu*/
1261 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1262 gen_window_check2(dc, RRR_S, RRR_T);
1263 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1264 break;
1265
1266 case 15: /*NSAUu*/
1267 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1268 gen_window_check2(dc, RRR_S, RRR_T);
1269 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1270 break;
1271
1272 default: /*reserved*/
1273 RESERVED();
1274 break;
1275 }
1276 break;
1277
1278 case 5: /*TLB*/
1279 HAS_OPTION_BITS(
1280 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1281 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1282 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1283 gen_check_privilege(dc);
1284 gen_window_check2(dc, RRR_S, RRR_T);
1285 {
1286 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1287
1288 switch (RRR_R & 7) {
1289 case 3: /*RITLB0*/ /*RDTLB0*/
1290 gen_helper_rtlb0(cpu_R[RRR_T],
1291 cpu_env, cpu_R[RRR_S], dtlb);
1292 break;
1293
1294 case 4: /*IITLB*/ /*IDTLB*/
1295 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1296 /* This could change memory mapping, so exit tb */
1297 gen_jumpi_check_loop_end(dc, -1);
1298 break;
1299
1300 case 5: /*PITLB*/ /*PDTLB*/
1301 tcg_gen_movi_i32(cpu_pc, dc->pc);
1302 gen_helper_ptlb(cpu_R[RRR_T],
1303 cpu_env, cpu_R[RRR_S], dtlb);
1304 break;
1305
1306 case 6: /*WITLB*/ /*WDTLB*/
1307 gen_helper_wtlb(
1308 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1309 /* This could change memory mapping, so exit tb */
1310 gen_jumpi_check_loop_end(dc, -1);
1311 break;
1312
1313 case 7: /*RITLB1*/ /*RDTLB1*/
1314 gen_helper_rtlb1(cpu_R[RRR_T],
1315 cpu_env, cpu_R[RRR_S], dtlb);
1316 break;
1317
1318 default:
1319 tcg_temp_free(dtlb);
1320 RESERVED();
1321 break;
1322 }
1323 tcg_temp_free(dtlb);
1324 }
1325 break;
1326
1327 case 6: /*RT0*/
1328 gen_window_check2(dc, RRR_R, RRR_T);
1329 switch (RRR_S) {
1330 case 0: /*NEG*/
1331 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1332 break;
1333
1334 case 1: /*ABS*/
1335 {
1336 int label = gen_new_label();
1337 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1338 tcg_gen_brcondi_i32(
1339 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1340 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1341 gen_set_label(label);
1342 }
1343 break;
1344
1345 default: /*reserved*/
1346 RESERVED();
1347 break;
1348 }
1349 break;
1350
1351 case 7: /*reserved*/
1352 RESERVED();
1353 break;
1354
1355 case 8: /*ADD*/
1356 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1357 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1358 break;
1359
1360 case 9: /*ADD**/
1361 case 10:
1362 case 11:
1363 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1364 {
1365 TCGv_i32 tmp = tcg_temp_new_i32();
1366 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1367 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1368 tcg_temp_free(tmp);
1369 }
1370 break;
1371
1372 case 12: /*SUB*/
1373 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1374 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1375 break;
1376
1377 case 13: /*SUB**/
1378 case 14:
1379 case 15:
1380 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1381 {
1382 TCGv_i32 tmp = tcg_temp_new_i32();
1383 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1384 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1385 tcg_temp_free(tmp);
1386 }
1387 break;
1388 }
1389 break;
1390
1391 case 1: /*RST1*/
1392 switch (OP2) {
1393 case 0: /*SLLI*/
1394 case 1:
1395 gen_window_check2(dc, RRR_R, RRR_S);
1396 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1397 32 - (RRR_T | ((OP2 & 1) << 4)));
1398 break;
1399
1400 case 2: /*SRAI*/
1401 case 3:
1402 gen_window_check2(dc, RRR_R, RRR_T);
1403 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1404 RRR_S | ((OP2 & 1) << 4));
1405 break;
1406
1407 case 4: /*SRLI*/
1408 gen_window_check2(dc, RRR_R, RRR_T);
1409 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1410 break;
1411
1412 case 6: /*XSR*/
1413 {
1414 TCGv_i32 tmp = tcg_temp_new_i32();
1415 if (RSR_SR >= 64) {
1416 gen_check_privilege(dc);
1417 }
1418 gen_window_check1(dc, RRR_T);
1419 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1420 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1421 gen_wsr(dc, RSR_SR, tmp);
1422 tcg_temp_free(tmp);
1423 if (!sregnames[RSR_SR]) {
1424 TBD();
1425 }
1426 }
1427 break;
1428
1429 /*
1430 * Note: 64 bit ops are used here solely because SAR values
1431 * have range 0..63
1432 */
1433 #define gen_shift_reg(cmd, reg) do { \
1434 TCGv_i64 tmp = tcg_temp_new_i64(); \
1435 tcg_gen_extu_i32_i64(tmp, reg); \
1436 tcg_gen_##cmd##_i64(v, v, tmp); \
1437 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1438 tcg_temp_free_i64(v); \
1439 tcg_temp_free_i64(tmp); \
1440 } while (0)
1441
1442 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1443
1444 case 8: /*SRC*/
1445 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1446 {
1447 TCGv_i64 v = tcg_temp_new_i64();
1448 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1449 gen_shift(shr);
1450 }
1451 break;
1452
1453 case 9: /*SRL*/
1454 gen_window_check2(dc, RRR_R, RRR_T);
1455 if (dc->sar_5bit) {
1456 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1457 } else {
1458 TCGv_i64 v = tcg_temp_new_i64();
1459 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1460 gen_shift(shr);
1461 }
1462 break;
1463
1464 case 10: /*SLL*/
1465 gen_window_check2(dc, RRR_R, RRR_S);
1466 if (dc->sar_m32_5bit) {
1467 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1468 } else {
1469 TCGv_i64 v = tcg_temp_new_i64();
1470 TCGv_i32 s = tcg_const_i32(32);
1471 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1472 tcg_gen_andi_i32(s, s, 0x3f);
1473 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1474 gen_shift_reg(shl, s);
1475 tcg_temp_free(s);
1476 }
1477 break;
1478
1479 case 11: /*SRA*/
1480 gen_window_check2(dc, RRR_R, RRR_T);
1481 if (dc->sar_5bit) {
1482 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1483 } else {
1484 TCGv_i64 v = tcg_temp_new_i64();
1485 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1486 gen_shift(sar);
1487 }
1488 break;
1489 #undef gen_shift
1490 #undef gen_shift_reg
1491
1492 case 12: /*MUL16U*/
1493 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1494 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1495 {
1496 TCGv_i32 v1 = tcg_temp_new_i32();
1497 TCGv_i32 v2 = tcg_temp_new_i32();
1498 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1499 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1500 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1501 tcg_temp_free(v2);
1502 tcg_temp_free(v1);
1503 }
1504 break;
1505
1506 case 13: /*MUL16S*/
1507 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1508 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1509 {
1510 TCGv_i32 v1 = tcg_temp_new_i32();
1511 TCGv_i32 v2 = tcg_temp_new_i32();
1512 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1513 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1514 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1515 tcg_temp_free(v2);
1516 tcg_temp_free(v1);
1517 }
1518 break;
1519
1520 default: /*reserved*/
1521 RESERVED();
1522 break;
1523 }
1524 break;
1525
1526 case 2: /*RST2*/
1527 if (OP2 >= 8) {
1528 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1529 }
1530
1531 if (OP2 >= 12) {
1532 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1533 int label = gen_new_label();
1534 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1535 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1536 gen_set_label(label);
1537 }
1538
1539 switch (OP2) {
1540 #define BOOLEAN_LOGIC(fn, r, s, t) \
1541 do { \
1542 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1543 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1544 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1545 \
1546 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1547 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1548 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1549 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1550 tcg_temp_free(tmp1); \
1551 tcg_temp_free(tmp2); \
1552 } while (0)
1553
1554 case 0: /*ANDBp*/
1555 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1556 break;
1557
1558 case 1: /*ANDBCp*/
1559 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1560 break;
1561
1562 case 2: /*ORBp*/
1563 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1564 break;
1565
1566 case 3: /*ORBCp*/
1567 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1568 break;
1569
1570 case 4: /*XORBp*/
1571 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1572 break;
1573
1574 #undef BOOLEAN_LOGIC
1575
1576 case 8: /*MULLi*/
1577 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1578 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1579 break;
1580
1581 case 10: /*MULUHi*/
1582 case 11: /*MULSHi*/
1583 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1584 {
1585 TCGv_i64 r = tcg_temp_new_i64();
1586 TCGv_i64 s = tcg_temp_new_i64();
1587 TCGv_i64 t = tcg_temp_new_i64();
1588
1589 if (OP2 == 10) {
1590 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1591 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1592 } else {
1593 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1594 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1595 }
1596 tcg_gen_mul_i64(r, s, t);
1597 tcg_gen_shri_i64(r, r, 32);
1598 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1599
1600 tcg_temp_free_i64(r);
1601 tcg_temp_free_i64(s);
1602 tcg_temp_free_i64(t);
1603 }
1604 break;
1605
1606 case 12: /*QUOUi*/
1607 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1608 break;
1609
1610 case 13: /*QUOSi*/
1611 case 15: /*REMSi*/
1612 {
1613 int label1 = gen_new_label();
1614 int label2 = gen_new_label();
1615
1616 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1617 label1);
1618 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1619 label1);
1620 tcg_gen_movi_i32(cpu_R[RRR_R],
1621 OP2 == 13 ? 0x80000000 : 0);
1622 tcg_gen_br(label2);
1623 gen_set_label(label1);
1624 if (OP2 == 13) {
1625 tcg_gen_div_i32(cpu_R[RRR_R],
1626 cpu_R[RRR_S], cpu_R[RRR_T]);
1627 } else {
1628 tcg_gen_rem_i32(cpu_R[RRR_R],
1629 cpu_R[RRR_S], cpu_R[RRR_T]);
1630 }
1631 gen_set_label(label2);
1632 }
1633 break;
1634
1635 case 14: /*REMUi*/
1636 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1637 break;
1638
1639 default: /*reserved*/
1640 RESERVED();
1641 break;
1642 }
1643 break;
1644
1645 case 3: /*RST3*/
1646 switch (OP2) {
1647 case 0: /*RSR*/
1648 if (RSR_SR >= 64) {
1649 gen_check_privilege(dc);
1650 }
1651 gen_window_check1(dc, RRR_T);
1652 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1653 if (!sregnames[RSR_SR]) {
1654 TBD();
1655 }
1656 break;
1657
1658 case 1: /*WSR*/
1659 if (RSR_SR >= 64) {
1660 gen_check_privilege(dc);
1661 }
1662 gen_window_check1(dc, RRR_T);
1663 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1664 if (!sregnames[RSR_SR]) {
1665 TBD();
1666 }
1667 break;
1668
1669 case 2: /*SEXTu*/
1670 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1671 gen_window_check2(dc, RRR_R, RRR_S);
1672 {
1673 int shift = 24 - RRR_T;
1674
1675 if (shift == 24) {
1676 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1677 } else if (shift == 16) {
1678 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1679 } else {
1680 TCGv_i32 tmp = tcg_temp_new_i32();
1681 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1682 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1683 tcg_temp_free(tmp);
1684 }
1685 }
1686 break;
1687
1688 case 3: /*CLAMPSu*/
1689 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1690 gen_window_check2(dc, RRR_R, RRR_S);
1691 {
1692 TCGv_i32 tmp1 = tcg_temp_new_i32();
1693 TCGv_i32 tmp2 = tcg_temp_new_i32();
1694 int label = gen_new_label();
1695
1696 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1697 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1698 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1699 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1700 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1701
1702 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1703 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1704 0xffffffff >> (25 - RRR_T));
1705
1706 gen_set_label(label);
1707
1708 tcg_temp_free(tmp1);
1709 tcg_temp_free(tmp2);
1710 }
1711 break;
1712
1713 case 4: /*MINu*/
1714 case 5: /*MAXu*/
1715 case 6: /*MINUu*/
1716 case 7: /*MAXUu*/
1717 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1718 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1719 {
1720 static const TCGCond cond[] = {
1721 TCG_COND_LE,
1722 TCG_COND_GE,
1723 TCG_COND_LEU,
1724 TCG_COND_GEU
1725 };
1726 int label = gen_new_label();
1727
1728 if (RRR_R != RRR_T) {
1729 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1730 tcg_gen_brcond_i32(cond[OP2 - 4],
1731 cpu_R[RRR_S], cpu_R[RRR_T], label);
1732 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1733 } else {
1734 tcg_gen_brcond_i32(cond[OP2 - 4],
1735 cpu_R[RRR_T], cpu_R[RRR_S], label);
1736 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1737 }
1738 gen_set_label(label);
1739 }
1740 break;
1741
1742 case 8: /*MOVEQZ*/
1743 case 9: /*MOVNEZ*/
1744 case 10: /*MOVLTZ*/
1745 case 11: /*MOVGEZ*/
1746 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1747 {
1748 static const TCGCond cond[] = {
1749 TCG_COND_NE,
1750 TCG_COND_EQ,
1751 TCG_COND_GE,
1752 TCG_COND_LT
1753 };
1754 int label = gen_new_label();
1755 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1756 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1757 gen_set_label(label);
1758 }
1759 break;
1760
1761 case 12: /*MOVFp*/
1762 case 13: /*MOVTp*/
1763 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1764 gen_window_check2(dc, RRR_R, RRR_S);
1765 {
1766 int label = gen_new_label();
1767 TCGv_i32 tmp = tcg_temp_new_i32();
1768
1769 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1770 tcg_gen_brcondi_i32(
1771 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1772 tmp, 0, label);
1773 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1774 gen_set_label(label);
1775 tcg_temp_free(tmp);
1776 }
1777 break;
1778
1779 case 14: /*RUR*/
1780 gen_window_check1(dc, RRR_R);
1781 {
1782 int st = (RRR_S << 4) + RRR_T;
1783 if (uregnames[st]) {
1784 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1785 } else {
1786 qemu_log("RUR %d not implemented, ", st);
1787 TBD();
1788 }
1789 }
1790 break;
1791
1792 case 15: /*WUR*/
1793 gen_window_check1(dc, RRR_T);
1794 if (uregnames[RSR_SR]) {
1795 gen_wur(RSR_SR, cpu_R[RRR_T]);
1796 } else {
1797 qemu_log("WUR %d not implemented, ", RSR_SR);
1798 TBD();
1799 }
1800 break;
1801
1802 }
1803 break;
1804
1805 case 4: /*EXTUI*/
1806 case 5:
1807 gen_window_check2(dc, RRR_R, RRR_T);
1808 {
1809 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1810 int maskimm = (1 << (OP2 + 1)) - 1;
1811
1812 TCGv_i32 tmp = tcg_temp_new_i32();
1813
1814 if (shiftimm) {
1815 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1816 } else {
1817 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1818 }
1819
1820 switch (maskimm) {
1821 case 0xff:
1822 tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
1823 break;
1824
1825 case 0xffff:
1826 tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
1827 break;
1828
1829 default:
1830 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1831 break;
1832 }
1833 tcg_temp_free(tmp);
1834 }
1835 break;
1836
1837 case 6: /*CUST0*/
1838 RESERVED();
1839 break;
1840
1841 case 7: /*CUST1*/
1842 RESERVED();
1843 break;
1844
1845 case 8: /*LSCXp*/
1846 switch (OP2) {
1847 case 0: /*LSXf*/
1848 case 1: /*LSXUf*/
1849 case 4: /*SSXf*/
1850 case 5: /*SSXUf*/
1851 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1852 gen_window_check2(dc, RRR_S, RRR_T);
1853 {
1854 TCGv_i32 addr = tcg_temp_new_i32();
1855 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1856 gen_load_store_alignment(dc, 2, addr, false);
1857 if (OP2 & 0x4) {
1858 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1859 } else {
1860 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1861 }
1862 if (OP2 & 0x1) {
1863 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1864 }
1865 tcg_temp_free(addr);
1866 }
1867 break;
1868
1869 default: /*reserved*/
1870 RESERVED();
1871 break;
1872 }
1873 break;
1874
1875 case 9: /*LSC4*/
1876 gen_window_check2(dc, RRR_S, RRR_T);
1877 switch (OP2) {
1878 case 0: /*L32E*/
1879 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1880 gen_check_privilege(dc);
1881 {
1882 TCGv_i32 addr = tcg_temp_new_i32();
1883 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1884 (0xffffffc0 | (RRR_R << 2)));
1885 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1886 tcg_temp_free(addr);
1887 }
1888 break;
1889
1890 case 4: /*S32E*/
1891 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1892 gen_check_privilege(dc);
1893 {
1894 TCGv_i32 addr = tcg_temp_new_i32();
1895 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1896 (0xffffffc0 | (RRR_R << 2)));
1897 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1898 tcg_temp_free(addr);
1899 }
1900 break;
1901
1902 default:
1903 RESERVED();
1904 break;
1905 }
1906 break;
1907
1908 case 10: /*FP0*/
1909 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1910 TBD();
1911 break;
1912
1913 case 11: /*FP1*/
1914 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1915 TBD();
1916 break;
1917
1918 default: /*reserved*/
1919 RESERVED();
1920 break;
1921 }
1922 break;
1923
1924 case 1: /*L32R*/
1925 gen_window_check1(dc, RRR_T);
1926 {
1927 TCGv_i32 tmp = tcg_const_i32(
1928 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1929 0 : ((dc->pc + 3) & ~3)) +
1930 (0xfffc0000 | (RI16_IMM16 << 2)));
1931
1932 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1933 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1934 }
1935 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
1936 tcg_temp_free(tmp);
1937 }
1938 break;
1939
1940 case 2: /*LSAI*/
1941 #define gen_load_store(type, shift) do { \
1942 TCGv_i32 addr = tcg_temp_new_i32(); \
1943 gen_window_check2(dc, RRI8_S, RRI8_T); \
1944 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1945 if (shift) { \
1946 gen_load_store_alignment(dc, shift, addr, false); \
1947 } \
1948 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1949 tcg_temp_free(addr); \
1950 } while (0)
1951
1952 switch (RRI8_R) {
1953 case 0: /*L8UI*/
1954 gen_load_store(ld8u, 0);
1955 break;
1956
1957 case 1: /*L16UI*/
1958 gen_load_store(ld16u, 1);
1959 break;
1960
1961 case 2: /*L32I*/
1962 gen_load_store(ld32u, 2);
1963 break;
1964
1965 case 4: /*S8I*/
1966 gen_load_store(st8, 0);
1967 break;
1968
1969 case 5: /*S16I*/
1970 gen_load_store(st16, 1);
1971 break;
1972
1973 case 6: /*S32I*/
1974 gen_load_store(st32, 2);
1975 break;
1976
1977 case 7: /*CACHEc*/
1978 if (RRI8_T < 8) {
1979 HAS_OPTION(XTENSA_OPTION_DCACHE);
1980 }
1981
1982 switch (RRI8_T) {
1983 case 0: /*DPFRc*/
1984 break;
1985
1986 case 1: /*DPFWc*/
1987 break;
1988
1989 case 2: /*DPFROc*/
1990 break;
1991
1992 case 3: /*DPFWOc*/
1993 break;
1994
1995 case 4: /*DHWBc*/
1996 break;
1997
1998 case 5: /*DHWBIc*/
1999 break;
2000
2001 case 6: /*DHIc*/
2002 break;
2003
2004 case 7: /*DIIc*/
2005 break;
2006
2007 case 8: /*DCEc*/
2008 switch (OP1) {
2009 case 0: /*DPFLl*/
2010 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2011 break;
2012
2013 case 2: /*DHUl*/
2014 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2015 break;
2016
2017 case 3: /*DIUl*/
2018 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2019 break;
2020
2021 case 4: /*DIWBc*/
2022 HAS_OPTION(XTENSA_OPTION_DCACHE);
2023 break;
2024
2025 case 5: /*DIWBIc*/
2026 HAS_OPTION(XTENSA_OPTION_DCACHE);
2027 break;
2028
2029 default: /*reserved*/
2030 RESERVED();
2031 break;
2032
2033 }
2034 break;
2035
2036 case 12: /*IPFc*/
2037 HAS_OPTION(XTENSA_OPTION_ICACHE);
2038 break;
2039
2040 case 13: /*ICEc*/
2041 switch (OP1) {
2042 case 0: /*IPFLl*/
2043 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2044 break;
2045
2046 case 2: /*IHUl*/
2047 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2048 break;
2049
2050 case 3: /*IIUl*/
2051 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2052 break;
2053
2054 default: /*reserved*/
2055 RESERVED();
2056 break;
2057 }
2058 break;
2059
2060 case 14: /*IHIc*/
2061 HAS_OPTION(XTENSA_OPTION_ICACHE);
2062 break;
2063
2064 case 15: /*IIIc*/
2065 HAS_OPTION(XTENSA_OPTION_ICACHE);
2066 break;
2067
2068 default: /*reserved*/
2069 RESERVED();
2070 break;
2071 }
2072 break;
2073
2074 case 9: /*L16SI*/
2075 gen_load_store(ld16s, 1);
2076 break;
2077 #undef gen_load_store
2078
2079 case 10: /*MOVI*/
2080 gen_window_check1(dc, RRI8_T);
2081 tcg_gen_movi_i32(cpu_R[RRI8_T],
2082 RRI8_IMM8 | (RRI8_S << 8) |
2083 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2084 break;
2085
2086 #define gen_load_store_no_hw_align(type) do { \
2087 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2088 gen_window_check2(dc, RRI8_S, RRI8_T); \
2089 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2090 gen_load_store_alignment(dc, 2, addr, true); \
2091 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2092 tcg_temp_free(addr); \
2093 } while (0)
2094
2095 case 11: /*L32AIy*/
2096 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2097 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2098 break;
2099
2100 case 12: /*ADDI*/
2101 gen_window_check2(dc, RRI8_S, RRI8_T);
2102 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2103 break;
2104
2105 case 13: /*ADDMI*/
2106 gen_window_check2(dc, RRI8_S, RRI8_T);
2107 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2108 break;
2109
2110 case 14: /*S32C1Iy*/
2111 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2112 gen_window_check2(dc, RRI8_S, RRI8_T);
2113 {
2114 int label = gen_new_label();
2115 TCGv_i32 tmp = tcg_temp_local_new_i32();
2116 TCGv_i32 addr = tcg_temp_local_new_i32();
2117
2118 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2119 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2120 gen_load_store_alignment(dc, 2, addr, true);
2121 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2122 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2123 cpu_SR[SCOMPARE1], label);
2124
2125 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2126
2127 gen_set_label(label);
2128 tcg_temp_free(addr);
2129 tcg_temp_free(tmp);
2130 }
2131 break;
2132
2133 case 15: /*S32RIy*/
2134 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2135 gen_load_store_no_hw_align(st32); /*TODO release?*/
2136 break;
2137 #undef gen_load_store_no_hw_align
2138
2139 default: /*reserved*/
2140 RESERVED();
2141 break;
2142 }
2143 break;
2144
2145 case 3: /*LSCIp*/
2146 switch (RRI8_R) {
2147 case 0: /*LSIf*/
2148 case 4: /*SSIf*/
2149 case 8: /*LSIUf*/
2150 case 12: /*SSIUf*/
2151 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2152 gen_window_check1(dc, RRI8_S);
2153 {
2154 TCGv_i32 addr = tcg_temp_new_i32();
2155 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2156 gen_load_store_alignment(dc, 2, addr, false);
2157 if (RRI8_R & 0x4) {
2158 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2159 } else {
2160 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2161 }
2162 if (RRI8_R & 0x8) {
2163 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2164 }
2165 tcg_temp_free(addr);
2166 }
2167 break;
2168
2169 default: /*reserved*/
2170 RESERVED();
2171 break;
2172 }
2173 break;
2174
2175 case 4: /*MAC16d*/
2176 HAS_OPTION(XTENSA_OPTION_MAC16);
2177 {
2178 enum {
2179 MAC16_UMUL = 0x0,
2180 MAC16_MUL = 0x4,
2181 MAC16_MULA = 0x8,
2182 MAC16_MULS = 0xc,
2183 MAC16_NONE = 0xf,
2184 } op = OP1 & 0xc;
2185 bool is_m1_sr = (OP2 & 0x3) == 2;
2186 bool is_m2_sr = (OP2 & 0xc) == 0;
2187 uint32_t ld_offset = 0;
2188
2189 if (OP2 > 9) {
2190 RESERVED();
2191 }
2192
2193 switch (OP2 & 2) {
2194 case 0: /*MACI?/MACC?*/
2195 is_m1_sr = true;
2196 ld_offset = (OP2 & 1) ? -4 : 4;
2197
2198 if (OP2 >= 8) { /*MACI/MACC*/
2199 if (OP1 == 0) { /*LDINC/LDDEC*/
2200 op = MAC16_NONE;
2201 } else {
2202 RESERVED();
2203 }
2204 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2205 RESERVED();
2206 }
2207 break;
2208
2209 case 2: /*MACD?/MACA?*/
2210 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2211 RESERVED();
2212 }
2213 break;
2214 }
2215
2216 if (op != MAC16_NONE) {
2217 if (!is_m1_sr) {
2218 gen_window_check1(dc, RRR_S);
2219 }
2220 if (!is_m2_sr) {
2221 gen_window_check1(dc, RRR_T);
2222 }
2223 }
2224
2225 {
2226 TCGv_i32 vaddr = tcg_temp_new_i32();
2227 TCGv_i32 mem32 = tcg_temp_new_i32();
2228
2229 if (ld_offset) {
2230 gen_window_check1(dc, RRR_S);
2231 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2232 gen_load_store_alignment(dc, 2, vaddr, false);
2233 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2234 }
2235 if (op != MAC16_NONE) {
2236 TCGv_i32 m1 = gen_mac16_m(
2237 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2238 OP1 & 1, op == MAC16_UMUL);
2239 TCGv_i32 m2 = gen_mac16_m(
2240 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2241 OP1 & 2, op == MAC16_UMUL);
2242
2243 if (op == MAC16_MUL || op == MAC16_UMUL) {
2244 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2245 if (op == MAC16_UMUL) {
2246 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2247 } else {
2248 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2249 }
2250 } else {
2251 TCGv_i32 res = tcg_temp_new_i32();
2252 TCGv_i64 res64 = tcg_temp_new_i64();
2253 TCGv_i64 tmp = tcg_temp_new_i64();
2254
2255 tcg_gen_mul_i32(res, m1, m2);
2256 tcg_gen_ext_i32_i64(res64, res);
2257 tcg_gen_concat_i32_i64(tmp,
2258 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2259 if (op == MAC16_MULA) {
2260 tcg_gen_add_i64(tmp, tmp, res64);
2261 } else {
2262 tcg_gen_sub_i64(tmp, tmp, res64);
2263 }
2264 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2265 tcg_gen_shri_i64(tmp, tmp, 32);
2266 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2267 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2268
2269 tcg_temp_free(res);
2270 tcg_temp_free_i64(res64);
2271 tcg_temp_free_i64(tmp);
2272 }
2273 tcg_temp_free(m1);
2274 tcg_temp_free(m2);
2275 }
2276 if (ld_offset) {
2277 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2278 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2279 }
2280 tcg_temp_free(vaddr);
2281 tcg_temp_free(mem32);
2282 }
2283 }
2284 break;
2285
2286 case 5: /*CALLN*/
2287 switch (CALL_N) {
2288 case 0: /*CALL0*/
2289 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2290 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2291 break;
2292
2293 case 1: /*CALL4w*/
2294 case 2: /*CALL8w*/
2295 case 3: /*CALL12w*/
2296 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2297 gen_window_check1(dc, CALL_N << 2);
2298 gen_callwi(dc, CALL_N,
2299 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2300 break;
2301 }
2302 break;
2303
2304 case 6: /*SI*/
2305 switch (CALL_N) {
2306 case 0: /*J*/
2307 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2308 break;
2309
2310 case 1: /*BZ*/
2311 gen_window_check1(dc, BRI12_S);
2312 {
2313 static const TCGCond cond[] = {
2314 TCG_COND_EQ, /*BEQZ*/
2315 TCG_COND_NE, /*BNEZ*/
2316 TCG_COND_LT, /*BLTZ*/
2317 TCG_COND_GE, /*BGEZ*/
2318 };
2319
2320 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2321 4 + BRI12_IMM12_SE);
2322 }
2323 break;
2324
2325 case 2: /*BI0*/
2326 gen_window_check1(dc, BRI8_S);
2327 {
2328 static const TCGCond cond[] = {
2329 TCG_COND_EQ, /*BEQI*/
2330 TCG_COND_NE, /*BNEI*/
2331 TCG_COND_LT, /*BLTI*/
2332 TCG_COND_GE, /*BGEI*/
2333 };
2334
2335 gen_brcondi(dc, cond[BRI8_M & 3],
2336 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2337 }
2338 break;
2339
2340 case 3: /*BI1*/
2341 switch (BRI8_M) {
2342 case 0: /*ENTRYw*/
2343 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2344 {
2345 TCGv_i32 pc = tcg_const_i32(dc->pc);
2346 TCGv_i32 s = tcg_const_i32(BRI12_S);
2347 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2348 gen_advance_ccount(dc);
2349 gen_helper_entry(cpu_env, pc, s, imm);
2350 tcg_temp_free(imm);
2351 tcg_temp_free(s);
2352 tcg_temp_free(pc);
2353 reset_used_window(dc);
2354 }
2355 break;
2356
2357 case 1: /*B1*/
2358 switch (BRI8_R) {
2359 case 0: /*BFp*/
2360 case 1: /*BTp*/
2361 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2362 {
2363 TCGv_i32 tmp = tcg_temp_new_i32();
2364 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2365 gen_brcondi(dc,
2366 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2367 tmp, 0, 4 + RRI8_IMM8_SE);
2368 tcg_temp_free(tmp);
2369 }
2370 break;
2371
2372 case 8: /*LOOP*/
2373 case 9: /*LOOPNEZ*/
2374 case 10: /*LOOPGTZ*/
2375 HAS_OPTION(XTENSA_OPTION_LOOP);
2376 gen_window_check1(dc, RRI8_S);
2377 {
2378 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2379 TCGv_i32 tmp = tcg_const_i32(lend);
2380
2381 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2382 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2383 gen_helper_wsr_lend(cpu_env, tmp);
2384 tcg_temp_free(tmp);
2385
2386 if (BRI8_R > 8) {
2387 int label = gen_new_label();
2388 tcg_gen_brcondi_i32(
2389 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2390 cpu_R[RRI8_S], 0, label);
2391 gen_jumpi(dc, lend, 1);
2392 gen_set_label(label);
2393 }
2394
2395 gen_jumpi(dc, dc->next_pc, 0);
2396 }
2397 break;
2398
2399 default: /*reserved*/
2400 RESERVED();
2401 break;
2402
2403 }
2404 break;
2405
2406 case 2: /*BLTUI*/
2407 case 3: /*BGEUI*/
2408 gen_window_check1(dc, BRI8_S);
2409 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2410 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2411 break;
2412 }
2413 break;
2414
2415 }
2416 break;
2417
2418 case 7: /*B*/
2419 {
2420 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2421
2422 switch (RRI8_R & 7) {
2423 case 0: /*BNONE*/ /*BANY*/
2424 gen_window_check2(dc, RRI8_S, RRI8_T);
2425 {
2426 TCGv_i32 tmp = tcg_temp_new_i32();
2427 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2428 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2429 tcg_temp_free(tmp);
2430 }
2431 break;
2432
2433 case 1: /*BEQ*/ /*BNE*/
2434 case 2: /*BLT*/ /*BGE*/
2435 case 3: /*BLTU*/ /*BGEU*/
2436 gen_window_check2(dc, RRI8_S, RRI8_T);
2437 {
2438 static const TCGCond cond[] = {
2439 [1] = TCG_COND_EQ,
2440 [2] = TCG_COND_LT,
2441 [3] = TCG_COND_LTU,
2442 [9] = TCG_COND_NE,
2443 [10] = TCG_COND_GE,
2444 [11] = TCG_COND_GEU,
2445 };
2446 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2447 4 + RRI8_IMM8_SE);
2448 }
2449 break;
2450
2451 case 4: /*BALL*/ /*BNALL*/
2452 gen_window_check2(dc, RRI8_S, RRI8_T);
2453 {
2454 TCGv_i32 tmp = tcg_temp_new_i32();
2455 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2456 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2457 4 + RRI8_IMM8_SE);
2458 tcg_temp_free(tmp);
2459 }
2460 break;
2461
2462 case 5: /*BBC*/ /*BBS*/
2463 gen_window_check2(dc, RRI8_S, RRI8_T);
2464 {
2465 #ifdef TARGET_WORDS_BIGENDIAN
2466 TCGv_i32 bit = tcg_const_i32(0x80000000);
2467 #else
2468 TCGv_i32 bit = tcg_const_i32(0x00000001);
2469 #endif
2470 TCGv_i32 tmp = tcg_temp_new_i32();
2471 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2472 #ifdef TARGET_WORDS_BIGENDIAN
2473 tcg_gen_shr_i32(bit, bit, tmp);
2474 #else
2475 tcg_gen_shl_i32(bit, bit, tmp);
2476 #endif
2477 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2478 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2479 tcg_temp_free(tmp);
2480 tcg_temp_free(bit);
2481 }
2482 break;
2483
2484 case 6: /*BBCI*/ /*BBSI*/
2485 case 7:
2486 gen_window_check1(dc, RRI8_S);
2487 {
2488 TCGv_i32 tmp = tcg_temp_new_i32();
2489 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2490 #ifdef TARGET_WORDS_BIGENDIAN
2491 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2492 #else
2493 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2494 #endif
2495 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2496 tcg_temp_free(tmp);
2497 }
2498 break;
2499
2500 }
2501 }
2502 break;
2503
2504 #define gen_narrow_load_store(type) do { \
2505 TCGv_i32 addr = tcg_temp_new_i32(); \
2506 gen_window_check2(dc, RRRN_S, RRRN_T); \
2507 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2508 gen_load_store_alignment(dc, 2, addr, false); \
2509 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2510 tcg_temp_free(addr); \
2511 } while (0)
2512
2513 case 8: /*L32I.Nn*/
2514 gen_narrow_load_store(ld32u);
2515 break;
2516
2517 case 9: /*S32I.Nn*/
2518 gen_narrow_load_store(st32);
2519 break;
2520 #undef gen_narrow_load_store
2521
2522 case 10: /*ADD.Nn*/
2523 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2524 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2525 break;
2526
2527 case 11: /*ADDI.Nn*/
2528 gen_window_check2(dc, RRRN_R, RRRN_S);
2529 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2530 break;
2531
2532 case 12: /*ST2n*/
2533 gen_window_check1(dc, RRRN_S);
2534 if (RRRN_T < 8) { /*MOVI.Nn*/
2535 tcg_gen_movi_i32(cpu_R[RRRN_S],
2536 RRRN_R | (RRRN_T << 4) |
2537 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2538 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2539 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2540
2541 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2542 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2543 }
2544 break;
2545
2546 case 13: /*ST3n*/
2547 switch (RRRN_R) {
2548 case 0: /*MOV.Nn*/
2549 gen_window_check2(dc, RRRN_S, RRRN_T);
2550 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2551 break;
2552
2553 case 15: /*S3*/
2554 switch (RRRN_T) {
2555 case 0: /*RET.Nn*/
2556 gen_jump(dc, cpu_R[0]);
2557 break;
2558
2559 case 1: /*RETW.Nn*/
2560 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2561 {
2562 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2563 gen_advance_ccount(dc);
2564 gen_helper_retw(tmp, cpu_env, tmp);
2565 gen_jump(dc, tmp);
2566 tcg_temp_free(tmp);
2567 }
2568 break;
2569
2570 case 2: /*BREAK.Nn*/
2571 HAS_OPTION(XTENSA_OPTION_DEBUG);
2572 if (dc->debug) {
2573 gen_debug_exception(dc, DEBUGCAUSE_BN);
2574 }
2575 break;
2576
2577 case 3: /*NOP.Nn*/
2578 break;
2579
2580 case 6: /*ILL.Nn*/
2581 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2582 break;
2583
2584 default: /*reserved*/
2585 RESERVED();
2586 break;
2587 }
2588 break;
2589
2590 default: /*reserved*/
2591 RESERVED();
2592 break;
2593 }
2594 break;
2595
2596 default: /*reserved*/
2597 RESERVED();
2598 break;
2599 }
2600
2601 if (dc->is_jmp == DISAS_NEXT) {
2602 gen_check_loop_end(dc, 0);
2603 }
2604 dc->pc = dc->next_pc;
2605
2606 return;
2607
2608 invalid_opcode:
2609 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2610 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2611 #undef HAS_OPTION
2612 }
2613
2614 static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
2615 {
2616 CPUBreakpoint *bp;
2617
2618 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2619 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2620 if (bp->pc == dc->pc) {
2621 tcg_gen_movi_i32(cpu_pc, dc->pc);
2622 gen_exception(dc, EXCP_DEBUG);
2623 dc->is_jmp = DISAS_UPDATE;
2624 }
2625 }
2626 }
2627 }
2628
2629 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
2630 {
2631 unsigned i;
2632
2633 for (i = 0; i < dc->config->nibreak; ++i) {
2634 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2635 env->sregs[IBREAKA + i] == dc->pc) {
2636 gen_debug_exception(dc, DEBUGCAUSE_IB);
2637 break;
2638 }
2639 }
2640 }
2641
2642 static void gen_intermediate_code_internal(
2643 CPUXtensaState *env, TranslationBlock *tb, int search_pc)
2644 {
2645 DisasContext dc;
2646 int insn_count = 0;
2647 int j, lj = -1;
2648 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2649 int max_insns = tb->cflags & CF_COUNT_MASK;
2650 uint32_t pc_start = tb->pc;
2651 uint32_t next_page_start =
2652 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2653
2654 if (max_insns == 0) {
2655 max_insns = CF_COUNT_MASK;
2656 }
2657
2658 dc.config = env->config;
2659 dc.singlestep_enabled = env->singlestep_enabled;
2660 dc.tb = tb;
2661 dc.pc = pc_start;
2662 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2663 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
2664 dc.lbeg = env->sregs[LBEG];
2665 dc.lend = env->sregs[LEND];
2666 dc.is_jmp = DISAS_NEXT;
2667 dc.ccount_delta = 0;
2668 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
2669 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
2670
2671 init_litbase(&dc);
2672 init_sar_tracker(&dc);
2673 reset_used_window(&dc);
2674 if (dc.icount) {
2675 dc.next_icount = tcg_temp_local_new_i32();
2676 }
2677
2678 gen_icount_start();
2679
2680 if (env->singlestep_enabled && env->exception_taken) {
2681 env->exception_taken = 0;
2682 tcg_gen_movi_i32(cpu_pc, dc.pc);
2683 gen_exception(&dc, EXCP_DEBUG);
2684 }
2685
2686 do {
2687 check_breakpoint(env, &dc);
2688
2689 if (search_pc) {
2690 j = gen_opc_ptr - gen_opc_buf;
2691 if (lj < j) {
2692 lj++;
2693 while (lj < j) {
2694 gen_opc_instr_start[lj++] = 0;
2695 }
2696 }
2697 gen_opc_pc[lj] = dc.pc;
2698 gen_opc_instr_start[lj] = 1;
2699 gen_opc_icount[lj] = insn_count;
2700 }
2701
2702 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2703 tcg_gen_debug_insn_start(dc.pc);
2704 }
2705
2706 ++dc.ccount_delta;
2707
2708 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2709 gen_io_start();
2710 }
2711
2712 if (dc.icount) {
2713 int label = gen_new_label();
2714
2715 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2716 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2717 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2718 if (dc.debug) {
2719 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2720 }
2721 gen_set_label(label);
2722 }
2723
2724 if (dc.debug) {
2725 gen_ibreak_check(env, &dc);
2726 }
2727
2728 disas_xtensa_insn(&dc);
2729 ++insn_count;
2730 if (dc.icount) {
2731 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2732 }
2733 if (env->singlestep_enabled) {
2734 tcg_gen_movi_i32(cpu_pc, dc.pc);
2735 gen_exception(&dc, EXCP_DEBUG);
2736 break;
2737 }
2738 } while (dc.is_jmp == DISAS_NEXT &&
2739 insn_count < max_insns &&
2740 dc.pc < next_page_start &&
2741 gen_opc_ptr < gen_opc_end);
2742
2743 reset_litbase(&dc);
2744 reset_sar_tracker(&dc);
2745 if (dc.icount) {
2746 tcg_temp_free(dc.next_icount);
2747 }
2748
2749 if (tb->cflags & CF_LAST_IO) {
2750 gen_io_end();
2751 }
2752
2753 if (dc.is_jmp == DISAS_NEXT) {
2754 gen_jumpi(&dc, dc.pc, 0);
2755 }
2756 gen_icount_end(tb, insn_count);
2757 *gen_opc_ptr = INDEX_op_end;
2758
2759 if (!search_pc) {
2760 tb->size = dc.pc - pc_start;
2761 tb->icount = insn_count;
2762 }
2763 }
2764
2765 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
2766 {
2767 gen_intermediate_code_internal(env, tb, 0);
2768 }
2769
2770 void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
2771 {
2772 gen_intermediate_code_internal(env, tb, 1);
2773 }
2774
2775 void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
2776 int flags)
2777 {
2778 int i, j;
2779
2780 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2781
2782 for (i = j = 0; i < 256; ++i) {
2783 if (sregnames[i]) {
2784 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2785 (j++ % 4) == 3 ? '\n' : ' ');
2786 }
2787 }
2788
2789 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2790
2791 for (i = j = 0; i < 256; ++i) {
2792 if (uregnames[i]) {
2793 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2794 (j++ % 4) == 3 ? '\n' : ' ');
2795 }
2796 }
2797
2798 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2799
2800 for (i = 0; i < 16; ++i) {
2801 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2802 (i % 4) == 3 ? '\n' : ' ');
2803 }
2804
2805 cpu_fprintf(f, "\n");
2806
2807 for (i = 0; i < env->config->nareg; ++i) {
2808 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2809 (i % 4) == 3 ? '\n' : ' ');
2810 }
2811
2812 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
2813 cpu_fprintf(f, "\n");
2814
2815 for (i = 0; i < 16; ++i) {
2816 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
2817 float32_val(env->fregs[i]),
2818 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
2819 }
2820 }
2821 }
2822
2823 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
2824 {
2825 env->pc = gen_opc_pc[pc_pos];
2826 }
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