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Merge remote-tracking branch 'aneesh/for-upstream-4' into staging
[mirror_qemu.git] / target-xtensa / translate.c
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec-all.h"
35 #include "disas.h"
36 #include "tcg-op.h"
37 #include "qemu-log.h"
38 #include "sysemu.h"
39
40 #include "helpers.h"
41 #define GEN_HELPER 1
42 #include "helpers.h"
43
44 typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
49 int cring;
50 int ring;
51 uint32_t lbeg;
52 uint32_t lend;
53 TCGv_i32 litbase;
54 int is_jmp;
55 int singlestep_enabled;
56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
61
62 uint32_t ccount_delta;
63 unsigned used_window;
64 } DisasContext;
65
66 static TCGv_ptr cpu_env;
67 static TCGv_i32 cpu_pc;
68 static TCGv_i32 cpu_R[16];
69 static TCGv_i32 cpu_SR[256];
70 static TCGv_i32 cpu_UR[256];
71
72 #include "gen-icount.h"
73
74 static const char * const sregnames[256] = {
75 [LBEG] = "LBEG",
76 [LEND] = "LEND",
77 [LCOUNT] = "LCOUNT",
78 [SAR] = "SAR",
79 [BR] = "BR",
80 [LITBASE] = "LITBASE",
81 [SCOMPARE1] = "SCOMPARE1",
82 [WINDOW_BASE] = "WINDOW_BASE",
83 [WINDOW_START] = "WINDOW_START",
84 [PTEVADDR] = "PTEVADDR",
85 [RASID] = "RASID",
86 [ITLBCFG] = "ITLBCFG",
87 [DTLBCFG] = "DTLBCFG",
88 [EPC1] = "EPC1",
89 [EPC1 + 1] = "EPC2",
90 [EPC1 + 2] = "EPC3",
91 [EPC1 + 3] = "EPC4",
92 [EPC1 + 4] = "EPC5",
93 [EPC1 + 5] = "EPC6",
94 [EPC1 + 6] = "EPC7",
95 [DEPC] = "DEPC",
96 [EPS2] = "EPS2",
97 [EPS2 + 1] = "EPS3",
98 [EPS2 + 2] = "EPS4",
99 [EPS2 + 3] = "EPS5",
100 [EPS2 + 4] = "EPS6",
101 [EPS2 + 5] = "EPS7",
102 [EXCSAVE1] = "EXCSAVE1",
103 [EXCSAVE1 + 1] = "EXCSAVE2",
104 [EXCSAVE1 + 2] = "EXCSAVE3",
105 [EXCSAVE1 + 3] = "EXCSAVE4",
106 [EXCSAVE1 + 4] = "EXCSAVE5",
107 [EXCSAVE1 + 5] = "EXCSAVE6",
108 [EXCSAVE1 + 6] = "EXCSAVE7",
109 [CPENABLE] = "CPENABLE",
110 [INTSET] = "INTSET",
111 [INTCLEAR] = "INTCLEAR",
112 [INTENABLE] = "INTENABLE",
113 [PS] = "PS",
114 [VECBASE] = "VECBASE",
115 [EXCCAUSE] = "EXCCAUSE",
116 [CCOUNT] = "CCOUNT",
117 [PRID] = "PRID",
118 [EXCVADDR] = "EXCVADDR",
119 [CCOMPARE] = "CCOMPARE0",
120 [CCOMPARE + 1] = "CCOMPARE1",
121 [CCOMPARE + 2] = "CCOMPARE2",
122 };
123
124 static const char * const uregnames[256] = {
125 [THREADPTR] = "THREADPTR",
126 [FCR] = "FCR",
127 [FSR] = "FSR",
128 };
129
130 void xtensa_translate_init(void)
131 {
132 static const char * const regnames[] = {
133 "ar0", "ar1", "ar2", "ar3",
134 "ar4", "ar5", "ar6", "ar7",
135 "ar8", "ar9", "ar10", "ar11",
136 "ar12", "ar13", "ar14", "ar15",
137 };
138 int i;
139
140 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
141 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
142 offsetof(CPUState, pc), "pc");
143
144 for (i = 0; i < 16; i++) {
145 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
146 offsetof(CPUState, regs[i]),
147 regnames[i]);
148 }
149
150 for (i = 0; i < 256; ++i) {
151 if (sregnames[i]) {
152 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
153 offsetof(CPUState, sregs[i]),
154 sregnames[i]);
155 }
156 }
157
158 for (i = 0; i < 256; ++i) {
159 if (uregnames[i]) {
160 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, uregs[i]),
162 uregnames[i]);
163 }
164 }
165 #define GEN_HELPER 2
166 #include "helpers.h"
167 }
168
169 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
170 {
171 return xtensa_option_bits_enabled(dc->config, opt);
172 }
173
174 static inline bool option_enabled(DisasContext *dc, int opt)
175 {
176 return xtensa_option_enabled(dc->config, opt);
177 }
178
179 static void init_litbase(DisasContext *dc)
180 {
181 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
182 dc->litbase = tcg_temp_local_new_i32();
183 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
184 }
185 }
186
187 static void reset_litbase(DisasContext *dc)
188 {
189 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
190 tcg_temp_free(dc->litbase);
191 }
192 }
193
194 static void init_sar_tracker(DisasContext *dc)
195 {
196 dc->sar_5bit = false;
197 dc->sar_m32_5bit = false;
198 dc->sar_m32_allocated = false;
199 }
200
201 static void reset_sar_tracker(DisasContext *dc)
202 {
203 if (dc->sar_m32_allocated) {
204 tcg_temp_free(dc->sar_m32);
205 }
206 }
207
208 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
209 {
210 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
211 if (dc->sar_m32_5bit) {
212 tcg_gen_discard_i32(dc->sar_m32);
213 }
214 dc->sar_5bit = true;
215 dc->sar_m32_5bit = false;
216 }
217
218 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
219 {
220 TCGv_i32 tmp = tcg_const_i32(32);
221 if (!dc->sar_m32_allocated) {
222 dc->sar_m32 = tcg_temp_local_new_i32();
223 dc->sar_m32_allocated = true;
224 }
225 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
226 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
227 dc->sar_5bit = false;
228 dc->sar_m32_5bit = true;
229 tcg_temp_free(tmp);
230 }
231
232 static void gen_advance_ccount(DisasContext *dc)
233 {
234 if (dc->ccount_delta > 0) {
235 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
236 dc->ccount_delta = 0;
237 gen_helper_advance_ccount(tmp);
238 tcg_temp_free(tmp);
239 }
240 }
241
242 static void reset_used_window(DisasContext *dc)
243 {
244 dc->used_window = 0;
245 }
246
247 static void gen_exception(DisasContext *dc, int excp)
248 {
249 TCGv_i32 tmp = tcg_const_i32(excp);
250 gen_advance_ccount(dc);
251 gen_helper_exception(tmp);
252 tcg_temp_free(tmp);
253 }
254
255 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
256 {
257 TCGv_i32 tpc = tcg_const_i32(dc->pc);
258 TCGv_i32 tcause = tcg_const_i32(cause);
259 gen_advance_ccount(dc);
260 gen_helper_exception_cause(tpc, tcause);
261 tcg_temp_free(tpc);
262 tcg_temp_free(tcause);
263 }
264
265 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
266 TCGv_i32 vaddr)
267 {
268 TCGv_i32 tpc = tcg_const_i32(dc->pc);
269 TCGv_i32 tcause = tcg_const_i32(cause);
270 gen_advance_ccount(dc);
271 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
272 tcg_temp_free(tpc);
273 tcg_temp_free(tcause);
274 }
275
276 static void gen_check_privilege(DisasContext *dc)
277 {
278 if (dc->cring) {
279 gen_exception_cause(dc, PRIVILEGED_CAUSE);
280 }
281 }
282
283 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
284 {
285 tcg_gen_mov_i32(cpu_pc, dest);
286 if (dc->singlestep_enabled) {
287 gen_exception(dc, EXCP_DEBUG);
288 } else {
289 gen_advance_ccount(dc);
290 if (slot >= 0) {
291 tcg_gen_goto_tb(slot);
292 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
293 } else {
294 tcg_gen_exit_tb(0);
295 }
296 }
297 dc->is_jmp = DISAS_UPDATE;
298 }
299
300 static void gen_jump(DisasContext *dc, TCGv dest)
301 {
302 gen_jump_slot(dc, dest, -1);
303 }
304
305 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
306 {
307 TCGv_i32 tmp = tcg_const_i32(dest);
308 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
309 slot = -1;
310 }
311 gen_jump_slot(dc, tmp, slot);
312 tcg_temp_free(tmp);
313 }
314
315 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
316 int slot)
317 {
318 TCGv_i32 tcallinc = tcg_const_i32(callinc);
319
320 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
321 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
322 tcg_temp_free(tcallinc);
323 tcg_gen_movi_i32(cpu_R[callinc << 2],
324 (callinc << 30) | (dc->next_pc & 0x3fffffff));
325 gen_jump_slot(dc, dest, slot);
326 }
327
328 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
329 {
330 gen_callw_slot(dc, callinc, dest, -1);
331 }
332
333 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
334 {
335 TCGv_i32 tmp = tcg_const_i32(dest);
336 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
337 slot = -1;
338 }
339 gen_callw_slot(dc, callinc, tmp, slot);
340 tcg_temp_free(tmp);
341 }
342
343 static bool gen_check_loop_end(DisasContext *dc, int slot)
344 {
345 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
346 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
347 dc->next_pc == dc->lend) {
348 int label = gen_new_label();
349
350 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
351 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
352 gen_jumpi(dc, dc->lbeg, slot);
353 gen_set_label(label);
354 gen_jumpi(dc, dc->next_pc, -1);
355 return true;
356 }
357 return false;
358 }
359
360 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
361 {
362 if (!gen_check_loop_end(dc, slot)) {
363 gen_jumpi(dc, dc->next_pc, slot);
364 }
365 }
366
367 static void gen_brcond(DisasContext *dc, TCGCond cond,
368 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
369 {
370 int label = gen_new_label();
371
372 tcg_gen_brcond_i32(cond, t0, t1, label);
373 gen_jumpi_check_loop_end(dc, 0);
374 gen_set_label(label);
375 gen_jumpi(dc, dc->pc + offset, 1);
376 }
377
378 static void gen_brcondi(DisasContext *dc, TCGCond cond,
379 TCGv_i32 t0, uint32_t t1, uint32_t offset)
380 {
381 TCGv_i32 tmp = tcg_const_i32(t1);
382 gen_brcond(dc, cond, t0, tmp, offset);
383 tcg_temp_free(tmp);
384 }
385
386 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
387 {
388 gen_advance_ccount(dc);
389 tcg_gen_mov_i32(d, cpu_SR[sr]);
390 }
391
392 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
393 {
394 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
395 tcg_gen_or_i32(d, d, cpu_SR[sr]);
396 tcg_gen_andi_i32(d, d, 0xfffffffc);
397 }
398
399 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
400 {
401 static void (* const rsr_handler[256])(DisasContext *dc,
402 TCGv_i32 d, uint32_t sr) = {
403 [CCOUNT] = gen_rsr_ccount,
404 [PTEVADDR] = gen_rsr_ptevaddr,
405 };
406
407 if (sregnames[sr]) {
408 if (rsr_handler[sr]) {
409 rsr_handler[sr](dc, d, sr);
410 } else {
411 tcg_gen_mov_i32(d, cpu_SR[sr]);
412 }
413 } else {
414 qemu_log("RSR %d not implemented, ", sr);
415 }
416 }
417
418 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
419 {
420 gen_helper_wsr_lbeg(s);
421 }
422
423 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
424 {
425 gen_helper_wsr_lend(s);
426 }
427
428 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
429 {
430 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
431 if (dc->sar_m32_5bit) {
432 tcg_gen_discard_i32(dc->sar_m32);
433 }
434 dc->sar_5bit = false;
435 dc->sar_m32_5bit = false;
436 }
437
438 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
439 {
440 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
441 }
442
443 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
444 {
445 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
446 /* This can change tb->flags, so exit tb */
447 gen_jumpi_check_loop_end(dc, -1);
448 }
449
450 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
451 {
452 gen_helper_wsr_windowbase(v);
453 reset_used_window(dc);
454 }
455
456 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
457 {
458 tcg_gen_mov_i32(cpu_SR[sr], v);
459 reset_used_window(dc);
460 }
461
462 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
463 {
464 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
465 }
466
467 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
468 {
469 gen_helper_wsr_rasid(v);
470 /* This can change tb->flags, so exit tb */
471 gen_jumpi_check_loop_end(dc, -1);
472 }
473
474 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
475 {
476 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
477 }
478
479 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
480 {
481 tcg_gen_andi_i32(cpu_SR[sr], v,
482 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
483 gen_helper_check_interrupts(cpu_env);
484 gen_jumpi_check_loop_end(dc, 0);
485 }
486
487 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
488 {
489 TCGv_i32 tmp = tcg_temp_new_i32();
490
491 tcg_gen_andi_i32(tmp, v,
492 dc->config->inttype_mask[INTTYPE_EDGE] |
493 dc->config->inttype_mask[INTTYPE_NMI] |
494 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
495 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
496 tcg_temp_free(tmp);
497 gen_helper_check_interrupts(cpu_env);
498 }
499
500 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
501 {
502 tcg_gen_mov_i32(cpu_SR[sr], v);
503 gen_helper_check_interrupts(cpu_env);
504 gen_jumpi_check_loop_end(dc, 0);
505 }
506
507 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
508 {
509 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
510 PS_UM | PS_EXCM | PS_INTLEVEL;
511
512 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
513 mask |= PS_RING;
514 }
515 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
516 reset_used_window(dc);
517 gen_helper_check_interrupts(cpu_env);
518 /* This can change mmu index and tb->flags, so exit tb */
519 gen_jumpi_check_loop_end(dc, -1);
520 }
521
522 static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
523 {
524 }
525
526 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
527 {
528 uint32_t id = sr - CCOMPARE;
529 if (id < dc->config->nccompare) {
530 uint32_t int_bit = 1 << dc->config->timerint[id];
531 gen_advance_ccount(dc);
532 tcg_gen_mov_i32(cpu_SR[sr], v);
533 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
534 gen_helper_check_interrupts(cpu_env);
535 }
536 }
537
538 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
539 {
540 static void (* const wsr_handler[256])(DisasContext *dc,
541 uint32_t sr, TCGv_i32 v) = {
542 [LBEG] = gen_wsr_lbeg,
543 [LEND] = gen_wsr_lend,
544 [SAR] = gen_wsr_sar,
545 [BR] = gen_wsr_br,
546 [LITBASE] = gen_wsr_litbase,
547 [WINDOW_BASE] = gen_wsr_windowbase,
548 [WINDOW_START] = gen_wsr_windowstart,
549 [PTEVADDR] = gen_wsr_ptevaddr,
550 [RASID] = gen_wsr_rasid,
551 [ITLBCFG] = gen_wsr_tlbcfg,
552 [DTLBCFG] = gen_wsr_tlbcfg,
553 [INTSET] = gen_wsr_intset,
554 [INTCLEAR] = gen_wsr_intclear,
555 [INTENABLE] = gen_wsr_intenable,
556 [PS] = gen_wsr_ps,
557 [PRID] = gen_wsr_prid,
558 [CCOMPARE] = gen_wsr_ccompare,
559 [CCOMPARE + 1] = gen_wsr_ccompare,
560 [CCOMPARE + 2] = gen_wsr_ccompare,
561 };
562
563 if (sregnames[sr]) {
564 if (wsr_handler[sr]) {
565 wsr_handler[sr](dc, sr, s);
566 } else {
567 tcg_gen_mov_i32(cpu_SR[sr], s);
568 }
569 } else {
570 qemu_log("WSR %d not implemented, ", sr);
571 }
572 }
573
574 static void gen_load_store_alignment(DisasContext *dc, int shift,
575 TCGv_i32 addr, bool no_hw_alignment)
576 {
577 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
578 tcg_gen_andi_i32(addr, addr, ~0 << shift);
579 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
580 no_hw_alignment) {
581 int label = gen_new_label();
582 TCGv_i32 tmp = tcg_temp_new_i32();
583 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
584 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
585 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
586 gen_set_label(label);
587 tcg_temp_free(tmp);
588 }
589 }
590
591 static void gen_waiti(DisasContext *dc, uint32_t imm4)
592 {
593 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
594 TCGv_i32 intlevel = tcg_const_i32(imm4);
595 gen_advance_ccount(dc);
596 gen_helper_waiti(pc, intlevel);
597 tcg_temp_free(pc);
598 tcg_temp_free(intlevel);
599 }
600
601 static void gen_window_check1(DisasContext *dc, unsigned r1)
602 {
603 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
604 return;
605 }
606 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
607 r1 / 4 > dc->used_window) {
608 TCGv_i32 pc = tcg_const_i32(dc->pc);
609 TCGv_i32 w = tcg_const_i32(r1 / 4);
610
611 dc->used_window = r1 / 4;
612 gen_advance_ccount(dc);
613 gen_helper_window_check(pc, w);
614
615 tcg_temp_free(w);
616 tcg_temp_free(pc);
617 }
618 }
619
620 static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
621 {
622 gen_window_check1(dc, r1 > r2 ? r1 : r2);
623 }
624
625 static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
626 unsigned r3)
627 {
628 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
629 }
630
631 static void disas_xtensa_insn(DisasContext *dc)
632 {
633 #define HAS_OPTION_BITS(opt) do { \
634 if (!option_bits_enabled(dc, opt)) { \
635 qemu_log("Option is not enabled %s:%d\n", \
636 __FILE__, __LINE__); \
637 goto invalid_opcode; \
638 } \
639 } while (0)
640
641 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
642
643 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
644 #define RESERVED() do { \
645 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
646 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
647 goto invalid_opcode; \
648 } while (0)
649
650
651 #ifdef TARGET_WORDS_BIGENDIAN
652 #define OP0 (((b0) & 0xf0) >> 4)
653 #define OP1 (((b2) & 0xf0) >> 4)
654 #define OP2 ((b2) & 0xf)
655 #define RRR_R ((b1) & 0xf)
656 #define RRR_S (((b1) & 0xf0) >> 4)
657 #define RRR_T ((b0) & 0xf)
658 #else
659 #define OP0 (((b0) & 0xf))
660 #define OP1 (((b2) & 0xf))
661 #define OP2 (((b2) & 0xf0) >> 4)
662 #define RRR_R (((b1) & 0xf0) >> 4)
663 #define RRR_S (((b1) & 0xf))
664 #define RRR_T (((b0) & 0xf0) >> 4)
665 #endif
666
667 #define RRRN_R RRR_R
668 #define RRRN_S RRR_S
669 #define RRRN_T RRR_T
670
671 #define RRI8_R RRR_R
672 #define RRI8_S RRR_S
673 #define RRI8_T RRR_T
674 #define RRI8_IMM8 (b2)
675 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
676
677 #ifdef TARGET_WORDS_BIGENDIAN
678 #define RI16_IMM16 (((b1) << 8) | (b2))
679 #else
680 #define RI16_IMM16 (((b2) << 8) | (b1))
681 #endif
682
683 #ifdef TARGET_WORDS_BIGENDIAN
684 #define CALL_N (((b0) & 0xc) >> 2)
685 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
686 #else
687 #define CALL_N (((b0) & 0x30) >> 4)
688 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
689 #endif
690 #define CALL_OFFSET_SE \
691 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
692
693 #define CALLX_N CALL_N
694 #ifdef TARGET_WORDS_BIGENDIAN
695 #define CALLX_M ((b0) & 0x3)
696 #else
697 #define CALLX_M (((b0) & 0xc0) >> 6)
698 #endif
699 #define CALLX_S RRR_S
700
701 #define BRI12_M CALLX_M
702 #define BRI12_S RRR_S
703 #ifdef TARGET_WORDS_BIGENDIAN
704 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
705 #else
706 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
707 #endif
708 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
709
710 #define BRI8_M BRI12_M
711 #define BRI8_R RRI8_R
712 #define BRI8_S RRI8_S
713 #define BRI8_IMM8 RRI8_IMM8
714 #define BRI8_IMM8_SE RRI8_IMM8_SE
715
716 #define RSR_SR (b1)
717
718 uint8_t b0 = ldub_code(dc->pc);
719 uint8_t b1 = ldub_code(dc->pc + 1);
720 uint8_t b2 = ldub_code(dc->pc + 2);
721
722 static const uint32_t B4CONST[] = {
723 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
724 };
725
726 static const uint32_t B4CONSTU[] = {
727 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
728 };
729
730 if (OP0 >= 8) {
731 dc->next_pc = dc->pc + 2;
732 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
733 } else {
734 dc->next_pc = dc->pc + 3;
735 }
736
737 switch (OP0) {
738 case 0: /*QRST*/
739 switch (OP1) {
740 case 0: /*RST0*/
741 switch (OP2) {
742 case 0: /*ST0*/
743 if ((RRR_R & 0xc) == 0x8) {
744 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
745 }
746
747 switch (RRR_R) {
748 case 0: /*SNM0*/
749 switch (CALLX_M) {
750 case 0: /*ILL*/
751 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
752 break;
753
754 case 1: /*reserved*/
755 RESERVED();
756 break;
757
758 case 2: /*JR*/
759 switch (CALLX_N) {
760 case 0: /*RET*/
761 case 2: /*JX*/
762 gen_window_check1(dc, CALLX_S);
763 gen_jump(dc, cpu_R[CALLX_S]);
764 break;
765
766 case 1: /*RETWw*/
767 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
768 {
769 TCGv_i32 tmp = tcg_const_i32(dc->pc);
770 gen_advance_ccount(dc);
771 gen_helper_retw(tmp, tmp);
772 gen_jump(dc, tmp);
773 tcg_temp_free(tmp);
774 }
775 break;
776
777 case 3: /*reserved*/
778 RESERVED();
779 break;
780 }
781 break;
782
783 case 3: /*CALLX*/
784 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
785 switch (CALLX_N) {
786 case 0: /*CALLX0*/
787 {
788 TCGv_i32 tmp = tcg_temp_new_i32();
789 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
790 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
791 gen_jump(dc, tmp);
792 tcg_temp_free(tmp);
793 }
794 break;
795
796 case 1: /*CALLX4w*/
797 case 2: /*CALLX8w*/
798 case 3: /*CALLX12w*/
799 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
800 {
801 TCGv_i32 tmp = tcg_temp_new_i32();
802
803 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
804 gen_callw(dc, CALLX_N, tmp);
805 tcg_temp_free(tmp);
806 }
807 break;
808 }
809 break;
810 }
811 break;
812
813 case 1: /*MOVSPw*/
814 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
815 gen_window_check2(dc, RRR_T, RRR_S);
816 {
817 TCGv_i32 pc = tcg_const_i32(dc->pc);
818 gen_advance_ccount(dc);
819 gen_helper_movsp(pc);
820 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
821 tcg_temp_free(pc);
822 }
823 break;
824
825 case 2: /*SYNC*/
826 switch (RRR_T) {
827 case 0: /*ISYNC*/
828 break;
829
830 case 1: /*RSYNC*/
831 break;
832
833 case 2: /*ESYNC*/
834 break;
835
836 case 3: /*DSYNC*/
837 break;
838
839 case 8: /*EXCW*/
840 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
841 break;
842
843 case 12: /*MEMW*/
844 break;
845
846 case 13: /*EXTW*/
847 break;
848
849 case 15: /*NOP*/
850 break;
851
852 default: /*reserved*/
853 RESERVED();
854 break;
855 }
856 break;
857
858 case 3: /*RFEIx*/
859 switch (RRR_T) {
860 case 0: /*RFETx*/
861 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
862 switch (RRR_S) {
863 case 0: /*RFEx*/
864 gen_check_privilege(dc);
865 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
866 gen_helper_check_interrupts(cpu_env);
867 gen_jump(dc, cpu_SR[EPC1]);
868 break;
869
870 case 1: /*RFUEx*/
871 RESERVED();
872 break;
873
874 case 2: /*RFDEx*/
875 gen_check_privilege(dc);
876 gen_jump(dc, cpu_SR[
877 dc->config->ndepc ? DEPC : EPC1]);
878 break;
879
880 case 4: /*RFWOw*/
881 case 5: /*RFWUw*/
882 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
883 gen_check_privilege(dc);
884 {
885 TCGv_i32 tmp = tcg_const_i32(1);
886
887 tcg_gen_andi_i32(
888 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
889 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
890
891 if (RRR_S == 4) {
892 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
893 cpu_SR[WINDOW_START], tmp);
894 } else {
895 tcg_gen_or_i32(cpu_SR[WINDOW_START],
896 cpu_SR[WINDOW_START], tmp);
897 }
898
899 gen_helper_restore_owb();
900 gen_helper_check_interrupts(cpu_env);
901 gen_jump(dc, cpu_SR[EPC1]);
902
903 tcg_temp_free(tmp);
904 }
905 break;
906
907 default: /*reserved*/
908 RESERVED();
909 break;
910 }
911 break;
912
913 case 1: /*RFIx*/
914 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
915 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
916 gen_check_privilege(dc);
917 tcg_gen_mov_i32(cpu_SR[PS],
918 cpu_SR[EPS2 + RRR_S - 2]);
919 gen_helper_check_interrupts(cpu_env);
920 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
921 } else {
922 qemu_log("RFI %d is illegal\n", RRR_S);
923 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
924 }
925 break;
926
927 case 2: /*RFME*/
928 TBD();
929 break;
930
931 default: /*reserved*/
932 RESERVED();
933 break;
934
935 }
936 break;
937
938 case 4: /*BREAKx*/
939 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
940 TBD();
941 break;
942
943 case 5: /*SYSCALLx*/
944 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
945 switch (RRR_S) {
946 case 0: /*SYSCALLx*/
947 gen_exception_cause(dc, SYSCALL_CAUSE);
948 break;
949
950 case 1: /*SIMCALL*/
951 if (semihosting_enabled) {
952 gen_check_privilege(dc);
953 gen_helper_simcall(cpu_env);
954 } else {
955 qemu_log("SIMCALL but semihosting is disabled\n");
956 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
957 }
958 break;
959
960 default:
961 RESERVED();
962 break;
963 }
964 break;
965
966 case 6: /*RSILx*/
967 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
968 gen_check_privilege(dc);
969 gen_window_check1(dc, RRR_T);
970 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
971 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
972 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
973 gen_helper_check_interrupts(cpu_env);
974 gen_jumpi_check_loop_end(dc, 0);
975 break;
976
977 case 7: /*WAITIx*/
978 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
979 gen_check_privilege(dc);
980 gen_waiti(dc, RRR_S);
981 break;
982
983 case 8: /*ANY4p*/
984 case 9: /*ALL4p*/
985 case 10: /*ANY8p*/
986 case 11: /*ALL8p*/
987 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
988 {
989 const unsigned shift = (RRR_R & 2) ? 8 : 4;
990 TCGv_i32 mask = tcg_const_i32(
991 ((1 << shift) - 1) << RRR_S);
992 TCGv_i32 tmp = tcg_temp_new_i32();
993
994 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
995 if (RRR_R & 1) { /*ALL*/
996 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
997 } else { /*ANY*/
998 tcg_gen_add_i32(tmp, tmp, mask);
999 }
1000 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1001 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1002 tmp, RRR_T, 1);
1003 tcg_temp_free(mask);
1004 tcg_temp_free(tmp);
1005 }
1006 break;
1007
1008 default: /*reserved*/
1009 RESERVED();
1010 break;
1011
1012 }
1013 break;
1014
1015 case 1: /*AND*/
1016 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1017 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1018 break;
1019
1020 case 2: /*OR*/
1021 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1022 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1023 break;
1024
1025 case 3: /*XOR*/
1026 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1027 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1028 break;
1029
1030 case 4: /*ST1*/
1031 switch (RRR_R) {
1032 case 0: /*SSR*/
1033 gen_window_check1(dc, RRR_S);
1034 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1035 break;
1036
1037 case 1: /*SSL*/
1038 gen_window_check1(dc, RRR_S);
1039 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1040 break;
1041
1042 case 2: /*SSA8L*/
1043 gen_window_check1(dc, RRR_S);
1044 {
1045 TCGv_i32 tmp = tcg_temp_new_i32();
1046 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1047 gen_right_shift_sar(dc, tmp);
1048 tcg_temp_free(tmp);
1049 }
1050 break;
1051
1052 case 3: /*SSA8B*/
1053 gen_window_check1(dc, RRR_S);
1054 {
1055 TCGv_i32 tmp = tcg_temp_new_i32();
1056 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1057 gen_left_shift_sar(dc, tmp);
1058 tcg_temp_free(tmp);
1059 }
1060 break;
1061
1062 case 4: /*SSAI*/
1063 {
1064 TCGv_i32 tmp = tcg_const_i32(
1065 RRR_S | ((RRR_T & 1) << 4));
1066 gen_right_shift_sar(dc, tmp);
1067 tcg_temp_free(tmp);
1068 }
1069 break;
1070
1071 case 6: /*RER*/
1072 TBD();
1073 break;
1074
1075 case 7: /*WER*/
1076 TBD();
1077 break;
1078
1079 case 8: /*ROTWw*/
1080 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1081 gen_check_privilege(dc);
1082 {
1083 TCGv_i32 tmp = tcg_const_i32(
1084 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1085 gen_helper_rotw(tmp);
1086 tcg_temp_free(tmp);
1087 reset_used_window(dc);
1088 }
1089 break;
1090
1091 case 14: /*NSAu*/
1092 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1093 gen_window_check2(dc, RRR_S, RRR_T);
1094 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1095 break;
1096
1097 case 15: /*NSAUu*/
1098 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1099 gen_window_check2(dc, RRR_S, RRR_T);
1100 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1101 break;
1102
1103 default: /*reserved*/
1104 RESERVED();
1105 break;
1106 }
1107 break;
1108
1109 case 5: /*TLB*/
1110 HAS_OPTION_BITS(
1111 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1112 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1113 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1114 gen_check_privilege(dc);
1115 gen_window_check2(dc, RRR_S, RRR_T);
1116 {
1117 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1118
1119 switch (RRR_R & 7) {
1120 case 3: /*RITLB0*/ /*RDTLB0*/
1121 gen_helper_rtlb0(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1122 break;
1123
1124 case 4: /*IITLB*/ /*IDTLB*/
1125 gen_helper_itlb(cpu_R[RRR_S], dtlb);
1126 /* This could change memory mapping, so exit tb */
1127 gen_jumpi_check_loop_end(dc, -1);
1128 break;
1129
1130 case 5: /*PITLB*/ /*PDTLB*/
1131 tcg_gen_movi_i32(cpu_pc, dc->pc);
1132 gen_helper_ptlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1133 break;
1134
1135 case 6: /*WITLB*/ /*WDTLB*/
1136 gen_helper_wtlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1137 /* This could change memory mapping, so exit tb */
1138 gen_jumpi_check_loop_end(dc, -1);
1139 break;
1140
1141 case 7: /*RITLB1*/ /*RDTLB1*/
1142 gen_helper_rtlb1(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1143 break;
1144
1145 default:
1146 tcg_temp_free(dtlb);
1147 RESERVED();
1148 break;
1149 }
1150 tcg_temp_free(dtlb);
1151 }
1152 break;
1153
1154 case 6: /*RT0*/
1155 gen_window_check2(dc, RRR_R, RRR_T);
1156 switch (RRR_S) {
1157 case 0: /*NEG*/
1158 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1159 break;
1160
1161 case 1: /*ABS*/
1162 {
1163 int label = gen_new_label();
1164 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1165 tcg_gen_brcondi_i32(
1166 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1167 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1168 gen_set_label(label);
1169 }
1170 break;
1171
1172 default: /*reserved*/
1173 RESERVED();
1174 break;
1175 }
1176 break;
1177
1178 case 7: /*reserved*/
1179 RESERVED();
1180 break;
1181
1182 case 8: /*ADD*/
1183 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1184 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1185 break;
1186
1187 case 9: /*ADD**/
1188 case 10:
1189 case 11:
1190 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1191 {
1192 TCGv_i32 tmp = tcg_temp_new_i32();
1193 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1194 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1195 tcg_temp_free(tmp);
1196 }
1197 break;
1198
1199 case 12: /*SUB*/
1200 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1201 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1202 break;
1203
1204 case 13: /*SUB**/
1205 case 14:
1206 case 15:
1207 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1208 {
1209 TCGv_i32 tmp = tcg_temp_new_i32();
1210 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1211 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1212 tcg_temp_free(tmp);
1213 }
1214 break;
1215 }
1216 break;
1217
1218 case 1: /*RST1*/
1219 switch (OP2) {
1220 case 0: /*SLLI*/
1221 case 1:
1222 gen_window_check2(dc, RRR_R, RRR_S);
1223 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1224 32 - (RRR_T | ((OP2 & 1) << 4)));
1225 break;
1226
1227 case 2: /*SRAI*/
1228 case 3:
1229 gen_window_check2(dc, RRR_R, RRR_T);
1230 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1231 RRR_S | ((OP2 & 1) << 4));
1232 break;
1233
1234 case 4: /*SRLI*/
1235 gen_window_check2(dc, RRR_R, RRR_T);
1236 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1237 break;
1238
1239 case 6: /*XSR*/
1240 {
1241 TCGv_i32 tmp = tcg_temp_new_i32();
1242 if (RSR_SR >= 64) {
1243 gen_check_privilege(dc);
1244 }
1245 gen_window_check1(dc, RRR_T);
1246 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1247 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1248 gen_wsr(dc, RSR_SR, tmp);
1249 tcg_temp_free(tmp);
1250 if (!sregnames[RSR_SR]) {
1251 TBD();
1252 }
1253 }
1254 break;
1255
1256 /*
1257 * Note: 64 bit ops are used here solely because SAR values
1258 * have range 0..63
1259 */
1260 #define gen_shift_reg(cmd, reg) do { \
1261 TCGv_i64 tmp = tcg_temp_new_i64(); \
1262 tcg_gen_extu_i32_i64(tmp, reg); \
1263 tcg_gen_##cmd##_i64(v, v, tmp); \
1264 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1265 tcg_temp_free_i64(v); \
1266 tcg_temp_free_i64(tmp); \
1267 } while (0)
1268
1269 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1270
1271 case 8: /*SRC*/
1272 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1273 {
1274 TCGv_i64 v = tcg_temp_new_i64();
1275 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1276 gen_shift(shr);
1277 }
1278 break;
1279
1280 case 9: /*SRL*/
1281 gen_window_check2(dc, RRR_R, RRR_T);
1282 if (dc->sar_5bit) {
1283 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1284 } else {
1285 TCGv_i64 v = tcg_temp_new_i64();
1286 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1287 gen_shift(shr);
1288 }
1289 break;
1290
1291 case 10: /*SLL*/
1292 gen_window_check2(dc, RRR_R, RRR_S);
1293 if (dc->sar_m32_5bit) {
1294 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1295 } else {
1296 TCGv_i64 v = tcg_temp_new_i64();
1297 TCGv_i32 s = tcg_const_i32(32);
1298 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1299 tcg_gen_andi_i32(s, s, 0x3f);
1300 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1301 gen_shift_reg(shl, s);
1302 tcg_temp_free(s);
1303 }
1304 break;
1305
1306 case 11: /*SRA*/
1307 gen_window_check2(dc, RRR_R, RRR_T);
1308 if (dc->sar_5bit) {
1309 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1310 } else {
1311 TCGv_i64 v = tcg_temp_new_i64();
1312 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1313 gen_shift(sar);
1314 }
1315 break;
1316 #undef gen_shift
1317 #undef gen_shift_reg
1318
1319 case 12: /*MUL16U*/
1320 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1321 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1322 {
1323 TCGv_i32 v1 = tcg_temp_new_i32();
1324 TCGv_i32 v2 = tcg_temp_new_i32();
1325 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1326 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1327 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1328 tcg_temp_free(v2);
1329 tcg_temp_free(v1);
1330 }
1331 break;
1332
1333 case 13: /*MUL16S*/
1334 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1335 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1336 {
1337 TCGv_i32 v1 = tcg_temp_new_i32();
1338 TCGv_i32 v2 = tcg_temp_new_i32();
1339 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1340 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1341 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1342 tcg_temp_free(v2);
1343 tcg_temp_free(v1);
1344 }
1345 break;
1346
1347 default: /*reserved*/
1348 RESERVED();
1349 break;
1350 }
1351 break;
1352
1353 case 2: /*RST2*/
1354 if (OP2 >= 8) {
1355 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1356 }
1357
1358 if (OP2 >= 12) {
1359 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1360 int label = gen_new_label();
1361 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1362 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1363 gen_set_label(label);
1364 }
1365
1366 switch (OP2) {
1367 #define BOOLEAN_LOGIC(fn, r, s, t) \
1368 do { \
1369 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1370 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1371 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1372 \
1373 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1374 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1375 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1376 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1377 tcg_temp_free(tmp1); \
1378 tcg_temp_free(tmp2); \
1379 } while (0)
1380
1381 case 0: /*ANDBp*/
1382 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1383 break;
1384
1385 case 1: /*ANDBCp*/
1386 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1387 break;
1388
1389 case 2: /*ORBp*/
1390 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1391 break;
1392
1393 case 3: /*ORBCp*/
1394 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1395 break;
1396
1397 case 4: /*XORBp*/
1398 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1399 break;
1400
1401 #undef BOOLEAN_LOGIC
1402
1403 case 8: /*MULLi*/
1404 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1405 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1406 break;
1407
1408 case 10: /*MULUHi*/
1409 case 11: /*MULSHi*/
1410 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1411 {
1412 TCGv_i64 r = tcg_temp_new_i64();
1413 TCGv_i64 s = tcg_temp_new_i64();
1414 TCGv_i64 t = tcg_temp_new_i64();
1415
1416 if (OP2 == 10) {
1417 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1418 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1419 } else {
1420 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1421 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1422 }
1423 tcg_gen_mul_i64(r, s, t);
1424 tcg_gen_shri_i64(r, r, 32);
1425 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1426
1427 tcg_temp_free_i64(r);
1428 tcg_temp_free_i64(s);
1429 tcg_temp_free_i64(t);
1430 }
1431 break;
1432
1433 case 12: /*QUOUi*/
1434 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1435 break;
1436
1437 case 13: /*QUOSi*/
1438 case 15: /*REMSi*/
1439 {
1440 int label1 = gen_new_label();
1441 int label2 = gen_new_label();
1442
1443 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1444 label1);
1445 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1446 label1);
1447 tcg_gen_movi_i32(cpu_R[RRR_R],
1448 OP2 == 13 ? 0x80000000 : 0);
1449 tcg_gen_br(label2);
1450 gen_set_label(label1);
1451 if (OP2 == 13) {
1452 tcg_gen_div_i32(cpu_R[RRR_R],
1453 cpu_R[RRR_S], cpu_R[RRR_T]);
1454 } else {
1455 tcg_gen_rem_i32(cpu_R[RRR_R],
1456 cpu_R[RRR_S], cpu_R[RRR_T]);
1457 }
1458 gen_set_label(label2);
1459 }
1460 break;
1461
1462 case 14: /*REMUi*/
1463 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1464 break;
1465
1466 default: /*reserved*/
1467 RESERVED();
1468 break;
1469 }
1470 break;
1471
1472 case 3: /*RST3*/
1473 switch (OP2) {
1474 case 0: /*RSR*/
1475 if (RSR_SR >= 64) {
1476 gen_check_privilege(dc);
1477 }
1478 gen_window_check1(dc, RRR_T);
1479 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1480 if (!sregnames[RSR_SR]) {
1481 TBD();
1482 }
1483 break;
1484
1485 case 1: /*WSR*/
1486 if (RSR_SR >= 64) {
1487 gen_check_privilege(dc);
1488 }
1489 gen_window_check1(dc, RRR_T);
1490 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1491 if (!sregnames[RSR_SR]) {
1492 TBD();
1493 }
1494 break;
1495
1496 case 2: /*SEXTu*/
1497 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1498 gen_window_check2(dc, RRR_R, RRR_S);
1499 {
1500 int shift = 24 - RRR_T;
1501
1502 if (shift == 24) {
1503 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1504 } else if (shift == 16) {
1505 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1506 } else {
1507 TCGv_i32 tmp = tcg_temp_new_i32();
1508 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1509 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1510 tcg_temp_free(tmp);
1511 }
1512 }
1513 break;
1514
1515 case 3: /*CLAMPSu*/
1516 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1517 gen_window_check2(dc, RRR_R, RRR_S);
1518 {
1519 TCGv_i32 tmp1 = tcg_temp_new_i32();
1520 TCGv_i32 tmp2 = tcg_temp_new_i32();
1521 int label = gen_new_label();
1522
1523 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1524 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1525 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1526 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1527 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1528
1529 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1530 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1531 0xffffffff >> (25 - RRR_T));
1532
1533 gen_set_label(label);
1534
1535 tcg_temp_free(tmp1);
1536 tcg_temp_free(tmp2);
1537 }
1538 break;
1539
1540 case 4: /*MINu*/
1541 case 5: /*MAXu*/
1542 case 6: /*MINUu*/
1543 case 7: /*MAXUu*/
1544 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1545 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1546 {
1547 static const TCGCond cond[] = {
1548 TCG_COND_LE,
1549 TCG_COND_GE,
1550 TCG_COND_LEU,
1551 TCG_COND_GEU
1552 };
1553 int label = gen_new_label();
1554
1555 if (RRR_R != RRR_T) {
1556 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1557 tcg_gen_brcond_i32(cond[OP2 - 4],
1558 cpu_R[RRR_S], cpu_R[RRR_T], label);
1559 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1560 } else {
1561 tcg_gen_brcond_i32(cond[OP2 - 4],
1562 cpu_R[RRR_T], cpu_R[RRR_S], label);
1563 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1564 }
1565 gen_set_label(label);
1566 }
1567 break;
1568
1569 case 8: /*MOVEQZ*/
1570 case 9: /*MOVNEZ*/
1571 case 10: /*MOVLTZ*/
1572 case 11: /*MOVGEZ*/
1573 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1574 {
1575 static const TCGCond cond[] = {
1576 TCG_COND_NE,
1577 TCG_COND_EQ,
1578 TCG_COND_GE,
1579 TCG_COND_LT
1580 };
1581 int label = gen_new_label();
1582 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1583 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1584 gen_set_label(label);
1585 }
1586 break;
1587
1588 case 12: /*MOVFp*/
1589 case 13: /*MOVTp*/
1590 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1591 gen_window_check2(dc, RRR_R, RRR_S);
1592 {
1593 int label = gen_new_label();
1594 TCGv_i32 tmp = tcg_temp_new_i32();
1595
1596 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1597 tcg_gen_brcondi_i32(
1598 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1599 tmp, 0, label);
1600 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1601 gen_set_label(label);
1602 tcg_temp_free(tmp);
1603 }
1604 break;
1605
1606 case 14: /*RUR*/
1607 gen_window_check1(dc, RRR_R);
1608 {
1609 int st = (RRR_S << 4) + RRR_T;
1610 if (uregnames[st]) {
1611 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1612 } else {
1613 qemu_log("RUR %d not implemented, ", st);
1614 TBD();
1615 }
1616 }
1617 break;
1618
1619 case 15: /*WUR*/
1620 gen_window_check1(dc, RRR_T);
1621 {
1622 if (uregnames[RSR_SR]) {
1623 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1624 } else {
1625 qemu_log("WUR %d not implemented, ", RSR_SR);
1626 TBD();
1627 }
1628 }
1629 break;
1630
1631 }
1632 break;
1633
1634 case 4: /*EXTUI*/
1635 case 5:
1636 gen_window_check2(dc, RRR_R, RRR_T);
1637 {
1638 int shiftimm = RRR_S | (OP1 << 4);
1639 int maskimm = (1 << (OP2 + 1)) - 1;
1640
1641 TCGv_i32 tmp = tcg_temp_new_i32();
1642 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1643 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1644 tcg_temp_free(tmp);
1645 }
1646 break;
1647
1648 case 6: /*CUST0*/
1649 RESERVED();
1650 break;
1651
1652 case 7: /*CUST1*/
1653 RESERVED();
1654 break;
1655
1656 case 8: /*LSCXp*/
1657 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
1658 TBD();
1659 break;
1660
1661 case 9: /*LSC4*/
1662 gen_window_check2(dc, RRR_S, RRR_T);
1663 switch (OP2) {
1664 case 0: /*L32E*/
1665 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1666 gen_check_privilege(dc);
1667 {
1668 TCGv_i32 addr = tcg_temp_new_i32();
1669 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1670 (0xffffffc0 | (RRR_R << 2)));
1671 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1672 tcg_temp_free(addr);
1673 }
1674 break;
1675
1676 case 4: /*S32E*/
1677 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1678 gen_check_privilege(dc);
1679 {
1680 TCGv_i32 addr = tcg_temp_new_i32();
1681 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1682 (0xffffffc0 | (RRR_R << 2)));
1683 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1684 tcg_temp_free(addr);
1685 }
1686 break;
1687
1688 default:
1689 RESERVED();
1690 break;
1691 }
1692 break;
1693
1694 case 10: /*FP0*/
1695 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1696 TBD();
1697 break;
1698
1699 case 11: /*FP1*/
1700 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1701 TBD();
1702 break;
1703
1704 default: /*reserved*/
1705 RESERVED();
1706 break;
1707 }
1708 break;
1709
1710 case 1: /*L32R*/
1711 gen_window_check1(dc, RRR_T);
1712 {
1713 TCGv_i32 tmp = tcg_const_i32(
1714 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1715 0 : ((dc->pc + 3) & ~3)) +
1716 (0xfffc0000 | (RI16_IMM16 << 2)));
1717
1718 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1719 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1720 }
1721 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
1722 tcg_temp_free(tmp);
1723 }
1724 break;
1725
1726 case 2: /*LSAI*/
1727 #define gen_load_store(type, shift) do { \
1728 TCGv_i32 addr = tcg_temp_new_i32(); \
1729 gen_window_check2(dc, RRI8_S, RRI8_T); \
1730 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1731 if (shift) { \
1732 gen_load_store_alignment(dc, shift, addr, false); \
1733 } \
1734 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1735 tcg_temp_free(addr); \
1736 } while (0)
1737
1738 switch (RRI8_R) {
1739 case 0: /*L8UI*/
1740 gen_load_store(ld8u, 0);
1741 break;
1742
1743 case 1: /*L16UI*/
1744 gen_load_store(ld16u, 1);
1745 break;
1746
1747 case 2: /*L32I*/
1748 gen_load_store(ld32u, 2);
1749 break;
1750
1751 case 4: /*S8I*/
1752 gen_load_store(st8, 0);
1753 break;
1754
1755 case 5: /*S16I*/
1756 gen_load_store(st16, 1);
1757 break;
1758
1759 case 6: /*S32I*/
1760 gen_load_store(st32, 2);
1761 break;
1762
1763 case 7: /*CACHEc*/
1764 if (RRI8_T < 8) {
1765 HAS_OPTION(XTENSA_OPTION_DCACHE);
1766 }
1767
1768 switch (RRI8_T) {
1769 case 0: /*DPFRc*/
1770 break;
1771
1772 case 1: /*DPFWc*/
1773 break;
1774
1775 case 2: /*DPFROc*/
1776 break;
1777
1778 case 3: /*DPFWOc*/
1779 break;
1780
1781 case 4: /*DHWBc*/
1782 break;
1783
1784 case 5: /*DHWBIc*/
1785 break;
1786
1787 case 6: /*DHIc*/
1788 break;
1789
1790 case 7: /*DIIc*/
1791 break;
1792
1793 case 8: /*DCEc*/
1794 switch (OP1) {
1795 case 0: /*DPFLl*/
1796 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1797 break;
1798
1799 case 2: /*DHUl*/
1800 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1801 break;
1802
1803 case 3: /*DIUl*/
1804 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1805 break;
1806
1807 case 4: /*DIWBc*/
1808 HAS_OPTION(XTENSA_OPTION_DCACHE);
1809 break;
1810
1811 case 5: /*DIWBIc*/
1812 HAS_OPTION(XTENSA_OPTION_DCACHE);
1813 break;
1814
1815 default: /*reserved*/
1816 RESERVED();
1817 break;
1818
1819 }
1820 break;
1821
1822 case 12: /*IPFc*/
1823 HAS_OPTION(XTENSA_OPTION_ICACHE);
1824 break;
1825
1826 case 13: /*ICEc*/
1827 switch (OP1) {
1828 case 0: /*IPFLl*/
1829 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1830 break;
1831
1832 case 2: /*IHUl*/
1833 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1834 break;
1835
1836 case 3: /*IIUl*/
1837 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1838 break;
1839
1840 default: /*reserved*/
1841 RESERVED();
1842 break;
1843 }
1844 break;
1845
1846 case 14: /*IHIc*/
1847 HAS_OPTION(XTENSA_OPTION_ICACHE);
1848 break;
1849
1850 case 15: /*IIIc*/
1851 HAS_OPTION(XTENSA_OPTION_ICACHE);
1852 break;
1853
1854 default: /*reserved*/
1855 RESERVED();
1856 break;
1857 }
1858 break;
1859
1860 case 9: /*L16SI*/
1861 gen_load_store(ld16s, 1);
1862 break;
1863 #undef gen_load_store
1864
1865 case 10: /*MOVI*/
1866 gen_window_check1(dc, RRI8_T);
1867 tcg_gen_movi_i32(cpu_R[RRI8_T],
1868 RRI8_IMM8 | (RRI8_S << 8) |
1869 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1870 break;
1871
1872 #define gen_load_store_no_hw_align(type) do { \
1873 TCGv_i32 addr = tcg_temp_local_new_i32(); \
1874 gen_window_check2(dc, RRI8_S, RRI8_T); \
1875 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1876 gen_load_store_alignment(dc, 2, addr, true); \
1877 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1878 tcg_temp_free(addr); \
1879 } while (0)
1880
1881 case 11: /*L32AIy*/
1882 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1883 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
1884 break;
1885
1886 case 12: /*ADDI*/
1887 gen_window_check2(dc, RRI8_S, RRI8_T);
1888 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1889 break;
1890
1891 case 13: /*ADDMI*/
1892 gen_window_check2(dc, RRI8_S, RRI8_T);
1893 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1894 break;
1895
1896 case 14: /*S32C1Iy*/
1897 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1898 gen_window_check2(dc, RRI8_S, RRI8_T);
1899 {
1900 int label = gen_new_label();
1901 TCGv_i32 tmp = tcg_temp_local_new_i32();
1902 TCGv_i32 addr = tcg_temp_local_new_i32();
1903
1904 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1905 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
1906 gen_load_store_alignment(dc, 2, addr, true);
1907 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
1908 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1909 cpu_SR[SCOMPARE1], label);
1910
1911 tcg_gen_qemu_st32(tmp, addr, dc->cring);
1912
1913 gen_set_label(label);
1914 tcg_temp_free(addr);
1915 tcg_temp_free(tmp);
1916 }
1917 break;
1918
1919 case 15: /*S32RIy*/
1920 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1921 gen_load_store_no_hw_align(st32); /*TODO release?*/
1922 break;
1923 #undef gen_load_store_no_hw_align
1924
1925 default: /*reserved*/
1926 RESERVED();
1927 break;
1928 }
1929 break;
1930
1931 case 3: /*LSCIp*/
1932 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
1933 TBD();
1934 break;
1935
1936 case 4: /*MAC16d*/
1937 HAS_OPTION(XTENSA_OPTION_MAC16);
1938 TBD();
1939 break;
1940
1941 case 5: /*CALLN*/
1942 switch (CALL_N) {
1943 case 0: /*CALL0*/
1944 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1945 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1946 break;
1947
1948 case 1: /*CALL4w*/
1949 case 2: /*CALL8w*/
1950 case 3: /*CALL12w*/
1951 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1952 gen_window_check1(dc, CALL_N << 2);
1953 gen_callwi(dc, CALL_N,
1954 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1955 break;
1956 }
1957 break;
1958
1959 case 6: /*SI*/
1960 switch (CALL_N) {
1961 case 0: /*J*/
1962 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
1963 break;
1964
1965 case 1: /*BZ*/
1966 gen_window_check1(dc, BRI12_S);
1967 {
1968 static const TCGCond cond[] = {
1969 TCG_COND_EQ, /*BEQZ*/
1970 TCG_COND_NE, /*BNEZ*/
1971 TCG_COND_LT, /*BLTZ*/
1972 TCG_COND_GE, /*BGEZ*/
1973 };
1974
1975 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
1976 4 + BRI12_IMM12_SE);
1977 }
1978 break;
1979
1980 case 2: /*BI0*/
1981 gen_window_check1(dc, BRI8_S);
1982 {
1983 static const TCGCond cond[] = {
1984 TCG_COND_EQ, /*BEQI*/
1985 TCG_COND_NE, /*BNEI*/
1986 TCG_COND_LT, /*BLTI*/
1987 TCG_COND_GE, /*BGEI*/
1988 };
1989
1990 gen_brcondi(dc, cond[BRI8_M & 3],
1991 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
1992 }
1993 break;
1994
1995 case 3: /*BI1*/
1996 switch (BRI8_M) {
1997 case 0: /*ENTRYw*/
1998 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1999 {
2000 TCGv_i32 pc = tcg_const_i32(dc->pc);
2001 TCGv_i32 s = tcg_const_i32(BRI12_S);
2002 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2003 gen_advance_ccount(dc);
2004 gen_helper_entry(pc, s, imm);
2005 tcg_temp_free(imm);
2006 tcg_temp_free(s);
2007 tcg_temp_free(pc);
2008 reset_used_window(dc);
2009 }
2010 break;
2011
2012 case 1: /*B1*/
2013 switch (BRI8_R) {
2014 case 0: /*BFp*/
2015 case 1: /*BTp*/
2016 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2017 {
2018 TCGv_i32 tmp = tcg_temp_new_i32();
2019 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2020 gen_brcondi(dc,
2021 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2022 tmp, 0, 4 + RRI8_IMM8_SE);
2023 tcg_temp_free(tmp);
2024 }
2025 break;
2026
2027 case 8: /*LOOP*/
2028 case 9: /*LOOPNEZ*/
2029 case 10: /*LOOPGTZ*/
2030 HAS_OPTION(XTENSA_OPTION_LOOP);
2031 gen_window_check1(dc, RRI8_S);
2032 {
2033 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2034 TCGv_i32 tmp = tcg_const_i32(lend);
2035
2036 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2037 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2038 gen_wsr_lend(dc, LEND, tmp);
2039 tcg_temp_free(tmp);
2040
2041 if (BRI8_R > 8) {
2042 int label = gen_new_label();
2043 tcg_gen_brcondi_i32(
2044 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2045 cpu_R[RRI8_S], 0, label);
2046 gen_jumpi(dc, lend, 1);
2047 gen_set_label(label);
2048 }
2049
2050 gen_jumpi(dc, dc->next_pc, 0);
2051 }
2052 break;
2053
2054 default: /*reserved*/
2055 RESERVED();
2056 break;
2057
2058 }
2059 break;
2060
2061 case 2: /*BLTUI*/
2062 case 3: /*BGEUI*/
2063 gen_window_check1(dc, BRI8_S);
2064 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2065 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2066 break;
2067 }
2068 break;
2069
2070 }
2071 break;
2072
2073 case 7: /*B*/
2074 {
2075 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2076
2077 switch (RRI8_R & 7) {
2078 case 0: /*BNONE*/ /*BANY*/
2079 gen_window_check2(dc, RRI8_S, RRI8_T);
2080 {
2081 TCGv_i32 tmp = tcg_temp_new_i32();
2082 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2083 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2084 tcg_temp_free(tmp);
2085 }
2086 break;
2087
2088 case 1: /*BEQ*/ /*BNE*/
2089 case 2: /*BLT*/ /*BGE*/
2090 case 3: /*BLTU*/ /*BGEU*/
2091 gen_window_check2(dc, RRI8_S, RRI8_T);
2092 {
2093 static const TCGCond cond[] = {
2094 [1] = TCG_COND_EQ,
2095 [2] = TCG_COND_LT,
2096 [3] = TCG_COND_LTU,
2097 [9] = TCG_COND_NE,
2098 [10] = TCG_COND_GE,
2099 [11] = TCG_COND_GEU,
2100 };
2101 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2102 4 + RRI8_IMM8_SE);
2103 }
2104 break;
2105
2106 case 4: /*BALL*/ /*BNALL*/
2107 gen_window_check2(dc, RRI8_S, RRI8_T);
2108 {
2109 TCGv_i32 tmp = tcg_temp_new_i32();
2110 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2111 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2112 4 + RRI8_IMM8_SE);
2113 tcg_temp_free(tmp);
2114 }
2115 break;
2116
2117 case 5: /*BBC*/ /*BBS*/
2118 gen_window_check2(dc, RRI8_S, RRI8_T);
2119 {
2120 TCGv_i32 bit = tcg_const_i32(1);
2121 TCGv_i32 tmp = tcg_temp_new_i32();
2122 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2123 tcg_gen_shl_i32(bit, bit, tmp);
2124 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2125 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2126 tcg_temp_free(tmp);
2127 tcg_temp_free(bit);
2128 }
2129 break;
2130
2131 case 6: /*BBCI*/ /*BBSI*/
2132 case 7:
2133 gen_window_check1(dc, RRI8_S);
2134 {
2135 TCGv_i32 tmp = tcg_temp_new_i32();
2136 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2137 1 << (((RRI8_R & 1) << 4) | RRI8_T));
2138 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2139 tcg_temp_free(tmp);
2140 }
2141 break;
2142
2143 }
2144 }
2145 break;
2146
2147 #define gen_narrow_load_store(type) do { \
2148 TCGv_i32 addr = tcg_temp_new_i32(); \
2149 gen_window_check2(dc, RRRN_S, RRRN_T); \
2150 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2151 gen_load_store_alignment(dc, 2, addr, false); \
2152 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2153 tcg_temp_free(addr); \
2154 } while (0)
2155
2156 case 8: /*L32I.Nn*/
2157 gen_narrow_load_store(ld32u);
2158 break;
2159
2160 case 9: /*S32I.Nn*/
2161 gen_narrow_load_store(st32);
2162 break;
2163 #undef gen_narrow_load_store
2164
2165 case 10: /*ADD.Nn*/
2166 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2167 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2168 break;
2169
2170 case 11: /*ADDI.Nn*/
2171 gen_window_check2(dc, RRRN_R, RRRN_S);
2172 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2173 break;
2174
2175 case 12: /*ST2n*/
2176 gen_window_check1(dc, RRRN_S);
2177 if (RRRN_T < 8) { /*MOVI.Nn*/
2178 tcg_gen_movi_i32(cpu_R[RRRN_S],
2179 RRRN_R | (RRRN_T << 4) |
2180 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2181 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2182 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2183
2184 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2185 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2186 }
2187 break;
2188
2189 case 13: /*ST3n*/
2190 switch (RRRN_R) {
2191 case 0: /*MOV.Nn*/
2192 gen_window_check2(dc, RRRN_S, RRRN_T);
2193 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2194 break;
2195
2196 case 15: /*S3*/
2197 switch (RRRN_T) {
2198 case 0: /*RET.Nn*/
2199 gen_jump(dc, cpu_R[0]);
2200 break;
2201
2202 case 1: /*RETW.Nn*/
2203 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2204 {
2205 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2206 gen_advance_ccount(dc);
2207 gen_helper_retw(tmp, tmp);
2208 gen_jump(dc, tmp);
2209 tcg_temp_free(tmp);
2210 }
2211 break;
2212
2213 case 2: /*BREAK.Nn*/
2214 TBD();
2215 break;
2216
2217 case 3: /*NOP.Nn*/
2218 break;
2219
2220 case 6: /*ILL.Nn*/
2221 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2222 break;
2223
2224 default: /*reserved*/
2225 RESERVED();
2226 break;
2227 }
2228 break;
2229
2230 default: /*reserved*/
2231 RESERVED();
2232 break;
2233 }
2234 break;
2235
2236 default: /*reserved*/
2237 RESERVED();
2238 break;
2239 }
2240
2241 gen_check_loop_end(dc, 0);
2242 dc->pc = dc->next_pc;
2243
2244 return;
2245
2246 invalid_opcode:
2247 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2248 dc->pc = dc->next_pc;
2249 #undef HAS_OPTION
2250 }
2251
2252 static void check_breakpoint(CPUState *env, DisasContext *dc)
2253 {
2254 CPUBreakpoint *bp;
2255
2256 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2257 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2258 if (bp->pc == dc->pc) {
2259 tcg_gen_movi_i32(cpu_pc, dc->pc);
2260 gen_exception(dc, EXCP_DEBUG);
2261 dc->is_jmp = DISAS_UPDATE;
2262 }
2263 }
2264 }
2265 }
2266
2267 static void gen_intermediate_code_internal(
2268 CPUState *env, TranslationBlock *tb, int search_pc)
2269 {
2270 DisasContext dc;
2271 int insn_count = 0;
2272 int j, lj = -1;
2273 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2274 int max_insns = tb->cflags & CF_COUNT_MASK;
2275 uint32_t pc_start = tb->pc;
2276 uint32_t next_page_start =
2277 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2278
2279 if (max_insns == 0) {
2280 max_insns = CF_COUNT_MASK;
2281 }
2282
2283 dc.config = env->config;
2284 dc.singlestep_enabled = env->singlestep_enabled;
2285 dc.tb = tb;
2286 dc.pc = pc_start;
2287 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2288 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
2289 dc.lbeg = env->sregs[LBEG];
2290 dc.lend = env->sregs[LEND];
2291 dc.is_jmp = DISAS_NEXT;
2292 dc.ccount_delta = 0;
2293
2294 init_litbase(&dc);
2295 init_sar_tracker(&dc);
2296 reset_used_window(&dc);
2297
2298 gen_icount_start();
2299
2300 if (env->singlestep_enabled && env->exception_taken) {
2301 env->exception_taken = 0;
2302 tcg_gen_movi_i32(cpu_pc, dc.pc);
2303 gen_exception(&dc, EXCP_DEBUG);
2304 }
2305
2306 do {
2307 check_breakpoint(env, &dc);
2308
2309 if (search_pc) {
2310 j = gen_opc_ptr - gen_opc_buf;
2311 if (lj < j) {
2312 lj++;
2313 while (lj < j) {
2314 gen_opc_instr_start[lj++] = 0;
2315 }
2316 }
2317 gen_opc_pc[lj] = dc.pc;
2318 gen_opc_instr_start[lj] = 1;
2319 gen_opc_icount[lj] = insn_count;
2320 }
2321
2322 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2323 tcg_gen_debug_insn_start(dc.pc);
2324 }
2325
2326 ++dc.ccount_delta;
2327
2328 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2329 gen_io_start();
2330 }
2331
2332 disas_xtensa_insn(&dc);
2333 ++insn_count;
2334 if (env->singlestep_enabled) {
2335 tcg_gen_movi_i32(cpu_pc, dc.pc);
2336 gen_exception(&dc, EXCP_DEBUG);
2337 break;
2338 }
2339 } while (dc.is_jmp == DISAS_NEXT &&
2340 insn_count < max_insns &&
2341 dc.pc < next_page_start &&
2342 gen_opc_ptr < gen_opc_end);
2343
2344 reset_litbase(&dc);
2345 reset_sar_tracker(&dc);
2346
2347 if (tb->cflags & CF_LAST_IO) {
2348 gen_io_end();
2349 }
2350
2351 if (dc.is_jmp == DISAS_NEXT) {
2352 gen_jumpi(&dc, dc.pc, 0);
2353 }
2354 gen_icount_end(tb, insn_count);
2355 *gen_opc_ptr = INDEX_op_end;
2356
2357 if (!search_pc) {
2358 tb->size = dc.pc - pc_start;
2359 tb->icount = insn_count;
2360 }
2361 }
2362
2363 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2364 {
2365 gen_intermediate_code_internal(env, tb, 0);
2366 }
2367
2368 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2369 {
2370 gen_intermediate_code_internal(env, tb, 1);
2371 }
2372
2373 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
2374 int flags)
2375 {
2376 int i, j;
2377
2378 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2379
2380 for (i = j = 0; i < 256; ++i) {
2381 if (sregnames[i]) {
2382 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2383 (j++ % 4) == 3 ? '\n' : ' ');
2384 }
2385 }
2386
2387 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2388
2389 for (i = j = 0; i < 256; ++i) {
2390 if (uregnames[i]) {
2391 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2392 (j++ % 4) == 3 ? '\n' : ' ');
2393 }
2394 }
2395
2396 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2397
2398 for (i = 0; i < 16; ++i) {
2399 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2400 (i % 4) == 3 ? '\n' : ' ');
2401 }
2402
2403 cpu_fprintf(f, "\n");
2404
2405 for (i = 0; i < env->config->nareg; ++i) {
2406 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2407 (i % 4) == 3 ? '\n' : ' ');
2408 }
2409 }
2410
2411 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
2412 {
2413 env->pc = gen_opc_pc[pc_pos];
2414 }
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