3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
72 static TCGv_ptr cpu_env
;
73 static TCGv_i32 cpu_pc
;
74 static TCGv_i32 cpu_R
[16];
75 static TCGv_i32 cpu_FR
[16];
76 static TCGv_i32 cpu_SR
[256];
77 static TCGv_i32 cpu_UR
[256];
79 #include "gen-icount.h"
81 typedef struct XtensaReg
{
86 #define XTENSA_REG(regname, opt) { \
88 .opt_bits = XTENSA_OPTION_BIT(opt), \
91 #define XTENSA_REG_BITS(regname, opt) { \
96 static const XtensaReg sregnames
[256] = {
97 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
98 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
99 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
100 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
101 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
102 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
103 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
104 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
105 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
106 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
107 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
108 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
109 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
110 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
111 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
112 XTENSA_OPTION_WINDOWED_REGISTER
),
113 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
114 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
115 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
116 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
117 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
118 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
119 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
120 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
121 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
122 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
123 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
124 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
125 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
126 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
127 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
128 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
129 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
130 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
131 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
132 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
133 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
134 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
135 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
136 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
137 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
138 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
139 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
140 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
141 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
142 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
143 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
144 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
145 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
146 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
147 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
148 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
149 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
150 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
151 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
152 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
153 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
154 [INTSET
] = XTENSA_REG("INTSET", XTENSA_OPTION_INTERRUPT
),
155 [INTCLEAR
] = XTENSA_REG("INTCLEAR", XTENSA_OPTION_INTERRUPT
),
156 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
157 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
158 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
159 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
160 [DEBUGCAUSE
] = XTENSA_REG("DEBUGCAUSE", XTENSA_OPTION_DEBUG
),
161 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
162 [PRID
] = XTENSA_REG("PRID", XTENSA_OPTION_PROCESSOR_ID
),
163 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
164 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
165 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
166 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
167 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
168 XTENSA_OPTION_TIMER_INTERRUPT
),
169 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
170 XTENSA_OPTION_TIMER_INTERRUPT
),
173 static const XtensaReg uregnames
[256] = {
174 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
175 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
176 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
179 void xtensa_translate_init(void)
181 static const char * const regnames
[] = {
182 "ar0", "ar1", "ar2", "ar3",
183 "ar4", "ar5", "ar6", "ar7",
184 "ar8", "ar9", "ar10", "ar11",
185 "ar12", "ar13", "ar14", "ar15",
187 static const char * const fregnames
[] = {
188 "f0", "f1", "f2", "f3",
189 "f4", "f5", "f6", "f7",
190 "f8", "f9", "f10", "f11",
191 "f12", "f13", "f14", "f15",
195 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
196 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
197 offsetof(CPUXtensaState
, pc
), "pc");
199 for (i
= 0; i
< 16; i
++) {
200 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
201 offsetof(CPUXtensaState
, regs
[i
]),
205 for (i
= 0; i
< 16; i
++) {
206 cpu_FR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
207 offsetof(CPUXtensaState
, fregs
[i
]),
211 for (i
= 0; i
< 256; ++i
) {
212 if (sregnames
[i
].name
) {
213 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
214 offsetof(CPUXtensaState
, sregs
[i
]),
219 for (i
= 0; i
< 256; ++i
) {
220 if (uregnames
[i
].name
) {
221 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
222 offsetof(CPUXtensaState
, uregs
[i
]),
230 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
232 return xtensa_option_bits_enabled(dc
->config
, opt
);
235 static inline bool option_enabled(DisasContext
*dc
, int opt
)
237 return xtensa_option_enabled(dc
->config
, opt
);
240 static void init_litbase(DisasContext
*dc
)
242 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
243 dc
->litbase
= tcg_temp_local_new_i32();
244 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
248 static void reset_litbase(DisasContext
*dc
)
250 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
251 tcg_temp_free(dc
->litbase
);
255 static void init_sar_tracker(DisasContext
*dc
)
257 dc
->sar_5bit
= false;
258 dc
->sar_m32_5bit
= false;
259 dc
->sar_m32_allocated
= false;
262 static void reset_sar_tracker(DisasContext
*dc
)
264 if (dc
->sar_m32_allocated
) {
265 tcg_temp_free(dc
->sar_m32
);
269 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
271 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
272 if (dc
->sar_m32_5bit
) {
273 tcg_gen_discard_i32(dc
->sar_m32
);
276 dc
->sar_m32_5bit
= false;
279 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
281 TCGv_i32 tmp
= tcg_const_i32(32);
282 if (!dc
->sar_m32_allocated
) {
283 dc
->sar_m32
= tcg_temp_local_new_i32();
284 dc
->sar_m32_allocated
= true;
286 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
287 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
288 dc
->sar_5bit
= false;
289 dc
->sar_m32_5bit
= true;
293 static void gen_advance_ccount(DisasContext
*dc
)
295 if (dc
->ccount_delta
> 0) {
296 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
297 dc
->ccount_delta
= 0;
298 gen_helper_advance_ccount(cpu_env
, tmp
);
303 static void reset_used_window(DisasContext
*dc
)
308 static void gen_exception(DisasContext
*dc
, int excp
)
310 TCGv_i32 tmp
= tcg_const_i32(excp
);
311 gen_advance_ccount(dc
);
312 gen_helper_exception(cpu_env
, tmp
);
316 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
318 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
319 TCGv_i32 tcause
= tcg_const_i32(cause
);
320 gen_advance_ccount(dc
);
321 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
323 tcg_temp_free(tcause
);
324 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
325 cause
== SYSCALL_CAUSE
) {
326 dc
->is_jmp
= DISAS_UPDATE
;
330 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
333 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
334 TCGv_i32 tcause
= tcg_const_i32(cause
);
335 gen_advance_ccount(dc
);
336 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
338 tcg_temp_free(tcause
);
341 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
343 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
344 TCGv_i32 tcause
= tcg_const_i32(cause
);
345 gen_advance_ccount(dc
);
346 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
348 tcg_temp_free(tcause
);
349 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
350 dc
->is_jmp
= DISAS_UPDATE
;
354 static void gen_check_privilege(DisasContext
*dc
)
357 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
358 dc
->is_jmp
= DISAS_UPDATE
;
362 static void gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
364 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
365 !(dc
->cpenable
& (1 << cp
))) {
366 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
367 dc
->is_jmp
= DISAS_UPDATE
;
371 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
373 tcg_gen_mov_i32(cpu_pc
, dest
);
374 gen_advance_ccount(dc
);
376 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
378 if (dc
->singlestep_enabled
) {
379 gen_exception(dc
, EXCP_DEBUG
);
382 tcg_gen_goto_tb(slot
);
383 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
388 dc
->is_jmp
= DISAS_UPDATE
;
391 static void gen_jump(DisasContext
*dc
, TCGv dest
)
393 gen_jump_slot(dc
, dest
, -1);
396 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
398 TCGv_i32 tmp
= tcg_const_i32(dest
);
399 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
402 gen_jump_slot(dc
, tmp
, slot
);
406 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
409 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
411 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
412 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
413 tcg_temp_free(tcallinc
);
414 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
415 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
416 gen_jump_slot(dc
, dest
, slot
);
419 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
421 gen_callw_slot(dc
, callinc
, dest
, -1);
424 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
426 TCGv_i32 tmp
= tcg_const_i32(dest
);
427 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
430 gen_callw_slot(dc
, callinc
, tmp
, slot
);
434 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
436 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
437 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
438 dc
->next_pc
== dc
->lend
) {
439 int label
= gen_new_label();
441 gen_advance_ccount(dc
);
442 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
443 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
444 gen_jumpi(dc
, dc
->lbeg
, slot
);
445 gen_set_label(label
);
446 gen_jumpi(dc
, dc
->next_pc
, -1);
452 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
454 if (!gen_check_loop_end(dc
, slot
)) {
455 gen_jumpi(dc
, dc
->next_pc
, slot
);
459 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
460 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
462 int label
= gen_new_label();
464 gen_advance_ccount(dc
);
465 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
466 gen_jumpi_check_loop_end(dc
, 0);
467 gen_set_label(label
);
468 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
471 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
472 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
474 TCGv_i32 tmp
= tcg_const_i32(t1
);
475 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
479 static void gen_check_sr(DisasContext
*dc
, uint32_t sr
)
481 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
482 if (sregnames
[sr
].name
) {
483 qemu_log("SR %s is not configured\n", sregnames
[sr
].name
);
485 qemu_log("SR %d is not implemented\n", sr
);
487 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
491 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
493 gen_advance_ccount(dc
);
494 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
497 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
499 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
500 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
501 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
504 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
506 static void (* const rsr_handler
[256])(DisasContext
*dc
,
507 TCGv_i32 d
, uint32_t sr
) = {
508 [CCOUNT
] = gen_rsr_ccount
,
509 [PTEVADDR
] = gen_rsr_ptevaddr
,
512 if (rsr_handler
[sr
]) {
513 rsr_handler
[sr
](dc
, d
, sr
);
515 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
519 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
521 gen_helper_wsr_lbeg(cpu_env
, s
);
522 gen_jumpi_check_loop_end(dc
, 0);
525 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
527 gen_helper_wsr_lend(cpu_env
, s
);
528 gen_jumpi_check_loop_end(dc
, 0);
531 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
533 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
534 if (dc
->sar_m32_5bit
) {
535 tcg_gen_discard_i32(dc
->sar_m32
);
537 dc
->sar_5bit
= false;
538 dc
->sar_m32_5bit
= false;
541 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
543 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
546 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
548 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
549 /* This can change tb->flags, so exit tb */
550 gen_jumpi_check_loop_end(dc
, -1);
553 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
555 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
558 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
560 gen_helper_wsr_windowbase(cpu_env
, v
);
561 reset_used_window(dc
);
564 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
566 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
567 reset_used_window(dc
);
570 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
572 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
575 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
577 gen_helper_wsr_rasid(cpu_env
, v
);
578 /* This can change tb->flags, so exit tb */
579 gen_jumpi_check_loop_end(dc
, -1);
582 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
584 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
587 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
589 gen_helper_wsr_ibreakenable(cpu_env
, v
);
590 gen_jumpi_check_loop_end(dc
, 0);
593 static void gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
595 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
598 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
600 unsigned id
= sr
- IBREAKA
;
602 if (id
< dc
->config
->nibreak
) {
603 TCGv_i32 tmp
= tcg_const_i32(id
);
604 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
606 gen_jumpi_check_loop_end(dc
, 0);
610 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
612 unsigned id
= sr
- DBREAKA
;
614 if (id
< dc
->config
->ndbreak
) {
615 TCGv_i32 tmp
= tcg_const_i32(id
);
616 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
621 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
623 unsigned id
= sr
- DBREAKC
;
625 if (id
< dc
->config
->ndbreak
) {
626 TCGv_i32 tmp
= tcg_const_i32(id
);
627 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
632 static void gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
634 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
635 /* This can change tb->flags, so exit tb */
636 gen_jumpi_check_loop_end(dc
, -1);
639 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
641 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
642 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
643 gen_helper_check_interrupts(cpu_env
);
644 gen_jumpi_check_loop_end(dc
, 0);
647 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
649 TCGv_i32 tmp
= tcg_temp_new_i32();
651 tcg_gen_andi_i32(tmp
, v
,
652 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
653 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
654 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
655 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
657 gen_helper_check_interrupts(cpu_env
);
660 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
662 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
663 gen_helper_check_interrupts(cpu_env
);
664 gen_jumpi_check_loop_end(dc
, 0);
667 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
669 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
670 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
672 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
675 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
676 reset_used_window(dc
);
677 gen_helper_check_interrupts(cpu_env
);
678 /* This can change mmu index and tb->flags, so exit tb */
679 gen_jumpi_check_loop_end(dc
, -1);
682 static void gen_wsr_debugcause(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
686 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
690 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
693 tcg_gen_mov_i32(dc
->next_icount
, v
);
695 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
699 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
701 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
702 /* This can change tb->flags, so exit tb */
703 gen_jumpi_check_loop_end(dc
, -1);
706 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
708 uint32_t id
= sr
- CCOMPARE
;
709 if (id
< dc
->config
->nccompare
) {
710 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
711 gen_advance_ccount(dc
);
712 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
713 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
714 gen_helper_check_interrupts(cpu_env
);
718 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
720 static void (* const wsr_handler
[256])(DisasContext
*dc
,
721 uint32_t sr
, TCGv_i32 v
) = {
722 [LBEG
] = gen_wsr_lbeg
,
723 [LEND
] = gen_wsr_lend
,
726 [LITBASE
] = gen_wsr_litbase
,
727 [ACCHI
] = gen_wsr_acchi
,
728 [WINDOW_BASE
] = gen_wsr_windowbase
,
729 [WINDOW_START
] = gen_wsr_windowstart
,
730 [PTEVADDR
] = gen_wsr_ptevaddr
,
731 [RASID
] = gen_wsr_rasid
,
732 [ITLBCFG
] = gen_wsr_tlbcfg
,
733 [DTLBCFG
] = gen_wsr_tlbcfg
,
734 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
735 [ATOMCTL
] = gen_wsr_atomctl
,
736 [IBREAKA
] = gen_wsr_ibreaka
,
737 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
738 [DBREAKA
] = gen_wsr_dbreaka
,
739 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
740 [DBREAKC
] = gen_wsr_dbreakc
,
741 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
742 [CPENABLE
] = gen_wsr_cpenable
,
743 [INTSET
] = gen_wsr_intset
,
744 [INTCLEAR
] = gen_wsr_intclear
,
745 [INTENABLE
] = gen_wsr_intenable
,
747 [DEBUGCAUSE
] = gen_wsr_debugcause
,
748 [PRID
] = gen_wsr_prid
,
749 [ICOUNT
] = gen_wsr_icount
,
750 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
751 [CCOMPARE
] = gen_wsr_ccompare
,
752 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
753 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
756 if (wsr_handler
[sr
]) {
757 wsr_handler
[sr
](dc
, sr
, s
);
759 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
763 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
767 gen_helper_wur_fcr(cpu_env
, s
);
771 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
775 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
780 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
781 TCGv_i32 addr
, bool no_hw_alignment
)
783 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
784 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
785 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
787 int label
= gen_new_label();
788 TCGv_i32 tmp
= tcg_temp_new_i32();
789 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
790 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
791 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
792 gen_set_label(label
);
797 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
799 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
800 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
801 gen_advance_ccount(dc
);
802 gen_helper_waiti(cpu_env
, pc
, intlevel
);
804 tcg_temp_free(intlevel
);
807 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
809 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
812 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
813 r1
/ 4 > dc
->used_window
) {
814 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
815 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
817 dc
->used_window
= r1
/ 4;
818 gen_advance_ccount(dc
);
819 gen_helper_window_check(cpu_env
, pc
, w
);
826 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
828 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
831 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
834 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
837 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
839 TCGv_i32 m
= tcg_temp_new_i32();
842 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
844 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
849 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
851 #define HAS_OPTION_BITS(opt) do { \
852 if (!option_bits_enabled(dc, opt)) { \
853 qemu_log("Option is not enabled %s:%d\n", \
854 __FILE__, __LINE__); \
855 goto invalid_opcode; \
859 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
861 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
862 #define RESERVED() do { \
863 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
864 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
865 goto invalid_opcode; \
869 #ifdef TARGET_WORDS_BIGENDIAN
870 #define OP0 (((b0) & 0xf0) >> 4)
871 #define OP1 (((b2) & 0xf0) >> 4)
872 #define OP2 ((b2) & 0xf)
873 #define RRR_R ((b1) & 0xf)
874 #define RRR_S (((b1) & 0xf0) >> 4)
875 #define RRR_T ((b0) & 0xf)
877 #define OP0 (((b0) & 0xf))
878 #define OP1 (((b2) & 0xf))
879 #define OP2 (((b2) & 0xf0) >> 4)
880 #define RRR_R (((b1) & 0xf0) >> 4)
881 #define RRR_S (((b1) & 0xf))
882 #define RRR_T (((b0) & 0xf0) >> 4)
884 #define RRR_X ((RRR_R & 0x4) >> 2)
885 #define RRR_Y ((RRR_T & 0x4) >> 2)
886 #define RRR_W (RRR_R & 0x3)
895 #define RRI8_IMM8 (b2)
896 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
898 #ifdef TARGET_WORDS_BIGENDIAN
899 #define RI16_IMM16 (((b1) << 8) | (b2))
901 #define RI16_IMM16 (((b2) << 8) | (b1))
904 #ifdef TARGET_WORDS_BIGENDIAN
905 #define CALL_N (((b0) & 0xc) >> 2)
906 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
908 #define CALL_N (((b0) & 0x30) >> 4)
909 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
911 #define CALL_OFFSET_SE \
912 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
914 #define CALLX_N CALL_N
915 #ifdef TARGET_WORDS_BIGENDIAN
916 #define CALLX_M ((b0) & 0x3)
918 #define CALLX_M (((b0) & 0xc0) >> 6)
920 #define CALLX_S RRR_S
922 #define BRI12_M CALLX_M
923 #define BRI12_S RRR_S
924 #ifdef TARGET_WORDS_BIGENDIAN
925 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
927 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
929 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
931 #define BRI8_M BRI12_M
932 #define BRI8_R RRI8_R
933 #define BRI8_S RRI8_S
934 #define BRI8_IMM8 RRI8_IMM8
935 #define BRI8_IMM8_SE RRI8_IMM8_SE
939 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
940 uint8_t b1
= cpu_ldub_code(env
, dc
->pc
+ 1);
943 static const uint32_t B4CONST
[] = {
944 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
947 static const uint32_t B4CONSTU
[] = {
948 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
952 dc
->next_pc
= dc
->pc
+ 2;
953 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
955 dc
->next_pc
= dc
->pc
+ 3;
956 b2
= cpu_ldub_code(env
, dc
->pc
+ 2);
965 if ((RRR_R
& 0xc) == 0x8) {
966 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
973 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
984 gen_window_check1(dc
, CALLX_S
);
985 gen_jump(dc
, cpu_R
[CALLX_S
]);
989 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
991 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
992 gen_advance_ccount(dc
);
993 gen_helper_retw(tmp
, cpu_env
, tmp
);
1006 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
1010 TCGv_i32 tmp
= tcg_temp_new_i32();
1011 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
1012 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1020 case 3: /*CALLX12w*/
1021 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1023 TCGv_i32 tmp
= tcg_temp_new_i32();
1025 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
1026 gen_callw(dc
, CALLX_N
, tmp
);
1036 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1037 gen_window_check2(dc
, RRR_T
, RRR_S
);
1039 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1040 gen_advance_ccount(dc
);
1041 gen_helper_movsp(cpu_env
, pc
);
1042 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1062 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1074 default: /*reserved*/
1083 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1086 gen_check_privilege(dc
);
1087 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1088 gen_helper_check_interrupts(cpu_env
);
1089 gen_jump(dc
, cpu_SR
[EPC1
]);
1097 gen_check_privilege(dc
);
1098 gen_jump(dc
, cpu_SR
[
1099 dc
->config
->ndepc
? DEPC
: EPC1
]);
1104 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1105 gen_check_privilege(dc
);
1107 TCGv_i32 tmp
= tcg_const_i32(1);
1110 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1111 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1114 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1115 cpu_SR
[WINDOW_START
], tmp
);
1117 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1118 cpu_SR
[WINDOW_START
], tmp
);
1121 gen_helper_restore_owb(cpu_env
);
1122 gen_helper_check_interrupts(cpu_env
);
1123 gen_jump(dc
, cpu_SR
[EPC1
]);
1129 default: /*reserved*/
1136 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1137 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1138 gen_check_privilege(dc
);
1139 tcg_gen_mov_i32(cpu_SR
[PS
],
1140 cpu_SR
[EPS2
+ RRR_S
- 2]);
1141 gen_helper_check_interrupts(cpu_env
);
1142 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1144 qemu_log("RFI %d is illegal\n", RRR_S
);
1145 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1153 default: /*reserved*/
1161 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1163 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1167 case 5: /*SYSCALLx*/
1168 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1170 case 0: /*SYSCALLx*/
1171 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1175 if (semihosting_enabled
) {
1176 gen_check_privilege(dc
);
1177 gen_helper_simcall(cpu_env
);
1179 qemu_log("SIMCALL but semihosting is disabled\n");
1180 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1191 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1192 gen_check_privilege(dc
);
1193 gen_window_check1(dc
, RRR_T
);
1194 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1195 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1196 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1197 gen_helper_check_interrupts(cpu_env
);
1198 gen_jumpi_check_loop_end(dc
, 0);
1202 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1203 gen_check_privilege(dc
);
1204 gen_waiti(dc
, RRR_S
);
1211 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1213 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1214 TCGv_i32 mask
= tcg_const_i32(
1215 ((1 << shift
) - 1) << RRR_S
);
1216 TCGv_i32 tmp
= tcg_temp_new_i32();
1218 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1219 if (RRR_R
& 1) { /*ALL*/
1220 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1222 tcg_gen_add_i32(tmp
, tmp
, mask
);
1224 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1225 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1227 tcg_temp_free(mask
);
1232 default: /*reserved*/
1240 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1241 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1245 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1246 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1250 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1251 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1257 gen_window_check1(dc
, RRR_S
);
1258 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1262 gen_window_check1(dc
, RRR_S
);
1263 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1267 gen_window_check1(dc
, RRR_S
);
1269 TCGv_i32 tmp
= tcg_temp_new_i32();
1270 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1271 gen_right_shift_sar(dc
, tmp
);
1277 gen_window_check1(dc
, RRR_S
);
1279 TCGv_i32 tmp
= tcg_temp_new_i32();
1280 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1281 gen_left_shift_sar(dc
, tmp
);
1288 TCGv_i32 tmp
= tcg_const_i32(
1289 RRR_S
| ((RRR_T
& 1) << 4));
1290 gen_right_shift_sar(dc
, tmp
);
1304 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1305 gen_check_privilege(dc
);
1307 TCGv_i32 tmp
= tcg_const_i32(
1308 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1309 gen_helper_rotw(cpu_env
, tmp
);
1311 reset_used_window(dc
);
1316 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1317 gen_window_check2(dc
, RRR_S
, RRR_T
);
1318 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1322 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1323 gen_window_check2(dc
, RRR_S
, RRR_T
);
1324 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1327 default: /*reserved*/
1335 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1336 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1337 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1338 gen_check_privilege(dc
);
1339 gen_window_check2(dc
, RRR_S
, RRR_T
);
1341 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1343 switch (RRR_R
& 7) {
1344 case 3: /*RITLB0*/ /*RDTLB0*/
1345 gen_helper_rtlb0(cpu_R
[RRR_T
],
1346 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1349 case 4: /*IITLB*/ /*IDTLB*/
1350 gen_helper_itlb(cpu_env
, cpu_R
[RRR_S
], dtlb
);
1351 /* This could change memory mapping, so exit tb */
1352 gen_jumpi_check_loop_end(dc
, -1);
1355 case 5: /*PITLB*/ /*PDTLB*/
1356 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1357 gen_helper_ptlb(cpu_R
[RRR_T
],
1358 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1361 case 6: /*WITLB*/ /*WDTLB*/
1363 cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1364 /* This could change memory mapping, so exit tb */
1365 gen_jumpi_check_loop_end(dc
, -1);
1368 case 7: /*RITLB1*/ /*RDTLB1*/
1369 gen_helper_rtlb1(cpu_R
[RRR_T
],
1370 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1374 tcg_temp_free(dtlb
);
1378 tcg_temp_free(dtlb
);
1383 gen_window_check2(dc
, RRR_R
, RRR_T
);
1386 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1391 int label
= gen_new_label();
1392 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1393 tcg_gen_brcondi_i32(
1394 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1395 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1396 gen_set_label(label
);
1400 default: /*reserved*/
1406 case 7: /*reserved*/
1411 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1412 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1418 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1420 TCGv_i32 tmp
= tcg_temp_new_i32();
1421 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1422 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1428 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1429 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1435 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1437 TCGv_i32 tmp
= tcg_temp_new_i32();
1438 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1439 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1450 gen_window_check2(dc
, RRR_R
, RRR_S
);
1451 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1452 32 - (RRR_T
| ((OP2
& 1) << 4)));
1457 gen_window_check2(dc
, RRR_R
, RRR_T
);
1458 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1459 RRR_S
| ((OP2
& 1) << 4));
1463 gen_window_check2(dc
, RRR_R
, RRR_T
);
1464 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1469 TCGv_i32 tmp
= tcg_temp_new_i32();
1470 gen_check_sr(dc
, RSR_SR
);
1472 gen_check_privilege(dc
);
1474 gen_window_check1(dc
, RRR_T
);
1475 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1476 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1477 gen_wsr(dc
, RSR_SR
, tmp
);
1483 * Note: 64 bit ops are used here solely because SAR values
1486 #define gen_shift_reg(cmd, reg) do { \
1487 TCGv_i64 tmp = tcg_temp_new_i64(); \
1488 tcg_gen_extu_i32_i64(tmp, reg); \
1489 tcg_gen_##cmd##_i64(v, v, tmp); \
1490 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1491 tcg_temp_free_i64(v); \
1492 tcg_temp_free_i64(tmp); \
1495 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1498 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1500 TCGv_i64 v
= tcg_temp_new_i64();
1501 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1507 gen_window_check2(dc
, RRR_R
, RRR_T
);
1509 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1511 TCGv_i64 v
= tcg_temp_new_i64();
1512 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1518 gen_window_check2(dc
, RRR_R
, RRR_S
);
1519 if (dc
->sar_m32_5bit
) {
1520 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1522 TCGv_i64 v
= tcg_temp_new_i64();
1523 TCGv_i32 s
= tcg_const_i32(32);
1524 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1525 tcg_gen_andi_i32(s
, s
, 0x3f);
1526 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1527 gen_shift_reg(shl
, s
);
1533 gen_window_check2(dc
, RRR_R
, RRR_T
);
1535 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1537 TCGv_i64 v
= tcg_temp_new_i64();
1538 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1543 #undef gen_shift_reg
1546 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1547 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1549 TCGv_i32 v1
= tcg_temp_new_i32();
1550 TCGv_i32 v2
= tcg_temp_new_i32();
1551 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1552 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1553 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1560 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1561 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1563 TCGv_i32 v1
= tcg_temp_new_i32();
1564 TCGv_i32 v2
= tcg_temp_new_i32();
1565 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1566 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1567 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1573 default: /*reserved*/
1581 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1585 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1586 int label
= gen_new_label();
1587 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1588 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1589 gen_set_label(label
);
1593 #define BOOLEAN_LOGIC(fn, r, s, t) \
1595 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1596 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1597 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1599 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1600 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1601 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1602 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1603 tcg_temp_free(tmp1); \
1604 tcg_temp_free(tmp2); \
1608 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1612 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1616 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1620 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1624 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1627 #undef BOOLEAN_LOGIC
1630 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1631 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1636 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1638 TCGv_i64 r
= tcg_temp_new_i64();
1639 TCGv_i64 s
= tcg_temp_new_i64();
1640 TCGv_i64 t
= tcg_temp_new_i64();
1643 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1644 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1646 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1647 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1649 tcg_gen_mul_i64(r
, s
, t
);
1650 tcg_gen_shri_i64(r
, r
, 32);
1651 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1653 tcg_temp_free_i64(r
);
1654 tcg_temp_free_i64(s
);
1655 tcg_temp_free_i64(t
);
1660 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1666 int label1
= gen_new_label();
1667 int label2
= gen_new_label();
1669 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1671 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1673 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1674 OP2
== 13 ? 0x80000000 : 0);
1676 gen_set_label(label1
);
1678 tcg_gen_div_i32(cpu_R
[RRR_R
],
1679 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1681 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1682 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1684 gen_set_label(label2
);
1689 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1692 default: /*reserved*/
1701 gen_check_sr(dc
, RSR_SR
);
1703 gen_check_privilege(dc
);
1705 gen_window_check1(dc
, RRR_T
);
1706 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1710 gen_check_sr(dc
, RSR_SR
);
1712 gen_check_privilege(dc
);
1714 gen_window_check1(dc
, RRR_T
);
1715 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1719 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1720 gen_window_check2(dc
, RRR_R
, RRR_S
);
1722 int shift
= 24 - RRR_T
;
1725 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1726 } else if (shift
== 16) {
1727 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1729 TCGv_i32 tmp
= tcg_temp_new_i32();
1730 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1731 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1738 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1739 gen_window_check2(dc
, RRR_R
, RRR_S
);
1741 TCGv_i32 tmp1
= tcg_temp_new_i32();
1742 TCGv_i32 tmp2
= tcg_temp_new_i32();
1743 int label
= gen_new_label();
1745 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1746 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1747 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1748 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1749 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1751 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1752 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1753 0xffffffff >> (25 - RRR_T
));
1755 gen_set_label(label
);
1757 tcg_temp_free(tmp1
);
1758 tcg_temp_free(tmp2
);
1766 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1767 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1769 static const TCGCond cond
[] = {
1775 int label
= gen_new_label();
1777 if (RRR_R
!= RRR_T
) {
1778 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1779 tcg_gen_brcond_i32(cond
[OP2
- 4],
1780 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1781 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1783 tcg_gen_brcond_i32(cond
[OP2
- 4],
1784 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1785 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1787 gen_set_label(label
);
1795 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1797 static const TCGCond cond
[] = {
1803 int label
= gen_new_label();
1804 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1805 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1806 gen_set_label(label
);
1812 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1813 gen_window_check2(dc
, RRR_R
, RRR_S
);
1815 int label
= gen_new_label();
1816 TCGv_i32 tmp
= tcg_temp_new_i32();
1818 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1819 tcg_gen_brcondi_i32(
1820 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1822 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1823 gen_set_label(label
);
1829 gen_window_check1(dc
, RRR_R
);
1831 int st
= (RRR_S
<< 4) + RRR_T
;
1832 if (uregnames
[st
].name
) {
1833 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1835 qemu_log("RUR %d not implemented, ", st
);
1842 gen_window_check1(dc
, RRR_T
);
1843 if (uregnames
[RSR_SR
].name
) {
1844 gen_wur(RSR_SR
, cpu_R
[RRR_T
]);
1846 qemu_log("WUR %d not implemented, ", RSR_SR
);
1856 gen_window_check2(dc
, RRR_R
, RRR_T
);
1858 int shiftimm
= RRR_S
| ((OP1
& 1) << 4);
1859 int maskimm
= (1 << (OP2
+ 1)) - 1;
1861 TCGv_i32 tmp
= tcg_temp_new_i32();
1862 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1863 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1882 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1883 gen_window_check2(dc
, RRR_S
, RRR_T
);
1884 gen_check_cpenable(dc
, 0);
1886 TCGv_i32 addr
= tcg_temp_new_i32();
1887 tcg_gen_add_i32(addr
, cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1888 gen_load_store_alignment(dc
, 2, addr
, false);
1890 tcg_gen_qemu_st32(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1892 tcg_gen_qemu_ld32u(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1895 tcg_gen_mov_i32(cpu_R
[RRR_S
], addr
);
1897 tcg_temp_free(addr
);
1901 default: /*reserved*/
1908 gen_window_check2(dc
, RRR_S
, RRR_T
);
1911 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1912 gen_check_privilege(dc
);
1914 TCGv_i32 addr
= tcg_temp_new_i32();
1915 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1916 (0xffffffc0 | (RRR_R
<< 2)));
1917 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1918 tcg_temp_free(addr
);
1923 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1924 gen_check_privilege(dc
);
1926 TCGv_i32 addr
= tcg_temp_new_i32();
1927 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1928 (0xffffffc0 | (RRR_R
<< 2)));
1929 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1930 tcg_temp_free(addr
);
1941 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1944 gen_check_cpenable(dc
, 0);
1945 gen_helper_add_s(cpu_FR
[RRR_R
], cpu_env
,
1946 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1950 gen_check_cpenable(dc
, 0);
1951 gen_helper_sub_s(cpu_FR
[RRR_R
], cpu_env
,
1952 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1956 gen_check_cpenable(dc
, 0);
1957 gen_helper_mul_s(cpu_FR
[RRR_R
], cpu_env
,
1958 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1962 gen_check_cpenable(dc
, 0);
1963 gen_helper_madd_s(cpu_FR
[RRR_R
], cpu_env
,
1964 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1968 gen_check_cpenable(dc
, 0);
1969 gen_helper_msub_s(cpu_FR
[RRR_R
], cpu_env
,
1970 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
1973 case 8: /*ROUND.Sf*/
1974 case 9: /*TRUNC.Sf*/
1975 case 10: /*FLOOR.Sf*/
1976 case 11: /*CEIL.Sf*/
1977 case 14: /*UTRUNC.Sf*/
1978 gen_window_check1(dc
, RRR_R
);
1979 gen_check_cpenable(dc
, 0);
1981 static const unsigned rounding_mode_const
[] = {
1982 float_round_nearest_even
,
1983 float_round_to_zero
,
1986 [6] = float_round_to_zero
,
1988 TCGv_i32 rounding_mode
= tcg_const_i32(
1989 rounding_mode_const
[OP2
& 7]);
1990 TCGv_i32 scale
= tcg_const_i32(RRR_T
);
1993 gen_helper_ftoui(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1994 rounding_mode
, scale
);
1996 gen_helper_ftoi(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
1997 rounding_mode
, scale
);
2000 tcg_temp_free(rounding_mode
);
2001 tcg_temp_free(scale
);
2005 case 12: /*FLOAT.Sf*/
2006 case 13: /*UFLOAT.Sf*/
2007 gen_window_check1(dc
, RRR_S
);
2008 gen_check_cpenable(dc
, 0);
2010 TCGv_i32 scale
= tcg_const_i32(-RRR_T
);
2013 gen_helper_uitof(cpu_FR
[RRR_R
], cpu_env
,
2014 cpu_R
[RRR_S
], scale
);
2016 gen_helper_itof(cpu_FR
[RRR_R
], cpu_env
,
2017 cpu_R
[RRR_S
], scale
);
2019 tcg_temp_free(scale
);
2026 gen_check_cpenable(dc
, 0);
2027 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2031 gen_check_cpenable(dc
, 0);
2032 gen_helper_abs_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2036 gen_window_check1(dc
, RRR_R
);
2037 gen_check_cpenable(dc
, 0);
2038 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_FR
[RRR_S
]);
2042 gen_window_check1(dc
, RRR_S
);
2043 gen_check_cpenable(dc
, 0);
2044 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_R
[RRR_S
]);
2048 gen_check_cpenable(dc
, 0);
2049 gen_helper_neg_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2052 default: /*reserved*/
2058 default: /*reserved*/
2065 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2067 #define gen_compare(rel, br, a, b) \
2069 TCGv_i32 bit = tcg_const_i32(1 << br); \
2071 gen_check_cpenable(dc, 0); \
2072 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2073 tcg_temp_free(bit); \
2078 gen_compare(un_s
, RRR_R
, RRR_S
, RRR_T
);
2082 gen_compare(oeq_s
, RRR_R
, RRR_S
, RRR_T
);
2086 gen_compare(ueq_s
, RRR_R
, RRR_S
, RRR_T
);
2090 gen_compare(olt_s
, RRR_R
, RRR_S
, RRR_T
);
2094 gen_compare(ult_s
, RRR_R
, RRR_S
, RRR_T
);
2098 gen_compare(ole_s
, RRR_R
, RRR_S
, RRR_T
);
2102 gen_compare(ule_s
, RRR_R
, RRR_S
, RRR_T
);
2107 case 8: /*MOVEQZ.Sf*/
2108 case 9: /*MOVNEZ.Sf*/
2109 case 10: /*MOVLTZ.Sf*/
2110 case 11: /*MOVGEZ.Sf*/
2111 gen_window_check1(dc
, RRR_T
);
2112 gen_check_cpenable(dc
, 0);
2114 static const TCGCond cond
[] = {
2120 int label
= gen_new_label();
2121 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
2122 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2123 gen_set_label(label
);
2127 case 12: /*MOVF.Sf*/
2128 case 13: /*MOVT.Sf*/
2129 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2130 gen_check_cpenable(dc
, 0);
2132 int label
= gen_new_label();
2133 TCGv_i32 tmp
= tcg_temp_new_i32();
2135 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
2136 tcg_gen_brcondi_i32(
2137 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
2139 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2140 gen_set_label(label
);
2145 default: /*reserved*/
2151 default: /*reserved*/
2158 gen_window_check1(dc
, RRR_T
);
2160 TCGv_i32 tmp
= tcg_const_i32(
2161 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
2162 0 : ((dc
->pc
+ 3) & ~3)) +
2163 (0xfffc0000 | (RI16_IMM16
<< 2)));
2165 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
2166 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
2168 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
2174 #define gen_load_store(type, shift) do { \
2175 TCGv_i32 addr = tcg_temp_new_i32(); \
2176 gen_window_check2(dc, RRI8_S, RRI8_T); \
2177 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2179 gen_load_store_alignment(dc, shift, addr, false); \
2181 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2182 tcg_temp_free(addr); \
2187 gen_load_store(ld8u
, 0);
2191 gen_load_store(ld16u
, 1);
2195 gen_load_store(ld32u
, 2);
2199 gen_load_store(st8
, 0);
2203 gen_load_store(st16
, 1);
2207 gen_load_store(st32
, 2);
2212 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2243 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2247 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2251 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2255 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2259 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2262 default: /*reserved*/
2270 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2276 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2280 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2284 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2287 default: /*reserved*/
2294 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2298 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2301 default: /*reserved*/
2308 gen_load_store(ld16s
, 1);
2310 #undef gen_load_store
2313 gen_window_check1(dc
, RRI8_T
);
2314 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2315 RRI8_IMM8
| (RRI8_S
<< 8) |
2316 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2319 #define gen_load_store_no_hw_align(type) do { \
2320 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2321 gen_window_check2(dc, RRI8_S, RRI8_T); \
2322 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2323 gen_load_store_alignment(dc, 2, addr, true); \
2324 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2325 tcg_temp_free(addr); \
2329 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2330 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2334 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2335 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2339 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2340 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
2343 case 14: /*S32C1Iy*/
2344 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2345 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2347 int label
= gen_new_label();
2348 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2349 TCGv_i32 addr
= tcg_temp_local_new_i32();
2352 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2353 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2354 gen_load_store_alignment(dc
, 2, addr
, true);
2356 gen_advance_ccount(dc
);
2357 tpc
= tcg_const_i32(dc
->pc
);
2358 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2359 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2360 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2361 cpu_SR
[SCOMPARE1
], label
);
2363 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2365 gen_set_label(label
);
2367 tcg_temp_free(addr
);
2373 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2374 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2376 #undef gen_load_store_no_hw_align
2378 default: /*reserved*/
2390 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2391 gen_window_check1(dc
, RRI8_S
);
2392 gen_check_cpenable(dc
, 0);
2394 TCGv_i32 addr
= tcg_temp_new_i32();
2395 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2396 gen_load_store_alignment(dc
, 2, addr
, false);
2398 tcg_gen_qemu_st32(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2400 tcg_gen_qemu_ld32u(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2403 tcg_gen_mov_i32(cpu_R
[RRI8_S
], addr
);
2405 tcg_temp_free(addr
);
2409 default: /*reserved*/
2416 HAS_OPTION(XTENSA_OPTION_MAC16
);
2425 bool is_m1_sr
= (OP2
& 0x3) == 2;
2426 bool is_m2_sr
= (OP2
& 0xc) == 0;
2427 uint32_t ld_offset
= 0;
2434 case 0: /*MACI?/MACC?*/
2436 ld_offset
= (OP2
& 1) ? -4 : 4;
2438 if (OP2
>= 8) { /*MACI/MACC*/
2439 if (OP1
== 0) { /*LDINC/LDDEC*/
2444 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2449 case 2: /*MACD?/MACA?*/
2450 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2456 if (op
!= MAC16_NONE
) {
2458 gen_window_check1(dc
, RRR_S
);
2461 gen_window_check1(dc
, RRR_T
);
2466 TCGv_i32 vaddr
= tcg_temp_new_i32();
2467 TCGv_i32 mem32
= tcg_temp_new_i32();
2470 gen_window_check1(dc
, RRR_S
);
2471 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2472 gen_load_store_alignment(dc
, 2, vaddr
, false);
2473 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2475 if (op
!= MAC16_NONE
) {
2476 TCGv_i32 m1
= gen_mac16_m(
2477 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2478 OP1
& 1, op
== MAC16_UMUL
);
2479 TCGv_i32 m2
= gen_mac16_m(
2480 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2481 OP1
& 2, op
== MAC16_UMUL
);
2483 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2484 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2485 if (op
== MAC16_UMUL
) {
2486 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2488 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2491 TCGv_i32 res
= tcg_temp_new_i32();
2492 TCGv_i64 res64
= tcg_temp_new_i64();
2493 TCGv_i64 tmp
= tcg_temp_new_i64();
2495 tcg_gen_mul_i32(res
, m1
, m2
);
2496 tcg_gen_ext_i32_i64(res64
, res
);
2497 tcg_gen_concat_i32_i64(tmp
,
2498 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
]);
2499 if (op
== MAC16_MULA
) {
2500 tcg_gen_add_i64(tmp
, tmp
, res64
);
2502 tcg_gen_sub_i64(tmp
, tmp
, res64
);
2504 tcg_gen_trunc_i64_i32(cpu_SR
[ACCLO
], tmp
);
2505 tcg_gen_shri_i64(tmp
, tmp
, 32);
2506 tcg_gen_trunc_i64_i32(cpu_SR
[ACCHI
], tmp
);
2507 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2510 tcg_temp_free_i64(res64
);
2511 tcg_temp_free_i64(tmp
);
2517 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2518 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2520 tcg_temp_free(vaddr
);
2521 tcg_temp_free(mem32
);
2529 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2530 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2536 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2537 gen_window_check1(dc
, CALL_N
<< 2);
2538 gen_callwi(dc
, CALL_N
,
2539 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2547 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2551 gen_window_check1(dc
, BRI12_S
);
2553 static const TCGCond cond
[] = {
2554 TCG_COND_EQ
, /*BEQZ*/
2555 TCG_COND_NE
, /*BNEZ*/
2556 TCG_COND_LT
, /*BLTZ*/
2557 TCG_COND_GE
, /*BGEZ*/
2560 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2561 4 + BRI12_IMM12_SE
);
2566 gen_window_check1(dc
, BRI8_S
);
2568 static const TCGCond cond
[] = {
2569 TCG_COND_EQ
, /*BEQI*/
2570 TCG_COND_NE
, /*BNEI*/
2571 TCG_COND_LT
, /*BLTI*/
2572 TCG_COND_GE
, /*BGEI*/
2575 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2576 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2583 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2585 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2586 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2587 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2588 gen_advance_ccount(dc
);
2589 gen_helper_entry(cpu_env
, pc
, s
, imm
);
2593 reset_used_window(dc
);
2601 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2603 TCGv_i32 tmp
= tcg_temp_new_i32();
2604 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2606 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2607 tmp
, 0, 4 + RRI8_IMM8_SE
);
2614 case 10: /*LOOPGTZ*/
2615 HAS_OPTION(XTENSA_OPTION_LOOP
);
2616 gen_window_check1(dc
, RRI8_S
);
2618 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2619 TCGv_i32 tmp
= tcg_const_i32(lend
);
2621 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2622 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2623 gen_helper_wsr_lend(cpu_env
, tmp
);
2627 int label
= gen_new_label();
2628 tcg_gen_brcondi_i32(
2629 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2630 cpu_R
[RRI8_S
], 0, label
);
2631 gen_jumpi(dc
, lend
, 1);
2632 gen_set_label(label
);
2635 gen_jumpi(dc
, dc
->next_pc
, 0);
2639 default: /*reserved*/
2648 gen_window_check1(dc
, BRI8_S
);
2649 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2650 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2660 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2662 switch (RRI8_R
& 7) {
2663 case 0: /*BNONE*/ /*BANY*/
2664 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2666 TCGv_i32 tmp
= tcg_temp_new_i32();
2667 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2668 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2673 case 1: /*BEQ*/ /*BNE*/
2674 case 2: /*BLT*/ /*BGE*/
2675 case 3: /*BLTU*/ /*BGEU*/
2676 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2678 static const TCGCond cond
[] = {
2684 [11] = TCG_COND_GEU
,
2686 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2691 case 4: /*BALL*/ /*BNALL*/
2692 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2694 TCGv_i32 tmp
= tcg_temp_new_i32();
2695 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2696 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2702 case 5: /*BBC*/ /*BBS*/
2703 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2705 #ifdef TARGET_WORDS_BIGENDIAN
2706 TCGv_i32 bit
= tcg_const_i32(0x80000000);
2708 TCGv_i32 bit
= tcg_const_i32(0x00000001);
2710 TCGv_i32 tmp
= tcg_temp_new_i32();
2711 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2712 #ifdef TARGET_WORDS_BIGENDIAN
2713 tcg_gen_shr_i32(bit
, bit
, tmp
);
2715 tcg_gen_shl_i32(bit
, bit
, tmp
);
2717 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2718 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2724 case 6: /*BBCI*/ /*BBSI*/
2726 gen_window_check1(dc
, RRI8_S
);
2728 TCGv_i32 tmp
= tcg_temp_new_i32();
2729 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2730 #ifdef TARGET_WORDS_BIGENDIAN
2731 0x80000000 >> (((RRI8_R
& 1) << 4) | RRI8_T
));
2733 0x00000001 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2735 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2744 #define gen_narrow_load_store(type) do { \
2745 TCGv_i32 addr = tcg_temp_new_i32(); \
2746 gen_window_check2(dc, RRRN_S, RRRN_T); \
2747 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2748 gen_load_store_alignment(dc, 2, addr, false); \
2749 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2750 tcg_temp_free(addr); \
2754 gen_narrow_load_store(ld32u
);
2758 gen_narrow_load_store(st32
);
2760 #undef gen_narrow_load_store
2763 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2764 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2767 case 11: /*ADDI.Nn*/
2768 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2769 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2773 gen_window_check1(dc
, RRRN_S
);
2774 if (RRRN_T
< 8) { /*MOVI.Nn*/
2775 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2776 RRRN_R
| (RRRN_T
<< 4) |
2777 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2778 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2779 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2781 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2782 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2789 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2790 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2796 gen_jump(dc
, cpu_R
[0]);
2800 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2802 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2803 gen_advance_ccount(dc
);
2804 gen_helper_retw(tmp
, cpu_env
, tmp
);
2810 case 2: /*BREAK.Nn*/
2811 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2813 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2821 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2824 default: /*reserved*/
2830 default: /*reserved*/
2836 default: /*reserved*/
2841 if (dc
->is_jmp
== DISAS_NEXT
) {
2842 gen_check_loop_end(dc
, 0);
2844 dc
->pc
= dc
->next_pc
;
2849 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2850 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2854 static void check_breakpoint(CPUXtensaState
*env
, DisasContext
*dc
)
2858 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2859 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2860 if (bp
->pc
== dc
->pc
) {
2861 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2862 gen_exception(dc
, EXCP_DEBUG
);
2863 dc
->is_jmp
= DISAS_UPDATE
;
2869 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
2873 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
2874 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
2875 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
2876 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
2882 static void gen_intermediate_code_internal(
2883 CPUXtensaState
*env
, TranslationBlock
*tb
, int search_pc
)
2888 uint16_t *gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
2889 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2890 uint32_t pc_start
= tb
->pc
;
2891 uint32_t next_page_start
=
2892 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2894 if (max_insns
== 0) {
2895 max_insns
= CF_COUNT_MASK
;
2898 dc
.config
= env
->config
;
2899 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2902 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2903 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2904 dc
.lbeg
= env
->sregs
[LBEG
];
2905 dc
.lend
= env
->sregs
[LEND
];
2906 dc
.is_jmp
= DISAS_NEXT
;
2907 dc
.ccount_delta
= 0;
2908 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
2909 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
2910 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
2911 XTENSA_TBFLAG_CPENABLE_SHIFT
;
2914 init_sar_tracker(&dc
);
2915 reset_used_window(&dc
);
2917 dc
.next_icount
= tcg_temp_local_new_i32();
2922 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2923 env
->exception_taken
= 0;
2924 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2925 gen_exception(&dc
, EXCP_DEBUG
);
2929 check_breakpoint(env
, &dc
);
2932 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
2936 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
2939 tcg_ctx
.gen_opc_pc
[lj
] = dc
.pc
;
2940 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
2941 tcg_ctx
.gen_opc_icount
[lj
] = insn_count
;
2944 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2945 tcg_gen_debug_insn_start(dc
.pc
);
2950 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2955 int label
= gen_new_label();
2957 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
2958 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
2959 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
2961 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
2963 gen_set_label(label
);
2967 gen_ibreak_check(env
, &dc
);
2970 disas_xtensa_insn(env
, &dc
);
2973 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
2975 if (env
->singlestep_enabled
) {
2976 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2977 gen_exception(&dc
, EXCP_DEBUG
);
2980 } while (dc
.is_jmp
== DISAS_NEXT
&&
2981 insn_count
< max_insns
&&
2982 dc
.pc
< next_page_start
&&
2983 tcg_ctx
.gen_opc_ptr
< gen_opc_end
);
2986 reset_sar_tracker(&dc
);
2988 tcg_temp_free(dc
.next_icount
);
2991 if (tb
->cflags
& CF_LAST_IO
) {
2995 if (dc
.is_jmp
== DISAS_NEXT
) {
2996 gen_jumpi(&dc
, dc
.pc
, 0);
2998 gen_icount_end(tb
, insn_count
);
2999 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
3002 tb
->size
= dc
.pc
- pc_start
;
3003 tb
->icount
= insn_count
;
3007 void gen_intermediate_code(CPUXtensaState
*env
, TranslationBlock
*tb
)
3009 gen_intermediate_code_internal(env
, tb
, 0);
3012 void gen_intermediate_code_pc(CPUXtensaState
*env
, TranslationBlock
*tb
)
3014 gen_intermediate_code_internal(env
, tb
, 1);
3017 void cpu_dump_state(CPUXtensaState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
3022 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
3024 for (i
= j
= 0; i
< 256; ++i
) {
3025 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
3026 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
3027 (j
++ % 4) == 3 ? '\n' : ' ');
3031 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3033 for (i
= j
= 0; i
< 256; ++i
) {
3034 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
3035 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
3036 (j
++ % 4) == 3 ? '\n' : ' ');
3040 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3042 for (i
= 0; i
< 16; ++i
) {
3043 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
3044 (i
% 4) == 3 ? '\n' : ' ');
3047 cpu_fprintf(f
, "\n");
3049 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
3050 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
3051 (i
% 4) == 3 ? '\n' : ' ');
3054 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
3055 cpu_fprintf(f
, "\n");
3057 for (i
= 0; i
< 16; ++i
) {
3058 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
3059 float32_val(env
->fregs
[i
]),
3060 *(float *)&env
->fregs
[i
], (i
% 2) == 1 ? '\n' : ' ');
3065 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
, int pc_pos
)
3067 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];