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1 Tiny Code Generator - Fabrice Bellard.
2
3 1) Introduction
4
5 TCG (Tiny Code Generator) began as a generic backend for a C
6 compiler. It was simplified to be used in QEMU. It also has its roots
7 in the QOP code generator written by Paul Brook.
8
9 2) Definitions
10
11 TCG receives RISC-like "TCG ops" and performs some optimizations on them,
12 including liveness analysis and trivial constant expression
13 evaluation. TCG ops are then implemented in the host CPU back end,
14 also known as the TCG "target".
15
16 The TCG "target" is the architecture for which we generate the
17 code. It is of course not the same as the "target" of QEMU which is
18 the emulated architecture. As TCG started as a generic C backend used
19 for cross compiling, it is assumed that the TCG target is different
20 from the host, although it is never the case for QEMU.
21
22 In this document, we use "guest" to specify what architecture we are
23 emulating; "target" always means the TCG target, the machine on which
24 we are running QEMU.
25
26 A TCG "function" corresponds to a QEMU Translated Block (TB).
27
28 A TCG "temporary" is a variable only live in a basic
29 block. Temporaries are allocated explicitly in each function.
30
31 A TCG "local temporary" is a variable only live in a function. Local
32 temporaries are allocated explicitly in each function.
33
34 A TCG "global" is a variable which is live in all the functions
35 (equivalent of a C global variable). They are defined before the
36 functions defined. A TCG global can be a memory location (e.g. a QEMU
37 CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
38 or a memory location which is stored in a register outside QEMU TBs
39 (not implemented yet).
40
41 A TCG "basic block" corresponds to a list of instructions terminated
42 by a branch instruction.
43
44 An operation with "undefined behavior" may result in a crash.
45
46 An operation with "unspecified behavior" shall not crash. However,
47 the result may be one of several possibilities so may be considered
48 an "undefined result".
49
50 3) Intermediate representation
51
52 3.1) Introduction
53
54 TCG instructions operate on variables which are temporaries, local
55 temporaries or globals. TCG instructions and variables are strongly
56 typed. Two types are supported: 32 bit integers and 64 bit
57 integers. Pointers are defined as an alias to 32 bit or 64 bit
58 integers depending on the TCG target word size.
59
60 Each instruction has a fixed number of output variable operands, input
61 variable operands and always constant operands.
62
63 The notable exception is the call instruction which has a variable
64 number of outputs and inputs.
65
66 In the textual form, output operands usually come first, followed by
67 input operands, followed by constant operands. The output type is
68 included in the instruction name. Constants are prefixed with a '$'.
69
70 add_i32 t0, t1, t2 (t0 <- t1 + t2)
71
72 3.2) Assumptions
73
74 * Basic blocks
75
76 - Basic blocks end after branches (e.g. brcond_i32 instruction),
77 goto_tb and exit_tb instructions.
78 - Basic blocks start after the end of a previous basic block, or at a
79 set_label instruction.
80
81 After the end of a basic block, the content of temporaries is
82 destroyed, but local temporaries and globals are preserved.
83
84 * Floating point types are not supported yet
85
86 * Pointers: depending on the TCG target, pointer size is 32 bit or 64
87 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
88 TCG_TYPE_I64.
89
90 * Helpers:
91
92 Using the tcg_gen_helper_x_y it is possible to call any function
93 taking i32, i64 or pointer types. By default, before calling a helper,
94 all globals are stored at their canonical location and it is assumed
95 that the function can modify them. By default, the helper is allowed to
96 modify the CPU state or raise an exception.
97
98 This can be overridden using the following function modifiers:
99 - TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,
100 either directly or via an exception. They will not be saved to their
101 canonical locations before calling the helper.
102 - TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
103 They will only be saved to their canonical location before calling helpers,
104 but they won't be reloaded afterwise.
105 - TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
106 the return value is not used.
107
108 Note that TCG_CALL_NO_READ_GLOBALS implies TCG_CALL_NO_WRITE_GLOBALS.
109
110 On some TCG targets (e.g. x86), several calling conventions are
111 supported.
112
113 * Branches:
114
115 Use the instruction 'br' to jump to a label.
116
117 3.3) Code Optimizations
118
119 When generating instructions, you can count on at least the following
120 optimizations:
121
122 - Single instructions are simplified, e.g.
123
124 and_i32 t0, t0, $0xffffffff
125
126 is suppressed.
127
128 - A liveness analysis is done at the basic block level. The
129 information is used to suppress moves from a dead variable to
130 another one. It is also used to remove instructions which compute
131 dead results. The later is especially useful for condition code
132 optimization in QEMU.
133
134 In the following example:
135
136 add_i32 t0, t1, t2
137 add_i32 t0, t0, $1
138 mov_i32 t0, $1
139
140 only the last instruction is kept.
141
142 3.4) Instruction Reference
143
144 ********* Function call
145
146 * call <ret> <params> ptr
147
148 call function 'ptr' (pointer type)
149
150 <ret> optional 32 bit or 64 bit return value
151 <params> optional 32 bit or 64 bit parameters
152
153 ********* Jumps/Labels
154
155 * set_label $label
156
157 Define label 'label' at the current program point.
158
159 * br $label
160
161 Jump to label.
162
163 * brcond_i32/i64 t0, t1, cond, label
164
165 Conditional jump if t0 cond t1 is true. cond can be:
166 TCG_COND_EQ
167 TCG_COND_NE
168 TCG_COND_LT /* signed */
169 TCG_COND_GE /* signed */
170 TCG_COND_LE /* signed */
171 TCG_COND_GT /* signed */
172 TCG_COND_LTU /* unsigned */
173 TCG_COND_GEU /* unsigned */
174 TCG_COND_LEU /* unsigned */
175 TCG_COND_GTU /* unsigned */
176
177 ********* Arithmetic
178
179 * add_i32/i64 t0, t1, t2
180
181 t0=t1+t2
182
183 * sub_i32/i64 t0, t1, t2
184
185 t0=t1-t2
186
187 * neg_i32/i64 t0, t1
188
189 t0=-t1 (two's complement)
190
191 * mul_i32/i64 t0, t1, t2
192
193 t0=t1*t2
194
195 * div_i32/i64 t0, t1, t2
196
197 t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
198
199 * divu_i32/i64 t0, t1, t2
200
201 t0=t1/t2 (unsigned). Undefined behavior if division by zero.
202
203 * rem_i32/i64 t0, t1, t2
204
205 t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
206
207 * remu_i32/i64 t0, t1, t2
208
209 t0=t1%t2 (unsigned). Undefined behavior if division by zero.
210
211 ********* Logical
212
213 * and_i32/i64 t0, t1, t2
214
215 t0=t1&t2
216
217 * or_i32/i64 t0, t1, t2
218
219 t0=t1|t2
220
221 * xor_i32/i64 t0, t1, t2
222
223 t0=t1^t2
224
225 * not_i32/i64 t0, t1
226
227 t0=~t1
228
229 * andc_i32/i64 t0, t1, t2
230
231 t0=t1&~t2
232
233 * eqv_i32/i64 t0, t1, t2
234
235 t0=~(t1^t2), or equivalently, t0=t1^~t2
236
237 * nand_i32/i64 t0, t1, t2
238
239 t0=~(t1&t2)
240
241 * nor_i32/i64 t0, t1, t2
242
243 t0=~(t1|t2)
244
245 * orc_i32/i64 t0, t1, t2
246
247 t0=t1|~t2
248
249 * clz_i32/i64 t0, t1, t2
250
251 t0 = t1 ? clz(t1) : t2
252
253 * ctz_i32/i64 t0, t1, t2
254
255 t0 = t1 ? ctz(t1) : t2
256
257 ********* Shifts/Rotates
258
259 * shl_i32/i64 t0, t1, t2
260
261 t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
262
263 * shr_i32/i64 t0, t1, t2
264
265 t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
266
267 * sar_i32/i64 t0, t1, t2
268
269 t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
270
271 * rotl_i32/i64 t0, t1, t2
272
273 Rotation of t2 bits to the left.
274 Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
275
276 * rotr_i32/i64 t0, t1, t2
277
278 Rotation of t2 bits to the right.
279 Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
280
281 ********* Misc
282
283 * mov_i32/i64 t0, t1
284
285 t0 = t1
286
287 Move t1 to t0 (both operands must have the same type).
288
289 * ext8s_i32/i64 t0, t1
290 ext8u_i32/i64 t0, t1
291 ext16s_i32/i64 t0, t1
292 ext16u_i32/i64 t0, t1
293 ext32s_i64 t0, t1
294 ext32u_i64 t0, t1
295
296 8, 16 or 32 bit sign/zero extension (both operands must have the same type)
297
298 * bswap16_i32/i64 t0, t1
299
300 16 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
301 bytes are set to zero.
302
303 * bswap32_i32/i64 t0, t1
304
305 32 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
306 the four high order bytes are set to zero.
307
308 * bswap64_i64 t0, t1
309
310 64 bit byte swap
311
312 * discard_i32/i64 t0
313
314 Indicate that the value of t0 won't be used later. It is useful to
315 force dead code elimination.
316
317 * deposit_i32/i64 dest, t1, t2, pos, len
318
319 Deposit T2 as a bitfield into T1, placing the result in DEST.
320 The bitfield is described by POS/LEN, which are immediate values:
321
322 LEN - the length of the bitfield
323 POS - the position of the first bit, counting from the LSB
324
325 For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
326 at bit 8. This operation would be equivalent to
327
328 dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
329
330 * extract_i32/i64 dest, t1, pos, len
331 * sextract_i32/i64 dest, t1, pos, len
332
333 Extract a bitfield from T1, placing the result in DEST.
334 The bitfield is described by POS/LEN, which are immediate values,
335 as above for deposit. For extract_*, the result will be extended
336 to the left with zeros; for sextract_*, the result will be extended
337 to the left with copies of the bitfield sign bit at pos + len - 1.
338
339 For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
340 at bit 8. This operation would be equivalent to
341
342 dest = (t1 << 20) >> 28
343
344 (using an arithmetic right shift).
345
346 * extrl_i64_i32 t0, t1
347
348 For 64-bit hosts only, extract the low 32-bits of input T1 and place it
349 into 32-bit output T0. Depending on the host, this may be a simple move,
350 or may require additional canonicalization.
351
352 * extrh_i64_i32 t0, t1
353
354 For 64-bit hosts only, extract the high 32-bits of input T1 and place it
355 into 32-bit output T0. Depending on the host, this may be a simple shift,
356 or may require additional canonicalization.
357
358 ********* Conditional moves
359
360 * setcond_i32/i64 dest, t1, t2, cond
361
362 dest = (t1 cond t2)
363
364 Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
365
366 * movcond_i32/i64 dest, c1, c2, v1, v2, cond
367
368 dest = (c1 cond c2 ? v1 : v2)
369
370 Set DEST to V1 if (C1 cond C2) is true, otherwise set to V2.
371
372 ********* Type conversions
373
374 * ext_i32_i64 t0, t1
375 Convert t1 (32 bit) to t0 (64 bit) and does sign extension
376
377 * extu_i32_i64 t0, t1
378 Convert t1 (32 bit) to t0 (64 bit) and does zero extension
379
380 * trunc_i64_i32 t0, t1
381 Truncate t1 (64 bit) to t0 (32 bit)
382
383 * concat_i32_i64 t0, t1, t2
384 Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
385 from t2 (32 bit).
386
387 * concat32_i64 t0, t1, t2
388 Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
389 from t2 (64 bit).
390
391 ********* Load/Store
392
393 * ld_i32/i64 t0, t1, offset
394 ld8s_i32/i64 t0, t1, offset
395 ld8u_i32/i64 t0, t1, offset
396 ld16s_i32/i64 t0, t1, offset
397 ld16u_i32/i64 t0, t1, offset
398 ld32s_i64 t0, t1, offset
399 ld32u_i64 t0, t1, offset
400
401 t0 = read(t1 + offset)
402 Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
403 offset must be a constant.
404
405 * st_i32/i64 t0, t1, offset
406 st8_i32/i64 t0, t1, offset
407 st16_i32/i64 t0, t1, offset
408 st32_i64 t0, t1, offset
409
410 write(t0, t1 + offset)
411 Write 8, 16, 32 or 64 bits to host memory.
412
413 All this opcodes assume that the pointed host memory doesn't correspond
414 to a global. In the latter case the behaviour is unpredictable.
415
416 ********* Multiword arithmetic support
417
418 * add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
419 * sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
420
421 Similar to add/sub, except that the double-word inputs T1 and T2 are
422 formed from two single-word arguments, and the double-word output T0
423 is returned in two single-word outputs.
424
425 * mulu2_i32/i64 t0_low, t0_high, t1, t2
426
427 Similar to mul, except two unsigned inputs T1 and T2 yielding the full
428 double-word product T0. The later is returned in two single-word outputs.
429
430 * muls2_i32/i64 t0_low, t0_high, t1, t2
431
432 Similar to mulu2, except the two inputs T1 and T2 are signed.
433
434 * mulsh_i32/i64 t0, t1, t2
435 * muluh_i32/i64 t0, t1, t2
436
437 Provide the high part of a signed or unsigned multiply, respectively.
438 If mulu2/muls2 are not provided by the backend, the tcg-op generator
439 can obtain the same results can be obtained by emitting a pair of
440 opcodes, mul+muluh/mulsh.
441
442 ********* Memory Barrier support
443
444 * mb <$arg>
445
446 Generate a target memory barrier instruction to ensure memory ordering as being
447 enforced by a corresponding guest memory barrier instruction. The ordering
448 enforced by the backend may be stricter than the ordering required by the guest.
449 It cannot be weaker. This opcode takes a constant argument which is required to
450 generate the appropriate barrier instruction. The backend should take care to
451 emit the target barrier instruction only when necessary i.e., for SMP guests and
452 when MTTCG is enabled.
453
454 The guest translators should generate this opcode for all guest instructions
455 which have ordering side effects.
456
457 Please see docs/devel/atomics.txt for more information on memory barriers.
458
459 ********* 64-bit guest on 32-bit host support
460
461 The following opcodes are internal to TCG. Thus they are to be implemented by
462 32-bit host code generators, but are not to be emitted by guest translators.
463 They are emitted as needed by inline functions within "tcg-op.h".
464
465 * brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
466
467 Similar to brcond, except that the 64-bit values T0 and T1
468 are formed from two 32-bit arguments.
469
470 * setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
471
472 Similar to setcond, except that the 64-bit values T1 and T2 are
473 formed from two 32-bit arguments. The result is a 32-bit value.
474
475 ********* QEMU specific operations
476
477 * exit_tb t0
478
479 Exit the current TB and return the value t0 (word type).
480
481 * goto_tb index
482
483 Exit the current TB and jump to the TB index 'index' (constant) if the
484 current TB was linked to this TB. Otherwise execute the next
485 instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
486 at most once with each slot index per TB.
487
488 * lookup_and_goto_ptr tb_addr
489
490 Look up a TB address ('tb_addr') and jump to it if valid. If not valid,
491 jump to the TCG epilogue to go back to the exec loop.
492
493 This operation is optional. If the TCG backend does not implement the
494 goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0).
495
496 * qemu_ld_i32/i64 t0, t1, flags, memidx
497 * qemu_st_i32/i64 t0, t1, flags, memidx
498
499 Load data at the guest address t1 into t0, or store data in t0 at guest
500 address t1. The _i32/_i64 size applies to the size of the input/output
501 register t0 only. The address t1 is always sized according to the guest,
502 and the width of the memory operation is controlled by flags.
503
504 Both t0 and t1 may be split into little-endian ordered pairs of registers
505 if dealing with 64-bit quantities on a 32-bit host.
506
507 The memidx selects the qemu tlb index to use (e.g. user or kernel access).
508 The flags are the TCGMemOp bits, selecting the sign, width, and endianness
509 of the memory access.
510
511 For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
512 64-bit memory access specified in flags.
513
514 ********* Host vector operations
515
516 All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE.
517 The former specifies the length of the vector in log2 64-bit units; the
518 later specifies the length of the element (if applicable) in log2 8-bit units.
519 E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
520
521 * mov_vec v0, v1
522 * ld_vec v0, t1
523 * st_vec v0, t1
524
525 Move, load and store.
526
527 * dup_vec v0, r1
528
529 Duplicate the low N bits of R1 into VECL/VECE copies across V0.
530
531 * dupi_vec v0, c
532
533 Similarly, for a constant.
534 Smaller values will be replicated to host register size by the expanders.
535
536 * dup2_vec v0, r1, r2
537
538 Duplicate r2:r1 into VECL/64 copies across V0. This opcode is
539 only present for 32-bit hosts.
540
541 * add_vec v0, v1, v2
542
543 v0 = v1 + v2, in elements across the vector.
544
545 * sub_vec v0, v1, v2
546
547 Similarly, v0 = v1 - v2.
548
549 * mul_vec v0, v1, v2
550
551 Similarly, v0 = v1 * v2.
552
553 * neg_vec v0, v1
554
555 Similarly, v0 = -v1.
556
557 * smin_vec:
558 * umin_vec:
559
560 Similarly, v0 = MIN(v1, v2), for signed and unsigned element types.
561
562 * smax_vec:
563 * umax_vec:
564
565 Similarly, v0 = MAX(v1, v2), for signed and unsigned element types.
566
567 * ssadd_vec:
568 * sssub_vec:
569 * usadd_vec:
570 * ussub_vec:
571
572 Signed and unsigned saturating addition and subtraction. If the true
573 result is not representable within the element type, the element is
574 set to the minimum or maximum value for the type.
575
576 * and_vec v0, v1, v2
577 * or_vec v0, v1, v2
578 * xor_vec v0, v1, v2
579 * andc_vec v0, v1, v2
580 * orc_vec v0, v1, v2
581 * not_vec v0, v1
582
583 Similarly, logical operations with and without complement.
584 Note that VECE is unused.
585
586 * shli_vec v0, v1, i2
587 * shls_vec v0, v1, s2
588
589 Shift all elements from v1 by a scalar i2/s2. I.e.
590
591 for (i = 0; i < VECL/VECE; ++i) {
592 v0[i] = v1[i] << s2;
593 }
594
595 * shri_vec v0, v1, i2
596 * sari_vec v0, v1, i2
597 * shrs_vec v0, v1, s2
598 * sars_vec v0, v1, s2
599
600 Similarly for logical and arithmetic right shift.
601
602 * shlv_vec v0, v1, v2
603
604 Shift elements from v1 by elements from v2. I.e.
605
606 for (i = 0; i < VECL/VECE; ++i) {
607 v0[i] = v1[i] << v2[i];
608 }
609
610 * shrv_vec v0, v1, v2
611 * sarv_vec v0, v1, v2
612
613 Similarly for logical and arithmetic right shift.
614
615 * cmp_vec v0, v1, v2, cond
616
617 Compare vectors by element, storing -1 for true and 0 for false.
618
619 *********
620
621 Note 1: Some shortcuts are defined when the last operand is known to be
622 a constant (e.g. addi for add, movi for mov).
623
624 Note 2: When using TCG, the opcodes must never be generated directly
625 as some of them may not be available as "real" opcodes. Always use the
626 function tcg_gen_xxx(args).
627
628 4) Backend
629
630 tcg-target.h contains the target specific definitions. tcg-target.inc.c
631 contains the target specific code; it is #included by tcg/tcg.c, rather
632 than being a standalone C file.
633
634 4.1) Assumptions
635
636 The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
637 64 bit. It is expected that the pointer has the same size as the word.
638
639 On a 32 bit target, all 64 bit operations are converted to 32 bits. A
640 few specific operations must be implemented to allow it (see add2_i32,
641 sub2_i32, brcond2_i32).
642
643 On a 64 bit target, the values are transferred between 32 and 64-bit
644 registers using the following ops:
645 - trunc_shr_i64_i32
646 - ext_i32_i64
647 - extu_i32_i64
648
649 They ensure that the values are correctly truncated or extended when
650 moved from a 32-bit to a 64-bit register or vice-versa. Note that the
651 trunc_shr_i64_i32 is an optional op. It is not necessary to implement
652 it if all the following conditions are met:
653 - 64-bit registers can hold 32-bit values
654 - 32-bit values in a 64-bit register do not need to stay zero or
655 sign extended
656 - all 32-bit TCG ops ignore the high part of 64-bit registers
657
658 Floating point operations are not supported in this version. A
659 previous incarnation of the code generator had full support of them,
660 but it is better to concentrate on integer operations first.
661
662 4.2) Constraints
663
664 GCC like constraints are used to define the constraints of every
665 instruction. Memory constraints are not supported in this
666 version. Aliases are specified in the input operands as for GCC.
667
668 The same register may be used for both an input and an output, even when
669 they are not explicitly aliased. If an op expands to multiple target
670 instructions then care must be taken to avoid clobbering input values.
671 GCC style "early clobber" outputs are supported, with '&'.
672
673 A target can define specific register or constant constraints. If an
674 operation uses a constant input constraint which does not allow all
675 constants, it must also accept registers in order to have a fallback.
676 The constraint 'i' is defined generically to accept any constant.
677 The constraint 'r' is not defined generically, but is consistently
678 used by each backend to indicate all registers.
679
680 The movi_i32 and movi_i64 operations must accept any constants.
681
682 The mov_i32 and mov_i64 operations must accept any registers of the
683 same type.
684
685 The ld/st/sti instructions must accept signed 32 bit constant offsets.
686 This can be implemented by reserving a specific register in which to
687 compute the address if the offset is too big.
688
689 The ld/st instructions must accept any destination (ld) or source (st)
690 register.
691
692 The sti instruction may fail if it cannot store the given constant.
693
694 4.3) Function call assumptions
695
696 - The only supported types for parameters and return value are: 32 and
697 64 bit integers and pointer.
698 - The stack grows downwards.
699 - The first N parameters are passed in registers.
700 - The next parameters are passed on the stack by storing them as words.
701 - Some registers are clobbered during the call.
702 - The function can return 0 or 1 value in registers. On a 32 bit
703 target, functions must be able to return 2 values in registers for
704 64 bit return type.
705
706 5) Recommended coding rules for best performance
707
708 - Use globals to represent the parts of the QEMU CPU state which are
709 often modified, e.g. the integer registers and the condition
710 codes. TCG will be able to use host registers to store them.
711
712 - Avoid globals stored in fixed registers. They must be used only to
713 store the pointer to the CPU state and possibly to store a pointer
714 to a register window.
715
716 - Use temporaries. Use local temporaries only when really needed,
717 e.g. when you need to use a value after a jump. Local temporaries
718 introduce a performance hit in the current TCG implementation: their
719 content is saved to memory at end of each basic block.
720
721 - Free temporaries and local temporaries when they are no longer used
722 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you
723 should free it after it is used. Freeing temporaries does not yield
724 a better generated code, but it reduces the memory usage of TCG and
725 the speed of the translation.
726
727 - Don't hesitate to use helpers for complicated or seldom used guest
728 instructions. There is little performance advantage in using TCG to
729 implement guest instructions taking more than about twenty TCG
730 instructions. Note that this rule of thumb is more applicable to
731 helpers doing complex logic or arithmetic, where the C compiler has
732 scope to do a good job of optimisation; it is less relevant where
733 the instruction is mostly doing loads and stores, and in those cases
734 inline TCG may still be faster for longer sequences.
735
736 - The hard limit on the number of TCG instructions you can generate
737 per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h --
738 you cannot exceed this without risking a buffer overrun.
739
740 - Use the 'discard' instruction if you know that TCG won't be able to
741 prove that a given global is "dead" at a given program point. The
742 x86 guest uses it to improve the condition codes optimisation.