2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "tcg-be-ldst.h"
28 /* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
30 # if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
31 || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
32 || defined(__ARM_ARCH_7EM__)
34 # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
35 || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
36 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
38 # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
39 || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
40 || defined(__ARM_ARCH_5TEJ__)
47 static int arm_arch
= __ARM_ARCH
;
49 #if defined(__ARM_ARCH_5T__) \
50 || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
51 # define use_armv5t_instructions 1
53 # define use_armv5t_instructions use_armv6_instructions
56 #define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
57 #define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
59 #ifndef use_idiv_instructions
60 bool use_idiv_instructions
;
63 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */
65 # define USING_SOFTMMU 1
67 # define USING_SOFTMMU 0
70 #ifdef CONFIG_DEBUG_TCG
71 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
91 static const int tcg_target_reg_alloc_order
[] = {
109 static const int tcg_target_call_iarg_regs
[4] = {
110 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
112 static const int tcg_target_call_oarg_regs
[2] = {
113 TCG_REG_R0
, TCG_REG_R1
116 #define TCG_REG_TMP TCG_REG_R12
118 static inline void reloc_pc24(tcg_insn_unit
*code_ptr
, tcg_insn_unit
*target
)
120 ptrdiff_t offset
= (tcg_ptr_byte_diff(target
, code_ptr
) - 8) >> 2;
121 *code_ptr
= (*code_ptr
& ~0xffffff) | (offset
& 0xffffff);
124 static inline void reloc_pc24_atomic(tcg_insn_unit
*code_ptr
, tcg_insn_unit
*target
)
126 ptrdiff_t offset
= (tcg_ptr_byte_diff(target
, code_ptr
) - 8) >> 2;
127 tcg_insn_unit insn
= atomic_read(code_ptr
);
128 tcg_debug_assert(offset
== sextract32(offset
, 0, 24));
129 atomic_set(code_ptr
, deposit32(insn
, 0, 24, offset
));
132 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
133 intptr_t value
, intptr_t addend
)
135 tcg_debug_assert(type
== R_ARM_PC24
);
136 tcg_debug_assert(addend
== 0);
137 reloc_pc24(code_ptr
, (tcg_insn_unit
*)value
);
140 #define TCG_CT_CONST_ARM 0x100
141 #define TCG_CT_CONST_INV 0x200
142 #define TCG_CT_CONST_NEG 0x400
143 #define TCG_CT_CONST_ZERO 0x800
145 /* parse target specific constraints */
146 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
153 ct
->ct
|= TCG_CT_CONST_ARM
;
156 ct
->ct
|= TCG_CT_CONST_INV
;
158 case 'N': /* The gcc constraint letter is L, already used here. */
159 ct
->ct
|= TCG_CT_CONST_NEG
;
162 ct
->ct
|= TCG_CT_CONST_ZERO
;
166 ct
->ct
|= TCG_CT_REG
;
167 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
170 /* qemu_ld address */
172 ct
->ct
|= TCG_CT_REG
;
173 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
174 #ifdef CONFIG_SOFTMMU
175 /* r0-r2,lr will be overwritten when reading the tlb entry,
176 so don't use these. */
177 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
178 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
179 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
180 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R14
);
184 /* qemu_st address & data */
186 ct
->ct
|= TCG_CT_REG
;
187 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
188 /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
189 and r0-r1 doing the byte swapping, so don't use these. */
190 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
191 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
192 #if defined(CONFIG_SOFTMMU)
193 /* Avoid clashes with registers being used for helper args */
194 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
195 #if TARGET_LONG_BITS == 64
196 /* Avoid clashes with registers being used for helper args */
197 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
199 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R14
);
212 static inline uint32_t rotl(uint32_t val
, int n
)
214 return (val
<< n
) | (val
>> (32 - n
));
217 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
218 right-rotated by an even amount between 0 and 30. */
219 static inline int encode_imm(uint32_t imm
)
223 /* simple case, only lower bits */
224 if ((imm
& ~0xff) == 0)
226 /* then try a simple even shift */
227 shift
= ctz32(imm
) & ~1;
228 if (((imm
>> shift
) & ~0xff) == 0)
230 /* now try harder with rotations */
231 if ((rotl(imm
, 2) & ~0xff) == 0)
233 if ((rotl(imm
, 4) & ~0xff) == 0)
235 if ((rotl(imm
, 6) & ~0xff) == 0)
237 /* imm can't be encoded */
241 static inline int check_fit_imm(uint32_t imm
)
243 return encode_imm(imm
) >= 0;
246 /* Test if a constant matches the constraint.
247 * TODO: define constraints for:
249 * ldr/str offset: between -0xfff and 0xfff
250 * ldrh/strh offset: between -0xff and 0xff
251 * mov operand2: values represented with x << (2 * y), x < 0x100
252 * add, sub, eor...: ditto
254 static inline int tcg_target_const_match(tcg_target_long val
, TCGType type
,
255 const TCGArgConstraint
*arg_ct
)
259 if (ct
& TCG_CT_CONST
) {
261 } else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
)) {
263 } else if ((ct
& TCG_CT_CONST_INV
) && check_fit_imm(~val
)) {
265 } else if ((ct
& TCG_CT_CONST_NEG
) && check_fit_imm(-val
)) {
267 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
274 #define TO_CPSR (1 << 20)
277 ARITH_AND
= 0x0 << 21,
278 ARITH_EOR
= 0x1 << 21,
279 ARITH_SUB
= 0x2 << 21,
280 ARITH_RSB
= 0x3 << 21,
281 ARITH_ADD
= 0x4 << 21,
282 ARITH_ADC
= 0x5 << 21,
283 ARITH_SBC
= 0x6 << 21,
284 ARITH_RSC
= 0x7 << 21,
285 ARITH_TST
= 0x8 << 21 | TO_CPSR
,
286 ARITH_CMP
= 0xa << 21 | TO_CPSR
,
287 ARITH_CMN
= 0xb << 21 | TO_CPSR
,
288 ARITH_ORR
= 0xc << 21,
289 ARITH_MOV
= 0xd << 21,
290 ARITH_BIC
= 0xe << 21,
291 ARITH_MVN
= 0xf << 21,
293 INSN_LDR_IMM
= 0x04100000,
294 INSN_LDR_REG
= 0x06100000,
295 INSN_STR_IMM
= 0x04000000,
296 INSN_STR_REG
= 0x06000000,
298 INSN_LDRH_IMM
= 0x005000b0,
299 INSN_LDRH_REG
= 0x001000b0,
300 INSN_LDRSH_IMM
= 0x005000f0,
301 INSN_LDRSH_REG
= 0x001000f0,
302 INSN_STRH_IMM
= 0x004000b0,
303 INSN_STRH_REG
= 0x000000b0,
305 INSN_LDRB_IMM
= 0x04500000,
306 INSN_LDRB_REG
= 0x06500000,
307 INSN_LDRSB_IMM
= 0x005000d0,
308 INSN_LDRSB_REG
= 0x001000d0,
309 INSN_STRB_IMM
= 0x04400000,
310 INSN_STRB_REG
= 0x06400000,
312 INSN_LDRD_IMM
= 0x004000d0,
313 INSN_LDRD_REG
= 0x000000d0,
314 INSN_STRD_IMM
= 0x004000f0,
315 INSN_STRD_REG
= 0x000000f0,
318 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
319 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
320 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
321 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
322 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
323 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
324 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
325 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
327 enum arm_cond_code_e
{
330 COND_CS
= 0x2, /* Unsigned greater or equal */
331 COND_CC
= 0x3, /* Unsigned less than */
332 COND_MI
= 0x4, /* Negative */
333 COND_PL
= 0x5, /* Zero or greater */
334 COND_VS
= 0x6, /* Overflow */
335 COND_VC
= 0x7, /* No overflow */
336 COND_HI
= 0x8, /* Unsigned greater than */
337 COND_LS
= 0x9, /* Unsigned less or equal */
345 static const uint8_t tcg_cond_to_arm_cond
[] = {
346 [TCG_COND_EQ
] = COND_EQ
,
347 [TCG_COND_NE
] = COND_NE
,
348 [TCG_COND_LT
] = COND_LT
,
349 [TCG_COND_GE
] = COND_GE
,
350 [TCG_COND_LE
] = COND_LE
,
351 [TCG_COND_GT
] = COND_GT
,
353 [TCG_COND_LTU
] = COND_CC
,
354 [TCG_COND_GEU
] = COND_CS
,
355 [TCG_COND_LEU
] = COND_LS
,
356 [TCG_COND_GTU
] = COND_HI
,
359 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
361 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
364 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
366 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
367 (((offset
- 8) >> 2) & 0x00ffffff));
370 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
372 /* We pay attention here to not modify the branch target by masking
373 the corresponding bytes. This ensure that caches and memory are
374 kept coherent during retranslation. */
375 tcg_out32(s
, deposit32(*s
->code_ptr
, 24, 8, (cond
<< 4) | 0x0a));
378 static inline void tcg_out_bl_noaddr(TCGContext
*s
, int cond
)
380 /* We pay attention here to not modify the branch target by masking
381 the corresponding bytes. This ensure that caches and memory are
382 kept coherent during retranslation. */
383 tcg_out32(s
, deposit32(*s
->code_ptr
, 24, 8, (cond
<< 4) | 0x0b));
386 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
388 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
389 (((offset
- 8) >> 2) & 0x00ffffff));
392 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
394 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
397 static inline void tcg_out_blx_imm(TCGContext
*s
, int32_t offset
)
399 tcg_out32(s
, 0xfa000000 | ((offset
& 2) << 23) |
400 (((offset
- 8) >> 2) & 0x00ffffff));
403 static inline void tcg_out_dat_reg(TCGContext
*s
,
404 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
406 tcg_out32(s
, (cond
<< 28) | (0 << 25) | opc
|
407 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
410 static inline void tcg_out_nop(TCGContext
*s
)
412 if (use_armv7_instructions
) {
413 /* Architected nop introduced in v6k. */
414 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
415 also Just So Happened to do nothing on pre-v6k so that we
416 don't need to conditionalize it? */
417 tcg_out32(s
, 0xe320f000);
419 /* Prior to that the assembler uses mov r0, r0. */
420 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, 0, 0, 0, SHIFT_IMM_LSL(0));
424 static inline void tcg_out_mov_reg(TCGContext
*s
, int cond
, int rd
, int rm
)
426 /* Simple reg-reg move, optimising out the 'do nothing' case */
428 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, rd
, 0, rm
, SHIFT_IMM_LSL(0));
432 static inline void tcg_out_dat_imm(TCGContext
*s
,
433 int cond
, int opc
, int rd
, int rn
, int im
)
435 tcg_out32(s
, (cond
<< 28) | (1 << 25) | opc
|
436 (rn
<< 16) | (rd
<< 12) | im
);
439 static void tcg_out_movi32(TCGContext
*s
, int cond
, int rd
, uint32_t arg
)
443 /* For armv7, make sure not to use movw+movt when mov/mvn would do.
444 Speed things up by only checking when movt would be required.
445 Prior to armv7, have one go at fully rotated immediates before
446 doing the decomposition thing below. */
447 if (!use_armv7_instructions
|| (arg
& 0xffff0000)) {
448 rot
= encode_imm(arg
);
450 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0,
451 rotl(arg
, rot
) | (rot
<< 7));
454 rot
= encode_imm(~arg
);
456 tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0,
457 rotl(~arg
, rot
) | (rot
<< 7));
462 /* Use movw + movt. */
463 if (use_armv7_instructions
) {
465 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
466 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
467 if (arg
& 0xffff0000) {
469 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
470 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
475 /* TODO: This is very suboptimal, we can easily have a constant
476 pool somewhere after all the instructions. */
479 /* If we have lots of leading 1's, we can shorten the sequence by
480 beginning with mvn and then clearing higher bits with eor. */
481 if (clz32(~arg
) > clz32(arg
)) {
482 opc
= ARITH_MVN
, arg
= ~arg
;
485 int i
= ctz32(arg
) & ~1;
486 rot
= ((32 - i
) << 7) & 0xf00;
487 tcg_out_dat_imm(s
, cond
, opc
, rd
, rn
, ((arg
>> i
) & 0xff) | rot
);
495 static inline void tcg_out_dat_rI(TCGContext
*s
, int cond
, int opc
, TCGArg dst
,
496 TCGArg lhs
, TCGArg rhs
, int rhs_is_const
)
498 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
499 * rhs must satisfy the "rI" constraint.
502 int rot
= encode_imm(rhs
);
503 tcg_debug_assert(rot
>= 0);
504 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
506 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
510 static void tcg_out_dat_rIK(TCGContext
*s
, int cond
, int opc
, int opinv
,
511 TCGReg dst
, TCGReg lhs
, TCGArg rhs
,
514 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
515 * rhs must satisfy the "rIK" constraint.
518 int rot
= encode_imm(rhs
);
521 rot
= encode_imm(rhs
);
522 tcg_debug_assert(rot
>= 0);
525 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
527 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
531 static void tcg_out_dat_rIN(TCGContext
*s
, int cond
, int opc
, int opneg
,
532 TCGArg dst
, TCGArg lhs
, TCGArg rhs
,
535 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
536 * rhs must satisfy the "rIN" constraint.
539 int rot
= encode_imm(rhs
);
542 rot
= encode_imm(rhs
);
543 tcg_debug_assert(rot
>= 0);
546 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
548 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
552 static inline void tcg_out_mul32(TCGContext
*s
, int cond
, TCGReg rd
,
553 TCGReg rn
, TCGReg rm
)
555 /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
556 if (!use_armv6_instructions
&& rd
== rn
) {
558 /* rd == rn == rm; copy an input to tmp first. */
559 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
560 rm
= rn
= TCG_REG_TMP
;
567 tcg_out32(s
, (cond
<< 28) | 0x90 | (rd
<< 16) | (rm
<< 8) | rn
);
570 static inline void tcg_out_umull32(TCGContext
*s
, int cond
, TCGReg rd0
,
571 TCGReg rd1
, TCGReg rn
, TCGReg rm
)
573 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
574 if (!use_armv6_instructions
&& (rd0
== rn
|| rd1
== rn
)) {
575 if (rd0
== rm
|| rd1
== rm
) {
576 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
585 tcg_out32(s
, (cond
<< 28) | 0x00800090 |
586 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rn
);
589 static inline void tcg_out_smull32(TCGContext
*s
, int cond
, TCGReg rd0
,
590 TCGReg rd1
, TCGReg rn
, TCGReg rm
)
592 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
593 if (!use_armv6_instructions
&& (rd0
== rn
|| rd1
== rn
)) {
594 if (rd0
== rm
|| rd1
== rm
) {
595 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
604 tcg_out32(s
, (cond
<< 28) | 0x00c00090 |
605 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rn
);
608 static inline void tcg_out_sdiv(TCGContext
*s
, int cond
, int rd
, int rn
, int rm
)
610 tcg_out32(s
, 0x0710f010 | (cond
<< 28) | (rd
<< 16) | rn
| (rm
<< 8));
613 static inline void tcg_out_udiv(TCGContext
*s
, int cond
, int rd
, int rn
, int rm
)
615 tcg_out32(s
, 0x0730f010 | (cond
<< 28) | (rd
<< 16) | rn
| (rm
<< 8));
618 static inline void tcg_out_ext8s(TCGContext
*s
, int cond
,
621 if (use_armv6_instructions
) {
623 tcg_out32(s
, 0x06af0070 | (cond
<< 28) | (rd
<< 12) | rn
);
625 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
626 rd
, 0, rn
, SHIFT_IMM_LSL(24));
627 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
628 rd
, 0, rd
, SHIFT_IMM_ASR(24));
632 static inline void tcg_out_ext8u(TCGContext
*s
, int cond
,
635 tcg_out_dat_imm(s
, cond
, ARITH_AND
, rd
, rn
, 0xff);
638 static inline void tcg_out_ext16s(TCGContext
*s
, int cond
,
641 if (use_armv6_instructions
) {
643 tcg_out32(s
, 0x06bf0070 | (cond
<< 28) | (rd
<< 12) | rn
);
645 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
646 rd
, 0, rn
, SHIFT_IMM_LSL(16));
647 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
648 rd
, 0, rd
, SHIFT_IMM_ASR(16));
652 static inline void tcg_out_ext16u(TCGContext
*s
, int cond
,
655 if (use_armv6_instructions
) {
657 tcg_out32(s
, 0x06ff0070 | (cond
<< 28) | (rd
<< 12) | rn
);
659 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
660 rd
, 0, rn
, SHIFT_IMM_LSL(16));
661 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
662 rd
, 0, rd
, SHIFT_IMM_LSR(16));
666 static inline void tcg_out_bswap16s(TCGContext
*s
, int cond
, int rd
, int rn
)
668 if (use_armv6_instructions
) {
670 tcg_out32(s
, 0x06ff0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
672 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
673 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSL(24));
674 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
675 TCG_REG_TMP
, 0, TCG_REG_TMP
, SHIFT_IMM_ASR(16));
676 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
677 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSR(8));
681 static inline void tcg_out_bswap16(TCGContext
*s
, int cond
, int rd
, int rn
)
683 if (use_armv6_instructions
) {
685 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
687 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
688 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSL(24));
689 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
690 TCG_REG_TMP
, 0, TCG_REG_TMP
, SHIFT_IMM_LSR(16));
691 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
692 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSR(8));
696 /* swap the two low bytes assuming that the two high input bytes and the
697 two high output bit can hold any value. */
698 static inline void tcg_out_bswap16st(TCGContext
*s
, int cond
, int rd
, int rn
)
700 if (use_armv6_instructions
) {
702 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
704 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
705 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSR(8));
706 tcg_out_dat_imm(s
, cond
, ARITH_AND
, TCG_REG_TMP
, TCG_REG_TMP
, 0xff);
707 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
708 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSL(8));
712 static inline void tcg_out_bswap32(TCGContext
*s
, int cond
, int rd
, int rn
)
714 if (use_armv6_instructions
) {
716 tcg_out32(s
, 0x06bf0f30 | (cond
<< 28) | (rd
<< 12) | rn
);
718 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
719 TCG_REG_TMP
, rn
, rn
, SHIFT_IMM_ROR(16));
720 tcg_out_dat_imm(s
, cond
, ARITH_BIC
,
721 TCG_REG_TMP
, TCG_REG_TMP
, 0xff | 0x800);
722 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
723 rd
, 0, rn
, SHIFT_IMM_ROR(8));
724 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
725 rd
, rd
, TCG_REG_TMP
, SHIFT_IMM_LSR(8));
729 bool tcg_target_deposit_valid(int ofs
, int len
)
731 /* ??? Without bfi, we could improve over generic code by combining
732 the right-shift from a non-zero ofs with the orr. We do run into
733 problems when rd == rs, and the mask generated from ofs+len doesn't
734 fit into an immediate. We would have to be careful not to pessimize
735 wrt the optimizations performed on the expanded code. */
736 return use_armv7_instructions
;
739 static inline void tcg_out_deposit(TCGContext
*s
, int cond
, TCGReg rd
,
740 TCGArg a1
, int ofs
, int len
, bool const_a1
)
743 /* bfi becomes bfc with rn == 15. */
747 tcg_out32(s
, 0x07c00010 | (cond
<< 28) | (rd
<< 12) | a1
748 | (ofs
<< 7) | ((ofs
+ len
- 1) << 16));
751 /* Note that this routine is used for both LDR and LDRH formats, so we do
752 not wish to include an immediate shift at this point. */
753 static void tcg_out_memop_r(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
754 TCGReg rn
, TCGReg rm
, bool u
, bool p
, bool w
)
756 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24)
757 | (w
<< 21) | (rn
<< 16) | (rt
<< 12) | rm
);
760 static void tcg_out_memop_8(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
761 TCGReg rn
, int imm8
, bool p
, bool w
)
768 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24) | (w
<< 21) |
769 (rn
<< 16) | (rt
<< 12) | ((imm8
& 0xf0) << 4) | (imm8
& 0xf));
772 static void tcg_out_memop_12(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
773 TCGReg rn
, int imm12
, bool p
, bool w
)
780 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24) | (w
<< 21) |
781 (rn
<< 16) | (rt
<< 12) | imm12
);
784 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
, TCGReg rt
,
785 TCGReg rn
, int imm12
)
787 tcg_out_memop_12(s
, cond
, INSN_LDR_IMM
, rt
, rn
, imm12
, 1, 0);
790 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
, TCGReg rt
,
791 TCGReg rn
, int imm12
)
793 tcg_out_memop_12(s
, cond
, INSN_STR_IMM
, rt
, rn
, imm12
, 1, 0);
796 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
, TCGReg rt
,
797 TCGReg rn
, TCGReg rm
)
799 tcg_out_memop_r(s
, cond
, INSN_LDR_REG
, rt
, rn
, rm
, 1, 1, 0);
802 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
, TCGReg rt
,
803 TCGReg rn
, TCGReg rm
)
805 tcg_out_memop_r(s
, cond
, INSN_STR_REG
, rt
, rn
, rm
, 1, 1, 0);
808 static inline void tcg_out_ldrd_8(TCGContext
*s
, int cond
, TCGReg rt
,
811 tcg_out_memop_8(s
, cond
, INSN_LDRD_IMM
, rt
, rn
, imm8
, 1, 0);
814 static inline void tcg_out_ldrd_r(TCGContext
*s
, int cond
, TCGReg rt
,
815 TCGReg rn
, TCGReg rm
)
817 tcg_out_memop_r(s
, cond
, INSN_LDRD_REG
, rt
, rn
, rm
, 1, 1, 0);
820 static inline void tcg_out_strd_8(TCGContext
*s
, int cond
, TCGReg rt
,
823 tcg_out_memop_8(s
, cond
, INSN_STRD_IMM
, rt
, rn
, imm8
, 1, 0);
826 static inline void tcg_out_strd_r(TCGContext
*s
, int cond
, TCGReg rt
,
827 TCGReg rn
, TCGReg rm
)
829 tcg_out_memop_r(s
, cond
, INSN_STRD_REG
, rt
, rn
, rm
, 1, 1, 0);
832 /* Register pre-increment with base writeback. */
833 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
, TCGReg rt
,
834 TCGReg rn
, TCGReg rm
)
836 tcg_out_memop_r(s
, cond
, INSN_LDR_REG
, rt
, rn
, rm
, 1, 1, 1);
839 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
, TCGReg rt
,
840 TCGReg rn
, TCGReg rm
)
842 tcg_out_memop_r(s
, cond
, INSN_STR_REG
, rt
, rn
, rm
, 1, 1, 1);
845 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
, TCGReg rt
,
848 tcg_out_memop_8(s
, cond
, INSN_LDRH_IMM
, rt
, rn
, imm8
, 1, 0);
851 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
, TCGReg rt
,
854 tcg_out_memop_8(s
, cond
, INSN_STRH_IMM
, rt
, rn
, imm8
, 1, 0);
857 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
, TCGReg rt
,
858 TCGReg rn
, TCGReg rm
)
860 tcg_out_memop_r(s
, cond
, INSN_LDRH_REG
, rt
, rn
, rm
, 1, 1, 0);
863 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
, TCGReg rt
,
864 TCGReg rn
, TCGReg rm
)
866 tcg_out_memop_r(s
, cond
, INSN_STRH_REG
, rt
, rn
, rm
, 1, 1, 0);
869 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
, TCGReg rt
,
872 tcg_out_memop_8(s
, cond
, INSN_LDRSH_IMM
, rt
, rn
, imm8
, 1, 0);
875 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
, TCGReg rt
,
876 TCGReg rn
, TCGReg rm
)
878 tcg_out_memop_r(s
, cond
, INSN_LDRSH_REG
, rt
, rn
, rm
, 1, 1, 0);
881 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
, TCGReg rt
,
882 TCGReg rn
, int imm12
)
884 tcg_out_memop_12(s
, cond
, INSN_LDRB_IMM
, rt
, rn
, imm12
, 1, 0);
887 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
, TCGReg rt
,
888 TCGReg rn
, int imm12
)
890 tcg_out_memop_12(s
, cond
, INSN_STRB_IMM
, rt
, rn
, imm12
, 1, 0);
893 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
, TCGReg rt
,
894 TCGReg rn
, TCGReg rm
)
896 tcg_out_memop_r(s
, cond
, INSN_LDRB_REG
, rt
, rn
, rm
, 1, 1, 0);
899 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
, TCGReg rt
,
900 TCGReg rn
, TCGReg rm
)
902 tcg_out_memop_r(s
, cond
, INSN_STRB_REG
, rt
, rn
, rm
, 1, 1, 0);
905 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
, TCGReg rt
,
908 tcg_out_memop_8(s
, cond
, INSN_LDRSB_IMM
, rt
, rn
, imm8
, 1, 0);
911 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
, TCGReg rt
,
912 TCGReg rn
, TCGReg rm
)
914 tcg_out_memop_r(s
, cond
, INSN_LDRSB_REG
, rt
, rn
, rm
, 1, 1, 0);
917 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
918 int rd
, int rn
, int32_t offset
)
920 if (offset
> 0xfff || offset
< -0xfff) {
921 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
922 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
924 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
927 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
928 int rd
, int rn
, int32_t offset
)
930 if (offset
> 0xfff || offset
< -0xfff) {
931 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
932 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
934 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
937 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
938 int rd
, int rn
, int32_t offset
)
940 if (offset
> 0xff || offset
< -0xff) {
941 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
942 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
944 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
947 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
948 int rd
, int rn
, int32_t offset
)
950 if (offset
> 0xff || offset
< -0xff) {
951 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
952 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
954 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
957 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
958 int rd
, int rn
, int32_t offset
)
960 if (offset
> 0xff || offset
< -0xff) {
961 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
962 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
964 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
967 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
968 int rd
, int rn
, int32_t offset
)
970 if (offset
> 0xfff || offset
< -0xfff) {
971 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
972 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
974 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
977 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
978 int rd
, int rn
, int32_t offset
)
980 if (offset
> 0xff || offset
< -0xff) {
981 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
982 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
984 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
987 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
988 int rd
, int rn
, int32_t offset
)
990 if (offset
> 0xfff || offset
< -0xfff) {
991 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
992 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
994 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
997 /* The _goto case is normally between TBs within the same code buffer, and
998 * with the code buffer limited to 16MB we wouldn't need the long case.
999 * But we also use it for the tail-call to the qemu_ld/st helpers, which does.
1001 static inline void tcg_out_goto(TCGContext
*s
, int cond
, tcg_insn_unit
*addr
)
1003 intptr_t addri
= (intptr_t)addr
;
1004 ptrdiff_t disp
= tcg_pcrel_diff(s
, addr
);
1006 if ((addri
& 1) == 0 && disp
- 8 < 0x01fffffd && disp
- 8 > -0x01fffffd) {
1007 tcg_out_b(s
, cond
, disp
);
1011 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, addri
);
1012 if (use_armv5t_instructions
) {
1013 tcg_out_bx(s
, cond
, TCG_REG_TMP
);
1018 tcg_out_mov_reg(s
, cond
, TCG_REG_PC
, TCG_REG_TMP
);
1022 /* The call case is mostly used for helpers - so it's not unreasonable
1023 * for them to be beyond branch range */
1024 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*addr
)
1026 intptr_t addri
= (intptr_t)addr
;
1027 ptrdiff_t disp
= tcg_pcrel_diff(s
, addr
);
1029 if (disp
- 8 < 0x02000000 && disp
- 8 >= -0x02000000) {
1031 /* Use BLX if the target is in Thumb mode */
1032 if (!use_armv5t_instructions
) {
1035 tcg_out_blx_imm(s
, disp
);
1037 tcg_out_bl(s
, COND_AL
, disp
);
1039 } else if (use_armv7_instructions
) {
1040 tcg_out_movi32(s
, COND_AL
, TCG_REG_TMP
, addri
);
1041 tcg_out_blx(s
, COND_AL
, TCG_REG_TMP
);
1043 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
1044 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1045 tcg_out32(s
, addri
);
1049 void arm_tb_set_jmp_target(uintptr_t jmp_addr
, uintptr_t addr
)
1051 tcg_insn_unit
*code_ptr
= (tcg_insn_unit
*)jmp_addr
;
1052 tcg_insn_unit
*target
= (tcg_insn_unit
*)addr
;
1054 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
1055 reloc_pc24_atomic(code_ptr
, target
);
1056 flush_icache_range(jmp_addr
, jmp_addr
+ 4);
1059 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, TCGLabel
*l
)
1062 tcg_out_goto(s
, cond
, l
->u
.value_ptr
);
1064 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, l
, 0);
1065 tcg_out_b_noaddr(s
, cond
);
1069 #ifdef CONFIG_SOFTMMU
1070 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
1071 * int mmu_idx, uintptr_t ra)
1073 static void * const qemu_ld_helpers
[16] = {
1074 [MO_UB
] = helper_ret_ldub_mmu
,
1075 [MO_SB
] = helper_ret_ldsb_mmu
,
1077 [MO_LEUW
] = helper_le_lduw_mmu
,
1078 [MO_LEUL
] = helper_le_ldul_mmu
,
1079 [MO_LEQ
] = helper_le_ldq_mmu
,
1080 [MO_LESW
] = helper_le_ldsw_mmu
,
1081 [MO_LESL
] = helper_le_ldul_mmu
,
1083 [MO_BEUW
] = helper_be_lduw_mmu
,
1084 [MO_BEUL
] = helper_be_ldul_mmu
,
1085 [MO_BEQ
] = helper_be_ldq_mmu
,
1086 [MO_BESW
] = helper_be_ldsw_mmu
,
1087 [MO_BESL
] = helper_be_ldul_mmu
,
1090 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
1091 * uintxx_t val, int mmu_idx, uintptr_t ra)
1093 static void * const qemu_st_helpers
[16] = {
1094 [MO_UB
] = helper_ret_stb_mmu
,
1095 [MO_LEUW
] = helper_le_stw_mmu
,
1096 [MO_LEUL
] = helper_le_stl_mmu
,
1097 [MO_LEQ
] = helper_le_stq_mmu
,
1098 [MO_BEUW
] = helper_be_stw_mmu
,
1099 [MO_BEUL
] = helper_be_stl_mmu
,
1100 [MO_BEQ
] = helper_be_stq_mmu
,
1103 /* Helper routines for marshalling helper function arguments into
1104 * the correct registers and stack.
1105 * argreg is where we want to put this argument, arg is the argument itself.
1106 * Return value is the updated argreg ready for the next call.
1107 * Note that argreg 0..3 is real registers, 4+ on stack.
1109 * We provide routines for arguments which are: immediate, 32 bit
1110 * value in register, 16 and 8 bit values in register (which must be zero
1111 * extended before use) and 64 bit value in a lo:hi register pair.
1113 #define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
1114 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
1117 MOV_ARG(s, COND_AL, argreg, arg); \
1119 int ofs = (argreg - 4) * 4; \
1121 tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
1122 tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
1124 return argreg + 1; \
1127 DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32
, uint32_t, tcg_out_movi32
,
1128 (tcg_out_movi32(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1129 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8
, TCGReg
, tcg_out_ext8u
,
1130 (tcg_out_ext8u(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1131 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16
, TCGReg
, tcg_out_ext16u
,
1132 (tcg_out_ext16u(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1133 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32
, TCGReg
, tcg_out_mov_reg
, )
1135 static TCGReg
tcg_out_arg_reg64(TCGContext
*s
, TCGReg argreg
,
1136 TCGReg arglo
, TCGReg arghi
)
1138 /* 64 bit arguments must go in even/odd register pairs
1139 * and in 8-aligned stack slots.
1144 if (use_armv6_instructions
&& argreg
>= 4
1145 && (arglo
& 1) == 0 && arghi
== arglo
+ 1) {
1146 tcg_out_strd_8(s
, COND_AL
, arglo
,
1147 TCG_REG_CALL_STACK
, (argreg
- 4) * 4);
1150 argreg
= tcg_out_arg_reg32(s
, argreg
, arglo
);
1151 argreg
= tcg_out_arg_reg32(s
, argreg
, arghi
);
1156 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1158 /* We're expecting to use an 8-bit immediate and to mask. */
1159 QEMU_BUILD_BUG_ON(CPU_TLB_BITS
> 8);
1161 /* We're expecting to use an 8-bit immediate add + 8-bit ldrd offset.
1162 Using the offset of the second entry in the last tlb table ensures
1163 that we can index all of the elements of the first entry. */
1164 QEMU_BUILD_BUG_ON(offsetof(CPUArchState
, tlb_table
[NB_MMU_MODES
- 1][1])
1167 /* Load and compare a TLB entry, leaving the flags set. Returns the register
1168 containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
1170 static TCGReg
tcg_out_tlb_read(TCGContext
*s
, TCGReg addrlo
, TCGReg addrhi
,
1171 TCGMemOp opc
, int mem_index
, bool is_load
)
1173 TCGReg base
= TCG_AREG0
;
1176 ? offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_read
)
1177 : offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_write
));
1178 int add_off
= offsetof(CPUArchState
, tlb_table
[mem_index
][0].addend
);
1179 unsigned s_bits
= opc
& MO_SIZE
;
1180 unsigned a_bits
= get_alignment_bits(opc
);
1182 /* Should generate something like the following:
1183 * shr tmp, addrlo, #TARGET_PAGE_BITS (1)
1184 * add r2, env, #high
1185 * and r0, tmp, #(CPU_TLB_SIZE - 1) (2)
1186 * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3)
1187 * ldr r0, [r2, #cmp] (4)
1188 * tst addrlo, #s_mask
1189 * ldr r2, [r2, #add] (5)
1190 * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS
1192 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_TMP
,
1193 0, addrlo
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1195 /* We checked that the offset is contained within 16 bits above. */
1196 if (add_off
> 0xfff || (use_armv6_instructions
&& cmp_off
> 0xff)) {
1197 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R2
, base
,
1198 (24 << 7) | (cmp_off
>> 8));
1200 add_off
-= cmp_off
& 0xff00;
1204 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1205 TCG_REG_R0
, TCG_REG_TMP
, CPU_TLB_SIZE
- 1);
1206 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R2
, base
,
1207 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1209 /* Load the tlb comparator. Use ldrd if needed and available,
1210 but due to how the pointer needs setting up, ldm isn't useful.
1211 Base arm5 doesn't have ldrd, but armv5te does. */
1212 if (use_armv6_instructions
&& TARGET_LONG_BITS
== 64) {
1213 tcg_out_ldrd_8(s
, COND_AL
, TCG_REG_R0
, TCG_REG_R2
, cmp_off
);
1215 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_R2
, cmp_off
);
1216 if (TARGET_LONG_BITS
== 64) {
1217 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R2
, cmp_off
+ 4);
1221 /* Check alignment. We don't support inline unaligned acceses,
1222 but we can easily support overalignment checks. */
1223 if (a_bits
< s_bits
) {
1227 tcg_out_dat_imm(s
, COND_AL
, ARITH_TST
, 0, addrlo
, (1 << a_bits
) - 1);
1230 /* Load the tlb addend. */
1231 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R2
, TCG_REG_R2
, add_off
);
1233 tcg_out_dat_reg(s
, (s_bits
? COND_EQ
: COND_AL
), ARITH_CMP
, 0,
1234 TCG_REG_R0
, TCG_REG_TMP
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1236 if (TARGET_LONG_BITS
== 64) {
1237 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1238 TCG_REG_R1
, addrhi
, SHIFT_IMM_LSL(0));
1244 /* Record the context of a call to the out of line helper code for the slow
1245 path for a load or store, so that we can later generate the correct
1247 static void add_qemu_ldst_label(TCGContext
*s
, bool is_ld
, TCGMemOpIdx oi
,
1248 TCGReg datalo
, TCGReg datahi
, TCGReg addrlo
,
1249 TCGReg addrhi
, tcg_insn_unit
*raddr
,
1250 tcg_insn_unit
*label_ptr
)
1252 TCGLabelQemuLdst
*label
= new_ldst_label(s
);
1254 label
->is_ld
= is_ld
;
1256 label
->datalo_reg
= datalo
;
1257 label
->datahi_reg
= datahi
;
1258 label
->addrlo_reg
= addrlo
;
1259 label
->addrhi_reg
= addrhi
;
1260 label
->raddr
= raddr
;
1261 label
->label_ptr
[0] = label_ptr
;
1264 static void tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1266 TCGReg argreg
, datalo
, datahi
;
1267 TCGMemOpIdx oi
= lb
->oi
;
1268 TCGMemOp opc
= get_memop(oi
);
1271 reloc_pc24(lb
->label_ptr
[0], s
->code_ptr
);
1273 argreg
= tcg_out_arg_reg32(s
, TCG_REG_R0
, TCG_AREG0
);
1274 if (TARGET_LONG_BITS
== 64) {
1275 argreg
= tcg_out_arg_reg64(s
, argreg
, lb
->addrlo_reg
, lb
->addrhi_reg
);
1277 argreg
= tcg_out_arg_reg32(s
, argreg
, lb
->addrlo_reg
);
1279 argreg
= tcg_out_arg_imm32(s
, argreg
, oi
);
1280 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_REG_R14
);
1282 /* For armv6 we can use the canonical unsigned helpers and minimize
1283 icache usage. For pre-armv6, use the signed helpers since we do
1284 not have a single insn sign-extend. */
1285 if (use_armv6_instructions
) {
1286 func
= qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)];
1288 func
= qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SSIZE
)];
1289 if (opc
& MO_SIGN
) {
1293 tcg_out_call(s
, func
);
1295 datalo
= lb
->datalo_reg
;
1296 datahi
= lb
->datahi_reg
;
1297 switch (opc
& MO_SSIZE
) {
1299 tcg_out_ext8s(s
, COND_AL
, datalo
, TCG_REG_R0
);
1302 tcg_out_ext16s(s
, COND_AL
, datalo
, TCG_REG_R0
);
1305 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_R0
);
1308 if (datalo
!= TCG_REG_R1
) {
1309 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_R0
);
1310 tcg_out_mov_reg(s
, COND_AL
, datahi
, TCG_REG_R1
);
1311 } else if (datahi
!= TCG_REG_R0
) {
1312 tcg_out_mov_reg(s
, COND_AL
, datahi
, TCG_REG_R1
);
1313 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_R0
);
1315 tcg_out_mov_reg(s
, COND_AL
, TCG_REG_TMP
, TCG_REG_R0
);
1316 tcg_out_mov_reg(s
, COND_AL
, datahi
, TCG_REG_R1
);
1317 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_TMP
);
1322 tcg_out_goto(s
, COND_AL
, lb
->raddr
);
1325 static void tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1327 TCGReg argreg
, datalo
, datahi
;
1328 TCGMemOpIdx oi
= lb
->oi
;
1329 TCGMemOp opc
= get_memop(oi
);
1331 reloc_pc24(lb
->label_ptr
[0], s
->code_ptr
);
1333 argreg
= TCG_REG_R0
;
1334 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_AREG0
);
1335 if (TARGET_LONG_BITS
== 64) {
1336 argreg
= tcg_out_arg_reg64(s
, argreg
, lb
->addrlo_reg
, lb
->addrhi_reg
);
1338 argreg
= tcg_out_arg_reg32(s
, argreg
, lb
->addrlo_reg
);
1341 datalo
= lb
->datalo_reg
;
1342 datahi
= lb
->datahi_reg
;
1343 switch (opc
& MO_SIZE
) {
1345 argreg
= tcg_out_arg_reg8(s
, argreg
, datalo
);
1348 argreg
= tcg_out_arg_reg16(s
, argreg
, datalo
);
1352 argreg
= tcg_out_arg_reg32(s
, argreg
, datalo
);
1355 argreg
= tcg_out_arg_reg64(s
, argreg
, datalo
, datahi
);
1359 argreg
= tcg_out_arg_imm32(s
, argreg
, oi
);
1360 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_REG_R14
);
1362 /* Tail-call to the helper, which will return to the fast path. */
1363 tcg_out_goto(s
, COND_AL
, qemu_st_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1365 #endif /* SOFTMMU */
1367 static inline void tcg_out_qemu_ld_index(TCGContext
*s
, TCGMemOp opc
,
1368 TCGReg datalo
, TCGReg datahi
,
1369 TCGReg addrlo
, TCGReg addend
)
1371 TCGMemOp bswap
= opc
& MO_BSWAP
;
1373 switch (opc
& MO_SSIZE
) {
1375 tcg_out_ld8_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1378 tcg_out_ld8s_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1381 tcg_out_ld16u_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1383 tcg_out_bswap16(s
, COND_AL
, datalo
, datalo
);
1388 tcg_out_ld16u_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1389 tcg_out_bswap16s(s
, COND_AL
, datalo
, datalo
);
1391 tcg_out_ld16s_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1396 tcg_out_ld32_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1398 tcg_out_bswap32(s
, COND_AL
, datalo
, datalo
);
1403 TCGReg dl
= (bswap
? datahi
: datalo
);
1404 TCGReg dh
= (bswap
? datalo
: datahi
);
1406 /* Avoid ldrd for user-only emulation, to handle unaligned. */
1407 if (USING_SOFTMMU
&& use_armv6_instructions
1408 && (dl
& 1) == 0 && dh
== dl
+ 1) {
1409 tcg_out_ldrd_r(s
, COND_AL
, dl
, addrlo
, addend
);
1410 } else if (dl
!= addend
) {
1411 tcg_out_ld32_rwb(s
, COND_AL
, dl
, addend
, addrlo
);
1412 tcg_out_ld32_12(s
, COND_AL
, dh
, addend
, 4);
1414 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_TMP
,
1415 addend
, addrlo
, SHIFT_IMM_LSL(0));
1416 tcg_out_ld32_12(s
, COND_AL
, dl
, TCG_REG_TMP
, 0);
1417 tcg_out_ld32_12(s
, COND_AL
, dh
, TCG_REG_TMP
, 4);
1420 tcg_out_bswap32(s
, COND_AL
, dl
, dl
);
1421 tcg_out_bswap32(s
, COND_AL
, dh
, dh
);
1428 static inline void tcg_out_qemu_ld_direct(TCGContext
*s
, TCGMemOp opc
,
1429 TCGReg datalo
, TCGReg datahi
,
1432 TCGMemOp bswap
= opc
& MO_BSWAP
;
1434 switch (opc
& MO_SSIZE
) {
1436 tcg_out_ld8_12(s
, COND_AL
, datalo
, addrlo
, 0);
1439 tcg_out_ld8s_8(s
, COND_AL
, datalo
, addrlo
, 0);
1442 tcg_out_ld16u_8(s
, COND_AL
, datalo
, addrlo
, 0);
1444 tcg_out_bswap16(s
, COND_AL
, datalo
, datalo
);
1449 tcg_out_ld16u_8(s
, COND_AL
, datalo
, addrlo
, 0);
1450 tcg_out_bswap16s(s
, COND_AL
, datalo
, datalo
);
1452 tcg_out_ld16s_8(s
, COND_AL
, datalo
, addrlo
, 0);
1457 tcg_out_ld32_12(s
, COND_AL
, datalo
, addrlo
, 0);
1459 tcg_out_bswap32(s
, COND_AL
, datalo
, datalo
);
1464 TCGReg dl
= (bswap
? datahi
: datalo
);
1465 TCGReg dh
= (bswap
? datalo
: datahi
);
1467 /* Avoid ldrd for user-only emulation, to handle unaligned. */
1468 if (USING_SOFTMMU
&& use_armv6_instructions
1469 && (dl
& 1) == 0 && dh
== dl
+ 1) {
1470 tcg_out_ldrd_8(s
, COND_AL
, dl
, addrlo
, 0);
1471 } else if (dl
== addrlo
) {
1472 tcg_out_ld32_12(s
, COND_AL
, dh
, addrlo
, bswap
? 0 : 4);
1473 tcg_out_ld32_12(s
, COND_AL
, dl
, addrlo
, bswap
? 4 : 0);
1475 tcg_out_ld32_12(s
, COND_AL
, dl
, addrlo
, bswap
? 4 : 0);
1476 tcg_out_ld32_12(s
, COND_AL
, dh
, addrlo
, bswap
? 0 : 4);
1479 tcg_out_bswap32(s
, COND_AL
, dl
, dl
);
1480 tcg_out_bswap32(s
, COND_AL
, dh
, dh
);
1487 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, bool is64
)
1489 TCGReg addrlo
, datalo
, datahi
, addrhi
__attribute__((unused
));
1492 #ifdef CONFIG_SOFTMMU
1495 tcg_insn_unit
*label_ptr
;
1499 datahi
= (is64
? *args
++ : 0);
1501 addrhi
= (TARGET_LONG_BITS
== 64 ? *args
++ : 0);
1503 opc
= get_memop(oi
);
1505 #ifdef CONFIG_SOFTMMU
1506 mem_index
= get_mmuidx(oi
);
1507 addend
= tcg_out_tlb_read(s
, addrlo
, addrhi
, opc
, mem_index
, 1);
1509 /* This a conditional BL only to load a pointer within this opcode into LR
1510 for the slow path. We will not be using the value for a tail call. */
1511 label_ptr
= s
->code_ptr
;
1512 tcg_out_bl_noaddr(s
, COND_NE
);
1514 tcg_out_qemu_ld_index(s
, opc
, datalo
, datahi
, addrlo
, addend
);
1516 add_qemu_ldst_label(s
, true, oi
, datalo
, datahi
, addrlo
, addrhi
,
1517 s
->code_ptr
, label_ptr
);
1518 #else /* !CONFIG_SOFTMMU */
1520 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP
, guest_base
);
1521 tcg_out_qemu_ld_index(s
, opc
, datalo
, datahi
, addrlo
, TCG_REG_TMP
);
1523 tcg_out_qemu_ld_direct(s
, opc
, datalo
, datahi
, addrlo
);
1528 static inline void tcg_out_qemu_st_index(TCGContext
*s
, int cond
, TCGMemOp opc
,
1529 TCGReg datalo
, TCGReg datahi
,
1530 TCGReg addrlo
, TCGReg addend
)
1532 TCGMemOp bswap
= opc
& MO_BSWAP
;
1534 switch (opc
& MO_SIZE
) {
1536 tcg_out_st8_r(s
, cond
, datalo
, addrlo
, addend
);
1540 tcg_out_bswap16st(s
, cond
, TCG_REG_R0
, datalo
);
1541 tcg_out_st16_r(s
, cond
, TCG_REG_R0
, addrlo
, addend
);
1543 tcg_out_st16_r(s
, cond
, datalo
, addrlo
, addend
);
1549 tcg_out_bswap32(s
, cond
, TCG_REG_R0
, datalo
);
1550 tcg_out_st32_r(s
, cond
, TCG_REG_R0
, addrlo
, addend
);
1552 tcg_out_st32_r(s
, cond
, datalo
, addrlo
, addend
);
1556 /* Avoid strd for user-only emulation, to handle unaligned. */
1558 tcg_out_bswap32(s
, cond
, TCG_REG_R0
, datahi
);
1559 tcg_out_st32_rwb(s
, cond
, TCG_REG_R0
, addend
, addrlo
);
1560 tcg_out_bswap32(s
, cond
, TCG_REG_R0
, datalo
);
1561 tcg_out_st32_12(s
, cond
, TCG_REG_R0
, addend
, 4);
1562 } else if (USING_SOFTMMU
&& use_armv6_instructions
1563 && (datalo
& 1) == 0 && datahi
== datalo
+ 1) {
1564 tcg_out_strd_r(s
, cond
, datalo
, addrlo
, addend
);
1566 tcg_out_st32_rwb(s
, cond
, datalo
, addend
, addrlo
);
1567 tcg_out_st32_12(s
, cond
, datahi
, addend
, 4);
1573 static inline void tcg_out_qemu_st_direct(TCGContext
*s
, TCGMemOp opc
,
1574 TCGReg datalo
, TCGReg datahi
,
1577 TCGMemOp bswap
= opc
& MO_BSWAP
;
1579 switch (opc
& MO_SIZE
) {
1581 tcg_out_st8_12(s
, COND_AL
, datalo
, addrlo
, 0);
1585 tcg_out_bswap16st(s
, COND_AL
, TCG_REG_R0
, datalo
);
1586 tcg_out_st16_8(s
, COND_AL
, TCG_REG_R0
, addrlo
, 0);
1588 tcg_out_st16_8(s
, COND_AL
, datalo
, addrlo
, 0);
1594 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, datalo
);
1595 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addrlo
, 0);
1597 tcg_out_st32_12(s
, COND_AL
, datalo
, addrlo
, 0);
1601 /* Avoid strd for user-only emulation, to handle unaligned. */
1603 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, datahi
);
1604 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addrlo
, 0);
1605 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, datalo
);
1606 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addrlo
, 4);
1607 } else if (USING_SOFTMMU
&& use_armv6_instructions
1608 && (datalo
& 1) == 0 && datahi
== datalo
+ 1) {
1609 tcg_out_strd_8(s
, COND_AL
, datalo
, addrlo
, 0);
1611 tcg_out_st32_12(s
, COND_AL
, datalo
, addrlo
, 0);
1612 tcg_out_st32_12(s
, COND_AL
, datahi
, addrlo
, 4);
1618 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, bool is64
)
1620 TCGReg addrlo
, datalo
, datahi
, addrhi
__attribute__((unused
));
1623 #ifdef CONFIG_SOFTMMU
1626 tcg_insn_unit
*label_ptr
;
1630 datahi
= (is64
? *args
++ : 0);
1632 addrhi
= (TARGET_LONG_BITS
== 64 ? *args
++ : 0);
1634 opc
= get_memop(oi
);
1636 #ifdef CONFIG_SOFTMMU
1637 mem_index
= get_mmuidx(oi
);
1638 addend
= tcg_out_tlb_read(s
, addrlo
, addrhi
, opc
, mem_index
, 0);
1640 tcg_out_qemu_st_index(s
, COND_EQ
, opc
, datalo
, datahi
, addrlo
, addend
);
1642 /* The conditional call must come last, as we're going to return here. */
1643 label_ptr
= s
->code_ptr
;
1644 tcg_out_bl_noaddr(s
, COND_NE
);
1646 add_qemu_ldst_label(s
, false, oi
, datalo
, datahi
, addrlo
, addrhi
,
1647 s
->code_ptr
, label_ptr
);
1648 #else /* !CONFIG_SOFTMMU */
1650 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP
, guest_base
);
1651 tcg_out_qemu_st_index(s
, COND_AL
, opc
, datalo
,
1652 datahi
, addrlo
, TCG_REG_TMP
);
1654 tcg_out_qemu_st_direct(s
, opc
, datalo
, datahi
, addrlo
);
1659 static tcg_insn_unit
*tb_ret_addr
;
1661 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1662 const TCGArg
*args
, const int *const_args
)
1664 TCGArg a0
, a1
, a2
, a3
, a4
, a5
;
1668 case INDEX_op_exit_tb
:
1669 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
, args
[0]);
1670 tcg_out_goto(s
, COND_AL
, tb_ret_addr
);
1672 case INDEX_op_goto_tb
:
1673 if (s
->tb_jmp_insn_offset
) {
1674 /* Direct jump method */
1675 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
1676 tcg_out_b_noaddr(s
, COND_AL
);
1678 /* Indirect jump method */
1679 intptr_t ptr
= (intptr_t)(s
->tb_jmp_target_addr
+ args
[0]);
1680 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
, ptr
& ~0xfff);
1681 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, ptr
& 0xfff);
1683 s
->tb_jmp_reset_offset
[args
[0]] = tcg_current_code_size(s
);
1686 tcg_out_goto_label(s
, COND_AL
, arg_label(args
[0]));
1689 case INDEX_op_ld8u_i32
:
1690 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1692 case INDEX_op_ld8s_i32
:
1693 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1695 case INDEX_op_ld16u_i32
:
1696 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1698 case INDEX_op_ld16s_i32
:
1699 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1701 case INDEX_op_ld_i32
:
1702 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1704 case INDEX_op_st8_i32
:
1705 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1707 case INDEX_op_st16_i32
:
1708 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1710 case INDEX_op_st_i32
:
1711 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1714 case INDEX_op_movcond_i32
:
1715 /* Constraints mean that v2 is always in the same register as dest,
1716 * so we only need to do "if condition passed, move v1 to dest".
1718 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1719 args
[1], args
[2], const_args
[2]);
1720 tcg_out_dat_rIK(s
, tcg_cond_to_arm_cond
[args
[5]], ARITH_MOV
,
1721 ARITH_MVN
, args
[0], 0, args
[3], const_args
[3]);
1723 case INDEX_op_add_i32
:
1724 tcg_out_dat_rIN(s
, COND_AL
, ARITH_ADD
, ARITH_SUB
,
1725 args
[0], args
[1], args
[2], const_args
[2]);
1727 case INDEX_op_sub_i32
:
1728 if (const_args
[1]) {
1729 if (const_args
[2]) {
1730 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1] - args
[2]);
1732 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSB
,
1733 args
[0], args
[2], args
[1], 1);
1736 tcg_out_dat_rIN(s
, COND_AL
, ARITH_SUB
, ARITH_ADD
,
1737 args
[0], args
[1], args
[2], const_args
[2]);
1740 case INDEX_op_and_i32
:
1741 tcg_out_dat_rIK(s
, COND_AL
, ARITH_AND
, ARITH_BIC
,
1742 args
[0], args
[1], args
[2], const_args
[2]);
1744 case INDEX_op_andc_i32
:
1745 tcg_out_dat_rIK(s
, COND_AL
, ARITH_BIC
, ARITH_AND
,
1746 args
[0], args
[1], args
[2], const_args
[2]);
1748 case INDEX_op_or_i32
:
1751 case INDEX_op_xor_i32
:
1755 tcg_out_dat_rI(s
, COND_AL
, c
, args
[0], args
[1], args
[2], const_args
[2]);
1757 case INDEX_op_add2_i32
:
1758 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1759 a3
= args
[3], a4
= args
[4], a5
= args
[5];
1760 if (a0
== a3
|| (a0
== a5
&& !const_args
[5])) {
1763 tcg_out_dat_rIN(s
, COND_AL
, ARITH_ADD
| TO_CPSR
, ARITH_SUB
| TO_CPSR
,
1764 a0
, a2
, a4
, const_args
[4]);
1765 tcg_out_dat_rIK(s
, COND_AL
, ARITH_ADC
, ARITH_SBC
,
1766 a1
, a3
, a5
, const_args
[5]);
1767 tcg_out_mov_reg(s
, COND_AL
, args
[0], a0
);
1769 case INDEX_op_sub2_i32
:
1770 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1771 a3
= args
[3], a4
= args
[4], a5
= args
[5];
1772 if ((a0
== a3
&& !const_args
[3]) || (a0
== a5
&& !const_args
[5])) {
1775 if (const_args
[2]) {
1776 if (const_args
[4]) {
1777 tcg_out_movi32(s
, COND_AL
, a0
, a4
);
1780 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSB
| TO_CPSR
, a0
, a4
, a2
, 1);
1782 tcg_out_dat_rIN(s
, COND_AL
, ARITH_SUB
| TO_CPSR
,
1783 ARITH_ADD
| TO_CPSR
, a0
, a2
, a4
, const_args
[4]);
1785 if (const_args
[3]) {
1786 if (const_args
[5]) {
1787 tcg_out_movi32(s
, COND_AL
, a1
, a5
);
1790 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSC
, a1
, a5
, a3
, 1);
1792 tcg_out_dat_rIK(s
, COND_AL
, ARITH_SBC
, ARITH_ADC
,
1793 a1
, a3
, a5
, const_args
[5]);
1795 tcg_out_mov_reg(s
, COND_AL
, args
[0], a0
);
1797 case INDEX_op_neg_i32
:
1798 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1800 case INDEX_op_not_i32
:
1801 tcg_out_dat_reg(s
, COND_AL
,
1802 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1804 case INDEX_op_mul_i32
:
1805 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1807 case INDEX_op_mulu2_i32
:
1808 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1810 case INDEX_op_muls2_i32
:
1811 tcg_out_smull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1813 /* XXX: Perhaps args[2] & 0x1f is wrong */
1814 case INDEX_op_shl_i32
:
1816 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1818 case INDEX_op_shr_i32
:
1819 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1820 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1822 case INDEX_op_sar_i32
:
1823 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1824 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1826 case INDEX_op_rotr_i32
:
1827 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ROR(args
[2] & 0x1f) :
1828 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args
[2]);
1831 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1834 case INDEX_op_rotl_i32
:
1835 if (const_args
[2]) {
1836 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1837 ((0x20 - args
[2]) & 0x1f) ?
1838 SHIFT_IMM_ROR((0x20 - args
[2]) & 0x1f) :
1841 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, TCG_REG_TMP
, args
[2], 0x20);
1842 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1843 SHIFT_REG_ROR(TCG_REG_TMP
));
1847 case INDEX_op_brcond_i32
:
1848 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1849 args
[0], args
[1], const_args
[1]);
1850 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]],
1851 arg_label(args
[3]));
1853 case INDEX_op_brcond2_i32
:
1854 /* The resulting conditions are:
1855 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1856 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1857 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1858 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1859 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1860 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1862 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1863 args
[1], args
[3], const_args
[3]);
1864 tcg_out_dat_rIN(s
, COND_EQ
, ARITH_CMP
, ARITH_CMN
, 0,
1865 args
[0], args
[2], const_args
[2]);
1866 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]],
1867 arg_label(args
[5]));
1869 case INDEX_op_setcond_i32
:
1870 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1871 args
[1], args
[2], const_args
[2]);
1872 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1873 ARITH_MOV
, args
[0], 0, 1);
1874 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1875 ARITH_MOV
, args
[0], 0, 0);
1877 case INDEX_op_setcond2_i32
:
1878 /* See brcond2_i32 comment */
1879 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1880 args
[2], args
[4], const_args
[4]);
1881 tcg_out_dat_rIN(s
, COND_EQ
, ARITH_CMP
, ARITH_CMN
, 0,
1882 args
[1], args
[3], const_args
[3]);
1883 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1884 ARITH_MOV
, args
[0], 0, 1);
1885 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1886 ARITH_MOV
, args
[0], 0, 0);
1889 case INDEX_op_qemu_ld_i32
:
1890 tcg_out_qemu_ld(s
, args
, 0);
1892 case INDEX_op_qemu_ld_i64
:
1893 tcg_out_qemu_ld(s
, args
, 1);
1895 case INDEX_op_qemu_st_i32
:
1896 tcg_out_qemu_st(s
, args
, 0);
1898 case INDEX_op_qemu_st_i64
:
1899 tcg_out_qemu_st(s
, args
, 1);
1902 case INDEX_op_bswap16_i32
:
1903 tcg_out_bswap16(s
, COND_AL
, args
[0], args
[1]);
1905 case INDEX_op_bswap32_i32
:
1906 tcg_out_bswap32(s
, COND_AL
, args
[0], args
[1]);
1909 case INDEX_op_ext8s_i32
:
1910 tcg_out_ext8s(s
, COND_AL
, args
[0], args
[1]);
1912 case INDEX_op_ext16s_i32
:
1913 tcg_out_ext16s(s
, COND_AL
, args
[0], args
[1]);
1915 case INDEX_op_ext16u_i32
:
1916 tcg_out_ext16u(s
, COND_AL
, args
[0], args
[1]);
1919 case INDEX_op_deposit_i32
:
1920 tcg_out_deposit(s
, COND_AL
, args
[0], args
[2],
1921 args
[3], args
[4], const_args
[2]);
1924 case INDEX_op_div_i32
:
1925 tcg_out_sdiv(s
, COND_AL
, args
[0], args
[1], args
[2]);
1927 case INDEX_op_divu_i32
:
1928 tcg_out_udiv(s
, COND_AL
, args
[0], args
[1], args
[2]);
1931 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
1932 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
1933 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
1939 static const TCGTargetOpDef arm_op_defs
[] = {
1940 { INDEX_op_exit_tb
, { } },
1941 { INDEX_op_goto_tb
, { } },
1942 { INDEX_op_br
, { } },
1944 { INDEX_op_ld8u_i32
, { "r", "r" } },
1945 { INDEX_op_ld8s_i32
, { "r", "r" } },
1946 { INDEX_op_ld16u_i32
, { "r", "r" } },
1947 { INDEX_op_ld16s_i32
, { "r", "r" } },
1948 { INDEX_op_ld_i32
, { "r", "r" } },
1949 { INDEX_op_st8_i32
, { "r", "r" } },
1950 { INDEX_op_st16_i32
, { "r", "r" } },
1951 { INDEX_op_st_i32
, { "r", "r" } },
1953 /* TODO: "r", "r", "ri" */
1954 { INDEX_op_add_i32
, { "r", "r", "rIN" } },
1955 { INDEX_op_sub_i32
, { "r", "rI", "rIN" } },
1956 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1957 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1958 { INDEX_op_muls2_i32
, { "r", "r", "r", "r" } },
1959 { INDEX_op_and_i32
, { "r", "r", "rIK" } },
1960 { INDEX_op_andc_i32
, { "r", "r", "rIK" } },
1961 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1962 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1963 { INDEX_op_neg_i32
, { "r", "r" } },
1964 { INDEX_op_not_i32
, { "r", "r" } },
1966 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1967 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1968 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1969 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1970 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1972 { INDEX_op_brcond_i32
, { "r", "rIN" } },
1973 { INDEX_op_setcond_i32
, { "r", "r", "rIN" } },
1974 { INDEX_op_movcond_i32
, { "r", "r", "rIN", "rIK", "0" } },
1976 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "rIN", "rIK" } },
1977 { INDEX_op_sub2_i32
, { "r", "r", "rI", "rI", "rIN", "rIK" } },
1978 { INDEX_op_brcond2_i32
, { "r", "r", "rIN", "rIN" } },
1979 { INDEX_op_setcond2_i32
, { "r", "r", "r", "rIN", "rIN" } },
1981 #if TARGET_LONG_BITS == 32
1982 { INDEX_op_qemu_ld_i32
, { "r", "l" } },
1983 { INDEX_op_qemu_ld_i64
, { "r", "r", "l" } },
1984 { INDEX_op_qemu_st_i32
, { "s", "s" } },
1985 { INDEX_op_qemu_st_i64
, { "s", "s", "s" } },
1987 { INDEX_op_qemu_ld_i32
, { "r", "l", "l" } },
1988 { INDEX_op_qemu_ld_i64
, { "r", "r", "l", "l" } },
1989 { INDEX_op_qemu_st_i32
, { "s", "s", "s" } },
1990 { INDEX_op_qemu_st_i64
, { "s", "s", "s", "s" } },
1993 { INDEX_op_bswap16_i32
, { "r", "r" } },
1994 { INDEX_op_bswap32_i32
, { "r", "r" } },
1996 { INDEX_op_ext8s_i32
, { "r", "r" } },
1997 { INDEX_op_ext16s_i32
, { "r", "r" } },
1998 { INDEX_op_ext16u_i32
, { "r", "r" } },
2000 { INDEX_op_deposit_i32
, { "r", "0", "rZ" } },
2002 { INDEX_op_div_i32
, { "r", "r", "r" } },
2003 { INDEX_op_divu_i32
, { "r", "r", "r" } },
2008 static void tcg_target_init(TCGContext
*s
)
2010 /* Only probe for the platform and capabilities if we havn't already
2011 determined maximum values at compile time. */
2012 #ifndef use_idiv_instructions
2014 unsigned long hwcap
= qemu_getauxval(AT_HWCAP
);
2015 use_idiv_instructions
= (hwcap
& HWCAP_ARM_IDIVA
) != 0;
2018 if (__ARM_ARCH
< 7) {
2019 const char *pl
= (const char *)qemu_getauxval(AT_PLATFORM
);
2020 if (pl
!= NULL
&& pl
[0] == 'v' && pl
[1] >= '4' && pl
[1] <= '9') {
2021 arm_arch
= pl
[1] - '0';
2025 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
2026 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
2031 (1 << TCG_REG_R12
) |
2032 (1 << TCG_REG_R14
));
2034 tcg_regset_clear(s
->reserved_regs
);
2035 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
2036 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TMP
);
2037 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
2039 tcg_add_target_add_op_defs(arm_op_defs
);
2042 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg arg
,
2043 TCGReg arg1
, intptr_t arg2
)
2045 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
2048 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
2049 TCGReg arg1
, intptr_t arg2
)
2051 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
2054 static inline bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
2055 TCGReg base
, intptr_t ofs
)
2060 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
2061 TCGReg ret
, TCGReg arg
)
2063 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
2066 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
2067 TCGReg ret
, tcg_target_long arg
)
2069 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
2072 /* Compute frame size via macros, to share between tcg_target_qemu_prologue
2073 and tcg_register_jit. */
2075 #define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
2077 #define FRAME_SIZE \
2079 + TCG_STATIC_CALL_ARGS_SIZE \
2080 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
2081 + TCG_TARGET_STACK_ALIGN - 1) \
2082 & -TCG_TARGET_STACK_ALIGN)
2084 static void tcg_target_qemu_prologue(TCGContext
*s
)
2088 /* Calling convention requires us to save r4-r11 and lr. */
2089 /* stmdb sp!, { r4 - r11, lr } */
2090 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4ff0);
2092 /* Reserve callee argument and tcg temp space. */
2093 stack_addend
= FRAME_SIZE
- PUSH_SIZE
;
2095 tcg_out_dat_rI(s
, COND_AL
, ARITH_SUB
, TCG_REG_CALL_STACK
,
2096 TCG_REG_CALL_STACK
, stack_addend
, 1);
2097 tcg_set_frame(s
, TCG_REG_CALL_STACK
, TCG_STATIC_CALL_ARGS_SIZE
,
2098 CPU_TEMP_BUF_NLONGS
* sizeof(long));
2100 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
2102 tcg_out_bx(s
, COND_AL
, tcg_target_call_iarg_regs
[1]);
2103 tb_ret_addr
= s
->code_ptr
;
2105 /* Epilogue. We branch here via tb_ret_addr. */
2106 tcg_out_dat_rI(s
, COND_AL
, ARITH_ADD
, TCG_REG_CALL_STACK
,
2107 TCG_REG_CALL_STACK
, stack_addend
, 1);
2109 /* ldmia sp!, { r4 - r11, pc } */
2110 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8ff0);
2115 uint8_t fde_def_cfa
[4];
2116 uint8_t fde_reg_ofs
[18];
2119 #define ELF_HOST_MACHINE EM_ARM
2121 /* We're expecting a 2 byte uleb128 encoded value. */
2122 QEMU_BUILD_BUG_ON(FRAME_SIZE
>= (1 << 14));
2124 static const DebugFrame debug_frame
= {
2125 .h
.cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2128 .h
.cie
.code_align
= 1,
2129 .h
.cie
.data_align
= 0x7c, /* sleb128 -4 */
2130 .h
.cie
.return_column
= 14,
2132 /* Total FDE size does not include the "len" member. */
2133 .h
.fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, h
.fde
.cie_offset
),
2136 12, 13, /* DW_CFA_def_cfa sp, ... */
2137 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2141 /* The following must match the stmdb in the prologue. */
2142 0x8e, 1, /* DW_CFA_offset, lr, -4 */
2143 0x8b, 2, /* DW_CFA_offset, r11, -8 */
2144 0x8a, 3, /* DW_CFA_offset, r10, -12 */
2145 0x89, 4, /* DW_CFA_offset, r9, -16 */
2146 0x88, 5, /* DW_CFA_offset, r8, -20 */
2147 0x87, 6, /* DW_CFA_offset, r7, -24 */
2148 0x86, 7, /* DW_CFA_offset, r6, -28 */
2149 0x85, 8, /* DW_CFA_offset, r5, -32 */
2150 0x84, 9, /* DW_CFA_offset, r4, -36 */
2154 void tcg_register_jit(void *buf
, size_t buf_size
)
2156 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));