tcg/loongarch64/tcg-target.c.inc

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
   5  *
   6  * Based on tcg/riscv/tcg-target.c.inc
   7  *
   8  * Copyright (c) 2018 SiFive, Inc
   9  * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
  10  * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
  11  * Copyright (c) 2008 Fabrice Bellard
  12  *
  13  * Permission is hereby granted, free of charge, to any person obtaining a copy
  14  * of this software and associated documentation files (the "Software"), to deal
  15  * in the Software without restriction, including without limitation the rights
  16  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  17  * copies of the Software, and to permit persons to whom the Software is
  18  * furnished to do so, subject to the following conditions:
  19  *
  20  * The above copyright notice and this permission notice shall be included in
  21  * all copies or substantial portions of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  26  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  27  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  28  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  29  * THE SOFTWARE.
  30  */
  31
  32 #include "../tcg-ldst.c.inc"
  33 #include <asm/hwcap.h>
  34
  35 bool use_lsx_instructions;
  36
  37 #ifdef CONFIG_DEBUG_TCG
  38 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  39     "zero",
  40     "ra",
  41     "tp",
  42     "sp",
  43     "a0",
  44     "a1",
  45     "a2",
  46     "a3",
  47     "a4",
  48     "a5",
  49     "a6",
  50     "a7",
  51     "t0",
  52     "t1",
  53     "t2",
  54     "t3",
  55     "t4",
  56     "t5",
  57     "t6",
  58     "t7",
  59     "t8",
  60     "r21", /* reserved in the LP64* ABI, hence no ABI name */
  61     "s9",
  62     "s0",
  63     "s1",
  64     "s2",
  65     "s3",
  66     "s4",
  67     "s5",
  68     "s6",
  69     "s7",
  70     "s8",
  71     "vr0",
  72     "vr1",
  73     "vr2",
  74     "vr3",
  75     "vr4",
  76     "vr5",
  77     "vr6",
  78     "vr7",
  79     "vr8",
  80     "vr9",
  81     "vr10",
  82     "vr11",
  83     "vr12",
  84     "vr13",
  85     "vr14",
  86     "vr15",
  87     "vr16",
  88     "vr17",
  89     "vr18",
  90     "vr19",
  91     "vr20",
  92     "vr21",
  93     "vr22",
  94     "vr23",
  95     "vr24",
  96     "vr25",
  97     "vr26",
  98     "vr27",
  99     "vr28",
 100     "vr29",
 101     "vr30",
 102     "vr31",
 103 };
 104 #endif
 105
 106 static const int tcg_target_reg_alloc_order[] = {
 107     /* Registers preserved across calls */
 108     /* TCG_REG_S0 reserved for TCG_AREG0 */
 109     TCG_REG_S1,
 110     TCG_REG_S2,
 111     TCG_REG_S3,
 112     TCG_REG_S4,
 113     TCG_REG_S5,
 114     TCG_REG_S6,
 115     TCG_REG_S7,
 116     TCG_REG_S8,
 117     TCG_REG_S9,
 118
 119     /* Registers (potentially) clobbered across calls */
 120     TCG_REG_T0,
 121     TCG_REG_T1,
 122     TCG_REG_T2,
 123     TCG_REG_T3,
 124     TCG_REG_T4,
 125     TCG_REG_T5,
 126     TCG_REG_T6,
 127     TCG_REG_T7,
 128     TCG_REG_T8,
 129
 130     /* Argument registers, opposite order of allocation.  */
 131     TCG_REG_A7,
 132     TCG_REG_A6,
 133     TCG_REG_A5,
 134     TCG_REG_A4,
 135     TCG_REG_A3,
 136     TCG_REG_A2,
 137     TCG_REG_A1,
 138     TCG_REG_A0,
 139
 140     /* Vector registers */
 141     TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
 142     TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
 143     TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
 144     TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
 145     TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
 146     TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
 147     /* V24 - V31 are caller-saved, and skipped.  */
 148 };
 149
 150 static const int tcg_target_call_iarg_regs[] = {
 151     TCG_REG_A0,
 152     TCG_REG_A1,
 153     TCG_REG_A2,
 154     TCG_REG_A3,
 155     TCG_REG_A4,
 156     TCG_REG_A5,
 157     TCG_REG_A6,
 158     TCG_REG_A7,
 159 };
 160
 161 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
 162 {
 163     tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
 164     tcg_debug_assert(slot >= 0 && slot <= 1);
 165     return TCG_REG_A0 + slot;
 166 }
 167
 168 #ifndef CONFIG_SOFTMMU
 169 #define USE_GUEST_BASE     (guest_base != 0)
 170 #define TCG_GUEST_BASE_REG TCG_REG_S1
 171 #endif
 172
 173 #define TCG_CT_CONST_ZERO  0x100
 174 #define TCG_CT_CONST_S12   0x200
 175 #define TCG_CT_CONST_S32   0x400
 176 #define TCG_CT_CONST_U12   0x800
 177 #define TCG_CT_CONST_C12   0x1000
 178 #define TCG_CT_CONST_WSZ   0x2000
 179 #define TCG_CT_CONST_VCMP  0x4000
 180 #define TCG_CT_CONST_VADD  0x8000
 181
 182 #define ALL_GENERAL_REGS   MAKE_64BIT_MASK(0, 32)
 183 #define ALL_VECTOR_REGS    MAKE_64BIT_MASK(32, 32)
 184
 185 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 186 {
 187     return sextract64(val, pos, len);
 188 }
 189
 190 /* test if a constant matches the constraint */
 191 static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
 192 {
 193     if (ct & TCG_CT_CONST) {
 194         return true;
 195     }
 196     if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
 197         return true;
 198     }
 199     if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
 200         return true;
 201     }
 202     if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
 203         return true;
 204     }
 205     if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
 206         return true;
 207     }
 208     if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
 209         return true;
 210     }
 211     if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
 212         return true;
 213     }
 214     int64_t vec_val = sextract64(val, 0, 8 << vece);
 215     if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) {
 216         return true;
 217     }
 218     if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) {
 219         return true;
 220     }
 221     return false;
 222 }
 223
 224 /*
 225  * Relocations
 226  */
 227
 228 /*
 229  * Relocation records defined in LoongArch ELF psABI v1.00 is way too
 230  * complicated; a whopping stack machine is needed to stuff the fields, at
 231  * the very least one SOP_PUSH and one SOP_POP (of the correct format) are
 232  * needed.
 233  *
 234  * Hence, define our own simpler relocation types. Numbers are chosen as to
 235  * not collide with potential future additions to the true ELF relocation
 236  * type enum.
 237  */
 238
 239 /* Field Sk16, shifted right by 2; suitable for conditional jumps */
 240 #define R_LOONGARCH_BR_SK16     256
 241 /* Field Sd10k16, shifted right by 2; suitable for B and BL */
 242 #define R_LOONGARCH_BR_SD10K16  257
 243
 244 static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 245 {
 246     const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
 247     intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
 248
 249     tcg_debug_assert((offset & 3) == 0);
 250     offset >>= 2;
 251     if (offset == sextreg(offset, 0, 16)) {
 252         *src_rw = deposit64(*src_rw, 10, 16, offset);
 253         return true;
 254     }
 255
 256     return false;
 257 }
 258
 259 static bool reloc_br_sd10k16(tcg_insn_unit *src_rw,
 260                              const tcg_insn_unit *target)
 261 {
 262     const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
 263     intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
 264
 265     tcg_debug_assert((offset & 3) == 0);
 266     offset >>= 2;
 267     if (offset == sextreg(offset, 0, 26)) {
 268         *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */
 269         *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */
 270         return true;
 271     }
 272
 273     return false;
 274 }
 275
 276 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 277                         intptr_t value, intptr_t addend)
 278 {
 279     tcg_debug_assert(addend == 0);
 280     switch (type) {
 281     case R_LOONGARCH_BR_SK16:
 282         return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value);
 283     case R_LOONGARCH_BR_SD10K16:
 284         return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value);
 285     default:
 286         g_assert_not_reached();
 287     }
 288 }
 289
 290 #include "tcg-insn-defs.c.inc"
 291
 292 /*
 293  * TCG intrinsics
 294  */
 295
 296 static void tcg_out_mb(TCGContext *s, TCGArg a0)
 297 {
 298     /* Baseline LoongArch only has the full barrier, unfortunately.  */
 299     tcg_out_opc_dbar(s, 0);
 300 }
 301
 302 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 303 {
 304     if (ret == arg) {
 305         return true;
 306     }
 307     switch (type) {
 308     case TCG_TYPE_I32:
 309     case TCG_TYPE_I64:
 310         /*
 311          * Conventional register-register move used in LoongArch is
 312          * `or dst, src, zero`.
 313          */
 314         tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
 315         break;
 316     default:
 317         g_assert_not_reached();
 318     }
 319     return true;
 320 }
 321
 322 /* Loads a 32-bit immediate into rd, sign-extended.  */
 323 static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val)
 324 {
 325     tcg_target_long lo = sextreg(val, 0, 12);
 326     tcg_target_long hi12 = sextreg(val, 12, 20);
 327
 328     /* Single-instruction cases.  */
 329     if (hi12 == 0) {
 330         /* val fits in uimm12: ori rd, zero, val */
 331         tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
 332         return;
 333     }
 334     if (hi12 == sextreg(lo, 12, 20)) {
 335         /* val fits in simm12: addi.w rd, zero, val */
 336         tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
 337         return;
 338     }
 339
 340     /* High bits must be set; load with lu12i.w + optional ori.  */
 341     tcg_out_opc_lu12i_w(s, rd, hi12);
 342     if (lo != 0) {
 343         tcg_out_opc_ori(s, rd, rd, lo & 0xfff);
 344     }
 345 }
 346
 347 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
 348                          tcg_target_long val)
 349 {
 350     /*
 351      * LoongArch conventionally loads 64-bit immediates in at most 4 steps,
 352      * with dedicated instructions for filling the respective bitfields
 353      * below:
 354      *
 355      *        6                   5                   4               3
 356      *  3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
 357      * +-----------------------+---------------------------------------+...
 358      * |          hi52         |                  hi32                 |
 359      * +-----------------------+---------------------------------------+...
 360      *       3                   2                   1
 361      *     1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 362      * ...+-------------------------------------+-------------------------+
 363      *    |                 hi12                |            lo           |
 364      * ...+-------------------------------------+-------------------------+
 365      *
 366      * Check if val belong to one of the several fast cases, before falling
 367      * back to the slow path.
 368      */
 369
 370     intptr_t pc_offset;
 371     tcg_target_long val_lo, val_hi, pc_hi, offset_hi;
 372     tcg_target_long hi12, hi32, hi52;
 373
 374     /* Value fits in signed i32.  */
 375     if (type == TCG_TYPE_I32 || val == (int32_t)val) {
 376         tcg_out_movi_i32(s, rd, val);
 377         return;
 378     }
 379
 380     /* PC-relative cases.  */
 381     pc_offset = tcg_pcrel_diff(s, (void *)val);
 382     if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
 383         /* Single pcaddu2i.  */
 384         tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
 385         return;
 386     }
 387
 388     if (pc_offset == (int32_t)pc_offset) {
 389         /* Offset within 32 bits; load with pcalau12i + ori.  */
 390         val_lo = sextreg(val, 0, 12);
 391         val_hi = val >> 12;
 392         pc_hi = (val - pc_offset) >> 12;
 393         offset_hi = val_hi - pc_hi;
 394
 395         tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20));
 396         tcg_out_opc_pcalau12i(s, rd, offset_hi);
 397         if (val_lo != 0) {
 398             tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff);
 399         }
 400         return;
 401     }
 402
 403     hi12 = sextreg(val, 12, 20);
 404     hi32 = sextreg(val, 32, 20);
 405     hi52 = sextreg(val, 52, 12);
 406
 407     /* Single cu52i.d case.  */
 408     if ((hi52 != 0) && (ctz64(val) >= 52)) {
 409         tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52);
 410         return;
 411     }
 412
 413     /* Slow path.  Initialize the low 32 bits, then concat high bits.  */
 414     tcg_out_movi_i32(s, rd, val);
 415
 416     /* Load hi32 and hi52 explicitly when they are unexpected values. */
 417     if (hi32 != sextreg(hi12, 20, 20)) {
 418         tcg_out_opc_cu32i_d(s, rd, hi32);
 419     }
 420
 421     if (hi52 != sextreg(hi32, 20, 12)) {
 422         tcg_out_opc_cu52i_d(s, rd, rd, hi52);
 423     }
 424 }
 425
 426 static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd,
 427                          TCGReg rs, tcg_target_long imm)
 428 {
 429     tcg_target_long lo12 = sextreg(imm, 0, 12);
 430     tcg_target_long hi16 = sextreg(imm - lo12, 16, 16);
 431
 432     /*
 433      * Note that there's a hole in between hi16 and lo12:
 434      *
 435      *       3                   2                   1                   0
 436      *     1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 437      * ...+-------------------------------+-------+-----------------------+
 438      *    |             hi16              |       |          lo12         |
 439      * ...+-------------------------------+-------+-----------------------+
 440      *
 441      * For bits within that hole, it's more efficient to use LU12I and ADD.
 442      */
 443     if (imm == (hi16 << 16) + lo12) {
 444         if (hi16) {
 445             tcg_out_opc_addu16i_d(s, rd, rs, hi16);
 446             rs = rd;
 447         }
 448         if (type == TCG_TYPE_I32) {
 449             tcg_out_opc_addi_w(s, rd, rs, lo12);
 450         } else if (lo12) {
 451             tcg_out_opc_addi_d(s, rd, rs, lo12);
 452         } else {
 453             tcg_out_mov(s, type, rd, rs);
 454         }
 455     } else {
 456         tcg_out_movi(s, type, TCG_REG_TMP0, imm);
 457         if (type == TCG_TYPE_I32) {
 458             tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0);
 459         } else {
 460             tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0);
 461         }
 462     }
 463 }
 464
 465 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
 466 {
 467     return false;
 468 }
 469
 470 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
 471                              tcg_target_long imm)
 472 {
 473     /* This function is only used for passing structs by reference. */
 474     g_assert_not_reached();
 475 }
 476
 477 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
 478 {
 479     tcg_out_opc_andi(s, ret, arg, 0xff);
 480 }
 481
 482 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
 483 {
 484     tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15);
 485 }
 486
 487 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
 488 {
 489     tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31);
 490 }
 491
 492 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 493 {
 494     tcg_out_opc_sext_b(s, ret, arg);
 495 }
 496
 497 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 498 {
 499     tcg_out_opc_sext_h(s, ret, arg);
 500 }
 501
 502 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
 503 {
 504     tcg_out_opc_addi_w(s, ret, arg, 0);
 505 }
 506
 507 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
 508 {
 509     if (ret != arg) {
 510         tcg_out_ext32s(s, ret, arg);
 511     }
 512 }
 513
 514 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
 515 {
 516     tcg_out_ext32u(s, ret, arg);
 517 }
 518
 519 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
 520 {
 521     tcg_out_ext32s(s, ret, arg);
 522 }
 523
 524 static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
 525                            TCGReg a0, TCGReg a1, TCGReg a2,
 526                            bool c2, bool is_32bit)
 527 {
 528     if (c2) {
 529         /*
 530          * Fast path: semantics already satisfied due to constraint and
 531          * insn behavior, single instruction is enough.
 532          */
 533         tcg_debug_assert(a2 == (is_32bit ? 32 : 64));
 534         /* all clz/ctz insns belong to DJ-format */
 535         tcg_out32(s, encode_dj_insn(opc, a0, a1));
 536         return;
 537     }
 538
 539     tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1));
 540     /* a0 = a1 ? REG_TMP0 : a2 */
 541     tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1);
 542     tcg_out_opc_masknez(s, a0, a2, a1);
 543     tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
 544 }
 545
 546 #define SETCOND_INV    TCG_TARGET_NB_REGS
 547 #define SETCOND_NEZ    (SETCOND_INV << 1)
 548 #define SETCOND_FLAGS  (SETCOND_INV | SETCOND_NEZ)
 549
 550 static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
 551                                TCGReg arg1, tcg_target_long arg2, bool c2)
 552 {
 553     int flags = 0;
 554
 555     switch (cond) {
 556     case TCG_COND_EQ:    /* -> NE  */
 557     case TCG_COND_GE:    /* -> LT  */
 558     case TCG_COND_GEU:   /* -> LTU */
 559     case TCG_COND_GT:    /* -> LE  */
 560     case TCG_COND_GTU:   /* -> LEU */
 561         cond = tcg_invert_cond(cond);
 562         flags ^= SETCOND_INV;
 563         break;
 564     default:
 565         break;
 566     }
 567
 568     switch (cond) {
 569     case TCG_COND_LE:
 570     case TCG_COND_LEU:
 571         /*
 572          * If we have a constant input, the most efficient way to implement
 573          * LE is by adding 1 and using LT.  Watch out for wrap around for LEU.
 574          * We don't need to care for this for LE because the constant input
 575          * is still constrained to int32_t, and INT32_MAX+1 is representable
 576          * in the 64-bit temporary register.
 577          */
 578         if (c2) {
 579             if (cond == TCG_COND_LEU) {
 580                 /* unsigned <= -1 is true */
 581                 if (arg2 == -1) {
 582                     tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV));
 583                     return ret;
 584                 }
 585                 cond = TCG_COND_LTU;
 586             } else {
 587                 cond = TCG_COND_LT;
 588             }
 589             arg2 += 1;
 590         } else {
 591             TCGReg tmp = arg2;
 592             arg2 = arg1;
 593             arg1 = tmp;
 594             cond = tcg_swap_cond(cond);    /* LE -> GE */
 595             cond = tcg_invert_cond(cond);  /* GE -> LT */
 596             flags ^= SETCOND_INV;
 597         }
 598         break;
 599     default:
 600         break;
 601     }
 602
 603     switch (cond) {
 604     case TCG_COND_NE:
 605         flags |= SETCOND_NEZ;
 606         if (!c2) {
 607             tcg_out_opc_xor(s, ret, arg1, arg2);
 608         } else if (arg2 == 0) {
 609             ret = arg1;
 610         } else if (arg2 >= 0 && arg2 <= 0xfff) {
 611             tcg_out_opc_xori(s, ret, arg1, arg2);
 612         } else {
 613             tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2);
 614         }
 615         break;
 616
 617     case TCG_COND_LT:
 618     case TCG_COND_LTU:
 619         if (c2) {
 620             if (arg2 >= -0x800 && arg2 <= 0x7ff) {
 621                 if (cond == TCG_COND_LT) {
 622                     tcg_out_opc_slti(s, ret, arg1, arg2);
 623                 } else {
 624                     tcg_out_opc_sltui(s, ret, arg1, arg2);
 625                 }
 626                 break;
 627             }
 628             tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2);
 629             arg2 = TCG_REG_TMP0;
 630         }
 631         if (cond == TCG_COND_LT) {
 632             tcg_out_opc_slt(s, ret, arg1, arg2);
 633         } else {
 634             tcg_out_opc_sltu(s, ret, arg1, arg2);
 635         }
 636         break;
 637
 638     default:
 639         g_assert_not_reached();
 640         break;
 641     }
 642
 643     return ret | flags;
 644 }
 645
 646 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
 647                             TCGReg arg1, tcg_target_long arg2, bool c2)
 648 {
 649     int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
 650
 651     if (tmpflags != ret) {
 652         TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
 653
 654         switch (tmpflags & SETCOND_FLAGS) {
 655         case SETCOND_INV:
 656             /* Intermediate result is boolean: simply invert. */
 657             tcg_out_opc_xori(s, ret, tmp, 1);
 658             break;
 659         case SETCOND_NEZ:
 660             /* Intermediate result is zero/non-zero: test != 0. */
 661             tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp);
 662             break;
 663         case SETCOND_NEZ | SETCOND_INV:
 664             /* Intermediate result is zero/non-zero: test == 0. */
 665             tcg_out_opc_sltui(s, ret, tmp, 1);
 666             break;
 667         default:
 668             g_assert_not_reached();
 669         }
 670     }
 671 }
 672
 673 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
 674                             TCGReg c1, tcg_target_long c2, bool const2,
 675                             TCGReg v1, TCGReg v2)
 676 {
 677     int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2);
 678     TCGReg t;
 679
 680     /* Standardize the test below to t != 0. */
 681     if (tmpflags & SETCOND_INV) {
 682         t = v1, v1 = v2, v2 = t;
 683     }
 684
 685     t = tmpflags & ~SETCOND_FLAGS;
 686     if (v1 == TCG_REG_ZERO) {
 687         tcg_out_opc_masknez(s, ret, v2, t);
 688     } else if (v2 == TCG_REG_ZERO) {
 689         tcg_out_opc_maskeqz(s, ret, v1, t);
 690     } else {
 691         tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */
 692         tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */
 693         tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2);
 694     }
 695 }
 696
 697 /*
 698  * Branch helpers
 699  */
 700
 701 static const struct {
 702     LoongArchInsn op;
 703     bool swap;
 704 } tcg_brcond_to_loongarch[] = {
 705     [TCG_COND_EQ] =  { OPC_BEQ,  false },
 706     [TCG_COND_NE] =  { OPC_BNE,  false },
 707     [TCG_COND_LT] =  { OPC_BGT,  true  },
 708     [TCG_COND_GE] =  { OPC_BLE,  true  },
 709     [TCG_COND_LE] =  { OPC_BLE,  false },
 710     [TCG_COND_GT] =  { OPC_BGT,  false },
 711     [TCG_COND_LTU] = { OPC_BGTU, true  },
 712     [TCG_COND_GEU] = { OPC_BLEU, true  },
 713     [TCG_COND_LEU] = { OPC_BLEU, false },
 714     [TCG_COND_GTU] = { OPC_BGTU, false }
 715 };
 716
 717 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
 718                            TCGReg arg2, TCGLabel *l)
 719 {
 720     LoongArchInsn op = tcg_brcond_to_loongarch[cond].op;
 721
 722     tcg_debug_assert(op != 0);
 723
 724     if (tcg_brcond_to_loongarch[cond].swap) {
 725         TCGReg t = arg1;
 726         arg1 = arg2;
 727         arg2 = t;
 728     }
 729
 730     /* all conditional branch insns belong to DJSk16-format */
 731     tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0);
 732     tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0));
 733 }
 734
 735 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
 736 {
 737     TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
 738     ptrdiff_t offset = tcg_pcrel_diff(s, arg);
 739
 740     tcg_debug_assert((offset & 3) == 0);
 741     if (offset == sextreg(offset, 0, 28)) {
 742         /* short jump: +/- 256MiB */
 743         if (tail) {
 744             tcg_out_opc_b(s, offset >> 2);
 745         } else {
 746             tcg_out_opc_bl(s, offset >> 2);
 747         }
 748     } else if (offset == sextreg(offset, 0, 38)) {
 749         /* long jump: +/- 256GiB */
 750         tcg_target_long lo = sextreg(offset, 0, 18);
 751         tcg_target_long hi = offset - lo;
 752         tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18);
 753         tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
 754     } else {
 755         /* far jump: 64-bit */
 756         tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18);
 757         tcg_target_long hi = (tcg_target_long)arg - lo;
 758         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi);
 759         tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
 760     }
 761 }
 762
 763 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
 764                          const TCGHelperInfo *info)
 765 {
 766     tcg_out_call_int(s, arg, false);
 767 }
 768
 769 /*
 770  * Load/store helpers
 771  */
 772
 773 static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data,
 774                          TCGReg addr, intptr_t offset)
 775 {
 776     intptr_t imm12 = sextreg(offset, 0, 12);
 777
 778     if (offset != imm12) {
 779         intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
 780
 781         if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
 782             imm12 = sextreg(diff, 0, 12);
 783             tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12);
 784         } else {
 785             tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
 786             if (addr != TCG_REG_ZERO) {
 787                 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr);
 788             }
 789         }
 790         addr = TCG_REG_TMP2;
 791     }
 792
 793     switch (opc) {
 794     case OPC_LD_B:
 795     case OPC_LD_BU:
 796     case OPC_LD_H:
 797     case OPC_LD_HU:
 798     case OPC_LD_W:
 799     case OPC_LD_WU:
 800     case OPC_LD_D:
 801     case OPC_ST_B:
 802     case OPC_ST_H:
 803     case OPC_ST_W:
 804     case OPC_ST_D:
 805         tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12));
 806         break;
 807     default:
 808         g_assert_not_reached();
 809     }
 810 }
 811
 812 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
 813                        TCGReg arg1, intptr_t arg2)
 814 {
 815     bool is_32bit = type == TCG_TYPE_I32;
 816     tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2);
 817 }
 818
 819 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
 820                        TCGReg arg1, intptr_t arg2)
 821 {
 822     bool is_32bit = type == TCG_TYPE_I32;
 823     tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2);
 824 }
 825
 826 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 827                         TCGReg base, intptr_t ofs)
 828 {
 829     if (val == 0) {
 830         tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
 831         return true;
 832     }
 833     return false;
 834 }
 835
 836 /*
 837  * Load/store helpers for SoftMMU, and qemu_ld/st implementations
 838  */
 839
 840 static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
 841 {
 842     tcg_out_opc_b(s, 0);
 843     return reloc_br_sd10k16(s->code_ptr - 1, target);
 844 }
 845
 846 static const TCGLdstHelperParam ldst_helper_param = {
 847     .ntmp = 1, .tmp = { TCG_REG_TMP0 }
 848 };
 849
 850 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 851 {
 852     MemOp opc = get_memop(l->oi);
 853
 854     /* resolve label address */
 855     if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
 856         return false;
 857     }
 858
 859     tcg_out_ld_helper_args(s, l, &ldst_helper_param);
 860     tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false);
 861     tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param);
 862     return tcg_out_goto(s, l->raddr);
 863 }
 864
 865 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 866 {
 867     MemOp opc = get_memop(l->oi);
 868
 869     /* resolve label address */
 870     if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
 871         return false;
 872     }
 873
 874     tcg_out_st_helper_args(s, l, &ldst_helper_param);
 875     tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
 876     return tcg_out_goto(s, l->raddr);
 877 }
 878
 879 typedef struct {
 880     TCGReg base;
 881     TCGReg index;
 882     TCGAtomAlign aa;
 883 } HostAddress;
 884
 885 bool tcg_target_has_memory_bswap(MemOp memop)
 886 {
 887     return false;
 888 }
 889
 890 /* We expect to use a 12-bit negative offset from ENV.  */
 891 #define MIN_TLB_MASK_TABLE_OFS  -(1 << 11)
 892
 893 /*
 894  * For softmmu, perform the TLB load and compare.
 895  * For useronly, perform any required alignment tests.
 896  * In both cases, return a TCGLabelQemuLdst structure if the slow path
 897  * is required and fill in @h with the host address for the fast path.
 898  */
 899 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
 900                                            TCGReg addr_reg, MemOpIdx oi,
 901                                            bool is_ld)
 902 {
 903     TCGType addr_type = s->addr_type;
 904     TCGLabelQemuLdst *ldst = NULL;
 905     MemOp opc = get_memop(oi);
 906     MemOp a_bits;
 907
 908     h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
 909     a_bits = h->aa.align;
 910
 911 #ifdef CONFIG_SOFTMMU
 912     unsigned s_bits = opc & MO_SIZE;
 913     int mem_index = get_mmuidx(oi);
 914     int fast_ofs = tlb_mask_table_ofs(s, mem_index);
 915     int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
 916     int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
 917
 918     ldst = new_ldst_label(s);
 919     ldst->is_ld = is_ld;
 920     ldst->oi = oi;
 921     ldst->addrlo_reg = addr_reg;
 922
 923     tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
 924     tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
 925
 926     tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
 927                     s->page_bits - CPU_TLB_ENTRY_BITS);
 928     tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
 929     tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
 930
 931     /* Load the tlb comparator and the addend.  */
 932     QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
 933     tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
 934                is_ld ? offsetof(CPUTLBEntry, addr_read)
 935                      : offsetof(CPUTLBEntry, addr_write));
 936     tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
 937                offsetof(CPUTLBEntry, addend));
 938
 939     /*
 940      * For aligned accesses, we check the first byte and include the alignment
 941      * bits within the address.  For unaligned access, we check that we don't
 942      * cross pages using the address of the last byte of the access.
 943      */
 944     if (a_bits < s_bits) {
 945         unsigned a_mask = (1u << a_bits) - 1;
 946         unsigned s_mask = (1u << s_bits) - 1;
 947         tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
 948     } else {
 949         tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
 950     }
 951     tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO,
 952                           a_bits, s->page_bits - 1);
 953
 954     /* Compare masked address with the TLB entry.  */
 955     ldst->label_ptr[0] = s->code_ptr;
 956     tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
 957
 958     h->index = TCG_REG_TMP2;
 959 #else
 960     if (a_bits) {
 961         ldst = new_ldst_label(s);
 962
 963         ldst->is_ld = is_ld;
 964         ldst->oi = oi;
 965         ldst->addrlo_reg = addr_reg;
 966
 967         /*
 968          * Without micro-architecture details, we don't know which of
 969          * bstrpick or andi is faster, so use bstrpick as it's not
 970          * constrained by imm field width. Not to say alignments >= 2^12
 971          * are going to happen any time soon.
 972          */
 973         tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
 974
 975         ldst->label_ptr[0] = s->code_ptr;
 976         tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
 977     }
 978
 979     h->index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
 980 #endif
 981
 982     if (addr_type == TCG_TYPE_I32) {
 983         h->base = TCG_REG_TMP0;
 984         tcg_out_ext32u(s, h->base, addr_reg);
 985     } else {
 986         h->base = addr_reg;
 987     }
 988
 989     return ldst;
 990 }
 991
 992 static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
 993                                     TCGReg rd, HostAddress h)
 994 {
 995     /* Byte swapping is left to middle-end expansion.  */
 996     tcg_debug_assert((opc & MO_BSWAP) == 0);
 997
 998     switch (opc & MO_SSIZE) {
 999     case MO_UB:
1000         tcg_out_opc_ldx_bu(s, rd, h.base, h.index);
1001         break;
1002     case MO_SB:
1003         tcg_out_opc_ldx_b(s, rd, h.base, h.index);
1004         break;
1005     case MO_UW:
1006         tcg_out_opc_ldx_hu(s, rd, h.base, h.index);
1007         break;
1008     case MO_SW:
1009         tcg_out_opc_ldx_h(s, rd, h.base, h.index);
1010         break;
1011     case MO_UL:
1012         if (type == TCG_TYPE_I64) {
1013             tcg_out_opc_ldx_wu(s, rd, h.base, h.index);
1014             break;
1015         }
1016         /* fallthrough */
1017     case MO_SL:
1018         tcg_out_opc_ldx_w(s, rd, h.base, h.index);
1019         break;
1020     case MO_UQ:
1021         tcg_out_opc_ldx_d(s, rd, h.base, h.index);
1022         break;
1023     default:
1024         g_assert_not_reached();
1025     }
1026 }
1027
1028 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1029                             MemOpIdx oi, TCGType data_type)
1030 {
1031     TCGLabelQemuLdst *ldst;
1032     HostAddress h;
1033
1034     ldst = prepare_host_addr(s, &h, addr_reg, oi, true);
1035     tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h);
1036
1037     if (ldst) {
1038         ldst->type = data_type;
1039         ldst->datalo_reg = data_reg;
1040         ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1041     }
1042 }
1043
1044 static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc,
1045                                     TCGReg rd, HostAddress h)
1046 {
1047     /* Byte swapping is left to middle-end expansion.  */
1048     tcg_debug_assert((opc & MO_BSWAP) == 0);
1049
1050     switch (opc & MO_SIZE) {
1051     case MO_8:
1052         tcg_out_opc_stx_b(s, rd, h.base, h.index);
1053         break;
1054     case MO_16:
1055         tcg_out_opc_stx_h(s, rd, h.base, h.index);
1056         break;
1057     case MO_32:
1058         tcg_out_opc_stx_w(s, rd, h.base, h.index);
1059         break;
1060     case MO_64:
1061         tcg_out_opc_stx_d(s, rd, h.base, h.index);
1062         break;
1063     default:
1064         g_assert_not_reached();
1065     }
1066 }
1067
1068 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1069                             MemOpIdx oi, TCGType data_type)
1070 {
1071     TCGLabelQemuLdst *ldst;
1072     HostAddress h;
1073
1074     ldst = prepare_host_addr(s, &h, addr_reg, oi, false);
1075     tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h);
1076
1077     if (ldst) {
1078         ldst->type = data_type;
1079         ldst->datalo_reg = data_reg;
1080         ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1081     }
1082 }
1083
1084 /*
1085  * Entry-points
1086  */
1087
1088 static const tcg_insn_unit *tb_ret_addr;
1089
1090 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1091 {
1092     /* Reuse the zeroing that exists for goto_ptr.  */
1093     if (a0 == 0) {
1094         tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1095     } else {
1096         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1097         tcg_out_call_int(s, tb_ret_addr, true);
1098     }
1099 }
1100
1101 static void tcg_out_goto_tb(TCGContext *s, int which)
1102 {
1103     /*
1104      * Direct branch, or load indirect address, to be patched
1105      * by tb_target_set_jmp_target.  Check indirect load offset
1106      * in range early, regardless of direct branch distance,
1107      * via assert within tcg_out_opc_pcaddu2i.
1108      */
1109     uintptr_t i_addr = get_jmp_target_addr(s, which);
1110     intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr);
1111
1112     set_jmp_insn_offset(s, which);
1113     tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2);
1114
1115     /* Finish the load and indirect branch. */
1116     tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0);
1117     tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1118     set_jmp_reset_offset(s, which);
1119 }
1120
1121 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1122                               uintptr_t jmp_rx, uintptr_t jmp_rw)
1123 {
1124     uintptr_t d_addr = tb->jmp_target_addr[n];
1125     ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2;
1126     tcg_insn_unit insn;
1127
1128     /* Either directly branch, or load slot address for indirect branch. */
1129     if (d_disp == sextreg(d_disp, 0, 26)) {
1130         insn = encode_sd10k16_insn(OPC_B, d_disp);
1131     } else {
1132         uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n];
1133         intptr_t i_disp = i_addr - jmp_rx;
1134         insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2);
1135     }
1136
1137     qatomic_set((tcg_insn_unit *)jmp_rw, insn);
1138     flush_idcache_range(jmp_rx, jmp_rw, 4);
1139 }
1140
1141 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1142                        const TCGArg args[TCG_MAX_OP_ARGS],
1143                        const int const_args[TCG_MAX_OP_ARGS])
1144 {
1145     TCGArg a0 = args[0];
1146     TCGArg a1 = args[1];
1147     TCGArg a2 = args[2];
1148     int c2 = const_args[2];
1149
1150     switch (opc) {
1151     case INDEX_op_mb:
1152         tcg_out_mb(s, a0);
1153         break;
1154
1155     case INDEX_op_goto_ptr:
1156         tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
1157         break;
1158
1159     case INDEX_op_br:
1160         tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0),
1161                       0);
1162         tcg_out_opc_b(s, 0);
1163         break;
1164
1165     case INDEX_op_brcond_i32:
1166     case INDEX_op_brcond_i64:
1167         tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1168         break;
1169
1170     case INDEX_op_extrh_i64_i32:
1171         tcg_out_opc_srai_d(s, a0, a1, 32);
1172         break;
1173
1174     case INDEX_op_not_i32:
1175     case INDEX_op_not_i64:
1176         tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
1177         break;
1178
1179     case INDEX_op_nor_i32:
1180     case INDEX_op_nor_i64:
1181         if (c2) {
1182             tcg_out_opc_ori(s, a0, a1, a2);
1183             tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
1184         } else {
1185             tcg_out_opc_nor(s, a0, a1, a2);
1186         }
1187         break;
1188
1189     case INDEX_op_andc_i32:
1190     case INDEX_op_andc_i64:
1191         if (c2) {
1192             /* guaranteed to fit due to constraint */
1193             tcg_out_opc_andi(s, a0, a1, ~a2);
1194         } else {
1195             tcg_out_opc_andn(s, a0, a1, a2);
1196         }
1197         break;
1198
1199     case INDEX_op_orc_i32:
1200     case INDEX_op_orc_i64:
1201         if (c2) {
1202             /* guaranteed to fit due to constraint */
1203             tcg_out_opc_ori(s, a0, a1, ~a2);
1204         } else {
1205             tcg_out_opc_orn(s, a0, a1, a2);
1206         }
1207         break;
1208
1209     case INDEX_op_and_i32:
1210     case INDEX_op_and_i64:
1211         if (c2) {
1212             tcg_out_opc_andi(s, a0, a1, a2);
1213         } else {
1214             tcg_out_opc_and(s, a0, a1, a2);
1215         }
1216         break;
1217
1218     case INDEX_op_or_i32:
1219     case INDEX_op_or_i64:
1220         if (c2) {
1221             tcg_out_opc_ori(s, a0, a1, a2);
1222         } else {
1223             tcg_out_opc_or(s, a0, a1, a2);
1224         }
1225         break;
1226
1227     case INDEX_op_xor_i32:
1228     case INDEX_op_xor_i64:
1229         if (c2) {
1230             tcg_out_opc_xori(s, a0, a1, a2);
1231         } else {
1232             tcg_out_opc_xor(s, a0, a1, a2);
1233         }
1234         break;
1235
1236     case INDEX_op_extract_i32:
1237         tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
1238         break;
1239     case INDEX_op_extract_i64:
1240         tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
1241         break;
1242
1243     case INDEX_op_deposit_i32:
1244         tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
1245         break;
1246     case INDEX_op_deposit_i64:
1247         tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
1248         break;
1249
1250     case INDEX_op_bswap16_i32:
1251     case INDEX_op_bswap16_i64:
1252         tcg_out_opc_revb_2h(s, a0, a1);
1253         if (a2 & TCG_BSWAP_OS) {
1254             tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0);
1255         } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1256             tcg_out_ext16u(s, a0, a0);
1257         }
1258         break;
1259
1260     case INDEX_op_bswap32_i32:
1261         /* All 32-bit values are computed sign-extended in the register.  */
1262         a2 = TCG_BSWAP_OS;
1263         /* fallthrough */
1264     case INDEX_op_bswap32_i64:
1265         tcg_out_opc_revb_2w(s, a0, a1);
1266         if (a2 & TCG_BSWAP_OS) {
1267             tcg_out_ext32s(s, a0, a0);
1268         } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1269             tcg_out_ext32u(s, a0, a0);
1270         }
1271         break;
1272
1273     case INDEX_op_bswap64_i64:
1274         tcg_out_opc_revb_d(s, a0, a1);
1275         break;
1276
1277     case INDEX_op_clz_i32:
1278         tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true);
1279         break;
1280     case INDEX_op_clz_i64:
1281         tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false);
1282         break;
1283
1284     case INDEX_op_ctz_i32:
1285         tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true);
1286         break;
1287     case INDEX_op_ctz_i64:
1288         tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
1289         break;
1290
1291     case INDEX_op_shl_i32:
1292         if (c2) {
1293             tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f);
1294         } else {
1295             tcg_out_opc_sll_w(s, a0, a1, a2);
1296         }
1297         break;
1298     case INDEX_op_shl_i64:
1299         if (c2) {
1300             tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f);
1301         } else {
1302             tcg_out_opc_sll_d(s, a0, a1, a2);
1303         }
1304         break;
1305
1306     case INDEX_op_shr_i32:
1307         if (c2) {
1308             tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f);
1309         } else {
1310             tcg_out_opc_srl_w(s, a0, a1, a2);
1311         }
1312         break;
1313     case INDEX_op_shr_i64:
1314         if (c2) {
1315             tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f);
1316         } else {
1317             tcg_out_opc_srl_d(s, a0, a1, a2);
1318         }
1319         break;
1320
1321     case INDEX_op_sar_i32:
1322         if (c2) {
1323             tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f);
1324         } else {
1325             tcg_out_opc_sra_w(s, a0, a1, a2);
1326         }
1327         break;
1328     case INDEX_op_sar_i64:
1329         if (c2) {
1330             tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f);
1331         } else {
1332             tcg_out_opc_sra_d(s, a0, a1, a2);
1333         }
1334         break;
1335
1336     case INDEX_op_rotl_i32:
1337         /* transform into equivalent rotr/rotri */
1338         if (c2) {
1339             tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f);
1340         } else {
1341             tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1342             tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0);
1343         }
1344         break;
1345     case INDEX_op_rotl_i64:
1346         /* transform into equivalent rotr/rotri */
1347         if (c2) {
1348             tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f);
1349         } else {
1350             tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1351             tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0);
1352         }
1353         break;
1354
1355     case INDEX_op_rotr_i32:
1356         if (c2) {
1357             tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f);
1358         } else {
1359             tcg_out_opc_rotr_w(s, a0, a1, a2);
1360         }
1361         break;
1362     case INDEX_op_rotr_i64:
1363         if (c2) {
1364             tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f);
1365         } else {
1366             tcg_out_opc_rotr_d(s, a0, a1, a2);
1367         }
1368         break;
1369
1370     case INDEX_op_add_i32:
1371         if (c2) {
1372             tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2);
1373         } else {
1374             tcg_out_opc_add_w(s, a0, a1, a2);
1375         }
1376         break;
1377     case INDEX_op_add_i64:
1378         if (c2) {
1379             tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2);
1380         } else {
1381             tcg_out_opc_add_d(s, a0, a1, a2);
1382         }
1383         break;
1384
1385     case INDEX_op_sub_i32:
1386         if (c2) {
1387             tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2);
1388         } else {
1389             tcg_out_opc_sub_w(s, a0, a1, a2);
1390         }
1391         break;
1392     case INDEX_op_sub_i64:
1393         if (c2) {
1394             tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2);
1395         } else {
1396             tcg_out_opc_sub_d(s, a0, a1, a2);
1397         }
1398         break;
1399
1400     case INDEX_op_mul_i32:
1401         tcg_out_opc_mul_w(s, a0, a1, a2);
1402         break;
1403     case INDEX_op_mul_i64:
1404         tcg_out_opc_mul_d(s, a0, a1, a2);
1405         break;
1406
1407     case INDEX_op_mulsh_i32:
1408         tcg_out_opc_mulh_w(s, a0, a1, a2);
1409         break;
1410     case INDEX_op_mulsh_i64:
1411         tcg_out_opc_mulh_d(s, a0, a1, a2);
1412         break;
1413
1414     case INDEX_op_muluh_i32:
1415         tcg_out_opc_mulh_wu(s, a0, a1, a2);
1416         break;
1417     case INDEX_op_muluh_i64:
1418         tcg_out_opc_mulh_du(s, a0, a1, a2);
1419         break;
1420
1421     case INDEX_op_div_i32:
1422         tcg_out_opc_div_w(s, a0, a1, a2);
1423         break;
1424     case INDEX_op_div_i64:
1425         tcg_out_opc_div_d(s, a0, a1, a2);
1426         break;
1427
1428     case INDEX_op_divu_i32:
1429         tcg_out_opc_div_wu(s, a0, a1, a2);
1430         break;
1431     case INDEX_op_divu_i64:
1432         tcg_out_opc_div_du(s, a0, a1, a2);
1433         break;
1434
1435     case INDEX_op_rem_i32:
1436         tcg_out_opc_mod_w(s, a0, a1, a2);
1437         break;
1438     case INDEX_op_rem_i64:
1439         tcg_out_opc_mod_d(s, a0, a1, a2);
1440         break;
1441
1442     case INDEX_op_remu_i32:
1443         tcg_out_opc_mod_wu(s, a0, a1, a2);
1444         break;
1445     case INDEX_op_remu_i64:
1446         tcg_out_opc_mod_du(s, a0, a1, a2);
1447         break;
1448
1449     case INDEX_op_setcond_i32:
1450     case INDEX_op_setcond_i64:
1451         tcg_out_setcond(s, args[3], a0, a1, a2, c2);
1452         break;
1453
1454     case INDEX_op_movcond_i32:
1455     case INDEX_op_movcond_i64:
1456         tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]);
1457         break;
1458
1459     case INDEX_op_ld8s_i32:
1460     case INDEX_op_ld8s_i64:
1461         tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
1462         break;
1463     case INDEX_op_ld8u_i32:
1464     case INDEX_op_ld8u_i64:
1465         tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2);
1466         break;
1467     case INDEX_op_ld16s_i32:
1468     case INDEX_op_ld16s_i64:
1469         tcg_out_ldst(s, OPC_LD_H, a0, a1, a2);
1470         break;
1471     case INDEX_op_ld16u_i32:
1472     case INDEX_op_ld16u_i64:
1473         tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2);
1474         break;
1475     case INDEX_op_ld_i32:
1476     case INDEX_op_ld32s_i64:
1477         tcg_out_ldst(s, OPC_LD_W, a0, a1, a2);
1478         break;
1479     case INDEX_op_ld32u_i64:
1480         tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2);
1481         break;
1482     case INDEX_op_ld_i64:
1483         tcg_out_ldst(s, OPC_LD_D, a0, a1, a2);
1484         break;
1485
1486     case INDEX_op_st8_i32:
1487     case INDEX_op_st8_i64:
1488         tcg_out_ldst(s, OPC_ST_B, a0, a1, a2);
1489         break;
1490     case INDEX_op_st16_i32:
1491     case INDEX_op_st16_i64:
1492         tcg_out_ldst(s, OPC_ST_H, a0, a1, a2);
1493         break;
1494     case INDEX_op_st_i32:
1495     case INDEX_op_st32_i64:
1496         tcg_out_ldst(s, OPC_ST_W, a0, a1, a2);
1497         break;
1498     case INDEX_op_st_i64:
1499         tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
1500         break;
1501
1502     case INDEX_op_qemu_ld_a32_i32:
1503     case INDEX_op_qemu_ld_a64_i32:
1504         tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1505         break;
1506     case INDEX_op_qemu_ld_a32_i64:
1507     case INDEX_op_qemu_ld_a64_i64:
1508         tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1509         break;
1510     case INDEX_op_qemu_st_a32_i32:
1511     case INDEX_op_qemu_st_a64_i32:
1512         tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1513         break;
1514     case INDEX_op_qemu_st_a32_i64:
1515     case INDEX_op_qemu_st_a64_i64:
1516         tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1517         break;
1518
1519     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
1520     case INDEX_op_mov_i64:
1521     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
1522     case INDEX_op_exit_tb:  /* Always emitted via tcg_out_exit_tb.  */
1523     case INDEX_op_goto_tb:  /* Always emitted via tcg_out_goto_tb.  */
1524     case INDEX_op_ext8s_i32:  /* Always emitted via tcg_reg_alloc_op.  */
1525     case INDEX_op_ext8s_i64:
1526     case INDEX_op_ext8u_i32:
1527     case INDEX_op_ext8u_i64:
1528     case INDEX_op_ext16s_i32:
1529     case INDEX_op_ext16s_i64:
1530     case INDEX_op_ext16u_i32:
1531     case INDEX_op_ext16u_i64:
1532     case INDEX_op_ext32s_i64:
1533     case INDEX_op_ext32u_i64:
1534     case INDEX_op_ext_i32_i64:
1535     case INDEX_op_extu_i32_i64:
1536     case INDEX_op_extrl_i64_i32:
1537     default:
1538         g_assert_not_reached();
1539     }
1540 }
1541
1542 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
1543                             TCGReg rd, TCGReg rs)
1544 {
1545     switch (vece) {
1546     case MO_8:
1547         tcg_out_opc_vreplgr2vr_b(s, rd, rs);
1548         break;
1549     case MO_16:
1550         tcg_out_opc_vreplgr2vr_h(s, rd, rs);
1551         break;
1552     case MO_32:
1553         tcg_out_opc_vreplgr2vr_w(s, rd, rs);
1554         break;
1555     case MO_64:
1556         tcg_out_opc_vreplgr2vr_d(s, rd, rs);
1557         break;
1558     default:
1559         g_assert_not_reached();
1560     }
1561     return true;
1562 }
1563
1564 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
1565                              TCGReg r, TCGReg base, intptr_t offset)
1566 {
1567     /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */
1568     if (offset < -0x800 || offset > 0x7ff || \
1569         (offset & ((1 << vece) - 1)) != 0) {
1570         tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset);
1571         base = TCG_REG_TMP0;
1572         offset = 0;
1573     }
1574     offset >>= vece;
1575
1576     switch (vece) {
1577     case MO_8:
1578         tcg_out_opc_vldrepl_b(s, r, base, offset);
1579         break;
1580     case MO_16:
1581         tcg_out_opc_vldrepl_h(s, r, base, offset);
1582         break;
1583     case MO_32:
1584         tcg_out_opc_vldrepl_w(s, r, base, offset);
1585         break;
1586     case MO_64:
1587         tcg_out_opc_vldrepl_d(s, r, base, offset);
1588         break;
1589     default:
1590         g_assert_not_reached();
1591     }
1592     return true;
1593 }
1594
1595 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1596                              TCGReg rd, int64_t v64)
1597 {
1598     /* Try vldi if imm can fit */
1599     int64_t value = sextract64(v64, 0, 8 << vece);
1600     if (-0x200 <= value && value <= 0x1FF) {
1601         uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF);
1602         tcg_out_opc_vldi(s, rd, imm);
1603         return;
1604     }
1605
1606     /* TODO: vldi patterns when imm 12 is set */
1607
1608     /* Fallback to vreplgr2vr */
1609     tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value);
1610     switch (vece) {
1611     case MO_8:
1612         tcg_out_opc_vreplgr2vr_b(s, rd, TCG_REG_TMP0);
1613         break;
1614     case MO_16:
1615         tcg_out_opc_vreplgr2vr_h(s, rd, TCG_REG_TMP0);
1616         break;
1617     case MO_32:
1618         tcg_out_opc_vreplgr2vr_w(s, rd, TCG_REG_TMP0);
1619         break;
1620     case MO_64:
1621         tcg_out_opc_vreplgr2vr_d(s, rd, TCG_REG_TMP0);
1622         break;
1623     default:
1624         g_assert_not_reached();
1625     }
1626 }
1627
1628 static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0,
1629                                const TCGArg a1, const TCGArg a2,
1630                                bool a2_is_const, bool is_add)
1631 {
1632     static const LoongArchInsn add_vec_insn[4] = {
1633         OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D
1634     };
1635     static const LoongArchInsn add_vec_imm_insn[4] = {
1636         OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU
1637     };
1638     static const LoongArchInsn sub_vec_insn[4] = {
1639         OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D
1640     };
1641     static const LoongArchInsn sub_vec_imm_insn[4] = {
1642         OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU
1643     };
1644
1645     if (a2_is_const) {
1646         int64_t value = sextract64(a2, 0, 8 << vece);
1647         if (!is_add) {
1648             value = -value;
1649         }
1650
1651         /* Try vaddi/vsubi */
1652         if (0 <= value && value <= 0x1f) {
1653             tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \
1654                                              a1, value));
1655             return;
1656         } else if (-0x1f <= value && value < 0) {
1657             tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \
1658                                              a1, -value));
1659             return;
1660         }
1661
1662         /* constraint TCG_CT_CONST_VADD ensures unreachable */
1663         g_assert_not_reached();
1664     }
1665
1666     if (is_add) {
1667         tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2));
1668     } else {
1669         tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2));
1670     }
1671 }
1672
1673 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
1674                            unsigned vecl, unsigned vece,
1675                            const TCGArg args[TCG_MAX_OP_ARGS],
1676                            const int const_args[TCG_MAX_OP_ARGS])
1677 {
1678     TCGType type = vecl + TCG_TYPE_V64;
1679     TCGArg a0, a1, a2;
1680     TCGReg temp = TCG_REG_TMP0;
1681     TCGReg temp_vec = TCG_VEC_TMP0;
1682
1683     static const LoongArchInsn cmp_vec_insn[16][4] = {
1684         [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D},
1685         [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D},
1686         [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU},
1687         [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D},
1688         [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU},
1689     };
1690     static const LoongArchInsn cmp_vec_imm_insn[16][4] = {
1691         [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D},
1692         [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D},
1693         [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU},
1694         [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D},
1695         [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU},
1696     };
1697     LoongArchInsn insn;
1698     static const LoongArchInsn neg_vec_insn[4] = {
1699         OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D
1700     };
1701
1702     a0 = args[0];
1703     a1 = args[1];
1704     a2 = args[2];
1705
1706     /* Currently only supports V128 */
1707     tcg_debug_assert(type == TCG_TYPE_V128);
1708
1709     switch (opc) {
1710     case INDEX_op_st_vec:
1711         /* Try to fit vst imm */
1712         if (-0x800 <= a2 && a2 <= 0x7ff) {
1713             tcg_out_opc_vst(s, a0, a1, a2);
1714         } else {
1715             tcg_out_movi(s, TCG_TYPE_I64, temp, a2);
1716             tcg_out_opc_vstx(s, a0, a1, temp);
1717         }
1718         break;
1719     case INDEX_op_ld_vec:
1720         /* Try to fit vld imm */
1721         if (-0x800 <= a2 && a2 <= 0x7ff) {
1722             tcg_out_opc_vld(s, a0, a1, a2);
1723         } else {
1724             tcg_out_movi(s, TCG_TYPE_I64, temp, a2);
1725             tcg_out_opc_vldx(s, a0, a1, temp);
1726         }
1727         break;
1728     case INDEX_op_and_vec:
1729         tcg_out_opc_vand_v(s, a0, a1, a2);
1730         break;
1731     case INDEX_op_andc_vec:
1732         /*
1733          * vandn vd, vj, vk: vd = vk & ~vj
1734          * andc_vec vd, vj, vk: vd = vj & ~vk
1735          * vk and vk are swapped
1736          */
1737         tcg_out_opc_vandn_v(s, a0, a2, a1);
1738         break;
1739     case INDEX_op_or_vec:
1740         tcg_out_opc_vor_v(s, a0, a1, a2);
1741         break;
1742     case INDEX_op_orc_vec:
1743         tcg_out_opc_vorn_v(s, a0, a1, a2);
1744         break;
1745     case INDEX_op_xor_vec:
1746         tcg_out_opc_vxor_v(s, a0, a1, a2);
1747         break;
1748     case INDEX_op_nor_vec:
1749         tcg_out_opc_vnor_v(s, a0, a1, a2);
1750         break;
1751     case INDEX_op_not_vec:
1752         tcg_out_opc_vnor_v(s, a0, a1, a1);
1753         break;
1754     case INDEX_op_cmp_vec:
1755         TCGCond cond = args[3];
1756         if (const_args[2]) {
1757             /*
1758              * cmp_vec dest, src, value
1759              * Try vseqi/vslei/vslti
1760              */
1761             int64_t value = sextract64(a2, 0, 8 << vece);
1762             if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \
1763                  cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) {
1764                 tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \
1765                                                  a0, a1, value));
1766                 break;
1767             } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) &&
1768                 (0x00 <= value && value <= 0x1f)) {
1769                 tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \
1770                                                  a0, a1, value));
1771                 break;
1772             }
1773
1774             /*
1775              * Fallback to:
1776              * dupi_vec temp, a2
1777              * cmp_vec a0, a1, temp, cond
1778              */
1779             tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
1780             a2 = temp_vec;
1781         }
1782
1783         insn = cmp_vec_insn[cond][vece];
1784         if (insn == 0) {
1785             TCGArg t;
1786             t = a1, a1 = a2, a2 = t;
1787             cond = tcg_swap_cond(cond);
1788             insn = cmp_vec_insn[cond][vece];
1789             tcg_debug_assert(insn != 0);
1790         }
1791         tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
1792         break;
1793     case INDEX_op_add_vec:
1794         tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true);
1795         break;
1796     case INDEX_op_sub_vec:
1797         tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false);
1798         break;
1799     case INDEX_op_neg_vec:
1800         tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1));
1801         break;
1802     case INDEX_op_dupm_vec:
1803         tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
1804         break;
1805     default:
1806         g_assert_not_reached();
1807     }
1808 }
1809
1810 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
1811 {
1812     switch (opc) {
1813     case INDEX_op_ld_vec:
1814     case INDEX_op_st_vec:
1815     case INDEX_op_dup_vec:
1816     case INDEX_op_dupm_vec:
1817     case INDEX_op_cmp_vec:
1818     case INDEX_op_add_vec:
1819     case INDEX_op_sub_vec:
1820     case INDEX_op_and_vec:
1821     case INDEX_op_andc_vec:
1822     case INDEX_op_or_vec:
1823     case INDEX_op_orc_vec:
1824     case INDEX_op_xor_vec:
1825     case INDEX_op_nor_vec:
1826     case INDEX_op_not_vec:
1827     case INDEX_op_neg_vec:
1828         return 1;
1829     default:
1830         return 0;
1831     }
1832 }
1833
1834 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
1835                        TCGArg a0, ...)
1836 {
1837     g_assert_not_reached();
1838 }
1839
1840 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
1841 {
1842     switch (op) {
1843     case INDEX_op_goto_ptr:
1844         return C_O0_I1(r);
1845
1846     case INDEX_op_st8_i32:
1847     case INDEX_op_st8_i64:
1848     case INDEX_op_st16_i32:
1849     case INDEX_op_st16_i64:
1850     case INDEX_op_st32_i64:
1851     case INDEX_op_st_i32:
1852     case INDEX_op_st_i64:
1853     case INDEX_op_qemu_st_a32_i32:
1854     case INDEX_op_qemu_st_a64_i32:
1855     case INDEX_op_qemu_st_a32_i64:
1856     case INDEX_op_qemu_st_a64_i64:
1857         return C_O0_I2(rZ, r);
1858
1859     case INDEX_op_brcond_i32:
1860     case INDEX_op_brcond_i64:
1861         return C_O0_I2(rZ, rZ);
1862
1863     case INDEX_op_ext8s_i32:
1864     case INDEX_op_ext8s_i64:
1865     case INDEX_op_ext8u_i32:
1866     case INDEX_op_ext8u_i64:
1867     case INDEX_op_ext16s_i32:
1868     case INDEX_op_ext16s_i64:
1869     case INDEX_op_ext16u_i32:
1870     case INDEX_op_ext16u_i64:
1871     case INDEX_op_ext32s_i64:
1872     case INDEX_op_ext32u_i64:
1873     case INDEX_op_extu_i32_i64:
1874     case INDEX_op_extrl_i64_i32:
1875     case INDEX_op_extrh_i64_i32:
1876     case INDEX_op_ext_i32_i64:
1877     case INDEX_op_not_i32:
1878     case INDEX_op_not_i64:
1879     case INDEX_op_extract_i32:
1880     case INDEX_op_extract_i64:
1881     case INDEX_op_bswap16_i32:
1882     case INDEX_op_bswap16_i64:
1883     case INDEX_op_bswap32_i32:
1884     case INDEX_op_bswap32_i64:
1885     case INDEX_op_bswap64_i64:
1886     case INDEX_op_ld8s_i32:
1887     case INDEX_op_ld8s_i64:
1888     case INDEX_op_ld8u_i32:
1889     case INDEX_op_ld8u_i64:
1890     case INDEX_op_ld16s_i32:
1891     case INDEX_op_ld16s_i64:
1892     case INDEX_op_ld16u_i32:
1893     case INDEX_op_ld16u_i64:
1894     case INDEX_op_ld32s_i64:
1895     case INDEX_op_ld32u_i64:
1896     case INDEX_op_ld_i32:
1897     case INDEX_op_ld_i64:
1898     case INDEX_op_qemu_ld_a32_i32:
1899     case INDEX_op_qemu_ld_a64_i32:
1900     case INDEX_op_qemu_ld_a32_i64:
1901     case INDEX_op_qemu_ld_a64_i64:
1902         return C_O1_I1(r, r);
1903
1904     case INDEX_op_andc_i32:
1905     case INDEX_op_andc_i64:
1906     case INDEX_op_orc_i32:
1907     case INDEX_op_orc_i64:
1908         /*
1909          * LoongArch insns for these ops don't have reg-imm forms, but we
1910          * can express using andi/ori if ~constant satisfies
1911          * TCG_CT_CONST_U12.
1912          */
1913         return C_O1_I2(r, r, rC);
1914
1915     case INDEX_op_shl_i32:
1916     case INDEX_op_shl_i64:
1917     case INDEX_op_shr_i32:
1918     case INDEX_op_shr_i64:
1919     case INDEX_op_sar_i32:
1920     case INDEX_op_sar_i64:
1921     case INDEX_op_rotl_i32:
1922     case INDEX_op_rotl_i64:
1923     case INDEX_op_rotr_i32:
1924     case INDEX_op_rotr_i64:
1925         return C_O1_I2(r, r, ri);
1926
1927     case INDEX_op_add_i32:
1928         return C_O1_I2(r, r, ri);
1929     case INDEX_op_add_i64:
1930         return C_O1_I2(r, r, rJ);
1931
1932     case INDEX_op_and_i32:
1933     case INDEX_op_and_i64:
1934     case INDEX_op_nor_i32:
1935     case INDEX_op_nor_i64:
1936     case INDEX_op_or_i32:
1937     case INDEX_op_or_i64:
1938     case INDEX_op_xor_i32:
1939     case INDEX_op_xor_i64:
1940         /* LoongArch reg-imm bitops have their imms ZERO-extended */
1941         return C_O1_I2(r, r, rU);
1942
1943     case INDEX_op_clz_i32:
1944     case INDEX_op_clz_i64:
1945     case INDEX_op_ctz_i32:
1946     case INDEX_op_ctz_i64:
1947         return C_O1_I2(r, r, rW);
1948
1949     case INDEX_op_deposit_i32:
1950     case INDEX_op_deposit_i64:
1951         /* Must deposit into the same register as input */
1952         return C_O1_I2(r, 0, rZ);
1953
1954     case INDEX_op_sub_i32:
1955     case INDEX_op_setcond_i32:
1956         return C_O1_I2(r, rZ, ri);
1957     case INDEX_op_sub_i64:
1958     case INDEX_op_setcond_i64:
1959         return C_O1_I2(r, rZ, rJ);
1960
1961     case INDEX_op_mul_i32:
1962     case INDEX_op_mul_i64:
1963     case INDEX_op_mulsh_i32:
1964     case INDEX_op_mulsh_i64:
1965     case INDEX_op_muluh_i32:
1966     case INDEX_op_muluh_i64:
1967     case INDEX_op_div_i32:
1968     case INDEX_op_div_i64:
1969     case INDEX_op_divu_i32:
1970     case INDEX_op_divu_i64:
1971     case INDEX_op_rem_i32:
1972     case INDEX_op_rem_i64:
1973     case INDEX_op_remu_i32:
1974     case INDEX_op_remu_i64:
1975         return C_O1_I2(r, rZ, rZ);
1976
1977     case INDEX_op_movcond_i32:
1978     case INDEX_op_movcond_i64:
1979         return C_O1_I4(r, rZ, rJ, rZ, rZ);
1980
1981     case INDEX_op_ld_vec:
1982     case INDEX_op_dupm_vec:
1983     case INDEX_op_dup_vec:
1984         return C_O1_I1(w, r);
1985
1986     case INDEX_op_st_vec:
1987         return C_O0_I2(w, r);
1988
1989     case INDEX_op_cmp_vec:
1990         return C_O1_I2(w, w, wM);
1991
1992     case INDEX_op_add_vec:
1993     case INDEX_op_sub_vec:
1994         return C_O1_I2(w, w, wA);
1995
1996     case INDEX_op_and_vec:
1997     case INDEX_op_andc_vec:
1998     case INDEX_op_or_vec:
1999     case INDEX_op_orc_vec:
2000     case INDEX_op_xor_vec:
2001     case INDEX_op_nor_vec:
2002         return C_O1_I2(w, w, w);
2003
2004     case INDEX_op_not_vec:
2005     case INDEX_op_neg_vec:
2006         return C_O1_I1(w, w);
2007
2008     default:
2009         g_assert_not_reached();
2010     }
2011 }
2012
2013 static const int tcg_target_callee_save_regs[] = {
2014     TCG_REG_S0,     /* used for the global env (TCG_AREG0) */
2015     TCG_REG_S1,
2016     TCG_REG_S2,
2017     TCG_REG_S3,
2018     TCG_REG_S4,
2019     TCG_REG_S5,
2020     TCG_REG_S6,
2021     TCG_REG_S7,
2022     TCG_REG_S8,
2023     TCG_REG_S9,
2024     TCG_REG_RA,     /* should be last for ABI compliance */
2025 };
2026
2027 /* Stack frame parameters.  */
2028 #define REG_SIZE   (TCG_TARGET_REG_BITS / 8)
2029 #define SAVE_SIZE  ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2030 #define TEMP_SIZE  (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2031 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2032                      + TCG_TARGET_STACK_ALIGN - 1) \
2033                     & -TCG_TARGET_STACK_ALIGN)
2034 #define SAVE_OFS   (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2035
2036 /* We're expecting to be able to use an immediate for frame allocation.  */
2037 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
2038
2039 /* Generate global QEMU prologue and epilogue code */
2040 static void tcg_target_qemu_prologue(TCGContext *s)
2041 {
2042     int i;
2043
2044     tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2045
2046     /* TB prologue */
2047     tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2048     for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2049         tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2050                    TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2051     }
2052
2053 #if !defined(CONFIG_SOFTMMU)
2054     if (USE_GUEST_BASE) {
2055         tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2056         tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2057     }
2058 #endif
2059
2060     /* Call generated code */
2061     tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2062     tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
2063
2064     /* Return path for goto_ptr. Set return value to 0 */
2065     tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2066     tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
2067
2068     /* TB epilogue */
2069     tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2070     for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2071         tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2072                    TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2073     }
2074
2075     tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2076     tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0);
2077 }
2078
2079 static void tcg_target_init(TCGContext *s)
2080 {
2081     unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2082
2083     /* Server and desktop class cpus have UAL; embedded cpus do not. */
2084     if (!(hwcap & HWCAP_LOONGARCH_UAL)) {
2085         error_report("TCG: unaligned access support required; exiting");
2086         exit(EXIT_FAILURE);
2087     }
2088
2089     if (hwcap & HWCAP_LOONGARCH_LSX) {
2090         use_lsx_instructions = 1;
2091     }
2092
2093     tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2094     tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
2095
2096     tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
2097     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
2098     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
2099     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
2100     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
2101     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
2102     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
2103     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
2104     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
2105     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
2106     tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
2107
2108     if (use_lsx_instructions) {
2109         tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2110         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
2111         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
2112         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26);
2113         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27);
2114         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28);
2115         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29);
2116         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30);
2117         tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31);
2118     }
2119
2120     s->reserved_regs = 0;
2121     tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
2122     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
2123     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
2124     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
2125     tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
2126     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
2127     tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
2128     tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
2129 }
2130
2131 typedef struct {
2132     DebugFrameHeader h;
2133     uint8_t fde_def_cfa[4];
2134     uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2135 } DebugFrame;
2136
2137 #define ELF_HOST_MACHINE EM_LOONGARCH
2138
2139 static const DebugFrame debug_frame = {
2140     .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2141     .h.cie.id = -1,
2142     .h.cie.version = 1,
2143     .h.cie.code_align = 1,
2144     .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2145     .h.cie.return_column = TCG_REG_RA,
2146
2147     /* Total FDE size does not include the "len" member.  */
2148     .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2149
2150     .fde_def_cfa = {
2151         12, TCG_REG_SP,                 /* DW_CFA_def_cfa sp, ...  */
2152         (FRAME_SIZE & 0x7f) | 0x80,     /* ... uleb128 FRAME_SIZE */
2153         (FRAME_SIZE >> 7)
2154     },
2155     .fde_reg_ofs = {
2156         0x80 + 23, 11,                  /* DW_CFA_offset, s0, -88 */
2157         0x80 + 24, 10,                  /* DW_CFA_offset, s1, -80 */
2158         0x80 + 25, 9,                   /* DW_CFA_offset, s2, -72 */
2159         0x80 + 26, 8,                   /* DW_CFA_offset, s3, -64 */
2160         0x80 + 27, 7,                   /* DW_CFA_offset, s4, -56 */
2161         0x80 + 28, 6,                   /* DW_CFA_offset, s5, -48 */
2162         0x80 + 29, 5,                   /* DW_CFA_offset, s6, -40 */
2163         0x80 + 30, 4,                   /* DW_CFA_offset, s7, -32 */
2164         0x80 + 31, 3,                   /* DW_CFA_offset, s8, -24 */
2165         0x80 + 22, 2,                   /* DW_CFA_offset, s9, -16 */
2166         0x80 + 1 , 1,                   /* DW_CFA_offset, ra, -8 */
2167     }
2168 };
2169
2170 void tcg_register_jit(const void *buf, size_t buf_size)
2171 {
2172     tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2173 }