2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
6 * Based on tcg/riscv/tcg-target.c.inc
8 * Copyright (c) 2018 SiFive, Inc
9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
11 * Copyright (c) 2008 Fabrice Bellard
13 * Permission is hereby granted, free of charge, to any person obtaining a copy
14 * of this software and associated documentation files (the "Software"), to deal
15 * in the Software without restriction, including without limitation the rights
16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
17 * copies of the Software, and to permit persons to whom the Software is
18 * furnished to do so, subject to the following conditions:
20 * The above copyright notice and this permission notice shall be included in
21 * all copies or substantial portions of the Software.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "../tcg-ldst.c.inc"
34 #ifdef CONFIG_DEBUG_TCG
35 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r21", /* reserved in the LP64* ABI, hence no ABI name */
71 static const int tcg_target_reg_alloc_order[] = {
72 /* Registers preserved across calls */
73 /* TCG_REG_S0 reserved for TCG_AREG0 */
84 /* Registers (potentially) clobbered across calls */
95 /* Argument registers, opposite order of allocation. */
106 static const int tcg_target_call_iarg_regs[] = {
117 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
119 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
120 tcg_debug_assert(slot >= 0 && slot <= 1);
121 return TCG_REG_A0 + slot;
124 #ifndef CONFIG_SOFTMMU
125 #define USE_GUEST_BASE (guest_base != 0)
126 #define TCG_GUEST_BASE_REG TCG_REG_S1
129 #define TCG_CT_CONST_ZERO 0x100
130 #define TCG_CT_CONST_S12 0x200
131 #define TCG_CT_CONST_S32 0x400
132 #define TCG_CT_CONST_U12 0x800
133 #define TCG_CT_CONST_C12 0x1000
134 #define TCG_CT_CONST_WSZ 0x2000
136 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
138 * For softmmu, we need to avoid conflicts with the first 5
139 * argument registers to call the helper. Some of these are
140 * also used for the tlb lookup.
142 #ifdef CONFIG_SOFTMMU
143 #define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
145 #define SOFTMMU_RESERVE_REGS 0
149 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
151 return sextract64(val, pos, len);
154 /* test if a constant matches the constraint */
155 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
157 if (ct & TCG_CT_CONST) {
160 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
163 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
166 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
169 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
172 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
175 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
186 * Relocation records defined in LoongArch ELF psABI v1.00 is way too
187 * complicated; a whopping stack machine is needed to stuff the fields, at
188 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are
191 * Hence, define our own simpler relocation types. Numbers are chosen as to
192 * not collide with potential future additions to the true ELF relocation
196 /* Field Sk16, shifted right by 2; suitable for conditional jumps */
197 #define R_LOONGARCH_BR_SK16 256
198 /* Field Sd10k16, shifted right by 2; suitable for B and BL */
199 #define R_LOONGARCH_BR_SD10K16 257
201 static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
203 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
204 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
206 tcg_debug_assert((offset & 3) == 0);
208 if (offset == sextreg(offset, 0, 16)) {
209 *src_rw = deposit64(*src_rw, 10, 16, offset);
216 static bool reloc_br_sd10k16(tcg_insn_unit *src_rw,
217 const tcg_insn_unit *target)
219 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
220 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
222 tcg_debug_assert((offset & 3) == 0);
224 if (offset == sextreg(offset, 0, 26)) {
225 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */
226 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */
233 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
234 intptr_t value, intptr_t addend)
236 tcg_debug_assert(addend == 0);
238 case R_LOONGARCH_BR_SK16:
239 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value);
240 case R_LOONGARCH_BR_SD10K16:
241 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value);
243 g_assert_not_reached();
247 #include "tcg-insn-defs.c.inc"
253 static void tcg_out_mb(TCGContext *s, TCGArg a0)
255 /* Baseline LoongArch only has the full barrier, unfortunately. */
256 tcg_out_opc_dbar(s, 0);
259 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
268 * Conventional register-register move used in LoongArch is
269 * `or dst, src, zero`.
271 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
274 g_assert_not_reached();
279 /* Loads a 32-bit immediate into rd, sign-extended. */
280 static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val)
282 tcg_target_long lo = sextreg(val, 0, 12);
283 tcg_target_long hi12 = sextreg(val, 12, 20);
285 /* Single-instruction cases. */
287 /* val fits in uimm12: ori rd, zero, val */
288 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
291 if (hi12 == sextreg(lo, 12, 20)) {
292 /* val fits in simm12: addi.w rd, zero, val */
293 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
297 /* High bits must be set; load with lu12i.w + optional ori. */
298 tcg_out_opc_lu12i_w(s, rd, hi12);
300 tcg_out_opc_ori(s, rd, rd, lo & 0xfff);
304 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
308 * LoongArch conventionally loads 64-bit immediates in at most 4 steps,
309 * with dedicated instructions for filling the respective bitfields
313 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
314 * +-----------------------+---------------------------------------+...
316 * +-----------------------+---------------------------------------+...
318 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
319 * ...+-------------------------------------+-------------------------+
321 * ...+-------------------------------------+-------------------------+
323 * Check if val belong to one of the several fast cases, before falling
324 * back to the slow path.
328 tcg_target_long val_lo, val_hi, pc_hi, offset_hi;
329 tcg_target_long hi12, hi32, hi52;
331 /* Value fits in signed i32. */
332 if (type == TCG_TYPE_I32 || val == (int32_t)val) {
333 tcg_out_movi_i32(s, rd, val);
337 /* PC-relative cases. */
338 pc_offset = tcg_pcrel_diff(s, (void *)val);
339 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
340 /* Single pcaddu2i. */
341 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
345 if (pc_offset == (int32_t)pc_offset) {
346 /* Offset within 32 bits; load with pcalau12i + ori. */
347 val_lo = sextreg(val, 0, 12);
349 pc_hi = (val - pc_offset) >> 12;
350 offset_hi = val_hi - pc_hi;
352 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20));
353 tcg_out_opc_pcalau12i(s, rd, offset_hi);
355 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff);
360 hi12 = sextreg(val, 12, 20);
361 hi32 = sextreg(val, 32, 20);
362 hi52 = sextreg(val, 52, 12);
364 /* Single cu52i.d case. */
365 if ((hi52 != 0) && (ctz64(val) >= 52)) {
366 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52);
370 /* Slow path. Initialize the low 32 bits, then concat high bits. */
371 tcg_out_movi_i32(s, rd, val);
373 /* Load hi32 and hi52 explicitly when they are unexpected values. */
374 if (hi32 != sextreg(hi12, 20, 20)) {
375 tcg_out_opc_cu32i_d(s, rd, hi32);
378 if (hi52 != sextreg(hi32, 20, 12)) {
379 tcg_out_opc_cu52i_d(s, rd, rd, hi52);
383 static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd,
384 TCGReg rs, tcg_target_long imm)
386 tcg_target_long lo12 = sextreg(imm, 0, 12);
387 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16);
390 * Note that there's a hole in between hi16 and lo12:
393 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
394 * ...+-------------------------------+-------+-----------------------+
396 * ...+-------------------------------+-------+-----------------------+
398 * For bits within that hole, it's more efficient to use LU12I and ADD.
400 if (imm == (hi16 << 16) + lo12) {
402 tcg_out_opc_addu16i_d(s, rd, rs, hi16);
405 if (type == TCG_TYPE_I32) {
406 tcg_out_opc_addi_w(s, rd, rs, lo12);
408 tcg_out_opc_addi_d(s, rd, rs, lo12);
410 tcg_out_mov(s, type, rd, rs);
413 tcg_out_movi(s, type, TCG_REG_TMP0, imm);
414 if (type == TCG_TYPE_I32) {
415 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0);
417 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0);
422 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
427 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
430 /* This function is only used for passing structs by reference. */
431 g_assert_not_reached();
434 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
436 tcg_out_opc_andi(s, ret, arg, 0xff);
439 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
441 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15);
444 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
446 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31);
449 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
451 tcg_out_opc_sext_b(s, ret, arg);
454 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
456 tcg_out_opc_sext_h(s, ret, arg);
459 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
461 tcg_out_opc_addi_w(s, ret, arg, 0);
464 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
467 tcg_out_ext32s(s, ret, arg);
471 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
473 tcg_out_ext32u(s, ret, arg);
476 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
478 tcg_out_ext32s(s, ret, arg);
481 static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
482 TCGReg a0, TCGReg a1, TCGReg a2,
483 bool c2, bool is_32bit)
487 * Fast path: semantics already satisfied due to constraint and
488 * insn behavior, single instruction is enough.
490 tcg_debug_assert(a2 == (is_32bit ? 32 : 64));
491 /* all clz/ctz insns belong to DJ-format */
492 tcg_out32(s, encode_dj_insn(opc, a0, a1));
496 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1));
497 /* a0 = a1 ? REG_TMP0 : a2 */
498 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1);
499 tcg_out_opc_masknez(s, a0, a2, a1);
500 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
503 #define SETCOND_INV TCG_TARGET_NB_REGS
504 #define SETCOND_NEZ (SETCOND_INV << 1)
505 #define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ)
507 static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
508 TCGReg arg1, tcg_target_long arg2, bool c2)
513 case TCG_COND_EQ: /* -> NE */
514 case TCG_COND_GE: /* -> LT */
515 case TCG_COND_GEU: /* -> LTU */
516 case TCG_COND_GT: /* -> LE */
517 case TCG_COND_GTU: /* -> LEU */
518 cond = tcg_invert_cond(cond);
519 flags ^= SETCOND_INV;
529 * If we have a constant input, the most efficient way to implement
530 * LE is by adding 1 and using LT. Watch out for wrap around for LEU.
531 * We don't need to care for this for LE because the constant input
532 * is still constrained to int32_t, and INT32_MAX+1 is representable
533 * in the 64-bit temporary register.
536 if (cond == TCG_COND_LEU) {
537 /* unsigned <= -1 is true */
539 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV));
551 cond = tcg_swap_cond(cond); /* LE -> GE */
552 cond = tcg_invert_cond(cond); /* GE -> LT */
553 flags ^= SETCOND_INV;
562 flags |= SETCOND_NEZ;
564 tcg_out_opc_xor(s, ret, arg1, arg2);
565 } else if (arg2 == 0) {
567 } else if (arg2 >= 0 && arg2 <= 0xfff) {
568 tcg_out_opc_xori(s, ret, arg1, arg2);
570 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2);
577 if (arg2 >= -0x800 && arg2 <= 0x7ff) {
578 if (cond == TCG_COND_LT) {
579 tcg_out_opc_slti(s, ret, arg1, arg2);
581 tcg_out_opc_sltui(s, ret, arg1, arg2);
585 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2);
588 if (cond == TCG_COND_LT) {
589 tcg_out_opc_slt(s, ret, arg1, arg2);
591 tcg_out_opc_sltu(s, ret, arg1, arg2);
596 g_assert_not_reached();
603 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
604 TCGReg arg1, tcg_target_long arg2, bool c2)
606 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
608 if (tmpflags != ret) {
609 TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
611 switch (tmpflags & SETCOND_FLAGS) {
613 /* Intermediate result is boolean: simply invert. */
614 tcg_out_opc_xori(s, ret, tmp, 1);
617 /* Intermediate result is zero/non-zero: test != 0. */
618 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp);
620 case SETCOND_NEZ | SETCOND_INV:
621 /* Intermediate result is zero/non-zero: test == 0. */
622 tcg_out_opc_sltui(s, ret, tmp, 1);
625 g_assert_not_reached();
630 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
631 TCGReg c1, tcg_target_long c2, bool const2,
632 TCGReg v1, TCGReg v2)
634 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2);
637 /* Standardize the test below to t != 0. */
638 if (tmpflags & SETCOND_INV) {
639 t = v1, v1 = v2, v2 = t;
642 t = tmpflags & ~SETCOND_FLAGS;
643 if (v1 == TCG_REG_ZERO) {
644 tcg_out_opc_masknez(s, ret, v2, t);
645 } else if (v2 == TCG_REG_ZERO) {
646 tcg_out_opc_maskeqz(s, ret, v1, t);
648 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */
649 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */
650 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2);
658 static const struct {
661 } tcg_brcond_to_loongarch[] = {
662 [TCG_COND_EQ] = { OPC_BEQ, false },
663 [TCG_COND_NE] = { OPC_BNE, false },
664 [TCG_COND_LT] = { OPC_BGT, true },
665 [TCG_COND_GE] = { OPC_BLE, true },
666 [TCG_COND_LE] = { OPC_BLE, false },
667 [TCG_COND_GT] = { OPC_BGT, false },
668 [TCG_COND_LTU] = { OPC_BGTU, true },
669 [TCG_COND_GEU] = { OPC_BLEU, true },
670 [TCG_COND_LEU] = { OPC_BLEU, false },
671 [TCG_COND_GTU] = { OPC_BGTU, false }
674 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
675 TCGReg arg2, TCGLabel *l)
677 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op;
679 tcg_debug_assert(op != 0);
681 if (tcg_brcond_to_loongarch[cond].swap) {
687 /* all conditional branch insns belong to DJSk16-format */
688 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0);
689 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0));
692 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
694 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
695 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
697 tcg_debug_assert((offset & 3) == 0);
698 if (offset == sextreg(offset, 0, 28)) {
699 /* short jump: +/- 256MiB */
701 tcg_out_opc_b(s, offset >> 2);
703 tcg_out_opc_bl(s, offset >> 2);
705 } else if (offset == sextreg(offset, 0, 38)) {
706 /* long jump: +/- 256GiB */
707 tcg_target_long lo = sextreg(offset, 0, 18);
708 tcg_target_long hi = offset - lo;
709 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18);
710 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
712 /* far jump: 64-bit */
713 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18);
714 tcg_target_long hi = (tcg_target_long)arg - lo;
715 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi);
716 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
720 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
721 const TCGHelperInfo *info)
723 tcg_out_call_int(s, arg, false);
730 static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data,
731 TCGReg addr, intptr_t offset)
733 intptr_t imm12 = sextreg(offset, 0, 12);
735 if (offset != imm12) {
736 intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
738 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
739 imm12 = sextreg(diff, 0, 12);
740 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12);
742 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
743 if (addr != TCG_REG_ZERO) {
744 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr);
762 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12));
765 g_assert_not_reached();
769 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
770 TCGReg arg1, intptr_t arg2)
772 bool is_32bit = type == TCG_TYPE_I32;
773 tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2);
776 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
777 TCGReg arg1, intptr_t arg2)
779 bool is_32bit = type == TCG_TYPE_I32;
780 tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2);
783 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
784 TCGReg base, intptr_t ofs)
787 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
794 * Load/store helpers for SoftMMU, and qemu_ld/st implementations
797 #if defined(CONFIG_SOFTMMU)
799 * helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
800 * MemOpIdx oi, uintptr_t ra)
802 static void * const qemu_ld_helpers[4] = {
803 [MO_8] = helper_ret_ldub_mmu,
804 [MO_16] = helper_le_lduw_mmu,
805 [MO_32] = helper_le_ldul_mmu,
806 [MO_64] = helper_le_ldq_mmu,
810 * helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
811 * uintxx_t val, MemOpIdx oi,
814 static void * const qemu_st_helpers[4] = {
815 [MO_8] = helper_ret_stb_mmu,
816 [MO_16] = helper_le_stw_mmu,
817 [MO_32] = helper_le_stl_mmu,
818 [MO_64] = helper_le_stq_mmu,
821 /* We expect to use a 12-bit negative offset from ENV. */
822 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
823 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
825 static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
828 return reloc_br_sd10k16(s->code_ptr - 1, target);
832 * Emits common code for TLB addend lookup, that eventually loads the
833 * addend in TCG_REG_TMP2.
835 static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi,
836 tcg_insn_unit **label_ptr, bool is_load)
838 MemOp opc = get_memop(oi);
839 unsigned s_bits = opc & MO_SIZE;
840 unsigned a_bits = get_alignment_bits(opc);
841 tcg_target_long compare_mask;
842 int mem_index = get_mmuidx(oi);
843 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
844 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
845 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
847 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
848 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
850 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl,
851 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
852 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
853 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
855 /* Load the tlb comparator and the addend. */
856 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
857 is_load ? offsetof(CPUTLBEntry, addr_read)
858 : offsetof(CPUTLBEntry, addr_write));
859 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
860 offsetof(CPUTLBEntry, addend));
862 /* We don't support unaligned accesses. */
863 if (a_bits < s_bits) {
866 /* Clear the non-page, non-alignment bits from the address. */
867 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
868 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
869 tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
871 /* Compare masked address with the TLB entry. */
872 label_ptr[0] = s->code_ptr;
873 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
875 /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */
878 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
880 TCGReg datalo, TCGReg addrlo,
881 void *raddr, tcg_insn_unit **label_ptr)
883 TCGLabelQemuLdst *label = new_ldst_label(s);
885 label->is_ld = is_ld;
888 label->datalo_reg = datalo;
889 label->datahi_reg = 0; /* unused */
890 label->addrlo_reg = addrlo;
891 label->addrhi_reg = 0; /* unused */
892 label->raddr = tcg_splitwx_to_rx(raddr);
893 label->label_ptr[0] = label_ptr[0];
896 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
899 MemOp opc = get_memop(oi);
900 MemOp size = opc & MO_SIZE;
902 /* resolve label address */
903 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
907 /* call load helper */
908 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
909 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg);
910 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi);
911 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr);
913 tcg_out_call_int(s, qemu_ld_helpers[size], false);
915 tcg_out_movext(s, l->type, l->datalo_reg,
916 TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0);
917 return tcg_out_goto(s, l->raddr);
920 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
923 MemOp opc = get_memop(oi);
924 MemOp size = opc & MO_SIZE;
926 /* resolve label address */
927 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
931 /* call store helper */
932 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
933 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg);
934 tcg_out_movext(s, size == MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG_REG_A2,
935 l->type, size, l->datalo_reg);
936 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi);
937 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr);
939 tcg_out_call_int(s, qemu_st_helpers[size], false);
941 return tcg_out_goto(s, l->raddr);
946 * Alignment helpers for user-mode emulation
949 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
952 TCGLabelQemuLdst *l = new_ldst_label(s);
955 l->addrlo_reg = addr_reg;
958 * Without micro-architecture details, we don't know which of bstrpick or
959 * andi is faster, so use bstrpick as it's not constrained by imm field
960 * width. (Not to say alignments >= 2^12 are going to happen any time
963 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
965 l->label_ptr[0] = s->code_ptr;
966 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
968 l->raddr = tcg_splitwx_to_rx(s->code_ptr);
971 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
973 /* resolve label address */
974 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
978 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
979 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
981 /* tail call, with the return address back inline. */
982 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr);
983 tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld
984 : helper_unaligned_st), true);
988 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
990 return tcg_out_fail_alignment(s, l);
993 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
995 return tcg_out_fail_alignment(s, l);
998 #endif /* CONFIG_SOFTMMU */
1001 * `ext32u` the address register into the temp register given,
1002 * if target is 32-bit, no-op otherwise.
1004 * Returns the address register ready for use with TLB addend.
1006 static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s,
1007 TCGReg addr, TCGReg tmp)
1009 if (TARGET_LONG_BITS == 32) {
1010 tcg_out_ext32u(s, tmp, addr);
1016 static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj,
1017 TCGReg rk, MemOp opc, TCGType type)
1019 /* Byte swapping is left to middle-end expansion. */
1020 tcg_debug_assert((opc & MO_BSWAP) == 0);
1022 switch (opc & MO_SSIZE) {
1024 tcg_out_opc_ldx_bu(s, rd, rj, rk);
1027 tcg_out_opc_ldx_b(s, rd, rj, rk);
1030 tcg_out_opc_ldx_hu(s, rd, rj, rk);
1033 tcg_out_opc_ldx_h(s, rd, rj, rk);
1036 if (type == TCG_TYPE_I64) {
1037 tcg_out_opc_ldx_wu(s, rd, rj, rk);
1042 tcg_out_opc_ldx_w(s, rd, rj, rk);
1045 tcg_out_opc_ldx_d(s, rd, rj, rk);
1048 g_assert_not_reached();
1052 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1053 MemOpIdx oi, TCGType data_type)
1055 MemOp opc = get_memop(oi);
1058 #ifdef CONFIG_SOFTMMU
1059 tcg_insn_unit *label_ptr[1];
1061 tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
1062 index = TCG_REG_TMP2;
1064 unsigned a_bits = get_alignment_bits(opc);
1066 tcg_out_test_alignment(s, true, addr_reg, a_bits);
1068 index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
1071 base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
1072 tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type);
1074 #ifdef CONFIG_SOFTMMU
1075 add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
1076 s->code_ptr, label_ptr);
1080 static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data,
1081 TCGReg rj, TCGReg rk, MemOp opc)
1083 /* Byte swapping is left to middle-end expansion. */
1084 tcg_debug_assert((opc & MO_BSWAP) == 0);
1086 switch (opc & MO_SIZE) {
1088 tcg_out_opc_stx_b(s, data, rj, rk);
1091 tcg_out_opc_stx_h(s, data, rj, rk);
1094 tcg_out_opc_stx_w(s, data, rj, rk);
1097 tcg_out_opc_stx_d(s, data, rj, rk);
1100 g_assert_not_reached();
1104 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1105 MemOpIdx oi, TCGType data_type)
1107 MemOp opc = get_memop(oi);
1110 #ifdef CONFIG_SOFTMMU
1111 tcg_insn_unit *label_ptr[1];
1113 tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
1114 index = TCG_REG_TMP2;
1116 unsigned a_bits = get_alignment_bits(opc);
1118 tcg_out_test_alignment(s, false, addr_reg, a_bits);
1120 index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
1123 base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
1124 tcg_out_qemu_st_indexed(s, data_reg, base, index, opc);
1126 #ifdef CONFIG_SOFTMMU
1127 add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
1128 s->code_ptr, label_ptr);
1136 static const tcg_insn_unit *tb_ret_addr;
1138 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1140 /* Reuse the zeroing that exists for goto_ptr. */
1142 tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1144 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1145 tcg_out_call_int(s, tb_ret_addr, true);
1149 static void tcg_out_goto_tb(TCGContext *s, int which)
1152 * Direct branch, or load indirect address, to be patched
1153 * by tb_target_set_jmp_target. Check indirect load offset
1154 * in range early, regardless of direct branch distance,
1155 * via assert within tcg_out_opc_pcaddu2i.
1157 uintptr_t i_addr = get_jmp_target_addr(s, which);
1158 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr);
1160 set_jmp_insn_offset(s, which);
1161 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2);
1163 /* Finish the load and indirect branch. */
1164 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0);
1165 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1166 set_jmp_reset_offset(s, which);
1169 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1170 uintptr_t jmp_rx, uintptr_t jmp_rw)
1172 uintptr_t d_addr = tb->jmp_target_addr[n];
1173 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2;
1176 /* Either directly branch, or load slot address for indirect branch. */
1177 if (d_disp == sextreg(d_disp, 0, 26)) {
1178 insn = encode_sd10k16_insn(OPC_B, d_disp);
1180 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n];
1181 intptr_t i_disp = i_addr - jmp_rx;
1182 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2);
1185 qatomic_set((tcg_insn_unit *)jmp_rw, insn);
1186 flush_idcache_range(jmp_rx, jmp_rw, 4);
1189 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1190 const TCGArg args[TCG_MAX_OP_ARGS],
1191 const int const_args[TCG_MAX_OP_ARGS])
1193 TCGArg a0 = args[0];
1194 TCGArg a1 = args[1];
1195 TCGArg a2 = args[2];
1196 int c2 = const_args[2];
1203 case INDEX_op_goto_ptr:
1204 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
1208 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0),
1210 tcg_out_opc_b(s, 0);
1213 case INDEX_op_brcond_i32:
1214 case INDEX_op_brcond_i64:
1215 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1218 case INDEX_op_extrh_i64_i32:
1219 tcg_out_opc_srai_d(s, a0, a1, 32);
1222 case INDEX_op_not_i32:
1223 case INDEX_op_not_i64:
1224 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
1227 case INDEX_op_nor_i32:
1228 case INDEX_op_nor_i64:
1230 tcg_out_opc_ori(s, a0, a1, a2);
1231 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
1233 tcg_out_opc_nor(s, a0, a1, a2);
1237 case INDEX_op_andc_i32:
1238 case INDEX_op_andc_i64:
1240 /* guaranteed to fit due to constraint */
1241 tcg_out_opc_andi(s, a0, a1, ~a2);
1243 tcg_out_opc_andn(s, a0, a1, a2);
1247 case INDEX_op_orc_i32:
1248 case INDEX_op_orc_i64:
1250 /* guaranteed to fit due to constraint */
1251 tcg_out_opc_ori(s, a0, a1, ~a2);
1253 tcg_out_opc_orn(s, a0, a1, a2);
1257 case INDEX_op_and_i32:
1258 case INDEX_op_and_i64:
1260 tcg_out_opc_andi(s, a0, a1, a2);
1262 tcg_out_opc_and(s, a0, a1, a2);
1266 case INDEX_op_or_i32:
1267 case INDEX_op_or_i64:
1269 tcg_out_opc_ori(s, a0, a1, a2);
1271 tcg_out_opc_or(s, a0, a1, a2);
1275 case INDEX_op_xor_i32:
1276 case INDEX_op_xor_i64:
1278 tcg_out_opc_xori(s, a0, a1, a2);
1280 tcg_out_opc_xor(s, a0, a1, a2);
1284 case INDEX_op_extract_i32:
1285 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
1287 case INDEX_op_extract_i64:
1288 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
1291 case INDEX_op_deposit_i32:
1292 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
1294 case INDEX_op_deposit_i64:
1295 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
1298 case INDEX_op_bswap16_i32:
1299 case INDEX_op_bswap16_i64:
1300 tcg_out_opc_revb_2h(s, a0, a1);
1301 if (a2 & TCG_BSWAP_OS) {
1302 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0);
1303 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1304 tcg_out_ext16u(s, a0, a0);
1308 case INDEX_op_bswap32_i32:
1309 /* All 32-bit values are computed sign-extended in the register. */
1312 case INDEX_op_bswap32_i64:
1313 tcg_out_opc_revb_2w(s, a0, a1);
1314 if (a2 & TCG_BSWAP_OS) {
1315 tcg_out_ext32s(s, a0, a0);
1316 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1317 tcg_out_ext32u(s, a0, a0);
1321 case INDEX_op_bswap64_i64:
1322 tcg_out_opc_revb_d(s, a0, a1);
1325 case INDEX_op_clz_i32:
1326 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true);
1328 case INDEX_op_clz_i64:
1329 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false);
1332 case INDEX_op_ctz_i32:
1333 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true);
1335 case INDEX_op_ctz_i64:
1336 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
1339 case INDEX_op_shl_i32:
1341 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f);
1343 tcg_out_opc_sll_w(s, a0, a1, a2);
1346 case INDEX_op_shl_i64:
1348 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f);
1350 tcg_out_opc_sll_d(s, a0, a1, a2);
1354 case INDEX_op_shr_i32:
1356 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f);
1358 tcg_out_opc_srl_w(s, a0, a1, a2);
1361 case INDEX_op_shr_i64:
1363 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f);
1365 tcg_out_opc_srl_d(s, a0, a1, a2);
1369 case INDEX_op_sar_i32:
1371 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f);
1373 tcg_out_opc_sra_w(s, a0, a1, a2);
1376 case INDEX_op_sar_i64:
1378 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f);
1380 tcg_out_opc_sra_d(s, a0, a1, a2);
1384 case INDEX_op_rotl_i32:
1385 /* transform into equivalent rotr/rotri */
1387 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f);
1389 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1390 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0);
1393 case INDEX_op_rotl_i64:
1394 /* transform into equivalent rotr/rotri */
1396 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f);
1398 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1399 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0);
1403 case INDEX_op_rotr_i32:
1405 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f);
1407 tcg_out_opc_rotr_w(s, a0, a1, a2);
1410 case INDEX_op_rotr_i64:
1412 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f);
1414 tcg_out_opc_rotr_d(s, a0, a1, a2);
1418 case INDEX_op_add_i32:
1420 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2);
1422 tcg_out_opc_add_w(s, a0, a1, a2);
1425 case INDEX_op_add_i64:
1427 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2);
1429 tcg_out_opc_add_d(s, a0, a1, a2);
1433 case INDEX_op_sub_i32:
1435 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2);
1437 tcg_out_opc_sub_w(s, a0, a1, a2);
1440 case INDEX_op_sub_i64:
1442 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2);
1444 tcg_out_opc_sub_d(s, a0, a1, a2);
1448 case INDEX_op_mul_i32:
1449 tcg_out_opc_mul_w(s, a0, a1, a2);
1451 case INDEX_op_mul_i64:
1452 tcg_out_opc_mul_d(s, a0, a1, a2);
1455 case INDEX_op_mulsh_i32:
1456 tcg_out_opc_mulh_w(s, a0, a1, a2);
1458 case INDEX_op_mulsh_i64:
1459 tcg_out_opc_mulh_d(s, a0, a1, a2);
1462 case INDEX_op_muluh_i32:
1463 tcg_out_opc_mulh_wu(s, a0, a1, a2);
1465 case INDEX_op_muluh_i64:
1466 tcg_out_opc_mulh_du(s, a0, a1, a2);
1469 case INDEX_op_div_i32:
1470 tcg_out_opc_div_w(s, a0, a1, a2);
1472 case INDEX_op_div_i64:
1473 tcg_out_opc_div_d(s, a0, a1, a2);
1476 case INDEX_op_divu_i32:
1477 tcg_out_opc_div_wu(s, a0, a1, a2);
1479 case INDEX_op_divu_i64:
1480 tcg_out_opc_div_du(s, a0, a1, a2);
1483 case INDEX_op_rem_i32:
1484 tcg_out_opc_mod_w(s, a0, a1, a2);
1486 case INDEX_op_rem_i64:
1487 tcg_out_opc_mod_d(s, a0, a1, a2);
1490 case INDEX_op_remu_i32:
1491 tcg_out_opc_mod_wu(s, a0, a1, a2);
1493 case INDEX_op_remu_i64:
1494 tcg_out_opc_mod_du(s, a0, a1, a2);
1497 case INDEX_op_setcond_i32:
1498 case INDEX_op_setcond_i64:
1499 tcg_out_setcond(s, args[3], a0, a1, a2, c2);
1502 case INDEX_op_movcond_i32:
1503 case INDEX_op_movcond_i64:
1504 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]);
1507 case INDEX_op_ld8s_i32:
1508 case INDEX_op_ld8s_i64:
1509 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
1511 case INDEX_op_ld8u_i32:
1512 case INDEX_op_ld8u_i64:
1513 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2);
1515 case INDEX_op_ld16s_i32:
1516 case INDEX_op_ld16s_i64:
1517 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2);
1519 case INDEX_op_ld16u_i32:
1520 case INDEX_op_ld16u_i64:
1521 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2);
1523 case INDEX_op_ld_i32:
1524 case INDEX_op_ld32s_i64:
1525 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2);
1527 case INDEX_op_ld32u_i64:
1528 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2);
1530 case INDEX_op_ld_i64:
1531 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2);
1534 case INDEX_op_st8_i32:
1535 case INDEX_op_st8_i64:
1536 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2);
1538 case INDEX_op_st16_i32:
1539 case INDEX_op_st16_i64:
1540 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2);
1542 case INDEX_op_st_i32:
1543 case INDEX_op_st32_i64:
1544 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2);
1546 case INDEX_op_st_i64:
1547 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
1550 case INDEX_op_qemu_ld_i32:
1551 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1553 case INDEX_op_qemu_ld_i64:
1554 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1556 case INDEX_op_qemu_st_i32:
1557 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1559 case INDEX_op_qemu_st_i64:
1560 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1563 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1564 case INDEX_op_mov_i64:
1565 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1566 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
1567 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
1568 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
1569 case INDEX_op_ext8s_i64:
1570 case INDEX_op_ext8u_i32:
1571 case INDEX_op_ext8u_i64:
1572 case INDEX_op_ext16s_i32:
1573 case INDEX_op_ext16s_i64:
1574 case INDEX_op_ext16u_i32:
1575 case INDEX_op_ext16u_i64:
1576 case INDEX_op_ext32s_i64:
1577 case INDEX_op_ext32u_i64:
1578 case INDEX_op_ext_i32_i64:
1579 case INDEX_op_extu_i32_i64:
1580 case INDEX_op_extrl_i64_i32:
1582 g_assert_not_reached();
1586 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
1589 case INDEX_op_goto_ptr:
1592 case INDEX_op_st8_i32:
1593 case INDEX_op_st8_i64:
1594 case INDEX_op_st16_i32:
1595 case INDEX_op_st16_i64:
1596 case INDEX_op_st32_i64:
1597 case INDEX_op_st_i32:
1598 case INDEX_op_st_i64:
1599 return C_O0_I2(rZ, r);
1601 case INDEX_op_brcond_i32:
1602 case INDEX_op_brcond_i64:
1603 return C_O0_I2(rZ, rZ);
1605 case INDEX_op_qemu_st_i32:
1606 case INDEX_op_qemu_st_i64:
1607 return C_O0_I2(LZ, L);
1609 case INDEX_op_ext8s_i32:
1610 case INDEX_op_ext8s_i64:
1611 case INDEX_op_ext8u_i32:
1612 case INDEX_op_ext8u_i64:
1613 case INDEX_op_ext16s_i32:
1614 case INDEX_op_ext16s_i64:
1615 case INDEX_op_ext16u_i32:
1616 case INDEX_op_ext16u_i64:
1617 case INDEX_op_ext32s_i64:
1618 case INDEX_op_ext32u_i64:
1619 case INDEX_op_extu_i32_i64:
1620 case INDEX_op_extrl_i64_i32:
1621 case INDEX_op_extrh_i64_i32:
1622 case INDEX_op_ext_i32_i64:
1623 case INDEX_op_not_i32:
1624 case INDEX_op_not_i64:
1625 case INDEX_op_extract_i32:
1626 case INDEX_op_extract_i64:
1627 case INDEX_op_bswap16_i32:
1628 case INDEX_op_bswap16_i64:
1629 case INDEX_op_bswap32_i32:
1630 case INDEX_op_bswap32_i64:
1631 case INDEX_op_bswap64_i64:
1632 case INDEX_op_ld8s_i32:
1633 case INDEX_op_ld8s_i64:
1634 case INDEX_op_ld8u_i32:
1635 case INDEX_op_ld8u_i64:
1636 case INDEX_op_ld16s_i32:
1637 case INDEX_op_ld16s_i64:
1638 case INDEX_op_ld16u_i32:
1639 case INDEX_op_ld16u_i64:
1640 case INDEX_op_ld32s_i64:
1641 case INDEX_op_ld32u_i64:
1642 case INDEX_op_ld_i32:
1643 case INDEX_op_ld_i64:
1644 return C_O1_I1(r, r);
1646 case INDEX_op_qemu_ld_i32:
1647 case INDEX_op_qemu_ld_i64:
1648 return C_O1_I1(r, L);
1650 case INDEX_op_andc_i32:
1651 case INDEX_op_andc_i64:
1652 case INDEX_op_orc_i32:
1653 case INDEX_op_orc_i64:
1655 * LoongArch insns for these ops don't have reg-imm forms, but we
1656 * can express using andi/ori if ~constant satisfies
1659 return C_O1_I2(r, r, rC);
1661 case INDEX_op_shl_i32:
1662 case INDEX_op_shl_i64:
1663 case INDEX_op_shr_i32:
1664 case INDEX_op_shr_i64:
1665 case INDEX_op_sar_i32:
1666 case INDEX_op_sar_i64:
1667 case INDEX_op_rotl_i32:
1668 case INDEX_op_rotl_i64:
1669 case INDEX_op_rotr_i32:
1670 case INDEX_op_rotr_i64:
1671 return C_O1_I2(r, r, ri);
1673 case INDEX_op_add_i32:
1674 return C_O1_I2(r, r, ri);
1675 case INDEX_op_add_i64:
1676 return C_O1_I2(r, r, rJ);
1678 case INDEX_op_and_i32:
1679 case INDEX_op_and_i64:
1680 case INDEX_op_nor_i32:
1681 case INDEX_op_nor_i64:
1682 case INDEX_op_or_i32:
1683 case INDEX_op_or_i64:
1684 case INDEX_op_xor_i32:
1685 case INDEX_op_xor_i64:
1686 /* LoongArch reg-imm bitops have their imms ZERO-extended */
1687 return C_O1_I2(r, r, rU);
1689 case INDEX_op_clz_i32:
1690 case INDEX_op_clz_i64:
1691 case INDEX_op_ctz_i32:
1692 case INDEX_op_ctz_i64:
1693 return C_O1_I2(r, r, rW);
1695 case INDEX_op_deposit_i32:
1696 case INDEX_op_deposit_i64:
1697 /* Must deposit into the same register as input */
1698 return C_O1_I2(r, 0, rZ);
1700 case INDEX_op_sub_i32:
1701 case INDEX_op_setcond_i32:
1702 return C_O1_I2(r, rZ, ri);
1703 case INDEX_op_sub_i64:
1704 case INDEX_op_setcond_i64:
1705 return C_O1_I2(r, rZ, rJ);
1707 case INDEX_op_mul_i32:
1708 case INDEX_op_mul_i64:
1709 case INDEX_op_mulsh_i32:
1710 case INDEX_op_mulsh_i64:
1711 case INDEX_op_muluh_i32:
1712 case INDEX_op_muluh_i64:
1713 case INDEX_op_div_i32:
1714 case INDEX_op_div_i64:
1715 case INDEX_op_divu_i32:
1716 case INDEX_op_divu_i64:
1717 case INDEX_op_rem_i32:
1718 case INDEX_op_rem_i64:
1719 case INDEX_op_remu_i32:
1720 case INDEX_op_remu_i64:
1721 return C_O1_I2(r, rZ, rZ);
1723 case INDEX_op_movcond_i32:
1724 case INDEX_op_movcond_i64:
1725 return C_O1_I4(r, rZ, rJ, rZ, rZ);
1728 g_assert_not_reached();
1732 static const int tcg_target_callee_save_regs[] = {
1733 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
1743 TCG_REG_RA, /* should be last for ABI compliance */
1746 /* Stack frame parameters. */
1747 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
1748 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
1749 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1750 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
1751 + TCG_TARGET_STACK_ALIGN - 1) \
1752 & -TCG_TARGET_STACK_ALIGN)
1753 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
1755 /* We're expecting to be able to use an immediate for frame allocation. */
1756 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
1758 /* Generate global QEMU prologue and epilogue code */
1759 static void tcg_target_qemu_prologue(TCGContext *s)
1763 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
1766 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
1767 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1768 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1769 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1772 #if !defined(CONFIG_SOFTMMU)
1773 if (USE_GUEST_BASE) {
1774 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1775 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1779 /* Call generated code */
1780 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1781 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1783 /* Return path for goto_ptr. Set return value to 0 */
1784 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
1785 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
1788 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
1789 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1790 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1791 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1794 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
1795 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0);
1798 static void tcg_target_init(TCGContext *s)
1800 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
1801 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
1803 tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
1804 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
1805 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
1806 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
1807 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
1808 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
1809 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
1810 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
1811 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
1812 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
1813 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
1815 s->reserved_regs = 0;
1816 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
1817 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
1818 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
1819 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
1820 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
1821 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
1822 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
1827 uint8_t fde_def_cfa[4];
1828 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
1831 #define ELF_HOST_MACHINE EM_LOONGARCH
1833 static const DebugFrame debug_frame = {
1834 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
1837 .h.cie.code_align = 1,
1838 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
1839 .h.cie.return_column = TCG_REG_RA,
1841 /* Total FDE size does not include the "len" member. */
1842 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1845 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
1846 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
1850 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */
1851 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */
1852 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */
1853 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */
1854 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */
1855 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */
1856 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */
1857 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */
1858 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */
1859 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */
1860 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
1864 void tcg_register_jit(const void *buf, size_t buf_size)
1866 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));