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[mirror_qemu.git] / tcg / mips / tcg-target.c.inc
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #ifdef HOST_WORDS_BIGENDIAN
28 # define MIPS_BE 1
29 #else
30 # define MIPS_BE 0
31 #endif
32
33 #if TCG_TARGET_REG_BITS == 32
34 # define LO_OFF (MIPS_BE * 4)
35 # define HI_OFF (4 - LO_OFF)
36 #else
37 /* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
39 int link_error(void);
40 # define LO_OFF link_error()
41 # define HI_OFF link_error()
42 #endif
43
44 #ifdef CONFIG_DEBUG_TCG
45 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
76 "s8",
77 "ra",
78 };
79 #endif
80
81 #define TCG_TMP0 TCG_REG_AT
82 #define TCG_TMP1 TCG_REG_T9
83 #define TCG_TMP2 TCG_REG_T8
84 #define TCG_TMP3 TCG_REG_T7
85
86 #ifndef CONFIG_SOFTMMU
87 #define TCG_GUEST_BASE_REG TCG_REG_S1
88 #endif
89
90 /* check if we really need so many registers :P */
91 static const int tcg_target_reg_alloc_order[] = {
92 /* Call saved registers. */
93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
101 TCG_REG_S8,
102
103 /* Call clobbered registers. */
104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
110 TCG_REG_V1,
111 TCG_REG_V0,
112
113 /* Argument registers, opposite order of allocation. */
114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
122 };
123
124 static const TCGReg tcg_target_call_iarg_regs[] = {
125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
128 TCG_REG_A3,
129 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134 #endif
135 };
136
137 static const TCGReg tcg_target_call_oarg_regs[2] = {
138 TCG_REG_V0,
139 TCG_REG_V1
140 };
141
142 static const tcg_insn_unit *tb_ret_addr;
143 static const tcg_insn_unit *bswap32_addr;
144 static const tcg_insn_unit *bswap32u_addr;
145 static const tcg_insn_unit *bswap64_addr;
146
147 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
148 {
149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
151 ptrdiff_t disp = target - (src_rx + 1);
152 if (disp == (int16_t)disp) {
153 *src_rw = deposit32(*src_rw, 0, 16, disp);
154 return true;
155 }
156 return false;
157 }
158
159 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
160 intptr_t value, intptr_t addend)
161 {
162 tcg_debug_assert(type == R_MIPS_PC16);
163 tcg_debug_assert(addend == 0);
164 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
165 }
166
167 #define TCG_CT_CONST_ZERO 0x100
168 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
169 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
170 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
171 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
172 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
173
174 #define ALL_GENERAL_REGS 0xffffffffu
175 #define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
176
177 #ifdef CONFIG_SOFTMMU
178 #define ALL_QLOAD_REGS \
179 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
180 #define ALL_QSTORE_REGS \
181 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
182 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
183 : (1 << TCG_REG_A1)))
184 #else
185 #define ALL_QLOAD_REGS NOA0_REGS
186 #define ALL_QSTORE_REGS NOA0_REGS
187 #endif
188
189
190 static bool is_p2m1(tcg_target_long val)
191 {
192 return val && ((val + 1) & val) == 0;
193 }
194
195 /* test if a constant matches the constraint */
196 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
197 {
198 if (ct & TCG_CT_CONST) {
199 return 1;
200 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
201 return 1;
202 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
203 return 1;
204 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
205 return 1;
206 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
207 return 1;
208 } else if ((ct & TCG_CT_CONST_P2M1)
209 && use_mips32r2_instructions && is_p2m1(val)) {
210 return 1;
211 } else if ((ct & TCG_CT_CONST_WSZ)
212 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
213 return 1;
214 }
215 return 0;
216 }
217
218 /* instruction opcodes */
219 typedef enum {
220 OPC_J = 002 << 26,
221 OPC_JAL = 003 << 26,
222 OPC_BEQ = 004 << 26,
223 OPC_BNE = 005 << 26,
224 OPC_BLEZ = 006 << 26,
225 OPC_BGTZ = 007 << 26,
226 OPC_ADDIU = 011 << 26,
227 OPC_SLTI = 012 << 26,
228 OPC_SLTIU = 013 << 26,
229 OPC_ANDI = 014 << 26,
230 OPC_ORI = 015 << 26,
231 OPC_XORI = 016 << 26,
232 OPC_LUI = 017 << 26,
233 OPC_DADDIU = 031 << 26,
234 OPC_LB = 040 << 26,
235 OPC_LH = 041 << 26,
236 OPC_LW = 043 << 26,
237 OPC_LBU = 044 << 26,
238 OPC_LHU = 045 << 26,
239 OPC_LWU = 047 << 26,
240 OPC_SB = 050 << 26,
241 OPC_SH = 051 << 26,
242 OPC_SW = 053 << 26,
243 OPC_LD = 067 << 26,
244 OPC_SD = 077 << 26,
245
246 OPC_SPECIAL = 000 << 26,
247 OPC_SLL = OPC_SPECIAL | 000,
248 OPC_SRL = OPC_SPECIAL | 002,
249 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
250 OPC_SRA = OPC_SPECIAL | 003,
251 OPC_SLLV = OPC_SPECIAL | 004,
252 OPC_SRLV = OPC_SPECIAL | 006,
253 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
254 OPC_SRAV = OPC_SPECIAL | 007,
255 OPC_JR_R5 = OPC_SPECIAL | 010,
256 OPC_JALR = OPC_SPECIAL | 011,
257 OPC_MOVZ = OPC_SPECIAL | 012,
258 OPC_MOVN = OPC_SPECIAL | 013,
259 OPC_SYNC = OPC_SPECIAL | 017,
260 OPC_MFHI = OPC_SPECIAL | 020,
261 OPC_MFLO = OPC_SPECIAL | 022,
262 OPC_DSLLV = OPC_SPECIAL | 024,
263 OPC_DSRLV = OPC_SPECIAL | 026,
264 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
265 OPC_DSRAV = OPC_SPECIAL | 027,
266 OPC_MULT = OPC_SPECIAL | 030,
267 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
268 OPC_MUH = OPC_SPECIAL | 030 | 0300,
269 OPC_MULTU = OPC_SPECIAL | 031,
270 OPC_MULU = OPC_SPECIAL | 031 | 0200,
271 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
272 OPC_DIV = OPC_SPECIAL | 032,
273 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
274 OPC_MOD = OPC_SPECIAL | 032 | 0300,
275 OPC_DIVU = OPC_SPECIAL | 033,
276 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
277 OPC_MODU = OPC_SPECIAL | 033 | 0300,
278 OPC_DMULT = OPC_SPECIAL | 034,
279 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
280 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
281 OPC_DMULTU = OPC_SPECIAL | 035,
282 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
283 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
284 OPC_DDIV = OPC_SPECIAL | 036,
285 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
286 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
287 OPC_DDIVU = OPC_SPECIAL | 037,
288 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
289 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
290 OPC_ADDU = OPC_SPECIAL | 041,
291 OPC_SUBU = OPC_SPECIAL | 043,
292 OPC_AND = OPC_SPECIAL | 044,
293 OPC_OR = OPC_SPECIAL | 045,
294 OPC_XOR = OPC_SPECIAL | 046,
295 OPC_NOR = OPC_SPECIAL | 047,
296 OPC_SLT = OPC_SPECIAL | 052,
297 OPC_SLTU = OPC_SPECIAL | 053,
298 OPC_DADDU = OPC_SPECIAL | 055,
299 OPC_DSUBU = OPC_SPECIAL | 057,
300 OPC_SELEQZ = OPC_SPECIAL | 065,
301 OPC_SELNEZ = OPC_SPECIAL | 067,
302 OPC_DSLL = OPC_SPECIAL | 070,
303 OPC_DSRL = OPC_SPECIAL | 072,
304 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
305 OPC_DSRA = OPC_SPECIAL | 073,
306 OPC_DSLL32 = OPC_SPECIAL | 074,
307 OPC_DSRL32 = OPC_SPECIAL | 076,
308 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
309 OPC_DSRA32 = OPC_SPECIAL | 077,
310 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
311 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
312
313 OPC_REGIMM = 001 << 26,
314 OPC_BLTZ = OPC_REGIMM | (000 << 16),
315 OPC_BGEZ = OPC_REGIMM | (001 << 16),
316
317 OPC_SPECIAL2 = 034 << 26,
318 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
319 OPC_CLZ = OPC_SPECIAL2 | 040,
320 OPC_DCLZ = OPC_SPECIAL2 | 044,
321
322 OPC_SPECIAL3 = 037 << 26,
323 OPC_EXT = OPC_SPECIAL3 | 000,
324 OPC_DEXTM = OPC_SPECIAL3 | 001,
325 OPC_DEXTU = OPC_SPECIAL3 | 002,
326 OPC_DEXT = OPC_SPECIAL3 | 003,
327 OPC_INS = OPC_SPECIAL3 | 004,
328 OPC_DINSM = OPC_SPECIAL3 | 005,
329 OPC_DINSU = OPC_SPECIAL3 | 006,
330 OPC_DINS = OPC_SPECIAL3 | 007,
331 OPC_WSBH = OPC_SPECIAL3 | 00240,
332 OPC_DSBH = OPC_SPECIAL3 | 00244,
333 OPC_DSHD = OPC_SPECIAL3 | 00544,
334 OPC_SEB = OPC_SPECIAL3 | 02040,
335 OPC_SEH = OPC_SPECIAL3 | 03040,
336
337 /* MIPS r6 doesn't have JR, JALR should be used instead */
338 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
339
340 /*
341 * MIPS r6 replaces MUL with an alternative encoding which is
342 * backwards-compatible at the assembly level.
343 */
344 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
345
346 /* MIPS r6 introduced names for weaker variants of SYNC. These are
347 backward compatible to previous architecture revisions. */
348 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
349 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
350 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
351 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
352 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
353
354 /* Aliases for convenience. */
355 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
356 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
357 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
358 ? OPC_SRL : OPC_DSRL,
359 } MIPSInsn;
360
361 /*
362 * Type reg
363 */
364 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
365 TCGReg rd, TCGReg rs, TCGReg rt)
366 {
367 int32_t inst;
368
369 inst = opc;
370 inst |= (rs & 0x1F) << 21;
371 inst |= (rt & 0x1F) << 16;
372 inst |= (rd & 0x1F) << 11;
373 tcg_out32(s, inst);
374 }
375
376 /*
377 * Type immediate
378 */
379 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
380 TCGReg rt, TCGReg rs, TCGArg imm)
381 {
382 int32_t inst;
383
384 inst = opc;
385 inst |= (rs & 0x1F) << 21;
386 inst |= (rt & 0x1F) << 16;
387 inst |= (imm & 0xffff);
388 tcg_out32(s, inst);
389 }
390
391 /*
392 * Type bitfield
393 */
394 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
395 TCGReg rs, int msb, int lsb)
396 {
397 int32_t inst;
398
399 inst = opc;
400 inst |= (rs & 0x1F) << 21;
401 inst |= (rt & 0x1F) << 16;
402 inst |= (msb & 0x1F) << 11;
403 inst |= (lsb & 0x1F) << 6;
404 tcg_out32(s, inst);
405 }
406
407 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
408 MIPSInsn oph, TCGReg rt, TCGReg rs,
409 int msb, int lsb)
410 {
411 if (lsb >= 32) {
412 opc = oph;
413 msb -= 32;
414 lsb -= 32;
415 } else if (msb >= 32) {
416 opc = opm;
417 msb -= 32;
418 }
419 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
420 }
421
422 /*
423 * Type branch
424 */
425 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
426 {
427 tcg_out_opc_imm(s, opc, rt, rs, 0);
428 }
429
430 /*
431 * Type sa
432 */
433 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
434 TCGReg rd, TCGReg rt, TCGArg sa)
435 {
436 int32_t inst;
437
438 inst = opc;
439 inst |= (rt & 0x1F) << 16;
440 inst |= (rd & 0x1F) << 11;
441 inst |= (sa & 0x1F) << 6;
442 tcg_out32(s, inst);
443
444 }
445
446 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
447 TCGReg rd, TCGReg rt, TCGArg sa)
448 {
449 int32_t inst;
450
451 inst = (sa & 32 ? opc2 : opc1);
452 inst |= (rt & 0x1F) << 16;
453 inst |= (rd & 0x1F) << 11;
454 inst |= (sa & 0x1F) << 6;
455 tcg_out32(s, inst);
456 }
457
458 /*
459 * Type jump.
460 * Returns true if the branch was in range and the insn was emitted.
461 */
462 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
463 {
464 uintptr_t dest = (uintptr_t)target;
465 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
466 int32_t inst;
467
468 /* The pc-region branch happens within the 256MB region of
469 the delay slot (thus the +4). */
470 if ((from ^ dest) & -(1 << 28)) {
471 return false;
472 }
473 tcg_debug_assert((dest & 3) == 0);
474
475 inst = opc;
476 inst |= (dest >> 2) & 0x3ffffff;
477 tcg_out32(s, inst);
478 return true;
479 }
480
481 static void tcg_out_nop(TCGContext *s)
482 {
483 tcg_out32(s, 0);
484 }
485
486 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
487 {
488 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
489 }
490
491 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
492 {
493 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
494 }
495
496 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
497 {
498 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
499 }
500
501 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
502 {
503 /* Simple reg-reg move, optimising out the 'do nothing' case */
504 if (ret != arg) {
505 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
506 }
507 return true;
508 }
509
510 static void tcg_out_movi(TCGContext *s, TCGType type,
511 TCGReg ret, tcg_target_long arg)
512 {
513 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
514 arg = (int32_t)arg;
515 }
516 if (arg == (int16_t)arg) {
517 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
518 return;
519 }
520 if (arg == (uint16_t)arg) {
521 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
522 return;
523 }
524 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
525 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
526 } else {
527 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
528 if (arg & 0xffff0000ull) {
529 tcg_out_dsll(s, ret, ret, 16);
530 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
531 tcg_out_dsll(s, ret, ret, 16);
532 } else {
533 tcg_out_dsll(s, ret, ret, 32);
534 }
535 }
536 if (arg & 0xffff) {
537 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
538 }
539 }
540
541 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
542 {
543 /* ret and arg can't be register tmp0 */
544 tcg_debug_assert(ret != TCG_TMP0);
545 tcg_debug_assert(arg != TCG_TMP0);
546
547 /* With arg = abcd: */
548 if (use_mips32r2_instructions) {
549 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
550 if (flags & TCG_BSWAP_OS) {
551 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
552 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
553 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
554 }
555 return;
556 }
557
558 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
559 if (!(flags & TCG_BSWAP_IZ)) {
560 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
561 }
562 if (flags & TCG_BSWAP_OS) {
563 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
564 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
565 } else {
566 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
567 if (flags & TCG_BSWAP_OZ) {
568 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
569 }
570 }
571 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
572 }
573
574 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
575 {
576 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
577 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
578 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
579 }
580 }
581
582 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
583 {
584 if (use_mips32r2_instructions) {
585 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
586 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
587 if (flags & TCG_BSWAP_OZ) {
588 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
589 }
590 } else {
591 if (flags & TCG_BSWAP_OZ) {
592 tcg_out_bswap_subr(s, bswap32u_addr);
593 } else {
594 tcg_out_bswap_subr(s, bswap32_addr);
595 }
596 /* delay slot -- never omit the insn, like tcg_out_mov might. */
597 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
598 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
599 }
600 }
601
602 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
603 {
604 if (use_mips32r2_instructions) {
605 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
606 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
607 } else {
608 tcg_out_bswap_subr(s, bswap64_addr);
609 /* delay slot -- never omit the insn, like tcg_out_mov might. */
610 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
611 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
612 }
613 }
614
615 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
616 {
617 if (use_mips32r2_instructions) {
618 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
619 } else {
620 tcg_out_dsll(s, ret, arg, 32);
621 tcg_out_dsrl(s, ret, ret, 32);
622 }
623 }
624
625 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
626 TCGReg addr, intptr_t ofs)
627 {
628 int16_t lo = ofs;
629 if (ofs != lo) {
630 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
631 if (addr != TCG_REG_ZERO) {
632 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
633 }
634 addr = TCG_TMP0;
635 }
636 tcg_out_opc_imm(s, opc, data, addr, lo);
637 }
638
639 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
640 TCGReg arg1, intptr_t arg2)
641 {
642 MIPSInsn opc = OPC_LD;
643 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
644 opc = OPC_LW;
645 }
646 tcg_out_ldst(s, opc, arg, arg1, arg2);
647 }
648
649 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
650 TCGReg arg1, intptr_t arg2)
651 {
652 MIPSInsn opc = OPC_SD;
653 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
654 opc = OPC_SW;
655 }
656 tcg_out_ldst(s, opc, arg, arg1, arg2);
657 }
658
659 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
660 TCGReg base, intptr_t ofs)
661 {
662 if (val == 0) {
663 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
664 return true;
665 }
666 return false;
667 }
668
669 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
670 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
671 bool cbh, bool is_sub)
672 {
673 TCGReg th = TCG_TMP1;
674
675 /* If we have a negative constant such that negating it would
676 make the high part zero, we can (usually) eliminate one insn. */
677 if (cbl && cbh && bh == -1 && bl != 0) {
678 bl = -bl;
679 bh = 0;
680 is_sub = !is_sub;
681 }
682
683 /* By operating on the high part first, we get to use the final
684 carry operation to move back from the temporary. */
685 if (!cbh) {
686 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
687 } else if (bh != 0 || ah == rl) {
688 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
689 } else {
690 th = ah;
691 }
692
693 /* Note that tcg optimization should eliminate the bl == 0 case. */
694 if (is_sub) {
695 if (cbl) {
696 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
697 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
698 } else {
699 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
700 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
701 }
702 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
703 } else {
704 if (cbl) {
705 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
706 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
707 } else if (rl == al && rl == bl) {
708 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
709 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
710 } else {
711 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
712 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
713 }
714 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
715 }
716 }
717
718 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
719 #define MIPS_CMP_INV 1
720 #define MIPS_CMP_SWAP 2
721
722 static const uint8_t mips_cmp_map[16] = {
723 [TCG_COND_LT] = 0,
724 [TCG_COND_LTU] = 0,
725 [TCG_COND_GE] = MIPS_CMP_INV,
726 [TCG_COND_GEU] = MIPS_CMP_INV,
727 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
728 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
729 [TCG_COND_GT] = MIPS_CMP_SWAP,
730 [TCG_COND_GTU] = MIPS_CMP_SWAP,
731 };
732
733 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
734 TCGReg arg1, TCGReg arg2)
735 {
736 MIPSInsn s_opc = OPC_SLTU;
737 int cmp_map;
738
739 switch (cond) {
740 case TCG_COND_EQ:
741 if (arg2 != 0) {
742 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
743 arg1 = ret;
744 }
745 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
746 break;
747
748 case TCG_COND_NE:
749 if (arg2 != 0) {
750 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
751 arg1 = ret;
752 }
753 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
754 break;
755
756 case TCG_COND_LT:
757 case TCG_COND_GE:
758 case TCG_COND_LE:
759 case TCG_COND_GT:
760 s_opc = OPC_SLT;
761 /* FALLTHRU */
762
763 case TCG_COND_LTU:
764 case TCG_COND_GEU:
765 case TCG_COND_LEU:
766 case TCG_COND_GTU:
767 cmp_map = mips_cmp_map[cond];
768 if (cmp_map & MIPS_CMP_SWAP) {
769 TCGReg t = arg1;
770 arg1 = arg2;
771 arg2 = t;
772 }
773 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
774 if (cmp_map & MIPS_CMP_INV) {
775 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
776 }
777 break;
778
779 default:
780 tcg_abort();
781 break;
782 }
783 }
784
785 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
786 TCGReg arg2, TCGLabel *l)
787 {
788 static const MIPSInsn b_zero[16] = {
789 [TCG_COND_LT] = OPC_BLTZ,
790 [TCG_COND_GT] = OPC_BGTZ,
791 [TCG_COND_LE] = OPC_BLEZ,
792 [TCG_COND_GE] = OPC_BGEZ,
793 };
794
795 MIPSInsn s_opc = OPC_SLTU;
796 MIPSInsn b_opc;
797 int cmp_map;
798
799 switch (cond) {
800 case TCG_COND_EQ:
801 b_opc = OPC_BEQ;
802 break;
803 case TCG_COND_NE:
804 b_opc = OPC_BNE;
805 break;
806
807 case TCG_COND_LT:
808 case TCG_COND_GT:
809 case TCG_COND_LE:
810 case TCG_COND_GE:
811 if (arg2 == 0) {
812 b_opc = b_zero[cond];
813 arg2 = arg1;
814 arg1 = 0;
815 break;
816 }
817 s_opc = OPC_SLT;
818 /* FALLTHRU */
819
820 case TCG_COND_LTU:
821 case TCG_COND_GTU:
822 case TCG_COND_LEU:
823 case TCG_COND_GEU:
824 cmp_map = mips_cmp_map[cond];
825 if (cmp_map & MIPS_CMP_SWAP) {
826 TCGReg t = arg1;
827 arg1 = arg2;
828 arg2 = t;
829 }
830 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
831 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
832 arg1 = TCG_TMP0;
833 arg2 = TCG_REG_ZERO;
834 break;
835
836 default:
837 tcg_abort();
838 break;
839 }
840
841 tcg_out_opc_br(s, b_opc, arg1, arg2);
842 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
843 tcg_out_nop(s);
844 }
845
846 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
847 TCGReg al, TCGReg ah,
848 TCGReg bl, TCGReg bh)
849 {
850 /* Merge highpart comparison into AH. */
851 if (bh != 0) {
852 if (ah != 0) {
853 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
854 ah = tmp0;
855 } else {
856 ah = bh;
857 }
858 }
859 /* Merge lowpart comparison into AL. */
860 if (bl != 0) {
861 if (al != 0) {
862 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
863 al = tmp1;
864 } else {
865 al = bl;
866 }
867 }
868 /* Merge high and low part comparisons into AL. */
869 if (ah != 0) {
870 if (al != 0) {
871 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
872 al = tmp0;
873 } else {
874 al = ah;
875 }
876 }
877 return al;
878 }
879
880 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
881 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
882 {
883 TCGReg tmp0 = TCG_TMP0;
884 TCGReg tmp1 = ret;
885
886 tcg_debug_assert(ret != TCG_TMP0);
887 if (ret == ah || ret == bh) {
888 tcg_debug_assert(ret != TCG_TMP1);
889 tmp1 = TCG_TMP1;
890 }
891
892 switch (cond) {
893 case TCG_COND_EQ:
894 case TCG_COND_NE:
895 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
896 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
897 break;
898
899 default:
900 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
901 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
902 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
903 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
904 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
905 break;
906 }
907 }
908
909 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
910 TCGReg bl, TCGReg bh, TCGLabel *l)
911 {
912 TCGCond b_cond = TCG_COND_NE;
913 TCGReg tmp = TCG_TMP1;
914
915 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
916 With setcond, we emit between 3 and 10 insns and only 1 branch,
917 which ought to get better branch prediction. */
918 switch (cond) {
919 case TCG_COND_EQ:
920 case TCG_COND_NE:
921 b_cond = cond;
922 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
923 break;
924
925 default:
926 /* Minimize code size by preferring a compare not requiring INV. */
927 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
928 cond = tcg_invert_cond(cond);
929 b_cond = TCG_COND_EQ;
930 }
931 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
932 break;
933 }
934
935 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
936 }
937
938 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
939 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
940 {
941 bool eqz = false;
942
943 /* If one of the values is zero, put it last to match SEL*Z instructions */
944 if (use_mips32r6_instructions && v1 == 0) {
945 v1 = v2;
946 v2 = 0;
947 cond = tcg_invert_cond(cond);
948 }
949
950 switch (cond) {
951 case TCG_COND_EQ:
952 eqz = true;
953 /* FALLTHRU */
954 case TCG_COND_NE:
955 if (c2 != 0) {
956 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
957 c1 = TCG_TMP0;
958 }
959 break;
960
961 default:
962 /* Minimize code size by preferring a compare not requiring INV. */
963 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
964 cond = tcg_invert_cond(cond);
965 eqz = true;
966 }
967 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
968 c1 = TCG_TMP0;
969 break;
970 }
971
972 if (use_mips32r6_instructions) {
973 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
974 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
975
976 if (v2 != 0) {
977 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
978 }
979 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
980 if (v2 != 0) {
981 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
982 }
983 } else {
984 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
985
986 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
987
988 /* This should be guaranteed via constraints */
989 tcg_debug_assert(v2 == ret);
990 }
991 }
992
993 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
994 {
995 /* Note that the ABI requires the called function's address to be
996 loaded into T9, even if a direct branch is in range. */
997 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
998
999 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1000 if (tail) {
1001 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1002 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1003 }
1004 } else {
1005 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1006 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1007 }
1008 }
1009 }
1010
1011 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
1012 {
1013 tcg_out_call_int(s, arg, false);
1014 tcg_out_nop(s);
1015 }
1016
1017 #if defined(CONFIG_SOFTMMU)
1018 #include "../tcg-ldst.c.inc"
1019
1020 static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
1021 [MO_UB] = helper_ret_ldub_mmu,
1022 [MO_SB] = helper_ret_ldsb_mmu,
1023 [MO_LEUW] = helper_le_lduw_mmu,
1024 [MO_LESW] = helper_le_ldsw_mmu,
1025 [MO_LEUL] = helper_le_ldul_mmu,
1026 [MO_LEUQ] = helper_le_ldq_mmu,
1027 [MO_BEUW] = helper_be_lduw_mmu,
1028 [MO_BESW] = helper_be_ldsw_mmu,
1029 [MO_BEUL] = helper_be_ldul_mmu,
1030 [MO_BEUQ] = helper_be_ldq_mmu,
1031 #if TCG_TARGET_REG_BITS == 64
1032 [MO_LESL] = helper_le_ldsl_mmu,
1033 [MO_BESL] = helper_be_ldsl_mmu,
1034 #endif
1035 };
1036
1037 static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
1038 [MO_UB] = helper_ret_stb_mmu,
1039 [MO_LEUW] = helper_le_stw_mmu,
1040 [MO_LEUL] = helper_le_stl_mmu,
1041 [MO_LEUQ] = helper_le_stq_mmu,
1042 [MO_BEUW] = helper_be_stw_mmu,
1043 [MO_BEUL] = helper_be_stl_mmu,
1044 [MO_BEUQ] = helper_be_stq_mmu,
1045 };
1046
1047 /* Helper routines for marshalling helper function arguments into
1048 * the correct registers and stack.
1049 * I is where we want to put this argument, and is updated and returned
1050 * for the next call. ARG is the argument itself.
1051 *
1052 * We provide routines for arguments which are: immediate, 32 bit
1053 * value in register, 16 and 8 bit values in register (which must be zero
1054 * extended before use) and 64 bit value in a lo:hi register pair.
1055 */
1056
1057 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1058 {
1059 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1060 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1061 } else {
1062 /* For N32 and N64, the initial offset is different. But there
1063 we also have 8 argument register so we don't run out here. */
1064 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1065 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1066 }
1067 return i + 1;
1068 }
1069
1070 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1071 {
1072 TCGReg tmp = TCG_TMP0;
1073 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1074 tmp = tcg_target_call_iarg_regs[i];
1075 }
1076 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1077 return tcg_out_call_iarg_reg(s, i, tmp);
1078 }
1079
1080 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1081 {
1082 TCGReg tmp = TCG_TMP0;
1083 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1084 tmp = tcg_target_call_iarg_regs[i];
1085 }
1086 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1087 return tcg_out_call_iarg_reg(s, i, tmp);
1088 }
1089
1090 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1091 {
1092 TCGReg tmp = TCG_TMP0;
1093 if (arg == 0) {
1094 tmp = TCG_REG_ZERO;
1095 } else {
1096 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1097 tmp = tcg_target_call_iarg_regs[i];
1098 }
1099 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1100 }
1101 return tcg_out_call_iarg_reg(s, i, tmp);
1102 }
1103
1104 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1105 {
1106 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1107 i = (i + 1) & ~1;
1108 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1109 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1110 return i;
1111 }
1112
1113 /* We expect to use a 16-bit negative offset from ENV. */
1114 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1115 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1116
1117 /*
1118 * Perform the tlb comparison operation.
1119 * The complete host address is placed in BASE.
1120 * Clobbers TMP0, TMP1, TMP2, TMP3.
1121 */
1122 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1123 TCGReg addrh, MemOpIdx oi,
1124 tcg_insn_unit *label_ptr[2], bool is_load)
1125 {
1126 MemOp opc = get_memop(oi);
1127 unsigned s_bits = opc & MO_SIZE;
1128 unsigned a_bits = get_alignment_bits(opc);
1129 int mem_index = get_mmuidx(oi);
1130 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1131 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1132 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1133 int add_off = offsetof(CPUTLBEntry, addend);
1134 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1135 : offsetof(CPUTLBEntry, addr_write));
1136 target_ulong mask;
1137
1138 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1139 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1140 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1141
1142 /* Extract the TLB index from the address into TMP3. */
1143 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1144 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1145 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1146
1147 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1148 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1149
1150 /* We don't currently support unaligned accesses.
1151 We could do so with mips32r6. */
1152 if (a_bits < s_bits) {
1153 a_bits = s_bits;
1154 }
1155
1156 /* Mask the page bits, keeping the alignment bits to compare against. */
1157 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1158
1159 /* Load the (low-half) tlb comparator. */
1160 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1161 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1162 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1163 } else {
1164 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1165 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1166 TCG_TMP0, TCG_TMP3, cmp_off);
1167 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1168 /* No second compare is required here;
1169 load the tlb addend for the fast path. */
1170 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1171 }
1172
1173 /* Zero extend a 32-bit guest address for a 64-bit host. */
1174 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1175 tcg_out_ext32u(s, base, addrl);
1176 addrl = base;
1177 }
1178 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1179
1180 label_ptr[0] = s->code_ptr;
1181 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1182
1183 /* Load and test the high half tlb comparator. */
1184 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1185 /* delay slot */
1186 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1187
1188 /* Load the tlb addend for the fast path. */
1189 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1190
1191 label_ptr[1] = s->code_ptr;
1192 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1193 }
1194
1195 /* delay slot */
1196 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1197 }
1198
1199 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
1200 TCGType ext,
1201 TCGReg datalo, TCGReg datahi,
1202 TCGReg addrlo, TCGReg addrhi,
1203 void *raddr, tcg_insn_unit *label_ptr[2])
1204 {
1205 TCGLabelQemuLdst *label = new_ldst_label(s);
1206
1207 label->is_ld = is_ld;
1208 label->oi = oi;
1209 label->type = ext;
1210 label->datalo_reg = datalo;
1211 label->datahi_reg = datahi;
1212 label->addrlo_reg = addrlo;
1213 label->addrhi_reg = addrhi;
1214 label->raddr = tcg_splitwx_to_rx(raddr);
1215 label->label_ptr[0] = label_ptr[0];
1216 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1217 label->label_ptr[1] = label_ptr[1];
1218 }
1219 }
1220
1221 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1222 {
1223 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1224 MemOpIdx oi = l->oi;
1225 MemOp opc = get_memop(oi);
1226 TCGReg v0;
1227 int i;
1228
1229 /* resolve label address */
1230 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1231 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1232 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1233 return false;
1234 }
1235
1236 i = 1;
1237 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1238 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1239 } else {
1240 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1241 }
1242 i = tcg_out_call_iarg_imm(s, i, oi);
1243 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1244 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1245 /* delay slot */
1246 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1247
1248 v0 = l->datalo_reg;
1249 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1250 /* We eliminated V0 from the possible output registers, so it
1251 cannot be clobbered here. So we must move V1 first. */
1252 if (MIPS_BE) {
1253 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1254 v0 = l->datahi_reg;
1255 } else {
1256 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1257 }
1258 }
1259
1260 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1261 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1262 return false;
1263 }
1264
1265 /* delay slot */
1266 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1267 /* we always sign-extend 32-bit loads */
1268 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1269 } else {
1270 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1271 }
1272 return true;
1273 }
1274
1275 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1276 {
1277 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1278 MemOpIdx oi = l->oi;
1279 MemOp opc = get_memop(oi);
1280 MemOp s_bits = opc & MO_SIZE;
1281 int i;
1282
1283 /* resolve label address */
1284 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1285 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1286 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1287 return false;
1288 }
1289
1290 i = 1;
1291 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1292 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1293 } else {
1294 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1295 }
1296 switch (s_bits) {
1297 case MO_8:
1298 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1299 break;
1300 case MO_16:
1301 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1302 break;
1303 case MO_32:
1304 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1305 break;
1306 case MO_64:
1307 if (TCG_TARGET_REG_BITS == 32) {
1308 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1309 } else {
1310 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1311 }
1312 break;
1313 default:
1314 tcg_abort();
1315 }
1316 i = tcg_out_call_iarg_imm(s, i, oi);
1317
1318 /* Tail call to the store helper. Thus force the return address
1319 computation to take place in the return address register. */
1320 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1321 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1322 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1323 /* delay slot */
1324 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1325 return true;
1326 }
1327 #endif
1328
1329 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1330 TCGReg base, MemOp opc, bool is_64)
1331 {
1332 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1333 case MO_UB:
1334 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1335 break;
1336 case MO_SB:
1337 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1338 break;
1339 case MO_UW | MO_BSWAP:
1340 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1341 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1342 break;
1343 case MO_UW:
1344 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1345 break;
1346 case MO_SW | MO_BSWAP:
1347 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1348 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS);
1349 break;
1350 case MO_SW:
1351 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1352 break;
1353 case MO_UL | MO_BSWAP:
1354 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1355 if (use_mips32r2_instructions) {
1356 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1357 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1358 } else {
1359 tcg_out_bswap_subr(s, bswap32u_addr);
1360 /* delay slot */
1361 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1362 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1363 }
1364 break;
1365 }
1366 /* FALLTHRU */
1367 case MO_SL | MO_BSWAP:
1368 if (use_mips32r2_instructions) {
1369 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1370 tcg_out_bswap32(s, lo, lo, 0);
1371 } else {
1372 tcg_out_bswap_subr(s, bswap32_addr);
1373 /* delay slot */
1374 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1375 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1376 }
1377 break;
1378 case MO_UL:
1379 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1380 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1381 break;
1382 }
1383 /* FALLTHRU */
1384 case MO_SL:
1385 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1386 break;
1387 case MO_UQ | MO_BSWAP:
1388 if (TCG_TARGET_REG_BITS == 64) {
1389 if (use_mips32r2_instructions) {
1390 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1391 tcg_out_bswap64(s, lo, lo);
1392 } else {
1393 tcg_out_bswap_subr(s, bswap64_addr);
1394 /* delay slot */
1395 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1396 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1397 }
1398 } else if (use_mips32r2_instructions) {
1399 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1400 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1401 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1402 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1403 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1404 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1405 } else {
1406 tcg_out_bswap_subr(s, bswap32_addr);
1407 /* delay slot */
1408 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1409 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1410 tcg_out_bswap_subr(s, bswap32_addr);
1411 /* delay slot */
1412 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1413 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1414 }
1415 break;
1416 case MO_UQ:
1417 /* Prefer to load from offset 0 first, but allow for overlap. */
1418 if (TCG_TARGET_REG_BITS == 64) {
1419 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1420 } else if (MIPS_BE ? hi != base : lo == base) {
1421 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1422 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1423 } else {
1424 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1425 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1426 }
1427 break;
1428 default:
1429 tcg_abort();
1430 }
1431 }
1432
1433 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1434 {
1435 TCGReg addr_regl, addr_regh __attribute__((unused));
1436 TCGReg data_regl, data_regh;
1437 MemOpIdx oi;
1438 MemOp opc;
1439 #if defined(CONFIG_SOFTMMU)
1440 tcg_insn_unit *label_ptr[2];
1441 #endif
1442 TCGReg base = TCG_REG_A0;
1443
1444 data_regl = *args++;
1445 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1446 addr_regl = *args++;
1447 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1448 oi = *args++;
1449 opc = get_memop(oi);
1450
1451 #if defined(CONFIG_SOFTMMU)
1452 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1453 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1454 add_qemu_ldst_label(s, 1, oi,
1455 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1456 data_regl, data_regh, addr_regl, addr_regh,
1457 s->code_ptr, label_ptr);
1458 #else
1459 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1460 tcg_out_ext32u(s, base, addr_regl);
1461 addr_regl = base;
1462 }
1463 if (guest_base == 0 && data_regl != addr_regl) {
1464 base = addr_regl;
1465 } else if (guest_base == (int16_t)guest_base) {
1466 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1467 } else {
1468 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1469 }
1470 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1471 #endif
1472 }
1473
1474 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1475 TCGReg base, MemOp opc)
1476 {
1477 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1478 if ((lo | hi) == 0) {
1479 opc &= ~MO_BSWAP;
1480 }
1481
1482 switch (opc & (MO_SIZE | MO_BSWAP)) {
1483 case MO_8:
1484 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1485 break;
1486
1487 case MO_16 | MO_BSWAP:
1488 tcg_out_bswap16(s, TCG_TMP1, lo, 0);
1489 lo = TCG_TMP1;
1490 /* FALLTHRU */
1491 case MO_16:
1492 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1493 break;
1494
1495 case MO_32 | MO_BSWAP:
1496 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1497 lo = TCG_TMP3;
1498 /* FALLTHRU */
1499 case MO_32:
1500 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1501 break;
1502
1503 case MO_64 | MO_BSWAP:
1504 if (TCG_TARGET_REG_BITS == 64) {
1505 tcg_out_bswap64(s, TCG_TMP3, lo);
1506 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1507 } else if (use_mips32r2_instructions) {
1508 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1509 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1510 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1511 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1512 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1513 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1514 } else {
1515 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1516 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1517 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1518 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1519 }
1520 break;
1521 case MO_64:
1522 if (TCG_TARGET_REG_BITS == 64) {
1523 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1524 } else {
1525 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1526 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1527 }
1528 break;
1529
1530 default:
1531 tcg_abort();
1532 }
1533 }
1534
1535 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1536 {
1537 TCGReg addr_regl, addr_regh __attribute__((unused));
1538 TCGReg data_regl, data_regh;
1539 MemOpIdx oi;
1540 MemOp opc;
1541 #if defined(CONFIG_SOFTMMU)
1542 tcg_insn_unit *label_ptr[2];
1543 #endif
1544 TCGReg base = TCG_REG_A0;
1545
1546 data_regl = *args++;
1547 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1548 addr_regl = *args++;
1549 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1550 oi = *args++;
1551 opc = get_memop(oi);
1552
1553 #if defined(CONFIG_SOFTMMU)
1554 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1555 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1556 add_qemu_ldst_label(s, 0, oi,
1557 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1558 data_regl, data_regh, addr_regl, addr_regh,
1559 s->code_ptr, label_ptr);
1560 #else
1561 base = TCG_REG_A0;
1562 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1563 tcg_out_ext32u(s, base, addr_regl);
1564 addr_regl = base;
1565 }
1566 if (guest_base == 0) {
1567 base = addr_regl;
1568 } else if (guest_base == (int16_t)guest_base) {
1569 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1570 } else {
1571 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1572 }
1573 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1574 #endif
1575 }
1576
1577 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1578 {
1579 static const MIPSInsn sync[] = {
1580 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1581 as the former is an ordering barrier and the latter
1582 is a completion barrier. */
1583 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1584 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1585 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1586 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1587 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1588 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1589 };
1590 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1591 }
1592
1593 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1594 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1595 {
1596 if (use_mips32r6_instructions) {
1597 if (a2 == width) {
1598 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1599 } else {
1600 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1601 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1602 }
1603 } else {
1604 if (a2 == width) {
1605 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1606 } else if (a0 == a2) {
1607 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1608 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1609 } else if (a0 != a1) {
1610 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1611 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1612 } else {
1613 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1614 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1615 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1616 }
1617 }
1618 }
1619
1620 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1621 const TCGArg args[TCG_MAX_OP_ARGS],
1622 const int const_args[TCG_MAX_OP_ARGS])
1623 {
1624 MIPSInsn i1, i2;
1625 TCGArg a0, a1, a2;
1626 int c2;
1627
1628 /*
1629 * Note that many operands use the constraint set "rZ".
1630 * We make use of the fact that 0 is the ZERO register,
1631 * and hence such cases need not check for const_args.
1632 */
1633 a0 = args[0];
1634 a1 = args[1];
1635 a2 = args[2];
1636 c2 = const_args[2];
1637
1638 switch (opc) {
1639 case INDEX_op_exit_tb:
1640 {
1641 TCGReg b0 = TCG_REG_ZERO;
1642
1643 a0 = (intptr_t)a0;
1644 if (a0 & ~0xffff) {
1645 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1646 b0 = TCG_REG_V0;
1647 }
1648 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1649 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
1650 (uintptr_t)tb_ret_addr);
1651 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1652 }
1653 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1654 }
1655 break;
1656 case INDEX_op_goto_tb:
1657 /* indirect jump method */
1658 tcg_debug_assert(s->tb_jmp_insn_offset == 0);
1659 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1660 (uintptr_t)(s->tb_jmp_target_addr + a0));
1661 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1662 tcg_out_nop(s);
1663 set_jmp_reset_offset(s, a0);
1664 break;
1665 case INDEX_op_goto_ptr:
1666 /* jmp to the given host address (could be epilogue) */
1667 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1668 tcg_out_nop(s);
1669 break;
1670 case INDEX_op_br:
1671 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1672 arg_label(a0));
1673 break;
1674
1675 case INDEX_op_ld8u_i32:
1676 case INDEX_op_ld8u_i64:
1677 i1 = OPC_LBU;
1678 goto do_ldst;
1679 case INDEX_op_ld8s_i32:
1680 case INDEX_op_ld8s_i64:
1681 i1 = OPC_LB;
1682 goto do_ldst;
1683 case INDEX_op_ld16u_i32:
1684 case INDEX_op_ld16u_i64:
1685 i1 = OPC_LHU;
1686 goto do_ldst;
1687 case INDEX_op_ld16s_i32:
1688 case INDEX_op_ld16s_i64:
1689 i1 = OPC_LH;
1690 goto do_ldst;
1691 case INDEX_op_ld_i32:
1692 case INDEX_op_ld32s_i64:
1693 i1 = OPC_LW;
1694 goto do_ldst;
1695 case INDEX_op_ld32u_i64:
1696 i1 = OPC_LWU;
1697 goto do_ldst;
1698 case INDEX_op_ld_i64:
1699 i1 = OPC_LD;
1700 goto do_ldst;
1701 case INDEX_op_st8_i32:
1702 case INDEX_op_st8_i64:
1703 i1 = OPC_SB;
1704 goto do_ldst;
1705 case INDEX_op_st16_i32:
1706 case INDEX_op_st16_i64:
1707 i1 = OPC_SH;
1708 goto do_ldst;
1709 case INDEX_op_st_i32:
1710 case INDEX_op_st32_i64:
1711 i1 = OPC_SW;
1712 goto do_ldst;
1713 case INDEX_op_st_i64:
1714 i1 = OPC_SD;
1715 do_ldst:
1716 tcg_out_ldst(s, i1, a0, a1, a2);
1717 break;
1718
1719 case INDEX_op_add_i32:
1720 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1721 goto do_binary;
1722 case INDEX_op_add_i64:
1723 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1724 goto do_binary;
1725 case INDEX_op_or_i32:
1726 case INDEX_op_or_i64:
1727 i1 = OPC_OR, i2 = OPC_ORI;
1728 goto do_binary;
1729 case INDEX_op_xor_i32:
1730 case INDEX_op_xor_i64:
1731 i1 = OPC_XOR, i2 = OPC_XORI;
1732 do_binary:
1733 if (c2) {
1734 tcg_out_opc_imm(s, i2, a0, a1, a2);
1735 break;
1736 }
1737 do_binaryv:
1738 tcg_out_opc_reg(s, i1, a0, a1, a2);
1739 break;
1740
1741 case INDEX_op_sub_i32:
1742 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1743 goto do_subtract;
1744 case INDEX_op_sub_i64:
1745 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1746 do_subtract:
1747 if (c2) {
1748 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1749 break;
1750 }
1751 goto do_binaryv;
1752 case INDEX_op_and_i32:
1753 if (c2 && a2 != (uint16_t)a2) {
1754 int msb = ctz32(~a2) - 1;
1755 tcg_debug_assert(use_mips32r2_instructions);
1756 tcg_debug_assert(is_p2m1(a2));
1757 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1758 break;
1759 }
1760 i1 = OPC_AND, i2 = OPC_ANDI;
1761 goto do_binary;
1762 case INDEX_op_and_i64:
1763 if (c2 && a2 != (uint16_t)a2) {
1764 int msb = ctz64(~a2) - 1;
1765 tcg_debug_assert(use_mips32r2_instructions);
1766 tcg_debug_assert(is_p2m1(a2));
1767 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1768 break;
1769 }
1770 i1 = OPC_AND, i2 = OPC_ANDI;
1771 goto do_binary;
1772 case INDEX_op_nor_i32:
1773 case INDEX_op_nor_i64:
1774 i1 = OPC_NOR;
1775 goto do_binaryv;
1776
1777 case INDEX_op_mul_i32:
1778 if (use_mips32_instructions) {
1779 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1780 break;
1781 }
1782 i1 = OPC_MULT, i2 = OPC_MFLO;
1783 goto do_hilo1;
1784 case INDEX_op_mulsh_i32:
1785 if (use_mips32r6_instructions) {
1786 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1787 break;
1788 }
1789 i1 = OPC_MULT, i2 = OPC_MFHI;
1790 goto do_hilo1;
1791 case INDEX_op_muluh_i32:
1792 if (use_mips32r6_instructions) {
1793 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1794 break;
1795 }
1796 i1 = OPC_MULTU, i2 = OPC_MFHI;
1797 goto do_hilo1;
1798 case INDEX_op_div_i32:
1799 if (use_mips32r6_instructions) {
1800 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1801 break;
1802 }
1803 i1 = OPC_DIV, i2 = OPC_MFLO;
1804 goto do_hilo1;
1805 case INDEX_op_divu_i32:
1806 if (use_mips32r6_instructions) {
1807 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1808 break;
1809 }
1810 i1 = OPC_DIVU, i2 = OPC_MFLO;
1811 goto do_hilo1;
1812 case INDEX_op_rem_i32:
1813 if (use_mips32r6_instructions) {
1814 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1815 break;
1816 }
1817 i1 = OPC_DIV, i2 = OPC_MFHI;
1818 goto do_hilo1;
1819 case INDEX_op_remu_i32:
1820 if (use_mips32r6_instructions) {
1821 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1822 break;
1823 }
1824 i1 = OPC_DIVU, i2 = OPC_MFHI;
1825 goto do_hilo1;
1826 case INDEX_op_mul_i64:
1827 if (use_mips32r6_instructions) {
1828 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1829 break;
1830 }
1831 i1 = OPC_DMULT, i2 = OPC_MFLO;
1832 goto do_hilo1;
1833 case INDEX_op_mulsh_i64:
1834 if (use_mips32r6_instructions) {
1835 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1836 break;
1837 }
1838 i1 = OPC_DMULT, i2 = OPC_MFHI;
1839 goto do_hilo1;
1840 case INDEX_op_muluh_i64:
1841 if (use_mips32r6_instructions) {
1842 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1843 break;
1844 }
1845 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1846 goto do_hilo1;
1847 case INDEX_op_div_i64:
1848 if (use_mips32r6_instructions) {
1849 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1850 break;
1851 }
1852 i1 = OPC_DDIV, i2 = OPC_MFLO;
1853 goto do_hilo1;
1854 case INDEX_op_divu_i64:
1855 if (use_mips32r6_instructions) {
1856 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1857 break;
1858 }
1859 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1860 goto do_hilo1;
1861 case INDEX_op_rem_i64:
1862 if (use_mips32r6_instructions) {
1863 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1864 break;
1865 }
1866 i1 = OPC_DDIV, i2 = OPC_MFHI;
1867 goto do_hilo1;
1868 case INDEX_op_remu_i64:
1869 if (use_mips32r6_instructions) {
1870 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1871 break;
1872 }
1873 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1874 do_hilo1:
1875 tcg_out_opc_reg(s, i1, 0, a1, a2);
1876 tcg_out_opc_reg(s, i2, a0, 0, 0);
1877 break;
1878
1879 case INDEX_op_muls2_i32:
1880 i1 = OPC_MULT;
1881 goto do_hilo2;
1882 case INDEX_op_mulu2_i32:
1883 i1 = OPC_MULTU;
1884 goto do_hilo2;
1885 case INDEX_op_muls2_i64:
1886 i1 = OPC_DMULT;
1887 goto do_hilo2;
1888 case INDEX_op_mulu2_i64:
1889 i1 = OPC_DMULTU;
1890 do_hilo2:
1891 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1892 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1893 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1894 break;
1895
1896 case INDEX_op_not_i32:
1897 case INDEX_op_not_i64:
1898 i1 = OPC_NOR;
1899 goto do_unary;
1900 case INDEX_op_ext8s_i32:
1901 case INDEX_op_ext8s_i64:
1902 i1 = OPC_SEB;
1903 goto do_unary;
1904 case INDEX_op_ext16s_i32:
1905 case INDEX_op_ext16s_i64:
1906 i1 = OPC_SEH;
1907 do_unary:
1908 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1909 break;
1910
1911 case INDEX_op_bswap16_i32:
1912 case INDEX_op_bswap16_i64:
1913 tcg_out_bswap16(s, a0, a1, a2);
1914 break;
1915 case INDEX_op_bswap32_i32:
1916 tcg_out_bswap32(s, a0, a1, 0);
1917 break;
1918 case INDEX_op_bswap32_i64:
1919 tcg_out_bswap32(s, a0, a1, a2);
1920 break;
1921 case INDEX_op_bswap64_i64:
1922 tcg_out_bswap64(s, a0, a1);
1923 break;
1924 case INDEX_op_extrh_i64_i32:
1925 tcg_out_dsra(s, a0, a1, 32);
1926 break;
1927 case INDEX_op_ext32s_i64:
1928 case INDEX_op_ext_i32_i64:
1929 case INDEX_op_extrl_i64_i32:
1930 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
1931 break;
1932 case INDEX_op_ext32u_i64:
1933 case INDEX_op_extu_i32_i64:
1934 tcg_out_ext32u(s, a0, a1);
1935 break;
1936
1937 case INDEX_op_sar_i32:
1938 i1 = OPC_SRAV, i2 = OPC_SRA;
1939 goto do_shift;
1940 case INDEX_op_shl_i32:
1941 i1 = OPC_SLLV, i2 = OPC_SLL;
1942 goto do_shift;
1943 case INDEX_op_shr_i32:
1944 i1 = OPC_SRLV, i2 = OPC_SRL;
1945 goto do_shift;
1946 case INDEX_op_rotr_i32:
1947 i1 = OPC_ROTRV, i2 = OPC_ROTR;
1948 do_shift:
1949 if (c2) {
1950 tcg_out_opc_sa(s, i2, a0, a1, a2);
1951 break;
1952 }
1953 do_shiftv:
1954 tcg_out_opc_reg(s, i1, a0, a2, a1);
1955 break;
1956 case INDEX_op_rotl_i32:
1957 if (c2) {
1958 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
1959 } else {
1960 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
1961 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
1962 }
1963 break;
1964 case INDEX_op_sar_i64:
1965 if (c2) {
1966 tcg_out_dsra(s, a0, a1, a2);
1967 break;
1968 }
1969 i1 = OPC_DSRAV;
1970 goto do_shiftv;
1971 case INDEX_op_shl_i64:
1972 if (c2) {
1973 tcg_out_dsll(s, a0, a1, a2);
1974 break;
1975 }
1976 i1 = OPC_DSLLV;
1977 goto do_shiftv;
1978 case INDEX_op_shr_i64:
1979 if (c2) {
1980 tcg_out_dsrl(s, a0, a1, a2);
1981 break;
1982 }
1983 i1 = OPC_DSRLV;
1984 goto do_shiftv;
1985 case INDEX_op_rotr_i64:
1986 if (c2) {
1987 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
1988 break;
1989 }
1990 i1 = OPC_DROTRV;
1991 goto do_shiftv;
1992 case INDEX_op_rotl_i64:
1993 if (c2) {
1994 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
1995 } else {
1996 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
1997 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
1998 }
1999 break;
2000
2001 case INDEX_op_clz_i32:
2002 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2003 break;
2004 case INDEX_op_clz_i64:
2005 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2006 break;
2007
2008 case INDEX_op_deposit_i32:
2009 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2010 break;
2011 case INDEX_op_deposit_i64:
2012 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2013 args[3] + args[4] - 1, args[3]);
2014 break;
2015 case INDEX_op_extract_i32:
2016 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2017 break;
2018 case INDEX_op_extract_i64:
2019 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2020 args[3] - 1, a2);
2021 break;
2022
2023 case INDEX_op_brcond_i32:
2024 case INDEX_op_brcond_i64:
2025 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2026 break;
2027 case INDEX_op_brcond2_i32:
2028 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2029 break;
2030
2031 case INDEX_op_movcond_i32:
2032 case INDEX_op_movcond_i64:
2033 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2034 break;
2035
2036 case INDEX_op_setcond_i32:
2037 case INDEX_op_setcond_i64:
2038 tcg_out_setcond(s, args[3], a0, a1, a2);
2039 break;
2040 case INDEX_op_setcond2_i32:
2041 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2042 break;
2043
2044 case INDEX_op_qemu_ld_i32:
2045 tcg_out_qemu_ld(s, args, false);
2046 break;
2047 case INDEX_op_qemu_ld_i64:
2048 tcg_out_qemu_ld(s, args, true);
2049 break;
2050 case INDEX_op_qemu_st_i32:
2051 tcg_out_qemu_st(s, args, false);
2052 break;
2053 case INDEX_op_qemu_st_i64:
2054 tcg_out_qemu_st(s, args, true);
2055 break;
2056
2057 case INDEX_op_add2_i32:
2058 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2059 const_args[4], const_args[5], false);
2060 break;
2061 case INDEX_op_sub2_i32:
2062 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2063 const_args[4], const_args[5], true);
2064 break;
2065
2066 case INDEX_op_mb:
2067 tcg_out_mb(s, a0);
2068 break;
2069 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2070 case INDEX_op_mov_i64:
2071 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2072 default:
2073 tcg_abort();
2074 }
2075 }
2076
2077 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2078 {
2079 switch (op) {
2080 case INDEX_op_goto_ptr:
2081 return C_O0_I1(r);
2082
2083 case INDEX_op_ld8u_i32:
2084 case INDEX_op_ld8s_i32:
2085 case INDEX_op_ld16u_i32:
2086 case INDEX_op_ld16s_i32:
2087 case INDEX_op_ld_i32:
2088 case INDEX_op_not_i32:
2089 case INDEX_op_bswap16_i32:
2090 case INDEX_op_bswap32_i32:
2091 case INDEX_op_ext8s_i32:
2092 case INDEX_op_ext16s_i32:
2093 case INDEX_op_extract_i32:
2094 case INDEX_op_ld8u_i64:
2095 case INDEX_op_ld8s_i64:
2096 case INDEX_op_ld16u_i64:
2097 case INDEX_op_ld16s_i64:
2098 case INDEX_op_ld32s_i64:
2099 case INDEX_op_ld32u_i64:
2100 case INDEX_op_ld_i64:
2101 case INDEX_op_not_i64:
2102 case INDEX_op_bswap16_i64:
2103 case INDEX_op_bswap32_i64:
2104 case INDEX_op_bswap64_i64:
2105 case INDEX_op_ext8s_i64:
2106 case INDEX_op_ext16s_i64:
2107 case INDEX_op_ext32s_i64:
2108 case INDEX_op_ext32u_i64:
2109 case INDEX_op_ext_i32_i64:
2110 case INDEX_op_extu_i32_i64:
2111 case INDEX_op_extrl_i64_i32:
2112 case INDEX_op_extrh_i64_i32:
2113 case INDEX_op_extract_i64:
2114 return C_O1_I1(r, r);
2115
2116 case INDEX_op_st8_i32:
2117 case INDEX_op_st16_i32:
2118 case INDEX_op_st_i32:
2119 case INDEX_op_st8_i64:
2120 case INDEX_op_st16_i64:
2121 case INDEX_op_st32_i64:
2122 case INDEX_op_st_i64:
2123 return C_O0_I2(rZ, r);
2124
2125 case INDEX_op_add_i32:
2126 case INDEX_op_add_i64:
2127 return C_O1_I2(r, r, rJ);
2128 case INDEX_op_sub_i32:
2129 case INDEX_op_sub_i64:
2130 return C_O1_I2(r, rZ, rN);
2131 case INDEX_op_mul_i32:
2132 case INDEX_op_mulsh_i32:
2133 case INDEX_op_muluh_i32:
2134 case INDEX_op_div_i32:
2135 case INDEX_op_divu_i32:
2136 case INDEX_op_rem_i32:
2137 case INDEX_op_remu_i32:
2138 case INDEX_op_nor_i32:
2139 case INDEX_op_setcond_i32:
2140 case INDEX_op_mul_i64:
2141 case INDEX_op_mulsh_i64:
2142 case INDEX_op_muluh_i64:
2143 case INDEX_op_div_i64:
2144 case INDEX_op_divu_i64:
2145 case INDEX_op_rem_i64:
2146 case INDEX_op_remu_i64:
2147 case INDEX_op_nor_i64:
2148 case INDEX_op_setcond_i64:
2149 return C_O1_I2(r, rZ, rZ);
2150 case INDEX_op_muls2_i32:
2151 case INDEX_op_mulu2_i32:
2152 case INDEX_op_muls2_i64:
2153 case INDEX_op_mulu2_i64:
2154 return C_O2_I2(r, r, r, r);
2155 case INDEX_op_and_i32:
2156 case INDEX_op_and_i64:
2157 return C_O1_I2(r, r, rIK);
2158 case INDEX_op_or_i32:
2159 case INDEX_op_xor_i32:
2160 case INDEX_op_or_i64:
2161 case INDEX_op_xor_i64:
2162 return C_O1_I2(r, r, rI);
2163 case INDEX_op_shl_i32:
2164 case INDEX_op_shr_i32:
2165 case INDEX_op_sar_i32:
2166 case INDEX_op_rotr_i32:
2167 case INDEX_op_rotl_i32:
2168 case INDEX_op_shl_i64:
2169 case INDEX_op_shr_i64:
2170 case INDEX_op_sar_i64:
2171 case INDEX_op_rotr_i64:
2172 case INDEX_op_rotl_i64:
2173 return C_O1_I2(r, r, ri);
2174 case INDEX_op_clz_i32:
2175 case INDEX_op_clz_i64:
2176 return C_O1_I2(r, r, rWZ);
2177
2178 case INDEX_op_deposit_i32:
2179 case INDEX_op_deposit_i64:
2180 return C_O1_I2(r, 0, rZ);
2181 case INDEX_op_brcond_i32:
2182 case INDEX_op_brcond_i64:
2183 return C_O0_I2(rZ, rZ);
2184 case INDEX_op_movcond_i32:
2185 case INDEX_op_movcond_i64:
2186 return (use_mips32r6_instructions
2187 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2188 : C_O1_I4(r, rZ, rZ, rZ, 0));
2189 case INDEX_op_add2_i32:
2190 case INDEX_op_sub2_i32:
2191 return C_O2_I4(r, r, rZ, rZ, rN, rN);
2192 case INDEX_op_setcond2_i32:
2193 return C_O1_I4(r, rZ, rZ, rZ, rZ);
2194 case INDEX_op_brcond2_i32:
2195 return C_O0_I4(rZ, rZ, rZ, rZ);
2196
2197 case INDEX_op_qemu_ld_i32:
2198 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2199 ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
2200 case INDEX_op_qemu_st_i32:
2201 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2202 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
2203 case INDEX_op_qemu_ld_i64:
2204 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
2205 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
2206 : C_O2_I2(r, r, L, L));
2207 case INDEX_op_qemu_st_i64:
2208 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
2209 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
2210 : C_O0_I4(SZ, SZ, S, S));
2211
2212 default:
2213 g_assert_not_reached();
2214 }
2215 }
2216
2217 static const int tcg_target_callee_save_regs[] = {
2218 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2219 TCG_REG_S1,
2220 TCG_REG_S2,
2221 TCG_REG_S3,
2222 TCG_REG_S4,
2223 TCG_REG_S5,
2224 TCG_REG_S6,
2225 TCG_REG_S7,
2226 TCG_REG_S8,
2227 TCG_REG_RA, /* should be last for ABI compliance */
2228 };
2229
2230 /* The Linux kernel doesn't provide any information about the available
2231 instruction set. Probe it using a signal handler. */
2232
2233
2234 #ifndef use_movnz_instructions
2235 bool use_movnz_instructions = false;
2236 #endif
2237
2238 #ifndef use_mips32_instructions
2239 bool use_mips32_instructions = false;
2240 #endif
2241
2242 #ifndef use_mips32r2_instructions
2243 bool use_mips32r2_instructions = false;
2244 #endif
2245
2246 static volatile sig_atomic_t got_sigill;
2247
2248 static void sigill_handler(int signo, siginfo_t *si, void *data)
2249 {
2250 /* Skip the faulty instruction */
2251 ucontext_t *uc = (ucontext_t *)data;
2252 uc->uc_mcontext.pc += 4;
2253
2254 got_sigill = 1;
2255 }
2256
2257 static void tcg_target_detect_isa(void)
2258 {
2259 struct sigaction sa_old, sa_new;
2260
2261 memset(&sa_new, 0, sizeof(sa_new));
2262 sa_new.sa_flags = SA_SIGINFO;
2263 sa_new.sa_sigaction = sigill_handler;
2264 sigaction(SIGILL, &sa_new, &sa_old);
2265
2266 /* Probe for movn/movz, necessary to implement movcond. */
2267 #ifndef use_movnz_instructions
2268 got_sigill = 0;
2269 asm volatile(".set push\n"
2270 ".set mips32\n"
2271 "movn $zero, $zero, $zero\n"
2272 "movz $zero, $zero, $zero\n"
2273 ".set pop\n"
2274 : : : );
2275 use_movnz_instructions = !got_sigill;
2276 #endif
2277
2278 /* Probe for MIPS32 instructions. As no subsetting is allowed
2279 by the specification, it is only necessary to probe for one
2280 of the instructions. */
2281 #ifndef use_mips32_instructions
2282 got_sigill = 0;
2283 asm volatile(".set push\n"
2284 ".set mips32\n"
2285 "mul $zero, $zero\n"
2286 ".set pop\n"
2287 : : : );
2288 use_mips32_instructions = !got_sigill;
2289 #endif
2290
2291 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2292 available. As no subsetting is allowed by the specification,
2293 it is only necessary to probe for one of the instructions. */
2294 #ifndef use_mips32r2_instructions
2295 if (use_mips32_instructions) {
2296 got_sigill = 0;
2297 asm volatile(".set push\n"
2298 ".set mips32r2\n"
2299 "seb $zero, $zero\n"
2300 ".set pop\n"
2301 : : : );
2302 use_mips32r2_instructions = !got_sigill;
2303 }
2304 #endif
2305
2306 sigaction(SIGILL, &sa_old, NULL);
2307 }
2308
2309 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2310 {
2311 uintptr_t p = (uintptr_t)s->code_ptr;
2312 if (p & 15) {
2313 p = (p + 15) & -16;
2314 s->code_ptr = (void *)p;
2315 }
2316 return s->code_ptr;
2317 }
2318
2319 /* Stack frame parameters. */
2320 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2321 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2322 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2323
2324 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2325 + TCG_TARGET_STACK_ALIGN - 1) \
2326 & -TCG_TARGET_STACK_ALIGN)
2327 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2328
2329 /* We're expecting to be able to use an immediate for frame allocation. */
2330 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2331
2332 /* Generate global QEMU prologue and epilogue code */
2333 static void tcg_target_qemu_prologue(TCGContext *s)
2334 {
2335 int i;
2336
2337 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2338
2339 /* TB prologue */
2340 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2341 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2342 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2343 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2344 }
2345
2346 #ifndef CONFIG_SOFTMMU
2347 if (guest_base) {
2348 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2349 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2350 }
2351 #endif
2352
2353 /* Call generated code */
2354 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2355 /* delay slot */
2356 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2357
2358 /*
2359 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2360 * and fall through to the rest of the epilogue.
2361 */
2362 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2363 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2364
2365 /* TB epilogue */
2366 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2367 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2368 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2369 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2370 }
2371
2372 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2373 /* delay slot */
2374 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2375
2376 if (use_mips32r2_instructions) {
2377 return;
2378 }
2379
2380 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2381 clobbers TCG_TMP1, TCG_TMP2. */
2382
2383 /*
2384 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2385 */
2386 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2387 /* t3 = (ssss)d000 */
2388 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2389 /* t1 = 000a */
2390 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2391 /* t2 = 00c0 */
2392 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2393 /* t3 = d00a */
2394 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2395 /* t1 = 0abc */
2396 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2397 /* t2 = 0c00 */
2398 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2399 /* t1 = 00b0 */
2400 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2401 /* t3 = dc0a */
2402 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2403 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2404 /* t3 = dcba -- delay slot */
2405 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2406
2407 if (TCG_TARGET_REG_BITS == 32) {
2408 return;
2409 }
2410
2411 /*
2412 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2413 */
2414 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2415 /* t1 = (0000)000d */
2416 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2417 /* t3 = 000a */
2418 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2419 /* t1 = (0000)d000 */
2420 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2421 /* t2 = 00c0 */
2422 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2423 /* t3 = d00a */
2424 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2425 /* t1 = 0abc */
2426 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2427 /* t2 = 0c00 */
2428 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2429 /* t1 = 00b0 */
2430 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2431 /* t3 = dc0a */
2432 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2433 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2434 /* t3 = dcba -- delay slot */
2435 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2436
2437 /*
2438 * bswap64 -- 64-bit swap. a0 = abcdefgh
2439 */
2440 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2441 /* t3 = h0000000 */
2442 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2443 /* t1 = 0000000a */
2444 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2445
2446 /* t2 = 000000g0 */
2447 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2448 /* t3 = h000000a */
2449 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2450 /* t1 = 00000abc */
2451 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2452 /* t2 = 0g000000 */
2453 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2454 /* t1 = 000000b0 */
2455 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2456
2457 /* t3 = hg00000a */
2458 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2459 /* t2 = 0000abcd */
2460 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2461 /* t3 = hg0000ba */
2462 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2463
2464 /* t1 = 000000c0 */
2465 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2466 /* t2 = 0000000d */
2467 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2468 /* t1 = 00000c00 */
2469 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2470 /* t2 = 0000d000 */
2471 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2472
2473 /* t3 = hg000cba */
2474 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2475 /* t1 = 00abcdef */
2476 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2477 /* t3 = hg00dcba */
2478 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2479
2480 /* t2 = 0000000f */
2481 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2482 /* t1 = 000000e0 */
2483 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2484 /* t2 = 00f00000 */
2485 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2486 /* t1 = 000e0000 */
2487 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2488
2489 /* t3 = hgf0dcba */
2490 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2491 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2492 /* t3 = hgfedcba -- delay slot */
2493 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2494 }
2495
2496 static void tcg_target_init(TCGContext *s)
2497 {
2498 tcg_target_detect_isa();
2499 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2500 if (TCG_TARGET_REG_BITS == 64) {
2501 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2502 }
2503
2504 tcg_target_call_clobber_regs = 0;
2505 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2506 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2507 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2508 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2509 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2510 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2511 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2512 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2513 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2514 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2515 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2516 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2517 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2518 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2519 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2520 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2521
2522 s->reserved_regs = 0;
2523 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2524 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2525 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2526 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2527 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2528 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2529 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2530 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2531 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2532 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2533 }
2534
2535 typedef struct {
2536 DebugFrameHeader h;
2537 uint8_t fde_def_cfa[4];
2538 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2539 } DebugFrame;
2540
2541 #define ELF_HOST_MACHINE EM_MIPS
2542 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2543 which is good because they're really quite complicated for MIPS. */
2544
2545 static const DebugFrame debug_frame = {
2546 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2547 .h.cie.id = -1,
2548 .h.cie.version = 1,
2549 .h.cie.code_align = 1,
2550 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2551 .h.cie.return_column = TCG_REG_RA,
2552
2553 /* Total FDE size does not include the "len" member. */
2554 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2555
2556 .fde_def_cfa = {
2557 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2558 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2559 (FRAME_SIZE >> 7)
2560 },
2561 .fde_reg_ofs = {
2562 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2563 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2564 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2565 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2566 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2567 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2568 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2569 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2570 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2571 }
2572 };
2573
2574 void tcg_register_jit(const void *buf, size_t buf_size)
2575 {
2576 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2577 }
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