2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "../tcg-ldst.c.inc"
35 #if TCG_TARGET_REG_BITS == 32
36 # define LO_OFF (MIPS_BE * 4)
37 # define HI_OFF (4 - LO_OFF)
39 /* To assert at compile-time that these values are never used
40 for TCG_TARGET_REG_BITS == 64. */
42 # define LO_OFF link_error()
43 # define HI_OFF link_error()
46 #ifdef CONFIG_DEBUG_TCG
47 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
83 #define TCG_TMP0 TCG_REG_AT
84 #define TCG_TMP1 TCG_REG_T9
85 #define TCG_TMP2 TCG_REG_T8
86 #define TCG_TMP3 TCG_REG_T7
88 #ifndef CONFIG_SOFTMMU
89 #define TCG_GUEST_BASE_REG TCG_REG_S1
92 /* check if we really need so many registers :P */
93 static const int tcg_target_reg_alloc_order[] = {
94 /* Call saved registers. */
105 /* Call clobbered registers. */
115 /* Argument registers, opposite order of allocation. */
126 static const TCGReg tcg_target_call_iarg_regs[] = {
131 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
139 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
142 tcg_debug_assert(slot >= 0 && slot <= 1);
143 return TCG_REG_V0 + slot;
146 static const tcg_insn_unit *tb_ret_addr;
147 static const tcg_insn_unit *bswap32_addr;
148 static const tcg_insn_unit *bswap32u_addr;
149 static const tcg_insn_unit *bswap64_addr;
151 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
153 /* Let the compiler perform the right-shift as part of the arithmetic. */
154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
155 ptrdiff_t disp = target - (src_rx + 1);
156 if (disp == (int16_t)disp) {
157 *src_rw = deposit32(*src_rw, 0, 16, disp);
163 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
164 intptr_t value, intptr_t addend)
166 tcg_debug_assert(type == R_MIPS_PC16);
167 tcg_debug_assert(addend == 0);
168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
171 #define TCG_CT_CONST_ZERO 0x100
172 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
173 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
174 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
175 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
176 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
178 #define ALL_GENERAL_REGS 0xffffffffu
179 #define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
181 #ifdef CONFIG_SOFTMMU
182 #define ALL_QLOAD_REGS \
183 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
184 #define ALL_QSTORE_REGS \
185 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
186 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
187 : (1 << TCG_REG_A1)))
189 #define ALL_QLOAD_REGS NOA0_REGS
190 #define ALL_QSTORE_REGS NOA0_REGS
194 static bool is_p2m1(tcg_target_long val)
196 return val && ((val + 1) & val) == 0;
199 /* test if a constant matches the constraint */
200 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
202 if (ct & TCG_CT_CONST) {
204 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
212 } else if ((ct & TCG_CT_CONST_P2M1)
213 && use_mips32r2_instructions && is_p2m1(val)) {
215 } else if ((ct & TCG_CT_CONST_WSZ)
216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
222 /* instruction opcodes */
228 OPC_BLEZ = 006 << 26,
229 OPC_BGTZ = 007 << 26,
230 OPC_ADDIU = 011 << 26,
231 OPC_SLTI = 012 << 26,
232 OPC_SLTIU = 013 << 26,
233 OPC_ANDI = 014 << 26,
235 OPC_XORI = 016 << 26,
237 OPC_BNEL = 025 << 26,
238 OPC_BNEZALC_R6 = 030 << 26,
239 OPC_DADDIU = 031 << 26,
260 OPC_SPECIAL = 000 << 26,
261 OPC_SLL = OPC_SPECIAL | 000,
262 OPC_SRL = OPC_SPECIAL | 002,
263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
264 OPC_SRA = OPC_SPECIAL | 003,
265 OPC_SLLV = OPC_SPECIAL | 004,
266 OPC_SRLV = OPC_SPECIAL | 006,
267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
268 OPC_SRAV = OPC_SPECIAL | 007,
269 OPC_JR_R5 = OPC_SPECIAL | 010,
270 OPC_JALR = OPC_SPECIAL | 011,
271 OPC_MOVZ = OPC_SPECIAL | 012,
272 OPC_MOVN = OPC_SPECIAL | 013,
273 OPC_SYNC = OPC_SPECIAL | 017,
274 OPC_MFHI = OPC_SPECIAL | 020,
275 OPC_MFLO = OPC_SPECIAL | 022,
276 OPC_DSLLV = OPC_SPECIAL | 024,
277 OPC_DSRLV = OPC_SPECIAL | 026,
278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
279 OPC_DSRAV = OPC_SPECIAL | 027,
280 OPC_MULT = OPC_SPECIAL | 030,
281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
282 OPC_MUH = OPC_SPECIAL | 030 | 0300,
283 OPC_MULTU = OPC_SPECIAL | 031,
284 OPC_MULU = OPC_SPECIAL | 031 | 0200,
285 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
286 OPC_DIV = OPC_SPECIAL | 032,
287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
288 OPC_MOD = OPC_SPECIAL | 032 | 0300,
289 OPC_DIVU = OPC_SPECIAL | 033,
290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
291 OPC_MODU = OPC_SPECIAL | 033 | 0300,
292 OPC_DMULT = OPC_SPECIAL | 034,
293 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
294 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
295 OPC_DMULTU = OPC_SPECIAL | 035,
296 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
298 OPC_DDIV = OPC_SPECIAL | 036,
299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
300 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
301 OPC_DDIVU = OPC_SPECIAL | 037,
302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
303 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
304 OPC_ADDU = OPC_SPECIAL | 041,
305 OPC_SUBU = OPC_SPECIAL | 043,
306 OPC_AND = OPC_SPECIAL | 044,
307 OPC_OR = OPC_SPECIAL | 045,
308 OPC_XOR = OPC_SPECIAL | 046,
309 OPC_NOR = OPC_SPECIAL | 047,
310 OPC_SLT = OPC_SPECIAL | 052,
311 OPC_SLTU = OPC_SPECIAL | 053,
312 OPC_DADDU = OPC_SPECIAL | 055,
313 OPC_DSUBU = OPC_SPECIAL | 057,
314 OPC_SELEQZ = OPC_SPECIAL | 065,
315 OPC_SELNEZ = OPC_SPECIAL | 067,
316 OPC_DSLL = OPC_SPECIAL | 070,
317 OPC_DSRL = OPC_SPECIAL | 072,
318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
319 OPC_DSRA = OPC_SPECIAL | 073,
320 OPC_DSLL32 = OPC_SPECIAL | 074,
321 OPC_DSRL32 = OPC_SPECIAL | 076,
322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
323 OPC_DSRA32 = OPC_SPECIAL | 077,
324 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
327 OPC_REGIMM = 001 << 26,
328 OPC_BLTZ = OPC_REGIMM | (000 << 16),
329 OPC_BGEZ = OPC_REGIMM | (001 << 16),
331 OPC_SPECIAL2 = 034 << 26,
332 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
333 OPC_CLZ = OPC_SPECIAL2 | 040,
334 OPC_DCLZ = OPC_SPECIAL2 | 044,
336 OPC_SPECIAL3 = 037 << 26,
337 OPC_EXT = OPC_SPECIAL3 | 000,
338 OPC_DEXTM = OPC_SPECIAL3 | 001,
339 OPC_DEXTU = OPC_SPECIAL3 | 002,
340 OPC_DEXT = OPC_SPECIAL3 | 003,
341 OPC_INS = OPC_SPECIAL3 | 004,
342 OPC_DINSM = OPC_SPECIAL3 | 005,
343 OPC_DINSU = OPC_SPECIAL3 | 006,
344 OPC_DINS = OPC_SPECIAL3 | 007,
345 OPC_WSBH = OPC_SPECIAL3 | 00240,
346 OPC_DSBH = OPC_SPECIAL3 | 00244,
347 OPC_DSHD = OPC_SPECIAL3 | 00544,
348 OPC_SEB = OPC_SPECIAL3 | 02040,
349 OPC_SEH = OPC_SPECIAL3 | 03040,
351 /* MIPS r6 doesn't have JR, JALR should be used instead */
352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
355 * MIPS r6 replaces MUL with an alternative encoding which is
356 * backwards-compatible at the assembly level.
358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
360 /* MIPS r6 introduced names for weaker variants of SYNC. These are
361 backward compatible to previous architecture revisions. */
362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
368 /* Aliases for convenience. */
369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
371 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
372 ? OPC_SRL : OPC_DSRL,
378 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
379 TCGReg rd, TCGReg rs, TCGReg rt)
384 inst |= (rs & 0x1F) << 21;
385 inst |= (rt & 0x1F) << 16;
386 inst |= (rd & 0x1F) << 11;
393 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
394 TCGReg rt, TCGReg rs, TCGArg imm)
399 inst |= (rs & 0x1F) << 21;
400 inst |= (rt & 0x1F) << 16;
401 inst |= (imm & 0xffff);
408 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
409 TCGReg rs, int msb, int lsb)
414 inst |= (rs & 0x1F) << 21;
415 inst |= (rt & 0x1F) << 16;
416 inst |= (msb & 0x1F) << 11;
417 inst |= (lsb & 0x1F) << 6;
421 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
422 MIPSInsn oph, TCGReg rt, TCGReg rs,
429 } else if (msb >= 32) {
433 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
439 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
441 tcg_out_opc_imm(s, opc, rt, rs, 0);
447 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
448 TCGReg rd, TCGReg rt, TCGArg sa)
453 inst |= (rt & 0x1F) << 16;
454 inst |= (rd & 0x1F) << 11;
455 inst |= (sa & 0x1F) << 6;
460 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
461 TCGReg rd, TCGReg rt, TCGArg sa)
465 inst = (sa & 32 ? opc2 : opc1);
466 inst |= (rt & 0x1F) << 16;
467 inst |= (rd & 0x1F) << 11;
468 inst |= (sa & 0x1F) << 6;
474 * Returns true if the branch was in range and the insn was emitted.
476 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
478 uintptr_t dest = (uintptr_t)target;
479 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
482 /* The pc-region branch happens within the 256MB region of
483 the delay slot (thus the +4). */
484 if ((from ^ dest) & -(1 << 28)) {
487 tcg_debug_assert((dest & 3) == 0);
490 inst |= (dest >> 2) & 0x3ffffff;
495 static void tcg_out_nop(TCGContext *s)
500 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
502 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
505 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
507 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
510 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
512 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
515 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
517 /* Simple reg-reg move, optimising out the 'do nothing' case */
519 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
524 static void tcg_out_movi(TCGContext *s, TCGType type,
525 TCGReg ret, tcg_target_long arg)
527 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
530 if (arg == (int16_t)arg) {
531 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
534 if (arg == (uint16_t)arg) {
535 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
538 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
539 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
541 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
542 if (arg & 0xffff0000ull) {
543 tcg_out_dsll(s, ret, ret, 16);
544 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
545 tcg_out_dsll(s, ret, ret, 16);
547 tcg_out_dsll(s, ret, ret, 32);
551 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
555 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
557 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
558 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
561 static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
563 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
566 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
568 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32);
569 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs);
572 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
575 /* This function is only used for passing structs by reference. */
576 g_assert_not_reached();
579 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
581 /* ret and arg can't be register tmp0 */
582 tcg_debug_assert(ret != TCG_TMP0);
583 tcg_debug_assert(arg != TCG_TMP0);
585 /* With arg = abcd: */
586 if (use_mips32r2_instructions) {
587 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
588 if (flags & TCG_BSWAP_OS) {
589 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
590 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
591 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
596 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
597 if (!(flags & TCG_BSWAP_IZ)) {
598 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
600 if (flags & TCG_BSWAP_OS) {
601 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
602 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
604 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
605 if (flags & TCG_BSWAP_OZ) {
606 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
609 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
612 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
614 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
615 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
616 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
620 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
622 if (use_mips32r2_instructions) {
623 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
624 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
625 if (flags & TCG_BSWAP_OZ) {
626 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
629 if (flags & TCG_BSWAP_OZ) {
630 tcg_out_bswap_subr(s, bswap32u_addr);
632 tcg_out_bswap_subr(s, bswap32_addr);
634 /* delay slot -- never omit the insn, like tcg_out_mov might. */
635 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
636 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
640 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
642 if (use_mips32r2_instructions) {
643 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
644 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
646 tcg_out_bswap_subr(s, bswap64_addr);
647 /* delay slot -- never omit the insn, like tcg_out_mov might. */
648 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
649 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
653 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
655 if (use_mips32r2_instructions) {
656 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
658 tcg_out_dsll(s, ret, arg, 32);
659 tcg_out_dsrl(s, ret, ret, 32);
663 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
664 TCGReg addr, intptr_t ofs)
668 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
669 if (addr != TCG_REG_ZERO) {
670 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
674 tcg_out_opc_imm(s, opc, data, addr, lo);
677 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
678 TCGReg arg1, intptr_t arg2)
680 MIPSInsn opc = OPC_LD;
681 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
684 tcg_out_ldst(s, opc, arg, arg1, arg2);
687 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
688 TCGReg arg1, intptr_t arg2)
690 MIPSInsn opc = OPC_SD;
691 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
694 tcg_out_ldst(s, opc, arg, arg1, arg2);
697 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
698 TCGReg base, intptr_t ofs)
701 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
707 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
708 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
709 bool cbh, bool is_sub)
711 TCGReg th = TCG_TMP1;
713 /* If we have a negative constant such that negating it would
714 make the high part zero, we can (usually) eliminate one insn. */
715 if (cbl && cbh && bh == -1 && bl != 0) {
721 /* By operating on the high part first, we get to use the final
722 carry operation to move back from the temporary. */
724 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
725 } else if (bh != 0 || ah == rl) {
726 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
731 /* Note that tcg optimization should eliminate the bl == 0 case. */
734 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
735 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
737 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
738 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
740 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
743 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
744 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
745 } else if (rl == al && rl == bl) {
746 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
747 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
749 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
750 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
752 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
756 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
757 #define MIPS_CMP_INV 1
758 #define MIPS_CMP_SWAP 2
760 static const uint8_t mips_cmp_map[16] = {
763 [TCG_COND_GE] = MIPS_CMP_INV,
764 [TCG_COND_GEU] = MIPS_CMP_INV,
765 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
766 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
767 [TCG_COND_GT] = MIPS_CMP_SWAP,
768 [TCG_COND_GTU] = MIPS_CMP_SWAP,
771 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
772 TCGReg arg1, TCGReg arg2)
774 MIPSInsn s_opc = OPC_SLTU;
780 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
783 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
788 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
791 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
805 cmp_map = mips_cmp_map[cond];
806 if (cmp_map & MIPS_CMP_SWAP) {
811 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
812 if (cmp_map & MIPS_CMP_INV) {
813 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
818 g_assert_not_reached();
823 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
824 TCGReg arg2, TCGLabel *l)
826 static const MIPSInsn b_zero[16] = {
827 [TCG_COND_LT] = OPC_BLTZ,
828 [TCG_COND_GT] = OPC_BGTZ,
829 [TCG_COND_LE] = OPC_BLEZ,
830 [TCG_COND_GE] = OPC_BGEZ,
833 MIPSInsn s_opc = OPC_SLTU;
850 b_opc = b_zero[cond];
862 cmp_map = mips_cmp_map[cond];
863 if (cmp_map & MIPS_CMP_SWAP) {
868 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
869 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
875 g_assert_not_reached();
879 tcg_out_opc_br(s, b_opc, arg1, arg2);
880 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
884 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
885 TCGReg al, TCGReg ah,
886 TCGReg bl, TCGReg bh)
888 /* Merge highpart comparison into AH. */
891 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
897 /* Merge lowpart comparison into AL. */
900 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
906 /* Merge high and low part comparisons into AL. */
909 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
918 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
919 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
921 TCGReg tmp0 = TCG_TMP0;
924 tcg_debug_assert(ret != TCG_TMP0);
925 if (ret == ah || ret == bh) {
926 tcg_debug_assert(ret != TCG_TMP1);
933 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
934 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
938 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
939 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
940 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
941 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
942 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
947 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
948 TCGReg bl, TCGReg bh, TCGLabel *l)
950 TCGCond b_cond = TCG_COND_NE;
951 TCGReg tmp = TCG_TMP1;
953 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
954 With setcond, we emit between 3 and 10 insns and only 1 branch,
955 which ought to get better branch prediction. */
960 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
964 /* Minimize code size by preferring a compare not requiring INV. */
965 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
966 cond = tcg_invert_cond(cond);
967 b_cond = TCG_COND_EQ;
969 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
973 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
976 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
977 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
981 /* If one of the values is zero, put it last to match SEL*Z instructions */
982 if (use_mips32r6_instructions && v1 == 0) {
985 cond = tcg_invert_cond(cond);
994 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1000 /* Minimize code size by preferring a compare not requiring INV. */
1001 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1002 cond = tcg_invert_cond(cond);
1005 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1010 if (use_mips32r6_instructions) {
1011 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1012 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1015 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1017 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1019 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1022 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1024 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1026 /* This should be guaranteed via constraints */
1027 tcg_debug_assert(v2 == ret);
1031 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1033 /* Note that the ABI requires the called function's address to be
1034 loaded into T9, even if a direct branch is in range. */
1035 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1037 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1039 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1040 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1043 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1044 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1049 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1050 const TCGHelperInfo *info)
1052 tcg_out_call_int(s, arg, false);
1056 #if defined(CONFIG_SOFTMMU)
1057 static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
1058 [MO_UB] = helper_ret_ldub_mmu,
1059 [MO_SB] = helper_ret_ldsb_mmu,
1060 [MO_LEUW] = helper_le_lduw_mmu,
1061 [MO_LESW] = helper_le_ldsw_mmu,
1062 [MO_LEUL] = helper_le_ldul_mmu,
1063 [MO_LEUQ] = helper_le_ldq_mmu,
1064 [MO_BEUW] = helper_be_lduw_mmu,
1065 [MO_BESW] = helper_be_ldsw_mmu,
1066 [MO_BEUL] = helper_be_ldul_mmu,
1067 [MO_BEUQ] = helper_be_ldq_mmu,
1068 #if TCG_TARGET_REG_BITS == 64
1069 [MO_LESL] = helper_le_ldsl_mmu,
1070 [MO_BESL] = helper_be_ldsl_mmu,
1074 static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
1075 [MO_UB] = helper_ret_stb_mmu,
1076 [MO_LEUW] = helper_le_stw_mmu,
1077 [MO_LEUL] = helper_le_stl_mmu,
1078 [MO_LEUQ] = helper_le_stq_mmu,
1079 [MO_BEUW] = helper_be_stw_mmu,
1080 [MO_BEUL] = helper_be_stl_mmu,
1081 [MO_BEUQ] = helper_be_stq_mmu,
1084 /* Helper routines for marshalling helper function arguments into
1085 * the correct registers and stack.
1086 * I is where we want to put this argument, and is updated and returned
1087 * for the next call. ARG is the argument itself.
1089 * We provide routines for arguments which are: immediate, 32 bit
1090 * value in register, 16 and 8 bit values in register (which must be zero
1091 * extended before use) and 64 bit value in a lo:hi register pair.
1094 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1096 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1097 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1099 /* For N32 and N64, the initial offset is different. But there
1100 we also have 8 argument register so we don't run out here. */
1101 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1102 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1107 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1109 TCGReg tmp = TCG_TMP0;
1110 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1111 tmp = tcg_target_call_iarg_regs[i];
1113 tcg_out_ext8u(s, tmp, arg);
1114 return tcg_out_call_iarg_reg(s, i, tmp);
1117 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1119 TCGReg tmp = TCG_TMP0;
1120 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1121 tmp = tcg_target_call_iarg_regs[i];
1123 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1124 return tcg_out_call_iarg_reg(s, i, tmp);
1127 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1129 TCGReg tmp = TCG_TMP0;
1133 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1134 tmp = tcg_target_call_iarg_regs[i];
1136 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1138 return tcg_out_call_iarg_reg(s, i, tmp);
1141 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1143 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1145 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1146 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1150 /* We expect to use a 16-bit negative offset from ENV. */
1151 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1152 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1155 * Perform the tlb comparison operation.
1156 * The complete host address is placed in BASE.
1157 * Clobbers TMP0, TMP1, TMP2, TMP3.
1159 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1160 TCGReg addrh, MemOpIdx oi,
1161 tcg_insn_unit *label_ptr[2], bool is_load)
1163 MemOp opc = get_memop(oi);
1164 unsigned a_bits = get_alignment_bits(opc);
1165 unsigned s_bits = opc & MO_SIZE;
1166 unsigned a_mask = (1 << a_bits) - 1;
1167 unsigned s_mask = (1 << s_bits) - 1;
1168 int mem_index = get_mmuidx(oi);
1169 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1170 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1171 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1172 int add_off = offsetof(CPUTLBEntry, addend);
1173 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1174 : offsetof(CPUTLBEntry, addr_write));
1175 target_ulong tlb_mask;
1177 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1178 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1179 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1181 /* Extract the TLB index from the address into TMP3. */
1182 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1183 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1184 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1186 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1187 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1189 /* Load the (low-half) tlb comparator. */
1190 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1191 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1193 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1194 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1195 TCG_TMP0, TCG_TMP3, cmp_off);
1198 /* Zero extend a 32-bit guest address for a 64-bit host. */
1199 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1200 tcg_out_ext32u(s, base, addrl);
1205 * Mask the page bits, keeping the alignment bits to compare against.
1206 * For unaligned accesses, compare against the end of the access to
1207 * verify that it does not cross a page boundary.
1209 tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
1210 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask);
1211 if (a_mask >= s_mask) {
1212 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1214 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask);
1215 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
1218 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1219 /* Load the tlb addend for the fast path. */
1220 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1223 label_ptr[0] = s->code_ptr;
1224 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1226 /* Load and test the high half tlb comparator. */
1227 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1229 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1231 /* Load the tlb addend for the fast path. */
1232 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1234 label_ptr[1] = s->code_ptr;
1235 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1239 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1242 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
1244 TCGReg datalo, TCGReg datahi,
1245 TCGReg addrlo, TCGReg addrhi,
1246 void *raddr, tcg_insn_unit *label_ptr[2])
1248 TCGLabelQemuLdst *label = new_ldst_label(s);
1250 label->is_ld = is_ld;
1253 label->datalo_reg = datalo;
1254 label->datahi_reg = datahi;
1255 label->addrlo_reg = addrlo;
1256 label->addrhi_reg = addrhi;
1257 label->raddr = tcg_splitwx_to_rx(raddr);
1258 label->label_ptr[0] = label_ptr[0];
1259 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1260 label->label_ptr[1] = label_ptr[1];
1264 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1266 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1267 MemOpIdx oi = l->oi;
1268 MemOp opc = get_memop(oi);
1272 /* resolve label address */
1273 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1274 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1275 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1280 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1281 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1283 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1285 i = tcg_out_call_iarg_imm(s, i, oi);
1286 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1287 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1289 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1292 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1293 /* We eliminated V0 from the possible output registers, so it
1294 cannot be clobbered here. So we must move V1 first. */
1296 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1299 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1303 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1304 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1309 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1310 /* we always sign-extend 32-bit loads */
1311 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1313 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1318 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1320 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1321 MemOpIdx oi = l->oi;
1322 MemOp opc = get_memop(oi);
1323 MemOp s_bits = opc & MO_SIZE;
1326 /* resolve label address */
1327 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1328 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1329 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1334 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1335 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1337 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1341 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1344 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1347 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1350 if (TCG_TARGET_REG_BITS == 32) {
1351 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1353 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1357 g_assert_not_reached();
1359 i = tcg_out_call_iarg_imm(s, i, oi);
1361 /* Tail call to the store helper. Thus force the return address
1362 computation to take place in the return address register. */
1363 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1364 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1365 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1367 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1373 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
1374 TCGReg addrhi, unsigned a_bits)
1376 unsigned a_mask = (1 << a_bits) - 1;
1377 TCGLabelQemuLdst *l = new_ldst_label(s);
1380 l->addrlo_reg = addrlo;
1381 l->addrhi_reg = addrhi;
1383 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
1384 tcg_debug_assert(a_bits < 16);
1385 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1387 l->label_ptr[0] = s->code_ptr;
1388 if (use_mips32r6_instructions) {
1389 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1391 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1395 l->raddr = tcg_splitwx_to_rx(s->code_ptr);
1398 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
1402 if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1406 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1407 /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */
1408 TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg;
1409 TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg;
1411 if (a3 != TCG_REG_A2) {
1412 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1413 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1414 } else if (a2 != TCG_REG_A3) {
1415 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1416 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1418 tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2);
1419 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3);
1420 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0);
1423 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
1425 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
1428 * Tail call to the helper, with the return address back inline.
1429 * We have arrived here via BNEL, so $31 is already set.
1431 target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st);
1432 tcg_out_call_int(s, target, true);
1436 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1438 return tcg_out_fail_alignment(s, l);
1441 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1443 return tcg_out_fail_alignment(s, l);
1445 #endif /* SOFTMMU */
1447 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1448 TCGReg base, MemOp opc, bool is_64)
1450 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1452 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1455 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1457 case MO_UW | MO_BSWAP:
1458 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1459 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1462 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1464 case MO_SW | MO_BSWAP:
1465 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1466 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS);
1469 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1471 case MO_UL | MO_BSWAP:
1472 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1473 if (use_mips32r2_instructions) {
1474 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1475 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1477 tcg_out_bswap_subr(s, bswap32u_addr);
1479 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1480 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1485 case MO_SL | MO_BSWAP:
1486 if (use_mips32r2_instructions) {
1487 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1488 tcg_out_bswap32(s, lo, lo, 0);
1490 tcg_out_bswap_subr(s, bswap32_addr);
1492 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1493 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1497 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1498 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1503 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1505 case MO_UQ | MO_BSWAP:
1506 if (TCG_TARGET_REG_BITS == 64) {
1507 if (use_mips32r2_instructions) {
1508 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1509 tcg_out_bswap64(s, lo, lo);
1511 tcg_out_bswap_subr(s, bswap64_addr);
1513 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1514 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1516 } else if (use_mips32r2_instructions) {
1517 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1518 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1519 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1520 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1521 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1522 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1524 tcg_out_bswap_subr(s, bswap32_addr);
1526 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1527 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1528 tcg_out_bswap_subr(s, bswap32_addr);
1530 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1531 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1535 /* Prefer to load from offset 0 first, but allow for overlap. */
1536 if (TCG_TARGET_REG_BITS == 64) {
1537 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1538 } else if (MIPS_BE ? hi != base : lo == base) {
1539 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1540 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1542 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1543 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1547 g_assert_not_reached();
1551 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1552 TCGReg base, MemOp opc, bool is_64)
1554 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
1555 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
1556 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR;
1557 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL;
1559 bool sgn = (opc & MO_SIGN);
1561 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1564 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1565 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1566 if (use_mips32r2_instructions) {
1567 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1569 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1570 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1576 if (use_mips32r2_instructions && lo != base) {
1577 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1578 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1579 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1581 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1582 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1583 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1584 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1590 tcg_out_opc_imm(s, lw1, lo, base, 0);
1591 tcg_out_opc_imm(s, lw2, lo, base, 3);
1592 if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) {
1593 tcg_out_ext32u(s, lo, lo);
1597 case MO_UL | MO_BSWAP:
1598 case MO_SL | MO_BSWAP:
1599 if (use_mips32r2_instructions) {
1600 tcg_out_opc_imm(s, lw1, lo, base, 0);
1601 tcg_out_opc_imm(s, lw2, lo, base, 3);
1602 tcg_out_bswap32(s, lo, lo,
1603 TCG_TARGET_REG_BITS == 64 && is_64
1604 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0);
1606 const tcg_insn_unit *subr =
1607 (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn
1608 ? bswap32u_addr : bswap32_addr);
1610 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0);
1611 tcg_out_bswap_subr(s, subr);
1613 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3);
1614 tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3);
1619 if (TCG_TARGET_REG_BITS == 64) {
1620 tcg_out_opc_imm(s, ld1, lo, base, 0);
1621 tcg_out_opc_imm(s, ld2, lo, base, 7);
1623 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0);
1624 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3);
1625 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0);
1626 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3);
1630 case MO_UQ | MO_BSWAP:
1631 if (TCG_TARGET_REG_BITS == 64) {
1632 if (use_mips32r2_instructions) {
1633 tcg_out_opc_imm(s, ld1, lo, base, 0);
1634 tcg_out_opc_imm(s, ld2, lo, base, 7);
1635 tcg_out_bswap64(s, lo, lo);
1637 tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0);
1638 tcg_out_bswap_subr(s, bswap64_addr);
1640 tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7);
1641 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1643 } else if (use_mips32r2_instructions) {
1644 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
1645 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
1646 tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0);
1647 tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3);
1648 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1649 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1650 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1651 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1653 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
1654 tcg_out_bswap_subr(s, bswap32_addr);
1656 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
1657 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0);
1658 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1659 tcg_out_bswap_subr(s, bswap32_addr);
1661 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3);
1662 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1667 g_assert_not_reached();
1671 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1673 TCGReg addr_regl, addr_regh __attribute__((unused));
1674 TCGReg data_regl, data_regh;
1677 #if defined(CONFIG_SOFTMMU)
1678 tcg_insn_unit *label_ptr[2];
1681 unsigned a_bits, s_bits;
1682 TCGReg base = TCG_REG_A0;
1684 data_regl = *args++;
1685 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1686 addr_regl = *args++;
1687 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1689 opc = get_memop(oi);
1690 a_bits = get_alignment_bits(opc);
1691 s_bits = opc & MO_SIZE;
1694 * R6 removes the left/right instructions but requires the
1695 * system to support misaligned memory accesses.
1697 #if defined(CONFIG_SOFTMMU)
1698 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1699 if (use_mips32r6_instructions || a_bits >= s_bits) {
1700 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1702 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
1704 add_qemu_ldst_label(s, 1, oi,
1705 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1706 data_regl, data_regh, addr_regl, addr_regh,
1707 s->code_ptr, label_ptr);
1709 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1710 tcg_out_ext32u(s, base, addr_regl);
1713 if (guest_base == 0 && data_regl != addr_regl) {
1715 } else if (guest_base == (int16_t)guest_base) {
1716 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1718 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1720 if (use_mips32r6_instructions) {
1722 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1724 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1726 if (a_bits && a_bits != s_bits) {
1727 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1729 if (a_bits >= s_bits) {
1730 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1732 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
1738 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1739 TCGReg base, MemOp opc)
1741 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1742 if ((lo | hi) == 0) {
1746 switch (opc & (MO_SIZE | MO_BSWAP)) {
1748 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1751 case MO_16 | MO_BSWAP:
1752 tcg_out_bswap16(s, TCG_TMP1, lo, 0);
1756 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1759 case MO_32 | MO_BSWAP:
1760 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1764 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1767 case MO_64 | MO_BSWAP:
1768 if (TCG_TARGET_REG_BITS == 64) {
1769 tcg_out_bswap64(s, TCG_TMP3, lo);
1770 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1771 } else if (use_mips32r2_instructions) {
1772 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1773 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1774 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1775 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1776 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1777 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1779 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1780 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1781 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1782 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1786 if (TCG_TARGET_REG_BITS == 64) {
1787 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1789 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1790 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1795 g_assert_not_reached();
1799 static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1800 TCGReg base, MemOp opc)
1802 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR;
1803 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL;
1804 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR;
1805 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL;
1807 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1808 if ((lo | hi) == 0) {
1812 switch (opc & (MO_SIZE | MO_BSWAP)) {
1814 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1815 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0);
1816 tcg_out_opc_imm(s, OPC_SB, lo, base, 1);
1820 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1821 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1822 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1);
1825 case MO_32 | MO_BSWAP:
1826 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1830 tcg_out_opc_imm(s, sw1, lo, base, 0);
1831 tcg_out_opc_imm(s, sw2, lo, base, 3);
1834 case MO_64 | MO_BSWAP:
1835 if (TCG_TARGET_REG_BITS == 64) {
1836 tcg_out_bswap64(s, TCG_TMP3, lo);
1838 } else if (use_mips32r2_instructions) {
1839 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo);
1840 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi);
1841 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1842 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1843 hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1;
1844 lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0;
1846 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1847 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0);
1848 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3);
1849 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1850 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0);
1851 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3);
1856 if (TCG_TARGET_REG_BITS == 64) {
1857 tcg_out_opc_imm(s, sd1, lo, base, 0);
1858 tcg_out_opc_imm(s, sd2, lo, base, 7);
1860 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0);
1861 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3);
1862 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0);
1863 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3);
1868 g_assert_not_reached();
1871 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1873 TCGReg addr_regl, addr_regh __attribute__((unused));
1874 TCGReg data_regl, data_regh;
1877 #if defined(CONFIG_SOFTMMU)
1878 tcg_insn_unit *label_ptr[2];
1880 unsigned a_bits, s_bits;
1881 TCGReg base = TCG_REG_A0;
1883 data_regl = *args++;
1884 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1885 addr_regl = *args++;
1886 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1888 opc = get_memop(oi);
1889 a_bits = get_alignment_bits(opc);
1890 s_bits = opc & MO_SIZE;
1893 * R6 removes the left/right instructions but requires the
1894 * system to support misaligned memory accesses.
1896 #if defined(CONFIG_SOFTMMU)
1897 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1898 if (use_mips32r6_instructions || a_bits >= s_bits) {
1899 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1901 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
1903 add_qemu_ldst_label(s, 0, oi,
1904 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1905 data_regl, data_regh, addr_regl, addr_regh,
1906 s->code_ptr, label_ptr);
1908 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1909 tcg_out_ext32u(s, base, addr_regl);
1912 if (guest_base == 0) {
1914 } else if (guest_base == (int16_t)guest_base) {
1915 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1917 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1919 if (use_mips32r6_instructions) {
1921 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1923 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1925 if (a_bits && a_bits != s_bits) {
1926 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1928 if (a_bits >= s_bits) {
1929 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1931 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
1937 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1939 static const MIPSInsn sync[] = {
1940 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1941 as the former is an ordering barrier and the latter
1942 is a completion barrier. */
1943 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1944 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1945 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1946 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1947 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1948 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1950 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1953 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1954 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1956 if (use_mips32r6_instructions) {
1958 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1960 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1961 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1965 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1966 } else if (a0 == a2) {
1967 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1968 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1969 } else if (a0 != a1) {
1970 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1971 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1973 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1974 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1975 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1980 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1982 TCGReg b0 = TCG_REG_ZERO;
1985 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1988 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1989 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
1990 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1992 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1995 static void tcg_out_goto_tb(TCGContext *s, int which)
1997 /* indirect jump method */
1998 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1999 get_jmp_target_addr(s, which));
2000 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
2002 set_jmp_reset_offset(s, which);
2005 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
2006 uintptr_t jmp_rx, uintptr_t jmp_rw)
2008 /* Always indirect, nothing to do */
2011 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
2012 const TCGArg args[TCG_MAX_OP_ARGS],
2013 const int const_args[TCG_MAX_OP_ARGS])
2020 * Note that many operands use the constraint set "rZ".
2021 * We make use of the fact that 0 is the ZERO register,
2022 * and hence such cases need not check for const_args.
2030 case INDEX_op_goto_ptr:
2031 /* jmp to the given host address (could be epilogue) */
2032 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
2036 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
2040 case INDEX_op_ld8u_i32:
2041 case INDEX_op_ld8u_i64:
2044 case INDEX_op_ld8s_i32:
2045 case INDEX_op_ld8s_i64:
2048 case INDEX_op_ld16u_i32:
2049 case INDEX_op_ld16u_i64:
2052 case INDEX_op_ld16s_i32:
2053 case INDEX_op_ld16s_i64:
2056 case INDEX_op_ld_i32:
2057 case INDEX_op_ld32s_i64:
2060 case INDEX_op_ld32u_i64:
2063 case INDEX_op_ld_i64:
2066 case INDEX_op_st8_i32:
2067 case INDEX_op_st8_i64:
2070 case INDEX_op_st16_i32:
2071 case INDEX_op_st16_i64:
2074 case INDEX_op_st_i32:
2075 case INDEX_op_st32_i64:
2078 case INDEX_op_st_i64:
2081 tcg_out_ldst(s, i1, a0, a1, a2);
2084 case INDEX_op_add_i32:
2085 i1 = OPC_ADDU, i2 = OPC_ADDIU;
2087 case INDEX_op_add_i64:
2088 i1 = OPC_DADDU, i2 = OPC_DADDIU;
2090 case INDEX_op_or_i32:
2091 case INDEX_op_or_i64:
2092 i1 = OPC_OR, i2 = OPC_ORI;
2094 case INDEX_op_xor_i32:
2095 case INDEX_op_xor_i64:
2096 i1 = OPC_XOR, i2 = OPC_XORI;
2099 tcg_out_opc_imm(s, i2, a0, a1, a2);
2103 tcg_out_opc_reg(s, i1, a0, a1, a2);
2106 case INDEX_op_sub_i32:
2107 i1 = OPC_SUBU, i2 = OPC_ADDIU;
2109 case INDEX_op_sub_i64:
2110 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
2113 tcg_out_opc_imm(s, i2, a0, a1, -a2);
2117 case INDEX_op_and_i32:
2118 if (c2 && a2 != (uint16_t)a2) {
2119 int msb = ctz32(~a2) - 1;
2120 tcg_debug_assert(use_mips32r2_instructions);
2121 tcg_debug_assert(is_p2m1(a2));
2122 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
2125 i1 = OPC_AND, i2 = OPC_ANDI;
2127 case INDEX_op_and_i64:
2128 if (c2 && a2 != (uint16_t)a2) {
2129 int msb = ctz64(~a2) - 1;
2130 tcg_debug_assert(use_mips32r2_instructions);
2131 tcg_debug_assert(is_p2m1(a2));
2132 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
2135 i1 = OPC_AND, i2 = OPC_ANDI;
2137 case INDEX_op_nor_i32:
2138 case INDEX_op_nor_i64:
2142 case INDEX_op_mul_i32:
2143 if (use_mips32_instructions) {
2144 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
2147 i1 = OPC_MULT, i2 = OPC_MFLO;
2149 case INDEX_op_mulsh_i32:
2150 if (use_mips32r6_instructions) {
2151 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
2154 i1 = OPC_MULT, i2 = OPC_MFHI;
2156 case INDEX_op_muluh_i32:
2157 if (use_mips32r6_instructions) {
2158 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
2161 i1 = OPC_MULTU, i2 = OPC_MFHI;
2163 case INDEX_op_div_i32:
2164 if (use_mips32r6_instructions) {
2165 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
2168 i1 = OPC_DIV, i2 = OPC_MFLO;
2170 case INDEX_op_divu_i32:
2171 if (use_mips32r6_instructions) {
2172 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
2175 i1 = OPC_DIVU, i2 = OPC_MFLO;
2177 case INDEX_op_rem_i32:
2178 if (use_mips32r6_instructions) {
2179 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
2182 i1 = OPC_DIV, i2 = OPC_MFHI;
2184 case INDEX_op_remu_i32:
2185 if (use_mips32r6_instructions) {
2186 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
2189 i1 = OPC_DIVU, i2 = OPC_MFHI;
2191 case INDEX_op_mul_i64:
2192 if (use_mips32r6_instructions) {
2193 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
2196 i1 = OPC_DMULT, i2 = OPC_MFLO;
2198 case INDEX_op_mulsh_i64:
2199 if (use_mips32r6_instructions) {
2200 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
2203 i1 = OPC_DMULT, i2 = OPC_MFHI;
2205 case INDEX_op_muluh_i64:
2206 if (use_mips32r6_instructions) {
2207 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
2210 i1 = OPC_DMULTU, i2 = OPC_MFHI;
2212 case INDEX_op_div_i64:
2213 if (use_mips32r6_instructions) {
2214 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
2217 i1 = OPC_DDIV, i2 = OPC_MFLO;
2219 case INDEX_op_divu_i64:
2220 if (use_mips32r6_instructions) {
2221 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
2224 i1 = OPC_DDIVU, i2 = OPC_MFLO;
2226 case INDEX_op_rem_i64:
2227 if (use_mips32r6_instructions) {
2228 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
2231 i1 = OPC_DDIV, i2 = OPC_MFHI;
2233 case INDEX_op_remu_i64:
2234 if (use_mips32r6_instructions) {
2235 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
2238 i1 = OPC_DDIVU, i2 = OPC_MFHI;
2240 tcg_out_opc_reg(s, i1, 0, a1, a2);
2241 tcg_out_opc_reg(s, i2, a0, 0, 0);
2244 case INDEX_op_muls2_i32:
2247 case INDEX_op_mulu2_i32:
2250 case INDEX_op_muls2_i64:
2253 case INDEX_op_mulu2_i64:
2256 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
2257 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
2258 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2261 case INDEX_op_not_i32:
2262 case INDEX_op_not_i64:
2266 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
2269 case INDEX_op_bswap16_i32:
2270 case INDEX_op_bswap16_i64:
2271 tcg_out_bswap16(s, a0, a1, a2);
2273 case INDEX_op_bswap32_i32:
2274 tcg_out_bswap32(s, a0, a1, 0);
2276 case INDEX_op_bswap32_i64:
2277 tcg_out_bswap32(s, a0, a1, a2);
2279 case INDEX_op_bswap64_i64:
2280 tcg_out_bswap64(s, a0, a1);
2282 case INDEX_op_extrh_i64_i32:
2283 tcg_out_dsra(s, a0, a1, 32);
2285 case INDEX_op_ext32s_i64:
2286 case INDEX_op_ext_i32_i64:
2287 case INDEX_op_extrl_i64_i32:
2288 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2290 case INDEX_op_ext32u_i64:
2291 case INDEX_op_extu_i32_i64:
2292 tcg_out_ext32u(s, a0, a1);
2295 case INDEX_op_sar_i32:
2296 i1 = OPC_SRAV, i2 = OPC_SRA;
2298 case INDEX_op_shl_i32:
2299 i1 = OPC_SLLV, i2 = OPC_SLL;
2301 case INDEX_op_shr_i32:
2302 i1 = OPC_SRLV, i2 = OPC_SRL;
2304 case INDEX_op_rotr_i32:
2305 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2308 tcg_out_opc_sa(s, i2, a0, a1, a2);
2312 tcg_out_opc_reg(s, i1, a0, a2, a1);
2314 case INDEX_op_rotl_i32:
2316 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2318 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2319 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2322 case INDEX_op_sar_i64:
2324 tcg_out_dsra(s, a0, a1, a2);
2329 case INDEX_op_shl_i64:
2331 tcg_out_dsll(s, a0, a1, a2);
2336 case INDEX_op_shr_i64:
2338 tcg_out_dsrl(s, a0, a1, a2);
2343 case INDEX_op_rotr_i64:
2345 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2350 case INDEX_op_rotl_i64:
2352 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2354 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2355 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2359 case INDEX_op_clz_i32:
2360 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2362 case INDEX_op_clz_i64:
2363 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2366 case INDEX_op_deposit_i32:
2367 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2369 case INDEX_op_deposit_i64:
2370 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2371 args[3] + args[4] - 1, args[3]);
2373 case INDEX_op_extract_i32:
2374 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2376 case INDEX_op_extract_i64:
2377 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2381 case INDEX_op_brcond_i32:
2382 case INDEX_op_brcond_i64:
2383 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2385 case INDEX_op_brcond2_i32:
2386 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2389 case INDEX_op_movcond_i32:
2390 case INDEX_op_movcond_i64:
2391 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2394 case INDEX_op_setcond_i32:
2395 case INDEX_op_setcond_i64:
2396 tcg_out_setcond(s, args[3], a0, a1, a2);
2398 case INDEX_op_setcond2_i32:
2399 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2402 case INDEX_op_qemu_ld_i32:
2403 tcg_out_qemu_ld(s, args, false);
2405 case INDEX_op_qemu_ld_i64:
2406 tcg_out_qemu_ld(s, args, true);
2408 case INDEX_op_qemu_st_i32:
2409 tcg_out_qemu_st(s, args, false);
2411 case INDEX_op_qemu_st_i64:
2412 tcg_out_qemu_st(s, args, true);
2415 case INDEX_op_add2_i32:
2416 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2417 const_args[4], const_args[5], false);
2419 case INDEX_op_sub2_i32:
2420 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2421 const_args[4], const_args[5], true);
2427 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2428 case INDEX_op_mov_i64:
2429 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2430 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2431 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2432 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2433 case INDEX_op_ext8s_i64:
2434 case INDEX_op_ext8u_i32:
2435 case INDEX_op_ext8u_i64:
2436 case INDEX_op_ext16s_i32:
2437 case INDEX_op_ext16s_i64:
2439 g_assert_not_reached();
2443 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2446 case INDEX_op_goto_ptr:
2449 case INDEX_op_ld8u_i32:
2450 case INDEX_op_ld8s_i32:
2451 case INDEX_op_ld16u_i32:
2452 case INDEX_op_ld16s_i32:
2453 case INDEX_op_ld_i32:
2454 case INDEX_op_not_i32:
2455 case INDEX_op_bswap16_i32:
2456 case INDEX_op_bswap32_i32:
2457 case INDEX_op_ext8s_i32:
2458 case INDEX_op_ext16s_i32:
2459 case INDEX_op_extract_i32:
2460 case INDEX_op_ld8u_i64:
2461 case INDEX_op_ld8s_i64:
2462 case INDEX_op_ld16u_i64:
2463 case INDEX_op_ld16s_i64:
2464 case INDEX_op_ld32s_i64:
2465 case INDEX_op_ld32u_i64:
2466 case INDEX_op_ld_i64:
2467 case INDEX_op_not_i64:
2468 case INDEX_op_bswap16_i64:
2469 case INDEX_op_bswap32_i64:
2470 case INDEX_op_bswap64_i64:
2471 case INDEX_op_ext8s_i64:
2472 case INDEX_op_ext16s_i64:
2473 case INDEX_op_ext32s_i64:
2474 case INDEX_op_ext32u_i64:
2475 case INDEX_op_ext_i32_i64:
2476 case INDEX_op_extu_i32_i64:
2477 case INDEX_op_extrl_i64_i32:
2478 case INDEX_op_extrh_i64_i32:
2479 case INDEX_op_extract_i64:
2480 return C_O1_I1(r, r);
2482 case INDEX_op_st8_i32:
2483 case INDEX_op_st16_i32:
2484 case INDEX_op_st_i32:
2485 case INDEX_op_st8_i64:
2486 case INDEX_op_st16_i64:
2487 case INDEX_op_st32_i64:
2488 case INDEX_op_st_i64:
2489 return C_O0_I2(rZ, r);
2491 case INDEX_op_add_i32:
2492 case INDEX_op_add_i64:
2493 return C_O1_I2(r, r, rJ);
2494 case INDEX_op_sub_i32:
2495 case INDEX_op_sub_i64:
2496 return C_O1_I2(r, rZ, rN);
2497 case INDEX_op_mul_i32:
2498 case INDEX_op_mulsh_i32:
2499 case INDEX_op_muluh_i32:
2500 case INDEX_op_div_i32:
2501 case INDEX_op_divu_i32:
2502 case INDEX_op_rem_i32:
2503 case INDEX_op_remu_i32:
2504 case INDEX_op_nor_i32:
2505 case INDEX_op_setcond_i32:
2506 case INDEX_op_mul_i64:
2507 case INDEX_op_mulsh_i64:
2508 case INDEX_op_muluh_i64:
2509 case INDEX_op_div_i64:
2510 case INDEX_op_divu_i64:
2511 case INDEX_op_rem_i64:
2512 case INDEX_op_remu_i64:
2513 case INDEX_op_nor_i64:
2514 case INDEX_op_setcond_i64:
2515 return C_O1_I2(r, rZ, rZ);
2516 case INDEX_op_muls2_i32:
2517 case INDEX_op_mulu2_i32:
2518 case INDEX_op_muls2_i64:
2519 case INDEX_op_mulu2_i64:
2520 return C_O2_I2(r, r, r, r);
2521 case INDEX_op_and_i32:
2522 case INDEX_op_and_i64:
2523 return C_O1_I2(r, r, rIK);
2524 case INDEX_op_or_i32:
2525 case INDEX_op_xor_i32:
2526 case INDEX_op_or_i64:
2527 case INDEX_op_xor_i64:
2528 return C_O1_I2(r, r, rI);
2529 case INDEX_op_shl_i32:
2530 case INDEX_op_shr_i32:
2531 case INDEX_op_sar_i32:
2532 case INDEX_op_rotr_i32:
2533 case INDEX_op_rotl_i32:
2534 case INDEX_op_shl_i64:
2535 case INDEX_op_shr_i64:
2536 case INDEX_op_sar_i64:
2537 case INDEX_op_rotr_i64:
2538 case INDEX_op_rotl_i64:
2539 return C_O1_I2(r, r, ri);
2540 case INDEX_op_clz_i32:
2541 case INDEX_op_clz_i64:
2542 return C_O1_I2(r, r, rWZ);
2544 case INDEX_op_deposit_i32:
2545 case INDEX_op_deposit_i64:
2546 return C_O1_I2(r, 0, rZ);
2547 case INDEX_op_brcond_i32:
2548 case INDEX_op_brcond_i64:
2549 return C_O0_I2(rZ, rZ);
2550 case INDEX_op_movcond_i32:
2551 case INDEX_op_movcond_i64:
2552 return (use_mips32r6_instructions
2553 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2554 : C_O1_I4(r, rZ, rZ, rZ, 0));
2555 case INDEX_op_add2_i32:
2556 case INDEX_op_sub2_i32:
2557 return C_O2_I4(r, r, rZ, rZ, rN, rN);
2558 case INDEX_op_setcond2_i32:
2559 return C_O1_I4(r, rZ, rZ, rZ, rZ);
2560 case INDEX_op_brcond2_i32:
2561 return C_O0_I4(rZ, rZ, rZ, rZ);
2563 case INDEX_op_qemu_ld_i32:
2564 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2565 ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
2566 case INDEX_op_qemu_st_i32:
2567 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2568 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
2569 case INDEX_op_qemu_ld_i64:
2570 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
2571 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
2572 : C_O2_I2(r, r, L, L));
2573 case INDEX_op_qemu_st_i64:
2574 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
2575 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
2576 : C_O0_I4(SZ, SZ, S, S));
2579 g_assert_not_reached();
2583 static const int tcg_target_callee_save_regs[] = {
2584 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2593 TCG_REG_RA, /* should be last for ABI compliance */
2596 /* The Linux kernel doesn't provide any information about the available
2597 instruction set. Probe it using a signal handler. */
2600 #ifndef use_movnz_instructions
2601 bool use_movnz_instructions = false;
2604 #ifndef use_mips32_instructions
2605 bool use_mips32_instructions = false;
2608 #ifndef use_mips32r2_instructions
2609 bool use_mips32r2_instructions = false;
2612 static volatile sig_atomic_t got_sigill;
2614 static void sigill_handler(int signo, siginfo_t *si, void *data)
2616 /* Skip the faulty instruction */
2617 ucontext_t *uc = (ucontext_t *)data;
2618 uc->uc_mcontext.pc += 4;
2623 static void tcg_target_detect_isa(void)
2625 struct sigaction sa_old, sa_new;
2627 memset(&sa_new, 0, sizeof(sa_new));
2628 sa_new.sa_flags = SA_SIGINFO;
2629 sa_new.sa_sigaction = sigill_handler;
2630 sigaction(SIGILL, &sa_new, &sa_old);
2632 /* Probe for movn/movz, necessary to implement movcond. */
2633 #ifndef use_movnz_instructions
2635 asm volatile(".set push\n"
2637 "movn $zero, $zero, $zero\n"
2638 "movz $zero, $zero, $zero\n"
2641 use_movnz_instructions = !got_sigill;
2644 /* Probe for MIPS32 instructions. As no subsetting is allowed
2645 by the specification, it is only necessary to probe for one
2646 of the instructions. */
2647 #ifndef use_mips32_instructions
2649 asm volatile(".set push\n"
2651 "mul $zero, $zero\n"
2654 use_mips32_instructions = !got_sigill;
2657 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2658 available. As no subsetting is allowed by the specification,
2659 it is only necessary to probe for one of the instructions. */
2660 #ifndef use_mips32r2_instructions
2661 if (use_mips32_instructions) {
2663 asm volatile(".set push\n"
2665 "seb $zero, $zero\n"
2668 use_mips32r2_instructions = !got_sigill;
2672 sigaction(SIGILL, &sa_old, NULL);
2675 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2677 uintptr_t p = (uintptr_t)s->code_ptr;
2680 s->code_ptr = (void *)p;
2685 /* Stack frame parameters. */
2686 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2687 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2688 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2690 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2691 + TCG_TARGET_STACK_ALIGN - 1) \
2692 & -TCG_TARGET_STACK_ALIGN)
2693 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2695 /* We're expecting to be able to use an immediate for frame allocation. */
2696 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2698 /* Generate global QEMU prologue and epilogue code */
2699 static void tcg_target_qemu_prologue(TCGContext *s)
2703 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2706 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2707 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2708 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2709 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2712 #ifndef CONFIG_SOFTMMU
2714 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2715 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2719 /* Call generated code */
2720 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2722 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2725 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2726 * and fall through to the rest of the epilogue.
2728 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2729 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2732 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2733 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2734 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2735 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2738 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2740 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2742 if (use_mips32r2_instructions) {
2746 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2747 clobbers TCG_TMP1, TCG_TMP2. */
2750 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2752 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2753 /* t3 = (ssss)d000 */
2754 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2756 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2758 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2760 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2762 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2764 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2766 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2768 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2769 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2770 /* t3 = dcba -- delay slot */
2771 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2773 if (TCG_TARGET_REG_BITS == 32) {
2778 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2780 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2781 /* t1 = (0000)000d */
2782 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2784 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2785 /* t1 = (0000)d000 */
2786 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2788 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2790 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2792 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2794 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2796 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2798 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2799 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2800 /* t3 = dcba -- delay slot */
2801 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2804 * bswap64 -- 64-bit swap. a0 = abcdefgh
2806 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2808 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2810 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2813 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2815 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2817 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2819 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2821 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2824 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2826 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2828 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2831 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2833 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2835 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2837 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2840 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2842 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2844 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2847 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2849 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2851 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2853 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2856 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2857 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2858 /* t3 = hgfedcba -- delay slot */
2859 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2862 static void tcg_target_init(TCGContext *s)
2864 tcg_target_detect_isa();
2865 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2866 if (TCG_TARGET_REG_BITS == 64) {
2867 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2870 tcg_target_call_clobber_regs = 0;
2871 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2872 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2873 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2874 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2875 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2876 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2877 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2878 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2879 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2880 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2881 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2882 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2883 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2884 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2885 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2886 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2888 s->reserved_regs = 0;
2889 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2890 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2891 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2892 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2893 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2894 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2895 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2896 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2897 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2898 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2903 uint8_t fde_def_cfa[4];
2904 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2907 #define ELF_HOST_MACHINE EM_MIPS
2908 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2909 which is good because they're really quite complicated for MIPS. */
2911 static const DebugFrame debug_frame = {
2912 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2915 .h.cie.code_align = 1,
2916 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2917 .h.cie.return_column = TCG_REG_RA,
2919 /* Total FDE size does not include the "len" member. */
2920 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2923 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2924 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2928 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2929 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2930 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2931 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2932 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2933 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2934 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2935 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2936 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2940 void tcg_register_jit(const void *buf, size_t buf_size)
2942 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));