2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "../tcg-ldst.c.inc"
35 #if TCG_TARGET_REG_BITS == 32
36 # define LO_OFF (MIPS_BE * 4)
37 # define HI_OFF (4 - LO_OFF)
39 /* To assert at compile-time that these values are never used
40 for TCG_TARGET_REG_BITS == 64. */
42 # define LO_OFF link_error()
43 # define HI_OFF link_error()
46 #ifdef CONFIG_DEBUG_TCG
47 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
83 #define TCG_TMP0 TCG_REG_AT
84 #define TCG_TMP1 TCG_REG_T9
85 #define TCG_TMP2 TCG_REG_T8
86 #define TCG_TMP3 TCG_REG_T7
88 #ifndef CONFIG_SOFTMMU
89 #define TCG_GUEST_BASE_REG TCG_REG_S1
92 /* check if we really need so many registers :P */
93 static const int tcg_target_reg_alloc_order[] = {
94 /* Call saved registers. */
105 /* Call clobbered registers. */
115 /* Argument registers, opposite order of allocation. */
126 static const TCGReg tcg_target_call_iarg_regs[] = {
131 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
139 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
142 tcg_debug_assert(slot >= 0 && slot <= 1);
143 return TCG_REG_V0 + slot;
146 static const tcg_insn_unit *tb_ret_addr;
147 static const tcg_insn_unit *bswap32_addr;
148 static const tcg_insn_unit *bswap32u_addr;
149 static const tcg_insn_unit *bswap64_addr;
151 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
153 /* Let the compiler perform the right-shift as part of the arithmetic. */
154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
155 ptrdiff_t disp = target - (src_rx + 1);
156 if (disp == (int16_t)disp) {
157 *src_rw = deposit32(*src_rw, 0, 16, disp);
163 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
164 intptr_t value, intptr_t addend)
166 tcg_debug_assert(type == R_MIPS_PC16);
167 tcg_debug_assert(addend == 0);
168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
171 #define TCG_CT_CONST_ZERO 0x100
172 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
173 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
174 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
175 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
176 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
178 #define ALL_GENERAL_REGS 0xffffffffu
180 static bool is_p2m1(tcg_target_long val)
182 return val && ((val + 1) & val) == 0;
185 /* test if a constant matches the constraint */
186 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
188 if (ct & TCG_CT_CONST) {
190 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
192 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
194 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
196 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
198 } else if ((ct & TCG_CT_CONST_P2M1)
199 && use_mips32r2_instructions && is_p2m1(val)) {
201 } else if ((ct & TCG_CT_CONST_WSZ)
202 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
208 /* instruction opcodes */
214 OPC_BLEZ = 006 << 26,
215 OPC_BGTZ = 007 << 26,
216 OPC_ADDIU = 011 << 26,
217 OPC_SLTI = 012 << 26,
218 OPC_SLTIU = 013 << 26,
219 OPC_ANDI = 014 << 26,
221 OPC_XORI = 016 << 26,
223 OPC_BNEL = 025 << 26,
224 OPC_BNEZALC_R6 = 030 << 26,
225 OPC_DADDIU = 031 << 26,
246 OPC_SPECIAL = 000 << 26,
247 OPC_SLL = OPC_SPECIAL | 000,
248 OPC_SRL = OPC_SPECIAL | 002,
249 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
250 OPC_SRA = OPC_SPECIAL | 003,
251 OPC_SLLV = OPC_SPECIAL | 004,
252 OPC_SRLV = OPC_SPECIAL | 006,
253 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
254 OPC_SRAV = OPC_SPECIAL | 007,
255 OPC_JR_R5 = OPC_SPECIAL | 010,
256 OPC_JALR = OPC_SPECIAL | 011,
257 OPC_MOVZ = OPC_SPECIAL | 012,
258 OPC_MOVN = OPC_SPECIAL | 013,
259 OPC_SYNC = OPC_SPECIAL | 017,
260 OPC_MFHI = OPC_SPECIAL | 020,
261 OPC_MFLO = OPC_SPECIAL | 022,
262 OPC_DSLLV = OPC_SPECIAL | 024,
263 OPC_DSRLV = OPC_SPECIAL | 026,
264 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
265 OPC_DSRAV = OPC_SPECIAL | 027,
266 OPC_MULT = OPC_SPECIAL | 030,
267 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
268 OPC_MUH = OPC_SPECIAL | 030 | 0300,
269 OPC_MULTU = OPC_SPECIAL | 031,
270 OPC_MULU = OPC_SPECIAL | 031 | 0200,
271 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
272 OPC_DIV = OPC_SPECIAL | 032,
273 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
274 OPC_MOD = OPC_SPECIAL | 032 | 0300,
275 OPC_DIVU = OPC_SPECIAL | 033,
276 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
277 OPC_MODU = OPC_SPECIAL | 033 | 0300,
278 OPC_DMULT = OPC_SPECIAL | 034,
279 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
280 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
281 OPC_DMULTU = OPC_SPECIAL | 035,
282 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
283 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
284 OPC_DDIV = OPC_SPECIAL | 036,
285 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
286 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
287 OPC_DDIVU = OPC_SPECIAL | 037,
288 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
289 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
290 OPC_ADDU = OPC_SPECIAL | 041,
291 OPC_SUBU = OPC_SPECIAL | 043,
292 OPC_AND = OPC_SPECIAL | 044,
293 OPC_OR = OPC_SPECIAL | 045,
294 OPC_XOR = OPC_SPECIAL | 046,
295 OPC_NOR = OPC_SPECIAL | 047,
296 OPC_SLT = OPC_SPECIAL | 052,
297 OPC_SLTU = OPC_SPECIAL | 053,
298 OPC_DADDU = OPC_SPECIAL | 055,
299 OPC_DSUBU = OPC_SPECIAL | 057,
300 OPC_SELEQZ = OPC_SPECIAL | 065,
301 OPC_SELNEZ = OPC_SPECIAL | 067,
302 OPC_DSLL = OPC_SPECIAL | 070,
303 OPC_DSRL = OPC_SPECIAL | 072,
304 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
305 OPC_DSRA = OPC_SPECIAL | 073,
306 OPC_DSLL32 = OPC_SPECIAL | 074,
307 OPC_DSRL32 = OPC_SPECIAL | 076,
308 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
309 OPC_DSRA32 = OPC_SPECIAL | 077,
310 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
311 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
313 OPC_REGIMM = 001 << 26,
314 OPC_BLTZ = OPC_REGIMM | (000 << 16),
315 OPC_BGEZ = OPC_REGIMM | (001 << 16),
317 OPC_SPECIAL2 = 034 << 26,
318 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
319 OPC_CLZ = OPC_SPECIAL2 | 040,
320 OPC_DCLZ = OPC_SPECIAL2 | 044,
322 OPC_SPECIAL3 = 037 << 26,
323 OPC_EXT = OPC_SPECIAL3 | 000,
324 OPC_DEXTM = OPC_SPECIAL3 | 001,
325 OPC_DEXTU = OPC_SPECIAL3 | 002,
326 OPC_DEXT = OPC_SPECIAL3 | 003,
327 OPC_INS = OPC_SPECIAL3 | 004,
328 OPC_DINSM = OPC_SPECIAL3 | 005,
329 OPC_DINSU = OPC_SPECIAL3 | 006,
330 OPC_DINS = OPC_SPECIAL3 | 007,
331 OPC_WSBH = OPC_SPECIAL3 | 00240,
332 OPC_DSBH = OPC_SPECIAL3 | 00244,
333 OPC_DSHD = OPC_SPECIAL3 | 00544,
334 OPC_SEB = OPC_SPECIAL3 | 02040,
335 OPC_SEH = OPC_SPECIAL3 | 03040,
337 /* MIPS r6 doesn't have JR, JALR should be used instead */
338 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
341 * MIPS r6 replaces MUL with an alternative encoding which is
342 * backwards-compatible at the assembly level.
344 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
346 /* MIPS r6 introduced names for weaker variants of SYNC. These are
347 backward compatible to previous architecture revisions. */
348 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
349 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
350 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
351 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
352 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
354 /* Aliases for convenience. */
355 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
356 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
357 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
358 ? OPC_SRL : OPC_DSRL,
359 ALIAS_TADDI = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
360 ? OPC_ADDIU : OPC_DADDIU,
366 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
367 TCGReg rd, TCGReg rs, TCGReg rt)
372 inst |= (rs & 0x1F) << 21;
373 inst |= (rt & 0x1F) << 16;
374 inst |= (rd & 0x1F) << 11;
381 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
382 TCGReg rt, TCGReg rs, TCGArg imm)
387 inst |= (rs & 0x1F) << 21;
388 inst |= (rt & 0x1F) << 16;
389 inst |= (imm & 0xffff);
396 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
397 TCGReg rs, int msb, int lsb)
402 inst |= (rs & 0x1F) << 21;
403 inst |= (rt & 0x1F) << 16;
404 inst |= (msb & 0x1F) << 11;
405 inst |= (lsb & 0x1F) << 6;
409 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
410 MIPSInsn oph, TCGReg rt, TCGReg rs,
417 } else if (msb >= 32) {
421 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
427 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
429 tcg_out_opc_imm(s, opc, rt, rs, 0);
435 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
436 TCGReg rd, TCGReg rt, TCGArg sa)
441 inst |= (rt & 0x1F) << 16;
442 inst |= (rd & 0x1F) << 11;
443 inst |= (sa & 0x1F) << 6;
448 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
449 TCGReg rd, TCGReg rt, TCGArg sa)
453 inst = (sa & 32 ? opc2 : opc1);
454 inst |= (rt & 0x1F) << 16;
455 inst |= (rd & 0x1F) << 11;
456 inst |= (sa & 0x1F) << 6;
462 * Returns true if the branch was in range and the insn was emitted.
464 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
466 uintptr_t dest = (uintptr_t)target;
467 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
470 /* The pc-region branch happens within the 256MB region of
471 the delay slot (thus the +4). */
472 if ((from ^ dest) & -(1 << 28)) {
475 tcg_debug_assert((dest & 3) == 0);
478 inst |= (dest >> 2) & 0x3ffffff;
483 static void tcg_out_nop(TCGContext *s)
488 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
490 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
493 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
495 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
498 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
500 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
503 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
505 /* Simple reg-reg move, optimising out the 'do nothing' case */
507 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
512 static void tcg_out_movi(TCGContext *s, TCGType type,
513 TCGReg ret, tcg_target_long arg)
515 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
518 if (arg == (int16_t)arg) {
519 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
522 if (arg == (uint16_t)arg) {
523 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
526 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
527 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
529 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
530 if (arg & 0xffff0000ull) {
531 tcg_out_dsll(s, ret, ret, 16);
532 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
533 tcg_out_dsll(s, ret, ret, 16);
535 tcg_out_dsll(s, ret, ret, 32);
539 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
543 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
545 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
546 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
549 static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
551 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
554 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
556 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32);
557 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs);
560 static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs)
562 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff);
565 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs)
567 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
568 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0);
571 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
574 tcg_out_ext32s(s, rd, rs);
578 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
580 tcg_out_ext32u(s, rd, rs);
583 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
585 tcg_out_ext32s(s, rd, rs);
588 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
593 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
596 /* This function is only used for passing structs by reference. */
597 g_assert_not_reached();
600 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
602 /* ret and arg can't be register tmp0 */
603 tcg_debug_assert(ret != TCG_TMP0);
604 tcg_debug_assert(arg != TCG_TMP0);
606 /* With arg = abcd: */
607 if (use_mips32r2_instructions) {
608 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
609 if (flags & TCG_BSWAP_OS) {
610 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
611 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
612 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
617 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
618 if (!(flags & TCG_BSWAP_IZ)) {
619 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
621 if (flags & TCG_BSWAP_OS) {
622 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
623 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
625 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
626 if (flags & TCG_BSWAP_OZ) {
627 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
630 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
633 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
635 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
636 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
637 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
641 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
643 if (use_mips32r2_instructions) {
644 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
645 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
646 if (flags & TCG_BSWAP_OZ) {
647 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
650 if (flags & TCG_BSWAP_OZ) {
651 tcg_out_bswap_subr(s, bswap32u_addr);
653 tcg_out_bswap_subr(s, bswap32_addr);
655 /* delay slot -- never omit the insn, like tcg_out_mov might. */
656 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
657 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
661 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
663 if (use_mips32r2_instructions) {
664 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
665 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
667 tcg_out_bswap_subr(s, bswap64_addr);
668 /* delay slot -- never omit the insn, like tcg_out_mov might. */
669 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
670 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
674 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
676 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
677 if (use_mips32r2_instructions) {
678 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
680 tcg_out_dsll(s, ret, arg, 32);
681 tcg_out_dsrl(s, ret, ret, 32);
685 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
686 TCGReg addr, intptr_t ofs)
690 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
691 if (addr != TCG_REG_ZERO) {
692 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
696 tcg_out_opc_imm(s, opc, data, addr, lo);
699 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
700 TCGReg arg1, intptr_t arg2)
702 MIPSInsn opc = OPC_LD;
703 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
706 tcg_out_ldst(s, opc, arg, arg1, arg2);
709 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
710 TCGReg arg1, intptr_t arg2)
712 MIPSInsn opc = OPC_SD;
713 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
716 tcg_out_ldst(s, opc, arg, arg1, arg2);
719 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
720 TCGReg base, intptr_t ofs)
723 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
729 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
730 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
731 bool cbh, bool is_sub)
733 TCGReg th = TCG_TMP1;
735 /* If we have a negative constant such that negating it would
736 make the high part zero, we can (usually) eliminate one insn. */
737 if (cbl && cbh && bh == -1 && bl != 0) {
743 /* By operating on the high part first, we get to use the final
744 carry operation to move back from the temporary. */
746 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
747 } else if (bh != 0 || ah == rl) {
748 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
753 /* Note that tcg optimization should eliminate the bl == 0 case. */
756 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
757 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
759 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
760 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
762 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
765 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
766 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
767 } else if (rl == al && rl == bl) {
768 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
769 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
771 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
772 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
774 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
778 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
779 #define MIPS_CMP_INV 1
780 #define MIPS_CMP_SWAP 2
782 static const uint8_t mips_cmp_map[16] = {
785 [TCG_COND_GE] = MIPS_CMP_INV,
786 [TCG_COND_GEU] = MIPS_CMP_INV,
787 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
788 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
789 [TCG_COND_GT] = MIPS_CMP_SWAP,
790 [TCG_COND_GTU] = MIPS_CMP_SWAP,
793 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
794 TCGReg arg1, TCGReg arg2)
796 MIPSInsn s_opc = OPC_SLTU;
802 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
805 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
810 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
813 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
827 cmp_map = mips_cmp_map[cond];
828 if (cmp_map & MIPS_CMP_SWAP) {
833 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
834 if (cmp_map & MIPS_CMP_INV) {
835 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
840 g_assert_not_reached();
845 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
846 TCGReg arg2, TCGLabel *l)
848 static const MIPSInsn b_zero[16] = {
849 [TCG_COND_LT] = OPC_BLTZ,
850 [TCG_COND_GT] = OPC_BGTZ,
851 [TCG_COND_LE] = OPC_BLEZ,
852 [TCG_COND_GE] = OPC_BGEZ,
855 MIPSInsn s_opc = OPC_SLTU;
872 b_opc = b_zero[cond];
884 cmp_map = mips_cmp_map[cond];
885 if (cmp_map & MIPS_CMP_SWAP) {
890 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
891 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
897 g_assert_not_reached();
901 tcg_out_opc_br(s, b_opc, arg1, arg2);
902 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
906 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
907 TCGReg al, TCGReg ah,
908 TCGReg bl, TCGReg bh)
910 /* Merge highpart comparison into AH. */
913 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
919 /* Merge lowpart comparison into AL. */
922 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
928 /* Merge high and low part comparisons into AL. */
931 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
940 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
941 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
943 TCGReg tmp0 = TCG_TMP0;
946 tcg_debug_assert(ret != TCG_TMP0);
947 if (ret == ah || ret == bh) {
948 tcg_debug_assert(ret != TCG_TMP1);
955 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
956 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
960 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
961 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
962 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
963 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
964 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
969 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
970 TCGReg bl, TCGReg bh, TCGLabel *l)
972 TCGCond b_cond = TCG_COND_NE;
973 TCGReg tmp = TCG_TMP1;
975 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
976 With setcond, we emit between 3 and 10 insns and only 1 branch,
977 which ought to get better branch prediction. */
982 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
986 /* Minimize code size by preferring a compare not requiring INV. */
987 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
988 cond = tcg_invert_cond(cond);
989 b_cond = TCG_COND_EQ;
991 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
995 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
998 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
999 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1003 /* If one of the values is zero, put it last to match SEL*Z instructions */
1004 if (use_mips32r6_instructions && v1 == 0) {
1007 cond = tcg_invert_cond(cond);
1016 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1022 /* Minimize code size by preferring a compare not requiring INV. */
1023 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1024 cond = tcg_invert_cond(cond);
1027 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1032 if (use_mips32r6_instructions) {
1033 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1034 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1037 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1039 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1041 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1044 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1046 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1048 /* This should be guaranteed via constraints */
1049 tcg_debug_assert(v2 == ret);
1053 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1055 /* Note that the ABI requires the called function's address to be
1056 loaded into T9, even if a direct branch is in range. */
1057 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1059 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1061 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1062 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1065 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1066 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1071 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1072 const TCGHelperInfo *info)
1074 tcg_out_call_int(s, arg, false);
1078 #if defined(CONFIG_SOFTMMU)
1079 static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
1080 [MO_UB] = helper_ret_ldub_mmu,
1081 [MO_SB] = helper_ret_ldsb_mmu,
1083 [MO_UW] = helper_be_lduw_mmu,
1084 [MO_SW] = helper_be_ldsw_mmu,
1085 [MO_UL] = helper_be_ldul_mmu,
1086 [MO_SL] = helper_be_ldsl_mmu,
1087 [MO_UQ] = helper_be_ldq_mmu,
1089 [MO_UW] = helper_le_lduw_mmu,
1090 [MO_SW] = helper_le_ldsw_mmu,
1091 [MO_UL] = helper_le_ldul_mmu,
1092 [MO_UQ] = helper_le_ldq_mmu,
1093 [MO_SL] = helper_le_ldsl_mmu,
1097 static void * const qemu_st_helpers[MO_SIZE + 1] = {
1098 [MO_UB] = helper_ret_stb_mmu,
1100 [MO_UW] = helper_be_stw_mmu,
1101 [MO_UL] = helper_be_stl_mmu,
1102 [MO_UQ] = helper_be_stq_mmu,
1104 [MO_UW] = helper_le_stw_mmu,
1105 [MO_UL] = helper_le_stl_mmu,
1106 [MO_UQ] = helper_le_stq_mmu,
1110 /* We have four temps, we might as well expose three of them. */
1111 static const TCGLdstHelperParam ldst_helper_param = {
1112 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 }
1115 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1117 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1118 MemOp opc = get_memop(l->oi);
1120 /* resolve label address */
1121 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1122 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1123 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1127 tcg_out_ld_helper_args(s, l, &ldst_helper_param);
1129 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false);
1133 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param);
1135 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1136 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1145 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1147 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1148 MemOp opc = get_memop(l->oi);
1150 /* resolve label address */
1151 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1152 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1153 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1157 tcg_out_st_helper_args(s, l, &ldst_helper_param);
1159 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
1163 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1164 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1174 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
1178 if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1182 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1183 /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */
1184 TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg;
1185 TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg;
1187 if (a3 != TCG_REG_A2) {
1188 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1189 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1190 } else if (a2 != TCG_REG_A3) {
1191 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1192 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1194 tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2);
1195 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3);
1196 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0);
1199 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
1201 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
1204 * Tail call to the helper, with the return address back inline.
1205 * We have arrived here via BNEL, so $31 is already set.
1207 target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st);
1208 tcg_out_call_int(s, target, true);
1212 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1214 return tcg_out_fail_alignment(s, l);
1217 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1219 return tcg_out_fail_alignment(s, l);
1221 #endif /* SOFTMMU */
1229 * For softmmu, perform the TLB load and compare.
1230 * For useronly, perform any required alignment tests.
1231 * In both cases, return a TCGLabelQemuLdst structure if the slow path
1232 * is required and fill in @h with the host address for the fast path.
1234 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1235 TCGReg addrlo, TCGReg addrhi,
1236 MemOpIdx oi, bool is_ld)
1238 TCGLabelQemuLdst *ldst = NULL;
1239 MemOp opc = get_memop(oi);
1240 unsigned a_bits = get_alignment_bits(opc);
1241 unsigned s_bits = opc & MO_SIZE;
1242 unsigned a_mask = (1 << a_bits) - 1;
1245 #ifdef CONFIG_SOFTMMU
1246 unsigned s_mask = (1 << s_bits) - 1;
1247 int mem_index = get_mmuidx(oi);
1248 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1249 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1250 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1251 int add_off = offsetof(CPUTLBEntry, addend);
1252 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1253 : offsetof(CPUTLBEntry, addr_write);
1255 ldst = new_ldst_label(s);
1256 ldst->is_ld = is_ld;
1258 ldst->addrlo_reg = addrlo;
1259 ldst->addrhi_reg = addrhi;
1261 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1262 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1263 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1264 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1265 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1267 /* Extract the TLB index from the address into TMP3. */
1268 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo,
1269 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1270 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1272 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1273 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1275 /* Load the (low-half) tlb comparator. */
1276 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1277 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1279 tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off);
1282 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1283 /* Load the tlb addend for the fast path. */
1284 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
1288 * Mask the page bits, keeping the alignment bits to compare against.
1289 * For unaligned accesses, compare against the end of the access to
1290 * verify that it does not cross a page boundary.
1292 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask);
1293 if (a_mask < s_mask) {
1294 tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrlo, s_mask - a_mask);
1295 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
1297 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
1300 /* Zero extend a 32-bit guest address for a 64-bit host. */
1301 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1302 tcg_out_ext32u(s, TCG_TMP2, addrlo);
1306 ldst->label_ptr[0] = s->code_ptr;
1307 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1309 /* Load and test the high half tlb comparator. */
1310 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1312 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1314 /* Load the tlb addend for the fast path. */
1315 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
1317 ldst->label_ptr[1] = s->code_ptr;
1318 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
1323 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
1325 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
1326 ldst = new_ldst_label(s);
1328 ldst->is_ld = is_ld;
1330 ldst->addrlo_reg = addrlo;
1331 ldst->addrhi_reg = addrhi;
1333 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
1334 tcg_debug_assert(a_bits < 16);
1335 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1337 ldst->label_ptr[0] = s->code_ptr;
1338 if (use_mips32r6_instructions) {
1339 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1341 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1347 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1348 tcg_out_ext32u(s, TCG_REG_A0, base);
1352 if (guest_base == (int16_t)guest_base) {
1353 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
1355 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
1356 TCG_GUEST_BASE_REG);
1367 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1368 TCGReg base, MemOp opc, TCGType type)
1370 switch (opc & MO_SSIZE) {
1372 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1375 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1378 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1381 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1384 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
1385 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1390 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1393 /* Prefer to load from offset 0 first, but allow for overlap. */
1394 if (TCG_TARGET_REG_BITS == 64) {
1395 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1396 } else if (MIPS_BE ? hi != base : lo == base) {
1397 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1398 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1400 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1401 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1405 g_assert_not_reached();
1409 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1410 TCGReg base, MemOp opc, TCGType type)
1412 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
1413 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
1414 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR;
1415 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL;
1416 bool sgn = opc & MO_SIGN;
1418 switch (opc & MO_SIZE) {
1420 if (HOST_BIG_ENDIAN) {
1421 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1422 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1423 if (use_mips32r2_instructions) {
1424 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1426 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1427 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0);
1429 } else if (use_mips32r2_instructions && lo != base) {
1430 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1431 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1432 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1434 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1435 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1436 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1437 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1442 tcg_out_opc_imm(s, lw1, lo, base, 0);
1443 tcg_out_opc_imm(s, lw2, lo, base, 3);
1444 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {
1445 tcg_out_ext32u(s, lo, lo);
1450 if (TCG_TARGET_REG_BITS == 64) {
1451 tcg_out_opc_imm(s, ld1, lo, base, 0);
1452 tcg_out_opc_imm(s, ld2, lo, base, 7);
1454 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0);
1455 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3);
1456 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0);
1457 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3);
1462 g_assert_not_reached();
1466 static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
1467 TCGReg addrlo, TCGReg addrhi,
1468 MemOpIdx oi, TCGType data_type)
1470 MemOp opc = get_memop(oi);
1471 TCGLabelQemuLdst *ldst;
1474 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
1476 if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
1477 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
1479 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
1483 ldst->type = data_type;
1484 ldst->datalo_reg = datalo;
1485 ldst->datahi_reg = datahi;
1486 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1490 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1491 TCGReg base, MemOp opc)
1493 switch (opc & MO_SIZE) {
1495 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1498 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1501 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1504 if (TCG_TARGET_REG_BITS == 64) {
1505 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1507 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1508 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1512 g_assert_not_reached();
1516 static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1517 TCGReg base, MemOp opc)
1519 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR;
1520 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL;
1521 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR;
1522 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL;
1524 switch (opc & MO_SIZE) {
1526 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1527 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0);
1528 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1);
1532 tcg_out_opc_imm(s, sw1, lo, base, 0);
1533 tcg_out_opc_imm(s, sw2, lo, base, 3);
1537 if (TCG_TARGET_REG_BITS == 64) {
1538 tcg_out_opc_imm(s, sd1, lo, base, 0);
1539 tcg_out_opc_imm(s, sd2, lo, base, 7);
1541 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0);
1542 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3);
1543 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0);
1544 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3);
1549 g_assert_not_reached();
1553 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
1554 TCGReg addrlo, TCGReg addrhi,
1555 MemOpIdx oi, TCGType data_type)
1557 MemOp opc = get_memop(oi);
1558 TCGLabelQemuLdst *ldst;
1561 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
1563 if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
1564 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
1566 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
1570 ldst->type = data_type;
1571 ldst->datalo_reg = datalo;
1572 ldst->datahi_reg = datahi;
1573 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1577 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1579 static const MIPSInsn sync[] = {
1580 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1581 as the former is an ordering barrier and the latter
1582 is a completion barrier. */
1583 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1584 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1585 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1586 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1587 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1588 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1590 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1593 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1594 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1596 if (use_mips32r6_instructions) {
1598 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1600 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1601 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1605 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1606 } else if (a0 == a2) {
1607 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1608 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1609 } else if (a0 != a1) {
1610 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1611 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1613 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1614 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1615 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1620 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1622 TCGReg b0 = TCG_REG_ZERO;
1625 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1628 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1629 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
1630 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1632 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1635 static void tcg_out_goto_tb(TCGContext *s, int which)
1637 /* indirect jump method */
1638 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1639 get_jmp_target_addr(s, which));
1640 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1642 set_jmp_reset_offset(s, which);
1645 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1646 uintptr_t jmp_rx, uintptr_t jmp_rw)
1648 /* Always indirect, nothing to do */
1651 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1652 const TCGArg args[TCG_MAX_OP_ARGS],
1653 const int const_args[TCG_MAX_OP_ARGS])
1660 * Note that many operands use the constraint set "rZ".
1661 * We make use of the fact that 0 is the ZERO register,
1662 * and hence such cases need not check for const_args.
1670 case INDEX_op_goto_ptr:
1671 /* jmp to the given host address (could be epilogue) */
1672 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1676 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1680 case INDEX_op_ld8u_i32:
1681 case INDEX_op_ld8u_i64:
1684 case INDEX_op_ld8s_i32:
1685 case INDEX_op_ld8s_i64:
1688 case INDEX_op_ld16u_i32:
1689 case INDEX_op_ld16u_i64:
1692 case INDEX_op_ld16s_i32:
1693 case INDEX_op_ld16s_i64:
1696 case INDEX_op_ld_i32:
1697 case INDEX_op_ld32s_i64:
1700 case INDEX_op_ld32u_i64:
1703 case INDEX_op_ld_i64:
1706 case INDEX_op_st8_i32:
1707 case INDEX_op_st8_i64:
1710 case INDEX_op_st16_i32:
1711 case INDEX_op_st16_i64:
1714 case INDEX_op_st_i32:
1715 case INDEX_op_st32_i64:
1718 case INDEX_op_st_i64:
1721 tcg_out_ldst(s, i1, a0, a1, a2);
1724 case INDEX_op_add_i32:
1725 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1727 case INDEX_op_add_i64:
1728 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1730 case INDEX_op_or_i32:
1731 case INDEX_op_or_i64:
1732 i1 = OPC_OR, i2 = OPC_ORI;
1734 case INDEX_op_xor_i32:
1735 case INDEX_op_xor_i64:
1736 i1 = OPC_XOR, i2 = OPC_XORI;
1739 tcg_out_opc_imm(s, i2, a0, a1, a2);
1743 tcg_out_opc_reg(s, i1, a0, a1, a2);
1746 case INDEX_op_sub_i32:
1747 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1749 case INDEX_op_sub_i64:
1750 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1753 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1757 case INDEX_op_and_i32:
1758 if (c2 && a2 != (uint16_t)a2) {
1759 int msb = ctz32(~a2) - 1;
1760 tcg_debug_assert(use_mips32r2_instructions);
1761 tcg_debug_assert(is_p2m1(a2));
1762 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1765 i1 = OPC_AND, i2 = OPC_ANDI;
1767 case INDEX_op_and_i64:
1768 if (c2 && a2 != (uint16_t)a2) {
1769 int msb = ctz64(~a2) - 1;
1770 tcg_debug_assert(use_mips32r2_instructions);
1771 tcg_debug_assert(is_p2m1(a2));
1772 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1775 i1 = OPC_AND, i2 = OPC_ANDI;
1777 case INDEX_op_nor_i32:
1778 case INDEX_op_nor_i64:
1782 case INDEX_op_mul_i32:
1783 if (use_mips32_instructions) {
1784 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1787 i1 = OPC_MULT, i2 = OPC_MFLO;
1789 case INDEX_op_mulsh_i32:
1790 if (use_mips32r6_instructions) {
1791 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1794 i1 = OPC_MULT, i2 = OPC_MFHI;
1796 case INDEX_op_muluh_i32:
1797 if (use_mips32r6_instructions) {
1798 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1801 i1 = OPC_MULTU, i2 = OPC_MFHI;
1803 case INDEX_op_div_i32:
1804 if (use_mips32r6_instructions) {
1805 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1808 i1 = OPC_DIV, i2 = OPC_MFLO;
1810 case INDEX_op_divu_i32:
1811 if (use_mips32r6_instructions) {
1812 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1815 i1 = OPC_DIVU, i2 = OPC_MFLO;
1817 case INDEX_op_rem_i32:
1818 if (use_mips32r6_instructions) {
1819 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1822 i1 = OPC_DIV, i2 = OPC_MFHI;
1824 case INDEX_op_remu_i32:
1825 if (use_mips32r6_instructions) {
1826 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1829 i1 = OPC_DIVU, i2 = OPC_MFHI;
1831 case INDEX_op_mul_i64:
1832 if (use_mips32r6_instructions) {
1833 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1836 i1 = OPC_DMULT, i2 = OPC_MFLO;
1838 case INDEX_op_mulsh_i64:
1839 if (use_mips32r6_instructions) {
1840 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1843 i1 = OPC_DMULT, i2 = OPC_MFHI;
1845 case INDEX_op_muluh_i64:
1846 if (use_mips32r6_instructions) {
1847 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1850 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1852 case INDEX_op_div_i64:
1853 if (use_mips32r6_instructions) {
1854 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1857 i1 = OPC_DDIV, i2 = OPC_MFLO;
1859 case INDEX_op_divu_i64:
1860 if (use_mips32r6_instructions) {
1861 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1864 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1866 case INDEX_op_rem_i64:
1867 if (use_mips32r6_instructions) {
1868 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1871 i1 = OPC_DDIV, i2 = OPC_MFHI;
1873 case INDEX_op_remu_i64:
1874 if (use_mips32r6_instructions) {
1875 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1878 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1880 tcg_out_opc_reg(s, i1, 0, a1, a2);
1881 tcg_out_opc_reg(s, i2, a0, 0, 0);
1884 case INDEX_op_muls2_i32:
1887 case INDEX_op_mulu2_i32:
1890 case INDEX_op_muls2_i64:
1893 case INDEX_op_mulu2_i64:
1896 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1897 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1898 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1901 case INDEX_op_not_i32:
1902 case INDEX_op_not_i64:
1906 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1909 case INDEX_op_bswap16_i32:
1910 case INDEX_op_bswap16_i64:
1911 tcg_out_bswap16(s, a0, a1, a2);
1913 case INDEX_op_bswap32_i32:
1914 tcg_out_bswap32(s, a0, a1, 0);
1916 case INDEX_op_bswap32_i64:
1917 tcg_out_bswap32(s, a0, a1, a2);
1919 case INDEX_op_bswap64_i64:
1920 tcg_out_bswap64(s, a0, a1);
1922 case INDEX_op_extrh_i64_i32:
1923 tcg_out_dsra(s, a0, a1, 32);
1926 case INDEX_op_sar_i32:
1927 i1 = OPC_SRAV, i2 = OPC_SRA;
1929 case INDEX_op_shl_i32:
1930 i1 = OPC_SLLV, i2 = OPC_SLL;
1932 case INDEX_op_shr_i32:
1933 i1 = OPC_SRLV, i2 = OPC_SRL;
1935 case INDEX_op_rotr_i32:
1936 i1 = OPC_ROTRV, i2 = OPC_ROTR;
1939 tcg_out_opc_sa(s, i2, a0, a1, a2);
1943 tcg_out_opc_reg(s, i1, a0, a2, a1);
1945 case INDEX_op_rotl_i32:
1947 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
1949 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
1950 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
1953 case INDEX_op_sar_i64:
1955 tcg_out_dsra(s, a0, a1, a2);
1960 case INDEX_op_shl_i64:
1962 tcg_out_dsll(s, a0, a1, a2);
1967 case INDEX_op_shr_i64:
1969 tcg_out_dsrl(s, a0, a1, a2);
1974 case INDEX_op_rotr_i64:
1976 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
1981 case INDEX_op_rotl_i64:
1983 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
1985 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
1986 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
1990 case INDEX_op_clz_i32:
1991 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
1993 case INDEX_op_clz_i64:
1994 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
1997 case INDEX_op_deposit_i32:
1998 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2000 case INDEX_op_deposit_i64:
2001 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2002 args[3] + args[4] - 1, args[3]);
2004 case INDEX_op_extract_i32:
2005 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2007 case INDEX_op_extract_i64:
2008 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2012 case INDEX_op_brcond_i32:
2013 case INDEX_op_brcond_i64:
2014 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2016 case INDEX_op_brcond2_i32:
2017 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2020 case INDEX_op_movcond_i32:
2021 case INDEX_op_movcond_i64:
2022 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2025 case INDEX_op_setcond_i32:
2026 case INDEX_op_setcond_i64:
2027 tcg_out_setcond(s, args[3], a0, a1, a2);
2029 case INDEX_op_setcond2_i32:
2030 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2033 case INDEX_op_qemu_ld_i32:
2034 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
2035 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
2037 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
2040 case INDEX_op_qemu_ld_i64:
2041 if (TCG_TARGET_REG_BITS == 64) {
2042 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2043 } else if (TARGET_LONG_BITS == 32) {
2044 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
2046 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2049 case INDEX_op_qemu_st_i32:
2050 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
2051 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
2053 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
2056 case INDEX_op_qemu_st_i64:
2057 if (TCG_TARGET_REG_BITS == 64) {
2058 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2059 } else if (TARGET_LONG_BITS == 32) {
2060 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
2062 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2066 case INDEX_op_add2_i32:
2067 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2068 const_args[4], const_args[5], false);
2070 case INDEX_op_sub2_i32:
2071 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2072 const_args[4], const_args[5], true);
2078 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2079 case INDEX_op_mov_i64:
2080 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2081 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2082 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2083 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2084 case INDEX_op_ext8s_i64:
2085 case INDEX_op_ext8u_i32:
2086 case INDEX_op_ext8u_i64:
2087 case INDEX_op_ext16s_i32:
2088 case INDEX_op_ext16s_i64:
2089 case INDEX_op_ext32s_i64:
2090 case INDEX_op_ext32u_i64:
2091 case INDEX_op_ext_i32_i64:
2092 case INDEX_op_extu_i32_i64:
2093 case INDEX_op_extrl_i64_i32:
2095 g_assert_not_reached();
2099 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2102 case INDEX_op_goto_ptr:
2105 case INDEX_op_ld8u_i32:
2106 case INDEX_op_ld8s_i32:
2107 case INDEX_op_ld16u_i32:
2108 case INDEX_op_ld16s_i32:
2109 case INDEX_op_ld_i32:
2110 case INDEX_op_not_i32:
2111 case INDEX_op_bswap16_i32:
2112 case INDEX_op_bswap32_i32:
2113 case INDEX_op_ext8s_i32:
2114 case INDEX_op_ext16s_i32:
2115 case INDEX_op_extract_i32:
2116 case INDEX_op_ld8u_i64:
2117 case INDEX_op_ld8s_i64:
2118 case INDEX_op_ld16u_i64:
2119 case INDEX_op_ld16s_i64:
2120 case INDEX_op_ld32s_i64:
2121 case INDEX_op_ld32u_i64:
2122 case INDEX_op_ld_i64:
2123 case INDEX_op_not_i64:
2124 case INDEX_op_bswap16_i64:
2125 case INDEX_op_bswap32_i64:
2126 case INDEX_op_bswap64_i64:
2127 case INDEX_op_ext8s_i64:
2128 case INDEX_op_ext16s_i64:
2129 case INDEX_op_ext32s_i64:
2130 case INDEX_op_ext32u_i64:
2131 case INDEX_op_ext_i32_i64:
2132 case INDEX_op_extu_i32_i64:
2133 case INDEX_op_extrl_i64_i32:
2134 case INDEX_op_extrh_i64_i32:
2135 case INDEX_op_extract_i64:
2136 return C_O1_I1(r, r);
2138 case INDEX_op_st8_i32:
2139 case INDEX_op_st16_i32:
2140 case INDEX_op_st_i32:
2141 case INDEX_op_st8_i64:
2142 case INDEX_op_st16_i64:
2143 case INDEX_op_st32_i64:
2144 case INDEX_op_st_i64:
2145 return C_O0_I2(rZ, r);
2147 case INDEX_op_add_i32:
2148 case INDEX_op_add_i64:
2149 return C_O1_I2(r, r, rJ);
2150 case INDEX_op_sub_i32:
2151 case INDEX_op_sub_i64:
2152 return C_O1_I2(r, rZ, rN);
2153 case INDEX_op_mul_i32:
2154 case INDEX_op_mulsh_i32:
2155 case INDEX_op_muluh_i32:
2156 case INDEX_op_div_i32:
2157 case INDEX_op_divu_i32:
2158 case INDEX_op_rem_i32:
2159 case INDEX_op_remu_i32:
2160 case INDEX_op_nor_i32:
2161 case INDEX_op_setcond_i32:
2162 case INDEX_op_mul_i64:
2163 case INDEX_op_mulsh_i64:
2164 case INDEX_op_muluh_i64:
2165 case INDEX_op_div_i64:
2166 case INDEX_op_divu_i64:
2167 case INDEX_op_rem_i64:
2168 case INDEX_op_remu_i64:
2169 case INDEX_op_nor_i64:
2170 case INDEX_op_setcond_i64:
2171 return C_O1_I2(r, rZ, rZ);
2172 case INDEX_op_muls2_i32:
2173 case INDEX_op_mulu2_i32:
2174 case INDEX_op_muls2_i64:
2175 case INDEX_op_mulu2_i64:
2176 return C_O2_I2(r, r, r, r);
2177 case INDEX_op_and_i32:
2178 case INDEX_op_and_i64:
2179 return C_O1_I2(r, r, rIK);
2180 case INDEX_op_or_i32:
2181 case INDEX_op_xor_i32:
2182 case INDEX_op_or_i64:
2183 case INDEX_op_xor_i64:
2184 return C_O1_I2(r, r, rI);
2185 case INDEX_op_shl_i32:
2186 case INDEX_op_shr_i32:
2187 case INDEX_op_sar_i32:
2188 case INDEX_op_rotr_i32:
2189 case INDEX_op_rotl_i32:
2190 case INDEX_op_shl_i64:
2191 case INDEX_op_shr_i64:
2192 case INDEX_op_sar_i64:
2193 case INDEX_op_rotr_i64:
2194 case INDEX_op_rotl_i64:
2195 return C_O1_I2(r, r, ri);
2196 case INDEX_op_clz_i32:
2197 case INDEX_op_clz_i64:
2198 return C_O1_I2(r, r, rWZ);
2200 case INDEX_op_deposit_i32:
2201 case INDEX_op_deposit_i64:
2202 return C_O1_I2(r, 0, rZ);
2203 case INDEX_op_brcond_i32:
2204 case INDEX_op_brcond_i64:
2205 return C_O0_I2(rZ, rZ);
2206 case INDEX_op_movcond_i32:
2207 case INDEX_op_movcond_i64:
2208 return (use_mips32r6_instructions
2209 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2210 : C_O1_I4(r, rZ, rZ, rZ, 0));
2211 case INDEX_op_add2_i32:
2212 case INDEX_op_sub2_i32:
2213 return C_O2_I4(r, r, rZ, rZ, rN, rN);
2214 case INDEX_op_setcond2_i32:
2215 return C_O1_I4(r, rZ, rZ, rZ, rZ);
2216 case INDEX_op_brcond2_i32:
2217 return C_O0_I4(rZ, rZ, rZ, rZ);
2219 case INDEX_op_qemu_ld_i32:
2220 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2221 ? C_O1_I1(r, r) : C_O1_I2(r, r, r));
2222 case INDEX_op_qemu_st_i32:
2223 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2224 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r));
2225 case INDEX_op_qemu_ld_i64:
2226 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
2227 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, r)
2228 : C_O2_I2(r, r, r, r));
2229 case INDEX_op_qemu_st_i64:
2230 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
2231 : TARGET_LONG_BITS == 32 ? C_O0_I3(rZ, rZ, r)
2232 : C_O0_I4(rZ, rZ, r, r));
2235 g_assert_not_reached();
2239 static const int tcg_target_callee_save_regs[] = {
2240 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2249 TCG_REG_RA, /* should be last for ABI compliance */
2252 /* The Linux kernel doesn't provide any information about the available
2253 instruction set. Probe it using a signal handler. */
2256 #ifndef use_movnz_instructions
2257 bool use_movnz_instructions = false;
2260 #ifndef use_mips32_instructions
2261 bool use_mips32_instructions = false;
2264 #ifndef use_mips32r2_instructions
2265 bool use_mips32r2_instructions = false;
2268 static volatile sig_atomic_t got_sigill;
2270 static void sigill_handler(int signo, siginfo_t *si, void *data)
2272 /* Skip the faulty instruction */
2273 ucontext_t *uc = (ucontext_t *)data;
2274 uc->uc_mcontext.pc += 4;
2279 static void tcg_target_detect_isa(void)
2281 struct sigaction sa_old, sa_new;
2283 memset(&sa_new, 0, sizeof(sa_new));
2284 sa_new.sa_flags = SA_SIGINFO;
2285 sa_new.sa_sigaction = sigill_handler;
2286 sigaction(SIGILL, &sa_new, &sa_old);
2288 /* Probe for movn/movz, necessary to implement movcond. */
2289 #ifndef use_movnz_instructions
2291 asm volatile(".set push\n"
2293 "movn $zero, $zero, $zero\n"
2294 "movz $zero, $zero, $zero\n"
2297 use_movnz_instructions = !got_sigill;
2300 /* Probe for MIPS32 instructions. As no subsetting is allowed
2301 by the specification, it is only necessary to probe for one
2302 of the instructions. */
2303 #ifndef use_mips32_instructions
2305 asm volatile(".set push\n"
2307 "mul $zero, $zero\n"
2310 use_mips32_instructions = !got_sigill;
2313 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2314 available. As no subsetting is allowed by the specification,
2315 it is only necessary to probe for one of the instructions. */
2316 #ifndef use_mips32r2_instructions
2317 if (use_mips32_instructions) {
2319 asm volatile(".set push\n"
2321 "seb $zero, $zero\n"
2324 use_mips32r2_instructions = !got_sigill;
2328 sigaction(SIGILL, &sa_old, NULL);
2331 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2333 uintptr_t p = (uintptr_t)s->code_ptr;
2336 s->code_ptr = (void *)p;
2341 /* Stack frame parameters. */
2342 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2343 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2344 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2346 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2347 + TCG_TARGET_STACK_ALIGN - 1) \
2348 & -TCG_TARGET_STACK_ALIGN)
2349 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2351 /* We're expecting to be able to use an immediate for frame allocation. */
2352 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2354 /* Generate global QEMU prologue and epilogue code */
2355 static void tcg_target_qemu_prologue(TCGContext *s)
2359 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2362 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2363 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2364 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2365 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2368 #ifndef CONFIG_SOFTMMU
2370 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2371 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2375 /* Call generated code */
2376 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2378 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2381 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2382 * and fall through to the rest of the epilogue.
2384 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2385 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2388 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2389 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2390 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2391 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2394 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2396 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2398 if (use_mips32r2_instructions) {
2402 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2403 clobbers TCG_TMP1, TCG_TMP2. */
2406 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2408 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2409 /* t3 = (ssss)d000 */
2410 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2412 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2414 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2416 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2418 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2420 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2422 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2424 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2425 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2426 /* t3 = dcba -- delay slot */
2427 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2429 if (TCG_TARGET_REG_BITS == 32) {
2434 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2436 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2437 /* t1 = (0000)000d */
2438 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2440 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2441 /* t1 = (0000)d000 */
2442 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2444 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2446 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2448 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2450 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2452 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2454 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2455 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2456 /* t3 = dcba -- delay slot */
2457 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2460 * bswap64 -- 64-bit swap. a0 = abcdefgh
2462 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2464 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2466 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2469 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2471 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2473 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2475 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2477 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2480 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2482 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2484 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2487 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2489 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2491 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2493 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2496 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2498 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2500 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2503 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2505 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2507 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2509 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2512 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2513 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2514 /* t3 = hgfedcba -- delay slot */
2515 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2518 static void tcg_target_init(TCGContext *s)
2520 tcg_target_detect_isa();
2521 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2522 if (TCG_TARGET_REG_BITS == 64) {
2523 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2526 tcg_target_call_clobber_regs = 0;
2527 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2528 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2529 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2530 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2531 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2532 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2533 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2534 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2535 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2536 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2537 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2538 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2539 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2540 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2541 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2542 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2544 s->reserved_regs = 0;
2545 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2546 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2547 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2548 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2549 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2550 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2551 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2552 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2553 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2554 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2559 uint8_t fde_def_cfa[4];
2560 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2563 #define ELF_HOST_MACHINE EM_MIPS
2564 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2565 which is good because they're really quite complicated for MIPS. */
2567 static const DebugFrame debug_frame = {
2568 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2571 .h.cie.code_align = 1,
2572 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2573 .h.cie.return_column = TCG_REG_RA,
2575 /* Total FDE size does not include the "len" member. */
2576 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2579 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2580 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2584 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2585 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2586 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2587 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2588 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2589 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2590 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2591 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2592 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2596 void tcg_register_jit(const void *buf, size_t buf_size)
2598 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));