2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static uint8_t *tb_ret_addr
;
27 #if defined _CALL_DARWIN || defined __APPLE__
28 #define TCG_TARGET_CALL_DARWIN
31 #ifdef TCG_TARGET_CALL_DARWIN
32 #define LINKAGE_AREA_SIZE 24
34 #elif defined _CALL_AIX
35 #define LINKAGE_AREA_SIZE 52
38 #define LINKAGE_AREA_SIZE 8
48 #ifdef CONFIG_USE_GUEST_BASE
49 #define TCG_GUEST_BASE_REG 30
51 #define TCG_GUEST_BASE_REG 0
55 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
91 static const int tcg_target_reg_alloc_order
[] = {
106 #ifdef TCG_TARGET_CALL_DARWIN
117 #ifndef TCG_TARGET_CALL_DARWIN
130 static const int tcg_target_call_iarg_regs
[] = {
141 static const int tcg_target_call_oarg_regs
[2] = {
146 static const int tcg_target_callee_save_regs
[] = {
147 #ifdef TCG_TARGET_CALL_DARWIN
167 TCG_REG_R27
, /* currently used for the global env */
174 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
176 tcg_target_long disp
;
178 disp
= target
- (tcg_target_long
) pc
;
179 if ((disp
<< 6) >> 6 != disp
)
182 return disp
& 0x3fffffc;
185 static void reloc_pc24 (void *pc
, tcg_target_long target
)
187 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
188 | reloc_pc24_val (pc
, target
);
191 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
193 tcg_target_long disp
;
195 disp
= target
- (tcg_target_long
) pc
;
196 if (disp
!= (int16_t) disp
)
199 return disp
& 0xfffc;
202 static void reloc_pc14 (void *pc
, tcg_target_long target
)
204 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
205 | reloc_pc14_val (pc
, target
);
208 static void patch_reloc(uint8_t *code_ptr
, int type
,
209 tcg_target_long value
, tcg_target_long addend
)
214 reloc_pc14 (code_ptr
, value
);
217 reloc_pc24 (code_ptr
, value
);
224 /* maximum number of register used for input function arguments */
225 static int tcg_target_get_call_iarg_regs_count(int flags
)
227 return ARRAY_SIZE (tcg_target_call_iarg_regs
);
230 /* parse target specific constraints */
231 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
237 case 'A': case 'B': case 'C': case 'D':
238 ct
->ct
|= TCG_CT_REG
;
239 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
242 ct
->ct
|= TCG_CT_REG
;
243 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
245 #ifdef CONFIG_SOFTMMU
246 case 'L': /* qemu_ld constraint */
247 ct
->ct
|= TCG_CT_REG
;
248 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
249 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
250 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
251 #ifdef CONFIG_TCG_PASS_AREG0
252 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
253 #if TARGET_LONG_BITS == 64
254 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
255 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
256 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R7
);
260 #if TARGET_LONG_BITS == 64
261 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
265 case 'K': /* qemu_st[8..32] constraint */
266 ct
->ct
|= TCG_CT_REG
;
267 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
268 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
269 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
270 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
271 #ifdef CONFIG_TCG_PASS_AREG0
272 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
273 #if TARGET_LONG_BITS == 64
274 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R7
);
275 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
276 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R8
);
280 #if TARGET_LONG_BITS == 64
281 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
285 case 'M': /* qemu_st64 constraint */
286 ct
->ct
|= TCG_CT_REG
;
287 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
288 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
289 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
290 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
291 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
292 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R7
);
293 #if defined(CONFIG_TCG_PASS_AREG0)
294 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R8
);
295 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
296 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R9
);
303 ct
->ct
|= TCG_CT_REG
;
304 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
307 ct
->ct
|= TCG_CT_REG
;
308 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
309 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
320 /* test if a constant matches the constraint */
321 static int tcg_target_const_match(tcg_target_long val
,
322 const TCGArgConstraint
*arg_ct
)
327 if (ct
& TCG_CT_CONST
)
332 #define OPCD(opc) ((opc)<<26)
333 #define XO31(opc) (OPCD(31)|((opc)<<1))
334 #define XO19(opc) (OPCD(19)|((opc)<<1))
346 #define ADDIC OPCD(12)
347 #define ADDI OPCD(14)
348 #define ADDIS OPCD(15)
350 #define ORIS OPCD(25)
351 #define XORI OPCD(26)
352 #define XORIS OPCD(27)
353 #define ANDI OPCD(28)
354 #define ANDIS OPCD(29)
355 #define MULLI OPCD( 7)
356 #define CMPLI OPCD(10)
357 #define CMPI OPCD(11)
358 #define SUBFIC OPCD( 8)
360 #define LWZU OPCD(33)
361 #define STWU OPCD(37)
363 #define RLWIMI OPCD(20)
364 #define RLWINM OPCD(21)
365 #define RLWNM OPCD(23)
367 #define BCLR XO19( 16)
368 #define BCCTR XO19(528)
369 #define CRAND XO19(257)
370 #define CRANDC XO19(129)
371 #define CRNAND XO19(225)
372 #define CROR XO19(449)
373 #define CRNOR XO19( 33)
375 #define EXTSB XO31(954)
376 #define EXTSH XO31(922)
377 #define ADD XO31(266)
378 #define ADDE XO31(138)
379 #define ADDC XO31( 10)
380 #define AND XO31( 28)
381 #define SUBF XO31( 40)
382 #define SUBFC XO31( 8)
383 #define SUBFE XO31(136)
385 #define XOR XO31(316)
386 #define MULLW XO31(235)
387 #define MULHWU XO31( 11)
388 #define DIVW XO31(491)
389 #define DIVWU XO31(459)
391 #define CMPL XO31( 32)
392 #define LHBRX XO31(790)
393 #define LWBRX XO31(534)
394 #define STHBRX XO31(918)
395 #define STWBRX XO31(662)
396 #define MFSPR XO31(339)
397 #define MTSPR XO31(467)
398 #define SRAWI XO31(824)
399 #define NEG XO31(104)
400 #define MFCR XO31( 19)
401 #define CNTLZW XO31( 26)
402 #define NOR XO31(124)
403 #define ANDC XO31( 60)
404 #define ORC XO31(412)
405 #define EQV XO31(284)
406 #define NAND XO31(476)
408 #define LBZX XO31( 87)
409 #define LHZX XO31(279)
410 #define LHAX XO31(343)
411 #define LWZX XO31( 23)
412 #define STBX XO31(215)
413 #define STHX XO31(407)
414 #define STWX XO31(151)
416 #define SPR(a,b) ((((a)<<5)|(b))<<11)
418 #define CTR SPR(9, 0)
420 #define SLW XO31( 24)
421 #define SRW XO31(536)
422 #define SRAW XO31(792)
425 #define TRAP (TW | TO (31))
427 #define RT(r) ((r)<<21)
428 #define RS(r) ((r)<<21)
429 #define RA(r) ((r)<<16)
430 #define RB(r) ((r)<<11)
431 #define TO(t) ((t)<<21)
432 #define SH(s) ((s)<<11)
433 #define MB(b) ((b)<<6)
434 #define ME(e) ((e)<<1)
435 #define BO(o) ((o)<<21)
439 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
440 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
442 #define BF(n) ((n)<<23)
443 #define BI(n, c) (((c)+((n)*4))<<16)
444 #define BT(n, c) (((c)+((n)*4))<<21)
445 #define BA(n, c) (((c)+((n)*4))<<16)
446 #define BB(n, c) (((c)+((n)*4))<<11)
448 #define BO_COND_TRUE BO (12)
449 #define BO_COND_FALSE BO (4)
450 #define BO_ALWAYS BO (20)
459 static const uint32_t tcg_to_bc
[10] = {
460 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
461 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
462 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
463 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
464 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
465 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
466 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
467 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
468 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
469 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
472 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
474 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
477 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
478 TCGReg ret
, tcg_target_long arg
)
480 if (arg
== (int16_t) arg
)
481 tcg_out32 (s
, ADDI
| RT (ret
) | RA (0) | (arg
& 0xffff));
483 tcg_out32 (s
, ADDIS
| RT (ret
) | RA (0) | ((arg
>> 16) & 0xffff));
485 tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | (arg
& 0xffff));
489 static void tcg_out_ldst (TCGContext
*s
, int ret
, int addr
,
490 int offset
, int op1
, int op2
)
492 if (offset
== (int16_t) offset
)
493 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
495 tcg_out_movi (s
, TCG_TYPE_I32
, 0, offset
);
496 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
500 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
502 tcg_target_long disp
;
504 disp
= target
- (tcg_target_long
) s
->code_ptr
;
505 if ((disp
<< 6) >> 6 == disp
)
506 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
508 tcg_out_movi (s
, TCG_TYPE_I32
, 0, (tcg_target_long
) target
);
509 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
510 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
514 static void tcg_out_call (TCGContext
*s
, tcg_target_long arg
, int const_arg
)
521 tcg_out_movi (s
, TCG_TYPE_I32
, reg
, arg
);
525 tcg_out32 (s
, LWZ
| RT (0) | RA (reg
));
526 tcg_out32 (s
, MTSPR
| RA (0) | CTR
);
527 tcg_out32 (s
, LWZ
| RT (2) | RA (reg
) | 4);
528 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| LK
);
531 tcg_out_b (s
, LK
, arg
);
534 tcg_out32 (s
, MTSPR
| RS (arg
) | LR
);
535 tcg_out32 (s
, BCLR
| BO_ALWAYS
| LK
);
540 #if defined(CONFIG_SOFTMMU)
542 #include "../../softmmu_defs.h"
544 #ifdef CONFIG_TCG_PASS_AREG0
545 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
547 static const void * const qemu_ld_helpers
[4] = {
554 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
555 uintxx_t val, int mmu_idx) */
556 static const void * const qemu_st_helpers
[4] = {
563 /* legacy helper signature: __ld_mmu(target_ulong addr, int
565 static void *qemu_ld_helpers
[4] = {
572 /* legacy helper signature: __ld_mmu(target_ulong addr, int
574 static void *qemu_st_helpers
[4] = {
583 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
585 int addr_reg
, data_reg
, data_reg2
, r0
, r1
, rbase
, bswap
;
586 #ifdef CONFIG_SOFTMMU
587 int mem_index
, s_bits
, r2
, ir
;
588 void *label1_ptr
, *label2_ptr
;
589 #if TARGET_LONG_BITS == 64
601 #ifdef CONFIG_SOFTMMU
602 #if TARGET_LONG_BITS == 64
612 tcg_out32 (s
, (RLWINM
615 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
616 | MB (32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
))
617 | ME (31 - CPU_TLB_ENTRY_BITS
)
620 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
624 | offsetof (CPUArchState
, tlb_table
[mem_index
][0].addr_read
)
627 tcg_out32 (s
, (RLWINM
631 | MB ((32 - s_bits
) & 31)
632 | ME (31 - TARGET_PAGE_BITS
)
636 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
));
637 #if TARGET_LONG_BITS == 64
638 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
639 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
640 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
643 label1_ptr
= s
->code_ptr
;
645 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
650 #ifdef CONFIG_TCG_PASS_AREG0
651 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, TCG_AREG0
);
653 #if TARGET_LONG_BITS == 32
654 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, addr_reg
);
656 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
659 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, addr_reg2
);
660 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, addr_reg
);
662 tcg_out_movi (s
, TCG_TYPE_I32
, ir
, mem_index
);
664 tcg_out_call (s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
], 1);
667 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (3));
670 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (3));
676 tcg_out_mov (s
, TCG_TYPE_I32
, data_reg
, 3);
680 if (data_reg2
== 4) {
681 tcg_out_mov (s
, TCG_TYPE_I32
, 0, 4);
682 tcg_out_mov (s
, TCG_TYPE_I32
, 4, 3);
683 tcg_out_mov (s
, TCG_TYPE_I32
, 3, 0);
686 tcg_out_mov (s
, TCG_TYPE_I32
, data_reg2
, 3);
687 tcg_out_mov (s
, TCG_TYPE_I32
, 3, 4);
691 if (data_reg
!= 4) tcg_out_mov (s
, TCG_TYPE_I32
, data_reg
, 4);
692 if (data_reg2
!= 3) tcg_out_mov (s
, TCG_TYPE_I32
, data_reg2
, 3);
696 label2_ptr
= s
->code_ptr
;
699 /* label1: fast path */
701 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
704 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
708 | (offsetof (CPUTLBEntry
, addend
)
709 - offsetof (CPUTLBEntry
, addr_read
))
711 /* r0 = env->tlb_table[mem_index][index].addend */
712 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
713 /* r0 = env->tlb_table[mem_index][index].addend + addr */
715 #else /* !CONFIG_SOFTMMU */
718 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
721 #ifdef TARGET_WORDS_BIGENDIAN
730 tcg_out32 (s
, LBZX
| TAB (data_reg
, rbase
, r0
));
733 tcg_out32 (s
, LBZX
| TAB (data_reg
, rbase
, r0
));
734 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (data_reg
));
738 tcg_out32 (s
, LHBRX
| TAB (data_reg
, rbase
, r0
));
740 tcg_out32 (s
, LHZX
| TAB (data_reg
, rbase
, r0
));
744 tcg_out32 (s
, LHBRX
| TAB (data_reg
, rbase
, r0
));
745 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (data_reg
));
747 else tcg_out32 (s
, LHAX
| TAB (data_reg
, rbase
, r0
));
751 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
753 tcg_out32 (s
, LWZX
| TAB (data_reg
, rbase
, r0
));
757 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
758 tcg_out32 (s
, LWBRX
| TAB (data_reg
, rbase
, r0
));
759 tcg_out32 (s
, LWBRX
| TAB (data_reg2
, rbase
, r1
));
762 #ifdef CONFIG_USE_GUEST_BASE
763 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
764 tcg_out32 (s
, LWZX
| TAB (data_reg2
, rbase
, r0
));
765 tcg_out32 (s
, LWZX
| TAB (data_reg
, rbase
, r1
));
767 if (r0
== data_reg2
) {
768 tcg_out32 (s
, LWZ
| RT (0) | RA (r0
));
769 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
770 tcg_out_mov (s
, TCG_TYPE_I32
, data_reg2
, 0);
773 tcg_out32 (s
, LWZ
| RT (data_reg2
) | RA (r0
));
774 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
781 #ifdef CONFIG_SOFTMMU
782 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
786 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
788 int addr_reg
, r0
, r1
, data_reg
, data_reg2
, bswap
, rbase
;
789 #ifdef CONFIG_SOFTMMU
790 int mem_index
, r2
, ir
;
791 void *label1_ptr
, *label2_ptr
;
792 #if TARGET_LONG_BITS == 64
804 #ifdef CONFIG_SOFTMMU
805 #if TARGET_LONG_BITS == 64
814 tcg_out32 (s
, (RLWINM
817 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
818 | MB (32 - (CPU_TLB_ENTRY_BITS
+ CPU_TLB_BITS
))
819 | ME (31 - CPU_TLB_ENTRY_BITS
)
822 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
826 | offsetof (CPUArchState
, tlb_table
[mem_index
][0].addr_write
)
829 tcg_out32 (s
, (RLWINM
833 | MB ((32 - opc
) & 31)
834 | ME (31 - TARGET_PAGE_BITS
)
838 tcg_out32 (s
, CMP
| (7 << 23) | RA (r2
) | RB (r1
));
839 #if TARGET_LONG_BITS == 64
840 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
841 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
842 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
845 label1_ptr
= s
->code_ptr
;
847 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
852 #ifdef CONFIG_TCG_PASS_AREG0
853 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, TCG_AREG0
);
855 #if TARGET_LONG_BITS == 32
856 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, addr_reg
);
858 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
861 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, addr_reg2
);
862 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, addr_reg
);
867 tcg_out32 (s
, (RLWINM
875 tcg_out32 (s
, (RLWINM
883 tcg_out_mov (s
, TCG_TYPE_I32
, ir
, data_reg
);
886 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
889 tcg_out_mov (s
, TCG_TYPE_I32
, ir
++, data_reg2
);
890 tcg_out_mov (s
, TCG_TYPE_I32
, ir
, data_reg
);
895 tcg_out_movi (s
, TCG_TYPE_I32
, ir
, mem_index
);
896 tcg_out_call (s
, (tcg_target_long
) qemu_st_helpers
[opc
], 1);
897 label2_ptr
= s
->code_ptr
;
900 /* label1: fast path */
902 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
908 | (offsetof (CPUTLBEntry
, addend
)
909 - offsetof (CPUTLBEntry
, addr_write
))
911 /* r0 = env->tlb_table[mem_index][index].addend */
912 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
913 /* r0 = env->tlb_table[mem_index][index].addend + addr */
915 #else /* !CONFIG_SOFTMMU */
918 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
921 #ifdef TARGET_WORDS_BIGENDIAN
928 tcg_out32 (s
, STBX
| SAB (data_reg
, rbase
, r0
));
932 tcg_out32 (s
, STHBRX
| SAB (data_reg
, rbase
, r0
));
934 tcg_out32 (s
, STHX
| SAB (data_reg
, rbase
, r0
));
938 tcg_out32 (s
, STWBRX
| SAB (data_reg
, rbase
, r0
));
940 tcg_out32 (s
, STWX
| SAB (data_reg
, rbase
, r0
));
944 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
945 tcg_out32 (s
, STWBRX
| SAB (data_reg
, rbase
, r0
));
946 tcg_out32 (s
, STWBRX
| SAB (data_reg2
, rbase
, r1
));
949 #ifdef CONFIG_USE_GUEST_BASE
950 tcg_out32 (s
, STWX
| SAB (data_reg2
, rbase
, r0
));
951 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
952 tcg_out32 (s
, STWX
| SAB (data_reg
, rbase
, r1
));
954 tcg_out32 (s
, STW
| RS (data_reg2
) | RA (r0
));
955 tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
) | 4);
961 #ifdef CONFIG_SOFTMMU
962 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
966 static void tcg_target_qemu_prologue (TCGContext
*s
)
972 + TCG_STATIC_CALL_ARGS_SIZE
973 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 4
974 + CPU_TEMP_BUF_NLONGS
* sizeof(long)
976 frame_size
= (frame_size
+ 15) & ~15;
978 tcg_set_frame(s
, TCG_REG_CALL_STACK
, frame_size
979 - CPU_TEMP_BUF_NLONGS
* sizeof(long),
980 CPU_TEMP_BUF_NLONGS
* sizeof(long));
986 /* First emit adhoc function descriptor */
987 addr
= (uint32_t) s
->code_ptr
+ 12;
988 tcg_out32 (s
, addr
); /* entry point */
989 s
->code_ptr
+= 8; /* skip TOC and environment pointer */
992 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
993 tcg_out32 (s
, STWU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
994 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
996 | RS (tcg_target_callee_save_regs
[i
])
998 | (i
* 4 + LINKAGE_AREA_SIZE
+ TCG_STATIC_CALL_ARGS_SIZE
)
1001 tcg_out32 (s
, STW
| RS (0) | RA (1) | (frame_size
+ LR_OFFSET
));
1003 #ifdef CONFIG_USE_GUEST_BASE
1005 tcg_out_movi (s
, TCG_TYPE_I32
, TCG_GUEST_BASE_REG
, GUEST_BASE
);
1006 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
1010 tcg_out_mov (s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1011 tcg_out32 (s
, MTSPR
| RS (tcg_target_call_iarg_regs
[1]) | CTR
);
1012 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1013 tb_ret_addr
= s
->code_ptr
;
1015 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
1017 | RT (tcg_target_callee_save_regs
[i
])
1019 | (i
* 4 + LINKAGE_AREA_SIZE
+ TCG_STATIC_CALL_ARGS_SIZE
)
1022 tcg_out32 (s
, LWZ
| RT (0) | RA (1) | (frame_size
+ LR_OFFSET
));
1023 tcg_out32 (s
, MTSPR
| RS (0) | LR
);
1024 tcg_out32 (s
, ADDI
| RT (1) | RA (1) | frame_size
);
1025 tcg_out32 (s
, BCLR
| BO_ALWAYS
);
1028 static void tcg_out_ld (TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
1029 tcg_target_long arg2
)
1031 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
1034 static void tcg_out_st (TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
1035 tcg_target_long arg2
)
1037 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
1040 static void ppc_addi (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
1042 if (!si
&& rt
== ra
)
1045 if (si
== (int16_t) si
)
1046 tcg_out32 (s
, ADDI
| RT (rt
) | RA (ra
) | (si
& 0xffff));
1048 uint16_t h
= ((si
>> 16) & 0xffff) + ((uint16_t) si
>> 15);
1049 tcg_out32 (s
, ADDIS
| RT (rt
) | RA (ra
) | h
);
1050 tcg_out32 (s
, ADDI
| RT (rt
) | RA (rt
) | (si
& 0xffff));
1054 static void tcg_out_cmp (TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
1055 int const_arg2
, int cr
)
1064 if ((int16_t) arg2
== arg2
) {
1069 else if ((uint16_t) arg2
== arg2
) {
1084 if ((int16_t) arg2
== arg2
) {
1099 if ((uint16_t) arg2
== arg2
) {
1115 tcg_out32 (s
, op
| RA (arg1
) | (arg2
& 0xffff));
1118 tcg_out_movi (s
, TCG_TYPE_I32
, 0, arg2
);
1119 tcg_out32 (s
, op
| RA (arg1
) | RB (0));
1122 tcg_out32 (s
, op
| RA (arg1
) | RB (arg2
));
1127 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
1129 TCGLabel
*l
= &s
->labels
[label_index
];
1132 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
1134 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
1136 /* Thanks to Andrzej Zaborowski */
1137 tcg_out32 (s
, bc
| (val
& 0xfffc));
1138 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
1142 static void tcg_out_cr7eq_from_cond (TCGContext
*s
, const TCGArg
*args
,
1143 const int *const_args
)
1145 TCGCond cond
= args
[4];
1147 struct { int bit1
; int bit2
; int cond2
; } bits
[] = {
1148 [TCG_COND_LT
] = { CR_LT
, CR_LT
, TCG_COND_LT
},
1149 [TCG_COND_LE
] = { CR_LT
, CR_GT
, TCG_COND_LT
},
1150 [TCG_COND_GT
] = { CR_GT
, CR_GT
, TCG_COND_GT
},
1151 [TCG_COND_GE
] = { CR_GT
, CR_LT
, TCG_COND_GT
},
1152 [TCG_COND_LTU
] = { CR_LT
, CR_LT
, TCG_COND_LTU
},
1153 [TCG_COND_LEU
] = { CR_LT
, CR_GT
, TCG_COND_LTU
},
1154 [TCG_COND_GTU
] = { CR_GT
, CR_GT
, TCG_COND_GTU
},
1155 [TCG_COND_GEU
] = { CR_GT
, CR_LT
, TCG_COND_GTU
},
1156 }, *b
= &bits
[cond
];
1161 op
= (cond
== TCG_COND_EQ
) ? CRAND
: CRNAND
;
1162 tcg_out_cmp (s
, cond
, args
[0], args
[2], const_args
[2], 6);
1163 tcg_out_cmp (s
, cond
, args
[1], args
[3], const_args
[3], 7);
1164 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
1174 op
= (b
->bit1
!= b
->bit2
) ? CRANDC
: CRAND
;
1175 tcg_out_cmp (s
, b
->cond2
, args
[1], args
[3], const_args
[3], 5);
1176 tcg_out_cmp (s
, tcg_unsigned_cond (cond
), args
[0], args
[2],
1178 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (5, CR_EQ
) | BB (7, b
->bit2
));
1179 tcg_out32 (s
, CROR
| BT (7, CR_EQ
) | BA (5, b
->bit1
) | BB (7, CR_EQ
));
1186 static void tcg_out_setcond (TCGContext
*s
, TCGCond cond
, TCGArg arg0
,
1187 TCGArg arg1
, TCGArg arg2
, int const_arg2
)
1199 if ((uint16_t) arg2
== arg2
) {
1200 tcg_out32 (s
, XORI
| RS (arg1
) | RA (0) | arg2
);
1203 tcg_out_movi (s
, TCG_TYPE_I32
, 0, arg2
);
1204 tcg_out32 (s
, XOR
| SAB (arg1
, 0, 0));
1210 tcg_out32 (s
, XOR
| SAB (arg1
, 0, arg2
));
1212 tcg_out32 (s
, CNTLZW
| RS (arg
) | RA (0));
1213 tcg_out32 (s
, (RLWINM
1230 if ((uint16_t) arg2
== arg2
) {
1231 tcg_out32 (s
, XORI
| RS (arg1
) | RA (0) | arg2
);
1234 tcg_out_movi (s
, TCG_TYPE_I32
, 0, arg2
);
1235 tcg_out32 (s
, XOR
| SAB (arg1
, 0, 0));
1241 tcg_out32 (s
, XOR
| SAB (arg1
, 0, arg2
));
1244 if (arg
== arg1
&& arg1
== arg0
) {
1245 tcg_out32 (s
, ADDIC
| RT (0) | RA (arg
) | 0xffff);
1246 tcg_out32 (s
, SUBFE
| TAB (arg0
, 0, arg
));
1249 tcg_out32 (s
, ADDIC
| RT (arg0
) | RA (arg
) | 0xffff);
1250 tcg_out32 (s
, SUBFE
| TAB (arg0
, arg0
, arg
));
1269 crop
= CRNOR
| BT (7, CR_EQ
) | BA (7, CR_LT
) | BB (7, CR_LT
);
1275 crop
= CRNOR
| BT (7, CR_EQ
) | BA (7, CR_GT
) | BB (7, CR_GT
);
1277 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7);
1278 if (crop
) tcg_out32 (s
, crop
);
1279 tcg_out32 (s
, MFCR
| RT (0));
1280 tcg_out32 (s
, (RLWINM
1295 static void tcg_out_setcond2 (TCGContext
*s
, const TCGArg
*args
,
1296 const int *const_args
)
1298 tcg_out_cr7eq_from_cond (s
, args
+ 1, const_args
+ 1);
1299 tcg_out32 (s
, MFCR
| RT (0));
1300 tcg_out32 (s
, (RLWINM
1310 static void tcg_out_brcond (TCGContext
*s
, TCGCond cond
,
1311 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1314 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7);
1315 tcg_out_bc (s
, tcg_to_bc
[cond
], label_index
);
1318 /* XXX: we implement it at the target level to avoid having to
1319 handle cross basic blocks temporaries */
1320 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
1321 const int *const_args
)
1323 tcg_out_cr7eq_from_cond (s
, args
, const_args
);
1324 tcg_out_bc (s
, (BC
| BI (7, CR_EQ
) | BO_COND_TRUE
), args
[5]);
1327 void ppc_tb_set_jmp_target (unsigned long jmp_addr
, unsigned long addr
)
1330 long disp
= addr
- jmp_addr
;
1331 unsigned long patch_size
;
1333 ptr
= (uint32_t *)jmp_addr
;
1335 if ((disp
<< 6) >> 6 != disp
) {
1336 ptr
[0] = 0x3c000000 | (addr
>> 16); /* lis 0,addr@ha */
1337 ptr
[1] = 0x60000000 | (addr
& 0xffff); /* la 0,addr@l(0) */
1338 ptr
[2] = 0x7c0903a6; /* mtctr 0 */
1339 ptr
[3] = 0x4e800420; /* brctr */
1342 /* patch the branch destination */
1344 *ptr
= 0x48000000 | (disp
& 0x03fffffc); /* b disp */
1347 ptr
[0] = 0x60000000; /* nop */
1348 ptr
[1] = 0x60000000;
1349 ptr
[2] = 0x60000000;
1350 ptr
[3] = 0x60000000;
1355 flush_icache_range(jmp_addr
, jmp_addr
+ patch_size
);
1358 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1359 const int *const_args
)
1362 case INDEX_op_exit_tb
:
1363 tcg_out_movi (s
, TCG_TYPE_I32
, TCG_REG_R3
, args
[0]);
1364 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1366 case INDEX_op_goto_tb
:
1367 if (s
->tb_jmp_offset
) {
1368 /* direct jump method */
1370 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1376 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1380 TCGLabel
*l
= &s
->labels
[args
[0]];
1383 tcg_out_b (s
, 0, l
->u
.value
);
1386 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1388 /* Thanks to Andrzej Zaborowski */
1389 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1390 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1395 tcg_out_call (s
, args
[0], const_args
[0]);
1398 if (const_args
[0]) {
1399 tcg_out_b (s
, 0, args
[0]);
1402 tcg_out32 (s
, MTSPR
| RS (args
[0]) | CTR
);
1403 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1406 case INDEX_op_movi_i32
:
1407 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1409 case INDEX_op_ld8u_i32
:
1410 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1412 case INDEX_op_ld8s_i32
:
1413 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1414 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1416 case INDEX_op_ld16u_i32
:
1417 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1419 case INDEX_op_ld16s_i32
:
1420 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1422 case INDEX_op_ld_i32
:
1423 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1425 case INDEX_op_st8_i32
:
1426 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1428 case INDEX_op_st16_i32
:
1429 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1431 case INDEX_op_st_i32
:
1432 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1435 case INDEX_op_add_i32
:
1437 ppc_addi (s
, args
[0], args
[1], args
[2]);
1439 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1441 case INDEX_op_sub_i32
:
1443 ppc_addi (s
, args
[0], args
[1], -args
[2]);
1445 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1448 case INDEX_op_and_i32
:
1449 if (const_args
[2]) {
1455 tcg_out_movi (s
, TCG_TYPE_I32
, args
[0], 0);
1465 if ((t
& (t
- 1)) == 0) {
1468 if ((c
& 0x80000001) == 0x80000001) {
1483 tcg_out32 (s
, (RLWINM
1493 #endif /* !__PPU__ */
1495 if ((c
& 0xffff) == c
)
1496 tcg_out32 (s
, ANDI
| RS (args
[1]) | RA (args
[0]) | c
);
1497 else if ((c
& 0xffff0000) == c
)
1498 tcg_out32 (s
, ANDIS
| RS (args
[1]) | RA (args
[0])
1499 | ((c
>> 16) & 0xffff));
1501 tcg_out_movi (s
, TCG_TYPE_I32
, 0, c
);
1502 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], 0));
1507 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1509 case INDEX_op_or_i32
:
1510 if (const_args
[2]) {
1511 if (args
[2] & 0xffff) {
1512 tcg_out32 (s
, ORI
| RS (args
[1]) | RA (args
[0])
1513 | (args
[2] & 0xffff));
1515 tcg_out32 (s
, ORIS
| RS (args
[0]) | RA (args
[0])
1516 | ((args
[2] >> 16) & 0xffff));
1519 tcg_out32 (s
, ORIS
| RS (args
[1]) | RA (args
[0])
1520 | ((args
[2] >> 16) & 0xffff));
1524 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1526 case INDEX_op_xor_i32
:
1527 if (const_args
[2]) {
1528 if ((args
[2] & 0xffff) == args
[2])
1529 tcg_out32 (s
, XORI
| RS (args
[1]) | RA (args
[0])
1530 | (args
[2] & 0xffff));
1531 else if ((args
[2] & 0xffff0000) == args
[2])
1532 tcg_out32 (s
, XORIS
| RS (args
[1]) | RA (args
[0])
1533 | ((args
[2] >> 16) & 0xffff));
1535 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1536 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], 0));
1540 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1542 case INDEX_op_andc_i32
:
1543 tcg_out32 (s
, ANDC
| SAB (args
[1], args
[0], args
[2]));
1545 case INDEX_op_orc_i32
:
1546 tcg_out32 (s
, ORC
| SAB (args
[1], args
[0], args
[2]));
1548 case INDEX_op_eqv_i32
:
1549 tcg_out32 (s
, EQV
| SAB (args
[1], args
[0], args
[2]));
1551 case INDEX_op_nand_i32
:
1552 tcg_out32 (s
, NAND
| SAB (args
[1], args
[0], args
[2]));
1554 case INDEX_op_nor_i32
:
1555 tcg_out32 (s
, NOR
| SAB (args
[1], args
[0], args
[2]));
1558 case INDEX_op_mul_i32
:
1559 if (const_args
[2]) {
1560 if (args
[2] == (int16_t) args
[2])
1561 tcg_out32 (s
, MULLI
| RT (args
[0]) | RA (args
[1])
1562 | (args
[2] & 0xffff));
1564 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1565 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], 0));
1569 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], args
[2]));
1572 case INDEX_op_div_i32
:
1573 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1576 case INDEX_op_divu_i32
:
1577 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1580 case INDEX_op_rem_i32
:
1581 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1582 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1583 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1586 case INDEX_op_remu_i32
:
1587 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1588 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1589 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1592 case INDEX_op_mulu2_i32
:
1593 if (args
[0] == args
[2] || args
[0] == args
[3]) {
1594 tcg_out32 (s
, MULLW
| TAB (0, args
[2], args
[3]));
1595 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1596 tcg_out_mov (s
, TCG_TYPE_I32
, args
[0], 0);
1599 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[2], args
[3]));
1600 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1604 case INDEX_op_shl_i32
:
1605 if (const_args
[2]) {
1606 tcg_out32 (s
, (RLWINM
1616 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1618 case INDEX_op_shr_i32
:
1619 if (const_args
[2]) {
1620 tcg_out32 (s
, (RLWINM
1630 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1632 case INDEX_op_sar_i32
:
1634 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1636 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1638 case INDEX_op_rotl_i32
:
1645 | (const_args
[2] ? RLWINM
| SH (args
[2])
1646 : RLWNM
| RB (args
[2]))
1651 case INDEX_op_rotr_i32
:
1652 if (const_args
[2]) {
1654 tcg_out_mov (s
, TCG_TYPE_I32
, args
[0], args
[1]);
1657 tcg_out32 (s
, RLWINM
1667 tcg_out32 (s
, SUBFIC
| RT (0) | RA (args
[2]) | 32);
1678 case INDEX_op_add2_i32
:
1679 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1680 tcg_out32 (s
, ADDC
| TAB (0, args
[2], args
[4]));
1681 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1682 tcg_out_mov (s
, TCG_TYPE_I32
, args
[0], 0);
1685 tcg_out32 (s
, ADDC
| TAB (args
[0], args
[2], args
[4]));
1686 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1689 case INDEX_op_sub2_i32
:
1690 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1691 tcg_out32 (s
, SUBFC
| TAB (0, args
[4], args
[2]));
1692 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1693 tcg_out_mov (s
, TCG_TYPE_I32
, args
[0], 0);
1696 tcg_out32 (s
, SUBFC
| TAB (args
[0], args
[4], args
[2]));
1697 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1701 case INDEX_op_brcond_i32
:
1706 args[3] = r1 is const
1707 args[4] = label_index
1709 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3]);
1711 case INDEX_op_brcond2_i32
:
1712 tcg_out_brcond2(s
, args
, const_args
);
1715 case INDEX_op_neg_i32
:
1716 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1719 case INDEX_op_not_i32
:
1720 tcg_out32 (s
, NOR
| SAB (args
[1], args
[0], args
[1]));
1723 case INDEX_op_qemu_ld8u
:
1724 tcg_out_qemu_ld(s
, args
, 0);
1726 case INDEX_op_qemu_ld8s
:
1727 tcg_out_qemu_ld(s
, args
, 0 | 4);
1729 case INDEX_op_qemu_ld16u
:
1730 tcg_out_qemu_ld(s
, args
, 1);
1732 case INDEX_op_qemu_ld16s
:
1733 tcg_out_qemu_ld(s
, args
, 1 | 4);
1735 case INDEX_op_qemu_ld32
:
1736 tcg_out_qemu_ld(s
, args
, 2);
1738 case INDEX_op_qemu_ld64
:
1739 tcg_out_qemu_ld(s
, args
, 3);
1741 case INDEX_op_qemu_st8
:
1742 tcg_out_qemu_st(s
, args
, 0);
1744 case INDEX_op_qemu_st16
:
1745 tcg_out_qemu_st(s
, args
, 1);
1747 case INDEX_op_qemu_st32
:
1748 tcg_out_qemu_st(s
, args
, 2);
1750 case INDEX_op_qemu_st64
:
1751 tcg_out_qemu_st(s
, args
, 3);
1754 case INDEX_op_ext8s_i32
:
1755 tcg_out32 (s
, EXTSB
| RS (args
[1]) | RA (args
[0]));
1757 case INDEX_op_ext8u_i32
:
1758 tcg_out32 (s
, RLWINM
1766 case INDEX_op_ext16s_i32
:
1767 tcg_out32 (s
, EXTSH
| RS (args
[1]) | RA (args
[0]));
1769 case INDEX_op_ext16u_i32
:
1770 tcg_out32 (s
, RLWINM
1779 case INDEX_op_setcond_i32
:
1780 tcg_out_setcond (s
, args
[3], args
[0], args
[1], args
[2], const_args
[2]);
1782 case INDEX_op_setcond2_i32
:
1783 tcg_out_setcond2 (s
, args
, const_args
);
1786 case INDEX_op_bswap16_i32
:
1787 /* Stolen from gcc's builtin_bswap16 */
1791 /* r0 = (a1 << 8) & 0xff00 # 00d0 */
1792 tcg_out32 (s
, RLWINM
1800 /* a0 = rotate_left (a1, 24) & 0xff # 000c */
1801 tcg_out32 (s
, RLWINM
1809 /* a0 = a0 | r0 # 00dc */
1810 tcg_out32 (s
, OR
| SAB (0, args
[0], args
[0]));
1813 case INDEX_op_bswap32_i32
:
1814 /* Stolen from gcc's builtin_bswap32 */
1818 /* a1 = args[1] # abcd */
1820 if (a0
== args
[1]) {
1824 /* a0 = rotate_left (a1, 8) # bcda */
1825 tcg_out32 (s
, RLWINM
1833 /* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */
1834 tcg_out32 (s
, RLWIMI
1842 /* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */
1843 tcg_out32 (s
, RLWIMI
1852 tcg_out_mov (s
, TCG_TYPE_I32
, args
[0], a0
);
1857 case INDEX_op_deposit_i32
:
1858 tcg_out32 (s
, RLWIMI
1862 | MB (32 - args
[3] - args
[4])
1868 tcg_dump_ops (s
, stderr
);
1873 static const TCGTargetOpDef ppc_op_defs
[] = {
1874 { INDEX_op_exit_tb
, { } },
1875 { INDEX_op_goto_tb
, { } },
1876 { INDEX_op_call
, { "ri" } },
1877 { INDEX_op_jmp
, { "ri" } },
1878 { INDEX_op_br
, { } },
1880 { INDEX_op_mov_i32
, { "r", "r" } },
1881 { INDEX_op_movi_i32
, { "r" } },
1882 { INDEX_op_ld8u_i32
, { "r", "r" } },
1883 { INDEX_op_ld8s_i32
, { "r", "r" } },
1884 { INDEX_op_ld16u_i32
, { "r", "r" } },
1885 { INDEX_op_ld16s_i32
, { "r", "r" } },
1886 { INDEX_op_ld_i32
, { "r", "r" } },
1887 { INDEX_op_st8_i32
, { "r", "r" } },
1888 { INDEX_op_st16_i32
, { "r", "r" } },
1889 { INDEX_op_st_i32
, { "r", "r" } },
1891 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1892 { INDEX_op_mul_i32
, { "r", "r", "ri" } },
1893 { INDEX_op_div_i32
, { "r", "r", "r" } },
1894 { INDEX_op_divu_i32
, { "r", "r", "r" } },
1895 { INDEX_op_rem_i32
, { "r", "r", "r" } },
1896 { INDEX_op_remu_i32
, { "r", "r", "r" } },
1897 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1898 { INDEX_op_sub_i32
, { "r", "r", "ri" } },
1899 { INDEX_op_and_i32
, { "r", "r", "ri" } },
1900 { INDEX_op_or_i32
, { "r", "r", "ri" } },
1901 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
1903 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1904 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1905 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1907 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1908 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1910 { INDEX_op_brcond_i32
, { "r", "ri" } },
1912 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1913 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1914 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1916 { INDEX_op_neg_i32
, { "r", "r" } },
1917 { INDEX_op_not_i32
, { "r", "r" } },
1919 { INDEX_op_andc_i32
, { "r", "r", "r" } },
1920 { INDEX_op_orc_i32
, { "r", "r", "r" } },
1921 { INDEX_op_eqv_i32
, { "r", "r", "r" } },
1922 { INDEX_op_nand_i32
, { "r", "r", "r" } },
1923 { INDEX_op_nor_i32
, { "r", "r", "r" } },
1925 { INDEX_op_setcond_i32
, { "r", "r", "ri" } },
1926 { INDEX_op_setcond2_i32
, { "r", "r", "r", "ri", "ri" } },
1928 { INDEX_op_bswap16_i32
, { "r", "r" } },
1929 { INDEX_op_bswap32_i32
, { "r", "r" } },
1931 #if TARGET_LONG_BITS == 32
1932 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1933 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1934 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1935 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1936 { INDEX_op_qemu_ld32
, { "r", "L" } },
1937 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1939 { INDEX_op_qemu_st8
, { "K", "K" } },
1940 { INDEX_op_qemu_st16
, { "K", "K" } },
1941 { INDEX_op_qemu_st32
, { "K", "K" } },
1942 { INDEX_op_qemu_st64
, { "M", "M", "M" } },
1944 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1945 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1946 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1947 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1948 { INDEX_op_qemu_ld32
, { "r", "L", "L" } },
1949 { INDEX_op_qemu_ld64
, { "r", "L", "L", "L" } },
1951 { INDEX_op_qemu_st8
, { "K", "K", "K" } },
1952 { INDEX_op_qemu_st16
, { "K", "K", "K" } },
1953 { INDEX_op_qemu_st32
, { "K", "K", "K" } },
1954 { INDEX_op_qemu_st64
, { "M", "M", "M", "M" } },
1957 { INDEX_op_ext8s_i32
, { "r", "r" } },
1958 { INDEX_op_ext8u_i32
, { "r", "r" } },
1959 { INDEX_op_ext16s_i32
, { "r", "r" } },
1960 { INDEX_op_ext16u_i32
, { "r", "r" } },
1962 { INDEX_op_deposit_i32
, { "r", "0", "r" } },
1967 static void tcg_target_init(TCGContext
*s
)
1969 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1970 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1972 #ifdef TCG_TARGET_CALL_DARWIN
1982 (1 << TCG_REG_R10
) |
1983 (1 << TCG_REG_R11
) |
1987 tcg_regset_clear(s
->reserved_regs
);
1988 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
);
1989 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
);
1990 #ifndef TCG_TARGET_CALL_DARWIN
1991 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
);
1994 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
);
1997 tcg_add_target_add_op_defs(ppc_op_defs
);