2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "../tcg-pool.c.inc"
27 #include "../tcg-ldst.c.inc"
30 * Standardize on the _CALL_FOO symbols used by GCC:
31 * Apple XCode does not define _CALL_DARWIN.
32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit).
34 #if !defined(_CALL_SYSV) && \
35 !defined(_CALL_DARWIN) && \
36 !defined(_CALL_AIX) && \
38 # if defined(__APPLE__)
40 # elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32
47 #if TCG_TARGET_REG_BITS == 64
48 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND
49 # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
51 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
52 # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
55 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
56 # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF
58 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
59 # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
62 /* For some memory operations, we need a scratch that isn't R0. For the AIX
63 calling convention, we can re-use the TOC register since we'll be reloading
64 it at every call. Otherwise R12 will do nicely as neither a call-saved
65 register nor a parameter register. */
67 # define TCG_REG_TMP1 TCG_REG_R2
69 # define TCG_REG_TMP1 TCG_REG_R12
72 #define TCG_VEC_TMP1 TCG_REG_V0
73 #define TCG_VEC_TMP2 TCG_REG_V1
75 #define TCG_REG_TB TCG_REG_R31
76 #define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
78 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
79 #define SZP ((int)sizeof(void *))
81 /* Shorthand for size of a register. */
82 #define SZR (TCG_TARGET_REG_BITS / 8)
84 #define TCG_CT_CONST_S16 0x100
85 #define TCG_CT_CONST_U16 0x200
86 #define TCG_CT_CONST_S32 0x400
87 #define TCG_CT_CONST_U32 0x800
88 #define TCG_CT_CONST_ZERO 0x1000
89 #define TCG_CT_CONST_MONE 0x2000
90 #define TCG_CT_CONST_WSZ 0x4000
92 #define ALL_GENERAL_REGS 0xffffffffu
93 #define ALL_VECTOR_REGS 0xffffffff00000000ull
96 #define ALL_QLOAD_REGS \
98 ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
99 #define ALL_QSTORE_REGS \
100 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
101 (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
103 #define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
104 #define ALL_QSTORE_REGS ALL_QLOAD_REGS
107 TCGPowerISA have_isa;
108 static bool have_isel;
112 #ifndef CONFIG_SOFTMMU
113 #define TCG_GUEST_BASE_REG 30
116 #ifdef CONFIG_DEBUG_TCG
117 static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
122 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
123 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
124 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
125 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
129 static const int tcg_target_reg_alloc_order[] = {
130 TCG_REG_R14, /* call saved registers */
148 TCG_REG_R12, /* call clobbered, non-arguments */
152 TCG_REG_R10, /* call clobbered, arguments */
161 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
162 TCG_REG_V2, /* call clobbered, vectors */
182 static const int tcg_target_call_iarg_regs[] = {
193 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
195 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
196 tcg_debug_assert(slot >= 0 && slot <= 1);
197 return TCG_REG_R3 + slot;
200 static const int tcg_target_callee_save_regs[] = {
217 TCG_REG_R27, /* currently used for the global env */
224 static inline bool in_range_b(tcg_target_long target)
226 return target == sextract64(target, 0, 26);
229 static uint32_t reloc_pc24_val(const tcg_insn_unit *pc,
230 const tcg_insn_unit *target)
232 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
233 tcg_debug_assert(in_range_b(disp));
234 return disp & 0x3fffffc;
237 static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
239 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
240 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
242 if (in_range_b(disp)) {
243 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc);
249 static uint16_t reloc_pc14_val(const tcg_insn_unit *pc,
250 const tcg_insn_unit *target)
252 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
253 tcg_debug_assert(disp == (int16_t) disp);
254 return disp & 0xfffc;
257 static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
259 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
260 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
262 if (disp == (int16_t) disp) {
263 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc);
269 /* test if a constant matches the constraint */
270 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
272 if (ct & TCG_CT_CONST) {
276 /* The only 32-bit constraint we use aside from
277 TCG_CT_CONST is TCG_CT_CONST_S16. */
278 if (type == TCG_TYPE_I32) {
282 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
284 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
286 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
288 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
290 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
292 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
294 } else if ((ct & TCG_CT_CONST_WSZ)
295 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
301 #define OPCD(opc) ((opc)<<26)
302 #define XO19(opc) (OPCD(19)|((opc)<<1))
303 #define MD30(opc) (OPCD(30)|((opc)<<2))
304 #define MDS30(opc) (OPCD(30)|((opc)<<1))
305 #define XO31(opc) (OPCD(31)|((opc)<<1))
306 #define XO58(opc) (OPCD(58)|(opc))
307 #define XO62(opc) (OPCD(62)|(opc))
308 #define VX4(opc) (OPCD(4)|(opc))
312 #define LBZ OPCD( 34)
313 #define LHZ OPCD( 40)
314 #define LHA OPCD( 42)
315 #define LWZ OPCD( 32)
316 #define LWZUX XO31( 55)
317 #define STB OPCD( 38)
318 #define STH OPCD( 44)
319 #define STW OPCD( 36)
322 #define STDU XO62( 1)
323 #define STDX XO31(149)
326 #define LDX XO31( 21)
328 #define LDUX XO31( 53)
330 #define LWAX XO31(341)
332 #define ADDIC OPCD( 12)
333 #define ADDI OPCD( 14)
334 #define ADDIS OPCD( 15)
335 #define ORI OPCD( 24)
336 #define ORIS OPCD( 25)
337 #define XORI OPCD( 26)
338 #define XORIS OPCD( 27)
339 #define ANDI OPCD( 28)
340 #define ANDIS OPCD( 29)
341 #define MULLI OPCD( 7)
342 #define CMPLI OPCD( 10)
343 #define CMPI OPCD( 11)
344 #define SUBFIC OPCD( 8)
346 #define LWZU OPCD( 33)
347 #define STWU OPCD( 37)
349 #define RLWIMI OPCD( 20)
350 #define RLWINM OPCD( 21)
351 #define RLWNM OPCD( 23)
353 #define RLDICL MD30( 0)
354 #define RLDICR MD30( 1)
355 #define RLDIMI MD30( 3)
356 #define RLDCL MDS30( 8)
358 #define BCLR XO19( 16)
359 #define BCCTR XO19(528)
360 #define CRAND XO19(257)
361 #define CRANDC XO19(129)
362 #define CRNAND XO19(225)
363 #define CROR XO19(449)
364 #define CRNOR XO19( 33)
366 #define EXTSB XO31(954)
367 #define EXTSH XO31(922)
368 #define EXTSW XO31(986)
369 #define ADD XO31(266)
370 #define ADDE XO31(138)
371 #define ADDME XO31(234)
372 #define ADDZE XO31(202)
373 #define ADDC XO31( 10)
374 #define AND XO31( 28)
375 #define SUBF XO31( 40)
376 #define SUBFC XO31( 8)
377 #define SUBFE XO31(136)
378 #define SUBFME XO31(232)
379 #define SUBFZE XO31(200)
381 #define XOR XO31(316)
382 #define MULLW XO31(235)
383 #define MULHW XO31( 75)
384 #define MULHWU XO31( 11)
385 #define DIVW XO31(491)
386 #define DIVWU XO31(459)
387 #define MODSW XO31(779)
388 #define MODUW XO31(267)
390 #define CMPL XO31( 32)
391 #define LHBRX XO31(790)
392 #define LWBRX XO31(534)
393 #define LDBRX XO31(532)
394 #define STHBRX XO31(918)
395 #define STWBRX XO31(662)
396 #define STDBRX XO31(660)
397 #define MFSPR XO31(339)
398 #define MTSPR XO31(467)
399 #define SRAWI XO31(824)
400 #define NEG XO31(104)
401 #define MFCR XO31( 19)
402 #define MFOCRF (MFCR | (1u << 20))
403 #define NOR XO31(124)
404 #define CNTLZW XO31( 26)
405 #define CNTLZD XO31( 58)
406 #define CNTTZW XO31(538)
407 #define CNTTZD XO31(570)
408 #define CNTPOPW XO31(378)
409 #define CNTPOPD XO31(506)
410 #define ANDC XO31( 60)
411 #define ORC XO31(412)
412 #define EQV XO31(284)
413 #define NAND XO31(476)
414 #define ISEL XO31( 15)
416 #define MULLD XO31(233)
417 #define MULHD XO31( 73)
418 #define MULHDU XO31( 9)
419 #define DIVD XO31(489)
420 #define DIVDU XO31(457)
421 #define MODSD XO31(777)
422 #define MODUD XO31(265)
424 #define LBZX XO31( 87)
425 #define LHZX XO31(279)
426 #define LHAX XO31(343)
427 #define LWZX XO31( 23)
428 #define STBX XO31(215)
429 #define STHX XO31(407)
430 #define STWX XO31(151)
432 #define EIEIO XO31(854)
433 #define HWSYNC XO31(598)
434 #define LWSYNC (HWSYNC | (1u << 21))
436 #define SPR(a, b) ((((a)<<5)|(b))<<11)
438 #define CTR SPR(9, 0)
440 #define SLW XO31( 24)
441 #define SRW XO31(536)
442 #define SRAW XO31(792)
444 #define SLD XO31( 27)
445 #define SRD XO31(539)
446 #define SRAD XO31(794)
447 #define SRADI XO31(413<<1)
449 #define BRH XO31(219)
450 #define BRW XO31(155)
451 #define BRD XO31(187)
454 #define TRAP (TW | TO(31))
456 #define NOP ORI /* ori 0,0,0 */
458 #define LVX XO31(103)
459 #define LVEBX XO31(7)
460 #define LVEHX XO31(39)
461 #define LVEWX XO31(71)
462 #define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
463 #define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
464 #define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
465 #define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
466 #define LXSD (OPCD(57) | 2) /* v3.00 */
467 #define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
469 #define STVX XO31(231)
470 #define STVEWX XO31(199)
471 #define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
472 #define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
473 #define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
474 #define STXSD (OPCD(61) | 2) /* v3.00 */
476 #define VADDSBS VX4(768)
477 #define VADDUBS VX4(512)
478 #define VADDUBM VX4(0)
479 #define VADDSHS VX4(832)
480 #define VADDUHS VX4(576)
481 #define VADDUHM VX4(64)
482 #define VADDSWS VX4(896)
483 #define VADDUWS VX4(640)
484 #define VADDUWM VX4(128)
485 #define VADDUDM VX4(192) /* v2.07 */
487 #define VSUBSBS VX4(1792)
488 #define VSUBUBS VX4(1536)
489 #define VSUBUBM VX4(1024)
490 #define VSUBSHS VX4(1856)
491 #define VSUBUHS VX4(1600)
492 #define VSUBUHM VX4(1088)
493 #define VSUBSWS VX4(1920)
494 #define VSUBUWS VX4(1664)
495 #define VSUBUWM VX4(1152)
496 #define VSUBUDM VX4(1216) /* v2.07 */
498 #define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
499 #define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
501 #define VMAXSB VX4(258)
502 #define VMAXSH VX4(322)
503 #define VMAXSW VX4(386)
504 #define VMAXSD VX4(450) /* v2.07 */
505 #define VMAXUB VX4(2)
506 #define VMAXUH VX4(66)
507 #define VMAXUW VX4(130)
508 #define VMAXUD VX4(194) /* v2.07 */
509 #define VMINSB VX4(770)
510 #define VMINSH VX4(834)
511 #define VMINSW VX4(898)
512 #define VMINSD VX4(962) /* v2.07 */
513 #define VMINUB VX4(514)
514 #define VMINUH VX4(578)
515 #define VMINUW VX4(642)
516 #define VMINUD VX4(706) /* v2.07 */
518 #define VCMPEQUB VX4(6)
519 #define VCMPEQUH VX4(70)
520 #define VCMPEQUW VX4(134)
521 #define VCMPEQUD VX4(199) /* v2.07 */
522 #define VCMPGTSB VX4(774)
523 #define VCMPGTSH VX4(838)
524 #define VCMPGTSW VX4(902)
525 #define VCMPGTSD VX4(967) /* v2.07 */
526 #define VCMPGTUB VX4(518)
527 #define VCMPGTUH VX4(582)
528 #define VCMPGTUW VX4(646)
529 #define VCMPGTUD VX4(711) /* v2.07 */
530 #define VCMPNEB VX4(7) /* v3.00 */
531 #define VCMPNEH VX4(71) /* v3.00 */
532 #define VCMPNEW VX4(135) /* v3.00 */
534 #define VSLB VX4(260)
535 #define VSLH VX4(324)
536 #define VSLW VX4(388)
537 #define VSLD VX4(1476) /* v2.07 */
538 #define VSRB VX4(516)
539 #define VSRH VX4(580)
540 #define VSRW VX4(644)
541 #define VSRD VX4(1732) /* v2.07 */
542 #define VSRAB VX4(772)
543 #define VSRAH VX4(836)
544 #define VSRAW VX4(900)
545 #define VSRAD VX4(964) /* v2.07 */
548 #define VRLW VX4(132)
549 #define VRLD VX4(196) /* v2.07 */
551 #define VMULEUB VX4(520)
552 #define VMULEUH VX4(584)
553 #define VMULEUW VX4(648) /* v2.07 */
554 #define VMULOUB VX4(8)
555 #define VMULOUH VX4(72)
556 #define VMULOUW VX4(136) /* v2.07 */
557 #define VMULUWM VX4(137) /* v2.07 */
558 #define VMULLD VX4(457) /* v3.10 */
559 #define VMSUMUHM VX4(38)
561 #define VMRGHB VX4(12)
562 #define VMRGHH VX4(76)
563 #define VMRGHW VX4(140)
564 #define VMRGLB VX4(268)
565 #define VMRGLH VX4(332)
566 #define VMRGLW VX4(396)
568 #define VPKUHUM VX4(14)
569 #define VPKUWUM VX4(78)
571 #define VAND VX4(1028)
572 #define VANDC VX4(1092)
573 #define VNOR VX4(1284)
574 #define VOR VX4(1156)
575 #define VXOR VX4(1220)
576 #define VEQV VX4(1668) /* v2.07 */
577 #define VNAND VX4(1412) /* v2.07 */
578 #define VORC VX4(1348) /* v2.07 */
580 #define VSPLTB VX4(524)
581 #define VSPLTH VX4(588)
582 #define VSPLTW VX4(652)
583 #define VSPLTISB VX4(780)
584 #define VSPLTISH VX4(844)
585 #define VSPLTISW VX4(908)
587 #define VSLDOI VX4(44)
589 #define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
590 #define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
591 #define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
593 #define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
594 #define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
595 #define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
596 #define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
597 #define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
598 #define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
600 #define RT(r) ((r)<<21)
601 #define RS(r) ((r)<<21)
602 #define RA(r) ((r)<<16)
603 #define RB(r) ((r)<<11)
604 #define TO(t) ((t)<<21)
605 #define SH(s) ((s)<<11)
606 #define MB(b) ((b)<<6)
607 #define ME(e) ((e)<<1)
608 #define BO(o) ((o)<<21)
609 #define MB64(b) ((b)<<5)
610 #define FXM(b) (1 << (19 - (b)))
612 #define VRT(r) (((r) & 31) << 21)
613 #define VRA(r) (((r) & 31) << 16)
614 #define VRB(r) (((r) & 31) << 11)
615 #define VRC(r) (((r) & 31) << 6)
619 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
620 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
621 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
622 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
624 #define BF(n) ((n)<<23)
625 #define BI(n, c) (((c)+((n)*4))<<16)
626 #define BT(n, c) (((c)+((n)*4))<<21)
627 #define BA(n, c) (((c)+((n)*4))<<16)
628 #define BB(n, c) (((c)+((n)*4))<<11)
629 #define BC_(n, c) (((c)+((n)*4))<<6)
631 #define BO_COND_TRUE BO(12)
632 #define BO_COND_FALSE BO( 4)
633 #define BO_ALWAYS BO(20)
642 static const uint32_t tcg_to_bc[] = {
643 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
644 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
645 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
646 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
647 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
648 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
649 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
650 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
651 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
652 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
655 /* The low bit here is set if the RA and RB fields must be inverted. */
656 static const uint32_t tcg_to_isel[] = {
657 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
658 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
659 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
660 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
661 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
662 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
663 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
664 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
665 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
666 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
669 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
670 intptr_t value, intptr_t addend)
672 const tcg_insn_unit *target;
677 target = (const tcg_insn_unit *)value;
681 return reloc_pc14(code_ptr, target);
683 return reloc_pc24(code_ptr, target);
686 * We are (slightly) abusing this relocation type. In particular,
687 * assert that the low 2 bits are zero, and do not modify them.
688 * That way we can use this with LD et al that have opcode bits
689 * in the low 2 bits of the insn.
691 if ((value & 3) || value != (int16_t)value) {
694 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
698 * We are abusing this relocation type. Again, this points to
699 * a pair of insns, lis + load. This is an absolute address
700 * relocation for PPC32 so the lis cannot be removed.
704 if (hi + lo != value) {
707 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
708 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
711 g_assert_not_reached();
716 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
717 TCGReg base, tcg_target_long offset);
719 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
726 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
729 if (ret < TCG_REG_V0) {
730 if (arg < TCG_REG_V0) {
731 tcg_out32(s, OR | SAB(arg, ret, arg));
733 } else if (have_isa_2_07) {
734 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
735 | VRT(arg) | RA(ret));
738 /* Altivec does not support vector->integer moves. */
741 } else if (arg < TCG_REG_V0) {
743 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
744 | VRT(ret) | RA(arg));
747 /* Altivec does not support integer->vector moves. */
754 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
755 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
758 g_assert_not_reached();
763 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
766 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
767 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
768 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
769 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
772 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
773 int sh, int mb, int me)
775 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
778 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
780 tcg_out32(s, EXTSB | RA(dst) | RS(src));
783 static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src)
785 tcg_out32(s, ANDI | SAI(src, dst, 0xff));
788 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
790 tcg_out32(s, EXTSH | RA(dst) | RS(src));
793 static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src)
795 tcg_out32(s, ANDI | SAI(src, dst, 0xffff));
798 static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src)
800 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
801 tcg_out32(s, EXTSW | RA(dst) | RS(src));
804 static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
806 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
807 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
810 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src)
812 tcg_out_ext32s(s, dst, src);
815 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src)
817 tcg_out_ext32u(s, dst, src);
820 static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
822 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
825 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
827 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
830 static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c)
832 /* Limit immediate shift count lest we create an illegal insn. */
833 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31));
836 static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
838 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
841 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
843 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
846 static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
848 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
851 static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags)
853 TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
856 tcg_out32(s, BRH | RA(dst) | RS(src));
857 if (flags & TCG_BSWAP_OS) {
858 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst);
859 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
860 tcg_out_ext16u(s, dst, dst);
867 * dep(a, b, m) -> (a & ~m) | (b & m)
869 * Begin with: src = xxxxabcd
871 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */
872 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31);
873 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */
874 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23);
876 if (flags & TCG_BSWAP_OS) {
877 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp);
879 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
883 static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags)
885 TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
888 tcg_out32(s, BRW | RA(dst) | RS(src));
889 if (flags & TCG_BSWAP_OS) {
890 tcg_out_ext32s(s, dst, dst);
891 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
892 tcg_out_ext32u(s, dst, dst);
898 * Stolen from gcc's builtin_bswap32.
900 * dep(a, b, m) -> (a & ~m) | (b & m)
902 * Begin with: src = xxxxabcd
904 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */
905 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31);
906 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */
907 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7);
908 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */
909 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23);
911 if (flags & TCG_BSWAP_OS) {
912 tcg_out_ext32s(s, dst, tmp);
914 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
918 static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
920 TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
921 TCGReg t1 = dst == src ? dst : TCG_REG_R0;
924 tcg_out32(s, BRD | RA(dst) | RS(src));
930 * dep(a, b, m) -> (a & ~m) | (b & m)
932 * Begin with: src = abcdefgh
934 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
935 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
936 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
937 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
938 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
939 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
941 /* t0 = rol64(t0, 32) = hgfe0000 */
942 tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
943 /* t1 = rol64(src, 32) = efghabcd */
944 tcg_out_rld(s, RLDICL, t1, src, 32, 0);
946 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
947 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
948 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
949 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
950 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
951 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
953 tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
956 /* Emit a move into ret of arg, if it can be done in one insn. */
957 static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
959 if (arg == (int16_t)arg) {
960 tcg_out32(s, ADDI | TAI(ret, 0, arg));
963 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
964 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
970 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
971 tcg_target_long arg, bool in_prologue)
977 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
979 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
983 /* Load 16-bit immediates with one insn. */
984 if (tcg_out_movi_one(s, ret, arg)) {
988 /* Load addresses within the TB with one insn. */
989 tb_diff = tcg_tbrel_diff(s, (void *)arg);
990 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
991 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
995 /* Load 32-bit immediates with two insns. Note that we've already
996 eliminated bare ADDIS, so we know both insns are required. */
997 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
998 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
999 tcg_out32(s, ORI | SAI(ret, ret, arg));
1002 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
1003 tcg_out32(s, ADDI | TAI(ret, 0, arg));
1004 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
1008 /* Load masked 16-bit value. */
1009 if (arg > 0 && (arg & 0x8000)) {
1011 if ((tmp & (tmp + 1)) == 0) {
1012 int mb = clz64(tmp + 1) + 1;
1013 tcg_out32(s, ADDI | TAI(ret, 0, arg));
1014 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
1019 /* Load common masks with 2 insns. */
1022 if (tmp == (int16_t)tmp) {
1023 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
1024 tcg_out_shli64(s, ret, ret, shift);
1028 if (tcg_out_movi_one(s, ret, arg << shift)) {
1029 tcg_out_shri64(s, ret, ret, shift);
1033 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
1034 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
1035 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
1039 /* Use the constant pool, if possible. */
1040 if (!in_prologue && USE_REG_TB) {
1041 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
1042 tcg_tbrel_diff(s, NULL));
1043 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
1047 tmp = arg >> 31 >> 1;
1048 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
1050 tcg_out_shli64(s, ret, ret, 32);
1052 if (arg & 0xffff0000) {
1053 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
1056 tcg_out32(s, ORI | SAI(ret, ret, arg));
1060 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1061 TCGReg ret, int64_t val)
1070 if (low >= -16 && low < 16) {
1071 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
1074 if (have_isa_3_00) {
1075 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
1082 if (low >= -16 && low < 16) {
1083 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
1090 if (low >= -16 && low < 16) {
1091 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
1098 * Otherwise we must load the value from the constant pool.
1102 add = tcg_tbrel_diff(s, NULL);
1109 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
1110 load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
1111 if (TCG_TARGET_REG_BITS == 64) {
1112 new_pool_label(s, val, rel, s->code_ptr, add);
1114 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val);
1117 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
1118 if (TCG_TARGET_REG_BITS == 64) {
1119 new_pool_l2(s, rel, s->code_ptr, add, val, val);
1121 new_pool_l4(s, rel, s->code_ptr, add,
1122 val >> 32, val, val >> 32, val);
1127 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
1128 load_insn |= RA(TCG_REG_TB);
1130 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
1131 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
1133 tcg_out32(s, load_insn);
1136 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
1137 tcg_target_long arg)
1142 tcg_debug_assert(ret < TCG_REG_V0);
1143 tcg_out_movi_int(s, type, ret, arg, false);
1147 g_assert_not_reached();
1151 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
1152 tcg_target_long imm)
1154 /* This function is only used for passing structs by reference. */
1155 g_assert_not_reached();
1158 static bool mask_operand(uint32_t c, int *mb, int *me)
1162 /* Accept a bit pattern like:
1166 Keep track of the transitions. */
1167 if (c == 0 || c == -1) {
1173 if (test & (test - 1)) {
1178 *mb = test ? clz32(test & -test) + 1 : 0;
1182 static bool mask64_operand(uint64_t c, int *mb, int *me)
1191 /* Accept 1..10..0. */
1197 /* Accept 0..01..1. */
1198 if (lsb == 1 && (c & (c + 1)) == 0) {
1199 *mb = clz64(c + 1) + 1;
1206 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1210 if (mask_operand(c, &mb, &me)) {
1211 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
1212 } else if ((c & 0xffff) == c) {
1213 tcg_out32(s, ANDI | SAI(src, dst, c));
1215 } else if ((c & 0xffff0000) == c) {
1216 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1219 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
1220 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
1224 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
1228 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1229 if (mask64_operand(c, &mb, &me)) {
1231 tcg_out_rld(s, RLDICR, dst, src, 0, me);
1233 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
1235 } else if ((c & 0xffff) == c) {
1236 tcg_out32(s, ANDI | SAI(src, dst, c));
1238 } else if ((c & 0xffff0000) == c) {
1239 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1242 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
1243 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
1247 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
1248 int op_lo, int op_hi)
1251 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
1255 tcg_out32(s, op_lo | SAI(src, dst, c));
1260 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1262 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
1265 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1267 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
1270 static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target)
1272 ptrdiff_t disp = tcg_pcrel_diff(s, target);
1273 if (in_range_b(disp)) {
1274 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
1276 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
1277 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
1278 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
1282 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
1283 TCGReg base, tcg_target_long offset)
1285 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
1286 bool is_int_store = false;
1287 TCGReg rs = TCG_REG_TMP1;
1294 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
1310 case STB: case STH: case STW:
1311 is_int_store = true;
1315 /* For unaligned, or very large offsets, use the indexed form. */
1316 if (offset & align || offset != (int32_t)offset || opi == 0) {
1320 tcg_debug_assert(!is_int_store || rs != rt);
1321 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
1322 tcg_out32(s, opx | TAB(rt & 31, base, rs));
1326 l0 = (int16_t)offset;
1327 offset = (offset - l0) >> 16;
1328 l1 = (int16_t)offset;
1330 if (l1 < 0 && orig >= 0) {
1332 l1 = (int16_t)(offset - 0x4000);
1335 tcg_out32(s, ADDIS | TAI(rs, base, l1));
1339 tcg_out32(s, ADDIS | TAI(rs, base, extra));
1342 if (opi != ADDI || base != rt || l0 != 0) {
1343 tcg_out32(s, opi | TAI(rt & 31, base, l0));
1347 static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
1348 TCGReg va, TCGReg vb, int shb)
1350 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
1353 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1354 TCGReg base, intptr_t offset)
1360 if (ret < TCG_REG_V0) {
1361 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
1364 if (have_isa_2_07 && have_vsx) {
1365 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
1368 tcg_debug_assert((offset & 3) == 0);
1369 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
1370 shift = (offset - 4) & 0xc;
1372 tcg_out_vsldoi(s, ret, ret, ret, shift);
1376 if (ret < TCG_REG_V0) {
1377 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1378 tcg_out_mem_long(s, LD, LDX, ret, base, offset);
1383 tcg_debug_assert(ret >= TCG_REG_V0);
1385 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
1389 tcg_debug_assert((offset & 7) == 0);
1390 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
1392 tcg_out_vsldoi(s, ret, ret, ret, 8);
1396 tcg_debug_assert(ret >= TCG_REG_V0);
1397 tcg_debug_assert((offset & 15) == 0);
1398 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
1399 LVX, ret, base, offset);
1402 g_assert_not_reached();
1406 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1407 TCGReg base, intptr_t offset)
1413 if (arg < TCG_REG_V0) {
1414 tcg_out_mem_long(s, STW, STWX, arg, base, offset);
1417 if (have_isa_2_07 && have_vsx) {
1418 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
1421 assert((offset & 3) == 0);
1422 tcg_debug_assert((offset & 3) == 0);
1423 shift = (offset - 4) & 0xc;
1425 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
1428 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1431 if (arg < TCG_REG_V0) {
1432 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1433 tcg_out_mem_long(s, STD, STDX, arg, base, offset);
1438 tcg_debug_assert(arg >= TCG_REG_V0);
1440 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
1441 STXSDX, arg, base, offset);
1444 tcg_debug_assert((offset & 7) == 0);
1446 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
1449 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1450 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
1453 tcg_debug_assert(arg >= TCG_REG_V0);
1454 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
1455 STVX, arg, base, offset);
1458 g_assert_not_reached();
1462 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
1463 TCGReg base, intptr_t ofs)
1468 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1469 int const_arg2, int cr, TCGType type)
1474 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1476 /* Simplify the comparisons below wrt CMPI. */
1477 if (type == TCG_TYPE_I32) {
1478 arg2 = (int32_t)arg2;
1485 if ((int16_t) arg2 == arg2) {
1489 } else if ((uint16_t) arg2 == arg2) {
1504 if ((int16_t) arg2 == arg2) {
1519 if ((uint16_t) arg2 == arg2) {
1530 g_assert_not_reached();
1532 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1535 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1538 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1541 tcg_out32(s, op | RA(arg1) | RB(arg2));
1545 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1546 TCGReg dst, TCGReg src)
1548 if (type == TCG_TYPE_I32) {
1549 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1550 tcg_out_shri32(s, dst, dst, 5);
1552 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1553 tcg_out_shri64(s, dst, dst, 6);
1557 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1559 /* X != 0 implies X + -1 generates a carry. Extra addition
1560 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1562 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1563 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1565 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1566 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1570 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1574 if ((uint32_t)arg2 == arg2) {
1575 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1577 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1578 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1581 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1586 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1587 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1592 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1594 /* Ignore high bits of a potential constant arg2. */
1595 if (type == TCG_TYPE_I32) {
1596 arg2 = (uint32_t)arg2;
1599 /* Handle common and trivial cases before handling anything else. */
1603 tcg_out_setcond_eq0(s, type, arg0, arg1);
1606 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1607 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1610 tcg_out_setcond_ne0(s, arg0, arg1);
1613 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1617 /* Extract the sign bit. */
1618 if (type == TCG_TYPE_I32) {
1619 tcg_out_shri32(s, arg0, arg1, 31);
1621 tcg_out_shri64(s, arg0, arg1, 63);
1629 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1630 All other cases below are also at least 3 insns, so speed up the
1631 code generator by not considering them and always using ISEL. */
1635 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1637 isel = tcg_to_isel[cond];
1639 tcg_out_movi(s, type, arg0, 1);
1641 /* arg0 = (bc ? 0 : 1) */
1642 tab = TAB(arg0, 0, arg0);
1645 /* arg0 = (bc ? 1 : 0) */
1646 tcg_out_movi(s, type, TCG_REG_R0, 0);
1647 tab = TAB(arg0, arg0, TCG_REG_R0);
1649 tcg_out32(s, isel | tab);
1655 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1656 tcg_out_setcond_eq0(s, type, arg0, arg1);
1660 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1661 /* Discard the high bits only once, rather than both inputs. */
1662 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1663 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1666 tcg_out_setcond_ne0(s, arg0, arg1);
1684 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1690 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1692 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1696 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1697 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1701 g_assert_not_reached();
1705 static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
1708 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr);
1710 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
1715 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1716 TCGArg arg1, TCGArg arg2, int const_arg2,
1717 TCGLabel *l, TCGType type)
1719 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1720 tcg_out_bc(s, tcg_to_bc[cond], l);
1723 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1724 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1725 TCGArg v2, bool const_c2)
1727 /* If for some reason both inputs are zero, don't produce bad code. */
1728 if (v1 == 0 && v2 == 0) {
1729 tcg_out_movi(s, type, dest, 0);
1733 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1736 int isel = tcg_to_isel[cond];
1738 /* Swap the V operands if the operation indicates inversion. */
1745 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1747 tcg_out_movi(s, type, TCG_REG_R0, 0);
1749 tcg_out32(s, isel | TAB(dest, v1, v2));
1752 cond = tcg_invert_cond(cond);
1754 } else if (dest != v1) {
1756 tcg_out_movi(s, type, dest, 0);
1758 tcg_out_mov(s, type, dest, v1);
1761 /* Branch forward over one insn */
1762 tcg_out32(s, tcg_to_bc[cond] | 8);
1764 tcg_out_movi(s, type, dest, 0);
1766 tcg_out_mov(s, type, dest, v2);
1771 static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1772 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1774 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1775 tcg_out32(s, opc | RA(a0) | RS(a1));
1777 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1778 /* Note that the only other valid constant for a2 is 0. */
1780 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1781 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1782 } else if (!const_a2 && a0 == a2) {
1783 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1784 tcg_out32(s, opc | RA(a0) | RS(a1));
1786 tcg_out32(s, opc | RA(a0) | RS(a1));
1787 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1789 tcg_out_movi(s, type, a0, 0);
1791 tcg_out_mov(s, type, a0, a2);
1797 static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1798 const int *const_args)
1800 static const struct { uint8_t bit1, bit2; } bits[] = {
1801 [TCG_COND_LT ] = { CR_LT, CR_LT },
1802 [TCG_COND_LE ] = { CR_LT, CR_GT },
1803 [TCG_COND_GT ] = { CR_GT, CR_GT },
1804 [TCG_COND_GE ] = { CR_GT, CR_LT },
1805 [TCG_COND_LTU] = { CR_LT, CR_LT },
1806 [TCG_COND_LEU] = { CR_LT, CR_GT },
1807 [TCG_COND_GTU] = { CR_GT, CR_GT },
1808 [TCG_COND_GEU] = { CR_GT, CR_LT },
1811 TCGCond cond = args[4], cond2;
1812 TCGArg al, ah, bl, bh;
1813 int blconst, bhconst;
1820 blconst = const_args[2];
1821 bhconst = const_args[3];
1830 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1831 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1832 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1843 bit1 = bits[cond].bit1;
1844 bit2 = bits[cond].bit2;
1845 op = (bit1 != bit2 ? CRANDC : CRAND);
1846 cond2 = tcg_unsigned_cond(cond);
1848 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1849 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1850 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1851 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1855 g_assert_not_reached();
1859 static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1860 const int *const_args)
1862 tcg_out_cmp2(s, args + 1, const_args + 1);
1863 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1864 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1867 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1868 const int *const_args)
1870 tcg_out_cmp2(s, args, const_args);
1871 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
1874 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1878 if (a0 & TCG_MO_ST_LD) {
1887 static void tcg_out_call_int(TCGContext *s, int lk,
1888 const tcg_insn_unit *target)
1891 /* Look through the descriptor. If the branch is in range, and we
1892 don't have to spend too much effort on building the toc. */
1893 const void *tgt = ((const void * const *)target)[0];
1894 uintptr_t toc = ((const uintptr_t *)target)[1];
1895 intptr_t diff = tcg_pcrel_diff(s, tgt);
1897 if (in_range_b(diff) && toc == (uint32_t)toc) {
1898 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
1899 tcg_out_b(s, lk, tgt);
1901 /* Fold the low bits of the constant into the addresses below. */
1902 intptr_t arg = (intptr_t)target;
1903 int ofs = (int16_t)arg;
1905 if (ofs + 8 < 0x8000) {
1910 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1911 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
1912 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1913 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
1914 tcg_out32(s, BCCTR | BO_ALWAYS | lk);
1916 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1919 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1920 address, which the callee uses to compute its TOC address. */
1921 /* FIXME: when the branch is in range, we could avoid r12 load if we
1922 knew that the destination uses the same TOC, and what its local
1923 entry point offset is. */
1924 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1926 diff = tcg_pcrel_diff(s, target);
1927 if (in_range_b(diff)) {
1928 tcg_out_b(s, lk, target);
1930 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1931 tcg_out32(s, BCCTR | BO_ALWAYS | lk);
1934 tcg_out_b(s, lk, target);
1938 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target,
1939 const TCGHelperInfo *info)
1941 tcg_out_call_int(s, LK, target);
1944 static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = {
1951 [MO_BSWAP | MO_UB] = LBZX,
1952 [MO_BSWAP | MO_UW] = LHBRX,
1953 [MO_BSWAP | MO_UL] = LWBRX,
1954 [MO_BSWAP | MO_UQ] = LDBRX,
1957 static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = {
1962 [MO_BSWAP | MO_UB] = STBX,
1963 [MO_BSWAP | MO_UW] = STHBRX,
1964 [MO_BSWAP | MO_UL] = STWBRX,
1965 [MO_BSWAP | MO_UQ] = STDBRX,
1968 static const uint32_t qemu_exts_opc[4] = {
1969 EXTSB, EXTSH, EXTSW, 0
1972 #if defined (CONFIG_SOFTMMU)
1973 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1974 * int mmu_idx, uintptr_t ra)
1976 static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
1977 [MO_UB] = helper_ret_ldub_mmu,
1978 [MO_LEUW] = helper_le_lduw_mmu,
1979 [MO_LEUL] = helper_le_ldul_mmu,
1980 [MO_LEUQ] = helper_le_ldq_mmu,
1981 [MO_BEUW] = helper_be_lduw_mmu,
1982 [MO_BEUL] = helper_be_ldul_mmu,
1983 [MO_BEUQ] = helper_be_ldq_mmu,
1986 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1987 * uintxx_t val, int mmu_idx, uintptr_t ra)
1989 static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
1990 [MO_UB] = helper_ret_stb_mmu,
1991 [MO_LEUW] = helper_le_stw_mmu,
1992 [MO_LEUL] = helper_le_stl_mmu,
1993 [MO_LEUQ] = helper_le_stq_mmu,
1994 [MO_BEUW] = helper_be_stw_mmu,
1995 [MO_BEUL] = helper_be_stl_mmu,
1996 [MO_BEUQ] = helper_be_stq_mmu,
1999 /* We expect to use a 16-bit negative offset from ENV. */
2000 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
2001 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
2003 /* Perform the TLB load and compare. Places the result of the comparison
2004 in CR7, loads the addend of the TLB into R3, and returns the register
2005 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
2007 static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
2008 TCGReg addrlo, TCGReg addrhi,
2009 int mem_index, bool is_read)
2013 ? offsetof(CPUTLBEntry, addr_read)
2014 : offsetof(CPUTLBEntry, addr_write));
2015 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
2016 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
2017 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
2018 unsigned s_bits = opc & MO_SIZE;
2019 unsigned a_bits = get_alignment_bits(opc);
2021 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
2022 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
2023 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
2025 /* Extract the page index, shifted into place for tlb index. */
2026 if (TCG_TARGET_REG_BITS == 32) {
2027 tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
2028 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
2030 tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
2031 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
2033 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
2035 /* Load the TLB comparator. */
2036 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
2037 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
2039 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
2041 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
2042 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2043 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
2044 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
2046 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
2050 /* Load the TLB addend for use on the fast path. Do this asap
2051 to minimize any load use delay. */
2052 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
2053 offsetof(CPUTLBEntry, addend));
2055 /* Clear the non-page, non-alignment bits from the address */
2056 if (TCG_TARGET_REG_BITS == 32) {
2057 /* We don't support unaligned accesses on 32-bits.
2058 * Preserve the bottom bits and thus trigger a comparison
2059 * failure on unaligned accesses.
2061 if (a_bits < s_bits) {
2064 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
2065 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
2069 /* If the access is unaligned, we need to make sure we fail if we
2070 * cross a page boundary. The trick is to add the access size-1
2071 * to the address before masking the low bits. That will make the
2072 * address overflow to the next page if we cross a page boundary,
2073 * which will then force a mismatch of the TLB compare.
2075 if (a_bits < s_bits) {
2076 unsigned a_mask = (1 << a_bits) - 1;
2077 unsigned s_mask = (1 << s_bits) - 1;
2078 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
2082 /* Mask the address for the requested alignment. */
2083 if (TARGET_LONG_BITS == 32) {
2084 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
2085 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
2086 /* Zero-extend the address for use in the final address. */
2087 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
2088 addrlo = TCG_REG_R4;
2089 } else if (a_bits == 0) {
2090 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
2092 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
2093 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
2094 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
2098 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2099 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
2100 0, 7, TCG_TYPE_I32);
2101 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
2102 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
2104 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
2111 /* Record the context of a call to the out of line helper code for the slow
2112 path for a load or store, so that we can later generate the correct
2114 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
2115 TCGReg datalo_reg, TCGReg datahi_reg,
2116 TCGReg addrlo_reg, TCGReg addrhi_reg,
2117 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
2119 TCGLabelQemuLdst *label = new_ldst_label(s);
2121 label->is_ld = is_ld;
2123 label->datalo_reg = datalo_reg;
2124 label->datahi_reg = datahi_reg;
2125 label->addrlo_reg = addrlo_reg;
2126 label->addrhi_reg = addrhi_reg;
2127 label->raddr = tcg_splitwx_to_rx(raddr);
2128 label->label_ptr[0] = lptr;
2131 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
2133 MemOpIdx oi = lb->oi;
2134 MemOp opc = get_memop(oi);
2135 TCGReg hi, lo, arg = TCG_REG_R3;
2137 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
2141 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
2143 lo = lb->addrlo_reg;
2144 hi = lb->addrhi_reg;
2145 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2146 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
2147 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2148 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2150 /* If the address needed to be zero-extended, we'll have already
2151 placed it in R4. The only remaining case is 64-bit guest. */
2152 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2155 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
2156 tcg_out32(s, MFSPR | RT(arg) | LR);
2158 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
2160 lo = lb->datalo_reg;
2161 hi = lb->datahi_reg;
2162 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
2163 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
2164 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
2165 } else if (opc & MO_SIGN) {
2166 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
2167 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
2169 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
2172 tcg_out_b(s, 0, lb->raddr);
2176 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
2178 MemOpIdx oi = lb->oi;
2179 MemOp opc = get_memop(oi);
2180 MemOp s_bits = opc & MO_SIZE;
2181 TCGReg hi, lo, arg = TCG_REG_R3;
2183 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
2187 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
2189 lo = lb->addrlo_reg;
2190 hi = lb->addrhi_reg;
2191 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2192 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
2193 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2194 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2196 /* If the address needed to be zero-extended, we'll have already
2197 placed it in R4. The only remaining case is 64-bit guest. */
2198 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2201 lo = lb->datalo_reg;
2202 hi = lb->datahi_reg;
2203 if (TCG_TARGET_REG_BITS == 32) {
2206 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
2207 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2210 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2213 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
2217 if (s_bits == MO_64) {
2218 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
2220 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
2224 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
2225 tcg_out32(s, MFSPR | RT(arg) | LR);
2227 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
2229 tcg_out_b(s, 0, lb->raddr);
2234 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
2235 TCGReg addrhi, unsigned a_bits)
2237 unsigned a_mask = (1 << a_bits) - 1;
2238 TCGLabelQemuLdst *label = new_ldst_label(s);
2240 label->is_ld = is_ld;
2241 label->addrlo_reg = addrlo;
2242 label->addrhi_reg = addrhi;
2244 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
2245 tcg_debug_assert(a_bits < 16);
2246 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask));
2248 label->label_ptr[0] = s->code_ptr;
2249 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
2251 label->raddr = tcg_splitwx_to_rx(s->code_ptr);
2254 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
2256 if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
2260 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2261 TCGReg arg = TCG_REG_R4;
2263 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
2264 if (l->addrlo_reg != arg) {
2265 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
2266 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
2267 } else if (l->addrhi_reg != arg + 1) {
2268 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
2269 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
2271 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg);
2272 tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1);
2273 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0);
2276 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg);
2278 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0);
2280 /* "Tail call" to the helper, with the return address back inline. */
2281 tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld
2282 : helper_unaligned_st));
2286 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
2288 return tcg_out_fail_alignment(s, l);
2291 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
2293 return tcg_out_fail_alignment(s, l);
2296 #endif /* SOFTMMU */
2298 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
2300 TCGReg datalo, datahi, addrlo, rbase;
2301 TCGReg addrhi __attribute__((unused));
2304 #ifdef CONFIG_SOFTMMU
2306 tcg_insn_unit *label_ptr;
2312 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2314 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
2316 opc = get_memop(oi);
2317 s_bits = opc & MO_SIZE;
2319 #ifdef CONFIG_SOFTMMU
2320 mem_index = get_mmuidx(oi);
2321 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
2323 /* Load a pointer into the current opcode w/conditional branch-link. */
2324 label_ptr = s->code_ptr;
2325 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
2328 #else /* !CONFIG_SOFTMMU */
2329 a_bits = get_alignment_bits(opc);
2331 tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
2333 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
2334 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
2335 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2336 addrlo = TCG_REG_TMP1;
2340 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2341 if (opc & MO_BSWAP) {
2342 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2343 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2344 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
2345 } else if (rbase != 0) {
2346 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2347 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
2348 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
2349 } else if (addrlo == datahi) {
2350 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2351 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2353 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2354 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2357 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
2358 if (!have_isa_2_06 && insn == LDBRX) {
2359 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2360 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2361 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
2362 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
2364 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2366 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
2367 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2368 insn = qemu_exts_opc[s_bits];
2369 tcg_out32(s, insn | RA(datalo) | RS(datalo));
2373 #ifdef CONFIG_SOFTMMU
2374 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
2375 s->code_ptr, label_ptr);
2379 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
2381 TCGReg datalo, datahi, addrlo, rbase;
2382 TCGReg addrhi __attribute__((unused));
2385 #ifdef CONFIG_SOFTMMU
2387 tcg_insn_unit *label_ptr;
2393 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2395 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
2397 opc = get_memop(oi);
2398 s_bits = opc & MO_SIZE;
2400 #ifdef CONFIG_SOFTMMU
2401 mem_index = get_mmuidx(oi);
2402 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
2404 /* Load a pointer into the current opcode w/conditional branch-link. */
2405 label_ptr = s->code_ptr;
2406 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
2409 #else /* !CONFIG_SOFTMMU */
2410 a_bits = get_alignment_bits(opc);
2412 tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
2414 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
2415 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
2416 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2417 addrlo = TCG_REG_TMP1;
2421 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2422 if (opc & MO_BSWAP) {
2423 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2424 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
2425 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
2426 } else if (rbase != 0) {
2427 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2428 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
2429 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
2431 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
2432 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
2435 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
2436 if (!have_isa_2_06 && insn == STDBRX) {
2437 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
2438 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
2439 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
2440 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
2442 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
2446 #ifdef CONFIG_SOFTMMU
2447 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
2448 s->code_ptr, label_ptr);
2452 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2455 for (i = 0; i < count; ++i) {
2460 /* Parameters for function call generation, used in tcg.c. */
2461 #define TCG_TARGET_STACK_ALIGN 16
2464 # define LINK_AREA_SIZE (6 * SZR)
2465 # define LR_OFFSET (1 * SZR)
2466 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
2467 #elif defined(_CALL_DARWIN)
2468 # define LINK_AREA_SIZE (6 * SZR)
2469 # define LR_OFFSET (2 * SZR)
2470 #elif TCG_TARGET_REG_BITS == 64
2471 # if defined(_CALL_ELF) && _CALL_ELF == 2
2472 # define LINK_AREA_SIZE (4 * SZR)
2473 # define LR_OFFSET (1 * SZR)
2475 #else /* TCG_TARGET_REG_BITS == 32 */
2476 # if defined(_CALL_SYSV)
2477 # define LINK_AREA_SIZE (2 * SZR)
2478 # define LR_OFFSET (1 * SZR)
2482 # error "Unhandled abi"
2484 #ifndef TCG_TARGET_CALL_STACK_OFFSET
2485 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
2488 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2489 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
2491 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
2492 + TCG_STATIC_CALL_ARGS_SIZE \
2493 + CPU_TEMP_BUF_SIZE \
2495 + TCG_TARGET_STACK_ALIGN - 1) \
2496 & -TCG_TARGET_STACK_ALIGN)
2498 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
2500 static void tcg_target_qemu_prologue(TCGContext *s)
2505 const void **desc = (const void **)s->code_ptr;
2506 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */
2507 desc[1] = 0; /* environment pointer */
2508 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
2511 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
2515 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
2516 tcg_out32(s, (SZR == 8 ? STDU : STWU)
2517 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
2519 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
2520 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2521 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
2523 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
2525 #ifndef CONFIG_SOFTMMU
2527 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
2528 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2532 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2533 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
2535 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
2537 tcg_out32(s, BCCTR | BO_ALWAYS);
2540 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2542 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
2543 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
2544 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2545 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
2547 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
2548 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
2549 tcg_out32(s, BCLR | BO_ALWAYS);
2552 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg)
2554 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg);
2555 tcg_out_b(s, 0, tcg_code_gen_epilogue);
2558 static void tcg_out_goto_tb(TCGContext *s, int which)
2560 uintptr_t ptr = get_jmp_target_addr(s, which);
2563 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr);
2564 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset);
2566 /* Direct branch will be patched by tb_target_set_jmp_target. */
2567 set_jmp_insn_offset(s, which);
2568 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
2570 /* When branch is out of range, fall through to indirect. */
2571 tcg_out32(s, BCCTR | BO_ALWAYS);
2573 /* For the unlinked case, need to reset TCG_REG_TB. */
2574 set_jmp_reset_offset(s, which);
2575 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB,
2576 -tcg_current_code_size(s));
2578 /* Direct branch will be patched by tb_target_set_jmp_target. */
2579 set_jmp_insn_offset(s, which);
2582 /* When branch is out of range, fall through to indirect. */
2583 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr);
2584 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr);
2585 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
2586 tcg_out32(s, BCCTR | BO_ALWAYS);
2587 set_jmp_reset_offset(s, which);
2591 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
2592 uintptr_t jmp_rx, uintptr_t jmp_rw)
2594 uintptr_t addr = tb->jmp_target_addr[n];
2595 intptr_t diff = addr - jmp_rx;
2598 if (in_range_b(diff)) {
2599 insn = B | (diff & 0x3fffffc);
2600 } else if (USE_REG_TB) {
2601 insn = MTSPR | RS(TCG_REG_TB) | CTR;
2606 qatomic_set((uint32_t *)jmp_rw, insn);
2607 flush_idcache_range(jmp_rx, jmp_rw, 4);
2610 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
2611 const TCGArg args[TCG_MAX_OP_ARGS],
2612 const int const_args[TCG_MAX_OP_ARGS])
2617 case INDEX_op_goto_ptr:
2618 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
2620 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2622 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
2623 tcg_out32(s, BCCTR | BO_ALWAYS);
2627 TCGLabel *l = arg_label(args[0]);
2631 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr),
2634 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
2639 case INDEX_op_ld8u_i32:
2640 case INDEX_op_ld8u_i64:
2641 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
2643 case INDEX_op_ld8s_i32:
2644 case INDEX_op_ld8s_i64:
2645 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
2646 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]);
2648 case INDEX_op_ld16u_i32:
2649 case INDEX_op_ld16u_i64:
2650 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
2652 case INDEX_op_ld16s_i32:
2653 case INDEX_op_ld16s_i64:
2654 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
2656 case INDEX_op_ld_i32:
2657 case INDEX_op_ld32u_i64:
2658 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
2660 case INDEX_op_ld32s_i64:
2661 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
2663 case INDEX_op_ld_i64:
2664 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
2666 case INDEX_op_st8_i32:
2667 case INDEX_op_st8_i64:
2668 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
2670 case INDEX_op_st16_i32:
2671 case INDEX_op_st16_i64:
2672 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
2674 case INDEX_op_st_i32:
2675 case INDEX_op_st32_i64:
2676 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
2678 case INDEX_op_st_i64:
2679 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
2682 case INDEX_op_add_i32:
2683 a0 = args[0], a1 = args[1], a2 = args[2];
2684 if (const_args[2]) {
2686 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
2688 tcg_out32(s, ADD | TAB(a0, a1, a2));
2691 case INDEX_op_sub_i32:
2692 a0 = args[0], a1 = args[1], a2 = args[2];
2693 if (const_args[1]) {
2694 if (const_args[2]) {
2695 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2697 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2699 } else if (const_args[2]) {
2703 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2707 case INDEX_op_and_i32:
2708 a0 = args[0], a1 = args[1], a2 = args[2];
2709 if (const_args[2]) {
2710 tcg_out_andi32(s, a0, a1, a2);
2712 tcg_out32(s, AND | SAB(a1, a0, a2));
2715 case INDEX_op_and_i64:
2716 a0 = args[0], a1 = args[1], a2 = args[2];
2717 if (const_args[2]) {
2718 tcg_out_andi64(s, a0, a1, a2);
2720 tcg_out32(s, AND | SAB(a1, a0, a2));
2723 case INDEX_op_or_i64:
2724 case INDEX_op_or_i32:
2725 a0 = args[0], a1 = args[1], a2 = args[2];
2726 if (const_args[2]) {
2727 tcg_out_ori32(s, a0, a1, a2);
2729 tcg_out32(s, OR | SAB(a1, a0, a2));
2732 case INDEX_op_xor_i64:
2733 case INDEX_op_xor_i32:
2734 a0 = args[0], a1 = args[1], a2 = args[2];
2735 if (const_args[2]) {
2736 tcg_out_xori32(s, a0, a1, a2);
2738 tcg_out32(s, XOR | SAB(a1, a0, a2));
2741 case INDEX_op_andc_i32:
2742 a0 = args[0], a1 = args[1], a2 = args[2];
2743 if (const_args[2]) {
2744 tcg_out_andi32(s, a0, a1, ~a2);
2746 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2749 case INDEX_op_andc_i64:
2750 a0 = args[0], a1 = args[1], a2 = args[2];
2751 if (const_args[2]) {
2752 tcg_out_andi64(s, a0, a1, ~a2);
2754 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2757 case INDEX_op_orc_i32:
2758 if (const_args[2]) {
2759 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2763 case INDEX_op_orc_i64:
2764 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2766 case INDEX_op_eqv_i32:
2767 if (const_args[2]) {
2768 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2772 case INDEX_op_eqv_i64:
2773 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2775 case INDEX_op_nand_i32:
2776 case INDEX_op_nand_i64:
2777 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2779 case INDEX_op_nor_i32:
2780 case INDEX_op_nor_i64:
2781 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2784 case INDEX_op_clz_i32:
2785 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2786 args[2], const_args[2]);
2788 case INDEX_op_ctz_i32:
2789 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2790 args[2], const_args[2]);
2792 case INDEX_op_ctpop_i32:
2793 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2796 case INDEX_op_clz_i64:
2797 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2798 args[2], const_args[2]);
2800 case INDEX_op_ctz_i64:
2801 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2802 args[2], const_args[2]);
2804 case INDEX_op_ctpop_i64:
2805 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2808 case INDEX_op_mul_i32:
2809 a0 = args[0], a1 = args[1], a2 = args[2];
2810 if (const_args[2]) {
2811 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2813 tcg_out32(s, MULLW | TAB(a0, a1, a2));
2817 case INDEX_op_div_i32:
2818 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
2821 case INDEX_op_divu_i32:
2822 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
2825 case INDEX_op_rem_i32:
2826 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2]));
2829 case INDEX_op_remu_i32:
2830 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2]));
2833 case INDEX_op_shl_i32:
2834 if (const_args[2]) {
2835 /* Limit immediate shift count lest we create an illegal insn. */
2836 tcg_out_shli32(s, args[0], args[1], args[2] & 31);
2838 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
2841 case INDEX_op_shr_i32:
2842 if (const_args[2]) {
2843 /* Limit immediate shift count lest we create an illegal insn. */
2844 tcg_out_shri32(s, args[0], args[1], args[2] & 31);
2846 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
2849 case INDEX_op_sar_i32:
2850 if (const_args[2]) {
2851 tcg_out_sari32(s, args[0], args[1], args[2]);
2853 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2856 case INDEX_op_rotl_i32:
2857 if (const_args[2]) {
2858 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2860 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2864 case INDEX_op_rotr_i32:
2865 if (const_args[2]) {
2866 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2868 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2869 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
2874 case INDEX_op_brcond_i32:
2875 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2876 arg_label(args[3]), TCG_TYPE_I32);
2878 case INDEX_op_brcond_i64:
2879 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2880 arg_label(args[3]), TCG_TYPE_I64);
2882 case INDEX_op_brcond2_i32:
2883 tcg_out_brcond2(s, args, const_args);
2886 case INDEX_op_neg_i32:
2887 case INDEX_op_neg_i64:
2888 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
2891 case INDEX_op_not_i32:
2892 case INDEX_op_not_i64:
2893 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
2896 case INDEX_op_add_i64:
2897 a0 = args[0], a1 = args[1], a2 = args[2];
2898 if (const_args[2]) {
2900 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
2902 tcg_out32(s, ADD | TAB(a0, a1, a2));
2905 case INDEX_op_sub_i64:
2906 a0 = args[0], a1 = args[1], a2 = args[2];
2907 if (const_args[1]) {
2908 if (const_args[2]) {
2909 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2911 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2913 } else if (const_args[2]) {
2917 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2921 case INDEX_op_shl_i64:
2922 if (const_args[2]) {
2923 /* Limit immediate shift count lest we create an illegal insn. */
2924 tcg_out_shli64(s, args[0], args[1], args[2] & 63);
2926 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2929 case INDEX_op_shr_i64:
2930 if (const_args[2]) {
2931 /* Limit immediate shift count lest we create an illegal insn. */
2932 tcg_out_shri64(s, args[0], args[1], args[2] & 63);
2934 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2937 case INDEX_op_sar_i64:
2938 if (const_args[2]) {
2939 tcg_out_sari64(s, args[0], args[1], args[2]);
2941 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
2944 case INDEX_op_rotl_i64:
2945 if (const_args[2]) {
2946 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2948 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2951 case INDEX_op_rotr_i64:
2952 if (const_args[2]) {
2953 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2955 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2956 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
2960 case INDEX_op_mul_i64:
2961 a0 = args[0], a1 = args[1], a2 = args[2];
2962 if (const_args[2]) {
2963 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2965 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2968 case INDEX_op_div_i64:
2969 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
2971 case INDEX_op_divu_i64:
2972 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
2974 case INDEX_op_rem_i64:
2975 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2]));
2977 case INDEX_op_remu_i64:
2978 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2]));
2981 case INDEX_op_qemu_ld_i32:
2982 tcg_out_qemu_ld(s, args, false);
2984 case INDEX_op_qemu_ld_i64:
2985 tcg_out_qemu_ld(s, args, true);
2987 case INDEX_op_qemu_st_i32:
2988 tcg_out_qemu_st(s, args, false);
2990 case INDEX_op_qemu_st_i64:
2991 tcg_out_qemu_st(s, args, true);
2994 case INDEX_op_setcond_i32:
2995 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2998 case INDEX_op_setcond_i64:
2999 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
3002 case INDEX_op_setcond2_i32:
3003 tcg_out_setcond2(s, args, const_args);
3006 case INDEX_op_bswap16_i32:
3007 case INDEX_op_bswap16_i64:
3008 tcg_out_bswap16(s, args[0], args[1], args[2]);
3010 case INDEX_op_bswap32_i32:
3011 tcg_out_bswap32(s, args[0], args[1], 0);
3013 case INDEX_op_bswap32_i64:
3014 tcg_out_bswap32(s, args[0], args[1], args[2]);
3016 case INDEX_op_bswap64_i64:
3017 tcg_out_bswap64(s, args[0], args[1]);
3020 case INDEX_op_deposit_i32:
3021 if (const_args[2]) {
3022 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
3023 tcg_out_andi32(s, args[0], args[0], ~mask);
3025 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
3026 32 - args[3] - args[4], 31 - args[3]);
3029 case INDEX_op_deposit_i64:
3030 if (const_args[2]) {
3031 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
3032 tcg_out_andi64(s, args[0], args[0], ~mask);
3034 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
3035 64 - args[3] - args[4]);
3039 case INDEX_op_extract_i32:
3040 tcg_out_rlw(s, RLWINM, args[0], args[1],
3041 32 - args[2], 32 - args[3], 31);
3043 case INDEX_op_extract_i64:
3044 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
3047 case INDEX_op_movcond_i32:
3048 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
3049 args[3], args[4], const_args[2]);
3051 case INDEX_op_movcond_i64:
3052 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
3053 args[3], args[4], const_args[2]);
3056 #if TCG_TARGET_REG_BITS == 64
3057 case INDEX_op_add2_i64:
3059 case INDEX_op_add2_i32:
3061 /* Note that the CA bit is defined based on the word size of the
3062 environment. So in 64-bit mode it's always carry-out of bit 63.
3063 The fallback code using deposit works just as well for 32-bit. */
3064 a0 = args[0], a1 = args[1];
3065 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
3068 if (const_args[4]) {
3069 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
3071 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
3073 if (const_args[5]) {
3074 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
3076 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
3078 if (a0 != args[0]) {
3079 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
3083 #if TCG_TARGET_REG_BITS == 64
3084 case INDEX_op_sub2_i64:
3086 case INDEX_op_sub2_i32:
3088 a0 = args[0], a1 = args[1];
3089 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
3092 if (const_args[2]) {
3093 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
3095 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
3097 if (const_args[3]) {
3098 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
3100 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
3102 if (a0 != args[0]) {
3103 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
3107 case INDEX_op_muluh_i32:
3108 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
3110 case INDEX_op_mulsh_i32:
3111 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
3113 case INDEX_op_muluh_i64:
3114 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
3116 case INDEX_op_mulsh_i64:
3117 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
3121 tcg_out_mb(s, args[0]);
3124 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
3125 case INDEX_op_mov_i64:
3126 case INDEX_op_call: /* Always emitted via tcg_out_call. */
3127 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
3128 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
3129 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
3130 case INDEX_op_ext8s_i64:
3131 case INDEX_op_ext8u_i32:
3132 case INDEX_op_ext8u_i64:
3133 case INDEX_op_ext16s_i32:
3134 case INDEX_op_ext16s_i64:
3135 case INDEX_op_ext16u_i32:
3136 case INDEX_op_ext16u_i64:
3137 case INDEX_op_ext32s_i64:
3138 case INDEX_op_ext32u_i64:
3139 case INDEX_op_ext_i32_i64:
3140 case INDEX_op_extu_i32_i64:
3142 g_assert_not_reached();
3146 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
3149 case INDEX_op_and_vec:
3150 case INDEX_op_or_vec:
3151 case INDEX_op_xor_vec:
3152 case INDEX_op_andc_vec:
3153 case INDEX_op_not_vec:
3154 case INDEX_op_nor_vec:
3155 case INDEX_op_eqv_vec:
3156 case INDEX_op_nand_vec:
3158 case INDEX_op_orc_vec:
3159 return have_isa_2_07;
3160 case INDEX_op_add_vec:
3161 case INDEX_op_sub_vec:
3162 case INDEX_op_smax_vec:
3163 case INDEX_op_smin_vec:
3164 case INDEX_op_umax_vec:
3165 case INDEX_op_umin_vec:
3166 case INDEX_op_shlv_vec:
3167 case INDEX_op_shrv_vec:
3168 case INDEX_op_sarv_vec:
3169 case INDEX_op_rotlv_vec:
3170 return vece <= MO_32 || have_isa_2_07;
3171 case INDEX_op_ssadd_vec:
3172 case INDEX_op_sssub_vec:
3173 case INDEX_op_usadd_vec:
3174 case INDEX_op_ussub_vec:
3175 return vece <= MO_32;
3176 case INDEX_op_cmp_vec:
3177 case INDEX_op_shli_vec:
3178 case INDEX_op_shri_vec:
3179 case INDEX_op_sari_vec:
3180 case INDEX_op_rotli_vec:
3181 return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
3182 case INDEX_op_neg_vec:
3183 return vece >= MO_32 && have_isa_3_00;
3184 case INDEX_op_mul_vec:
3190 return have_isa_2_07 ? 1 : -1;
3192 return have_isa_3_10;
3195 case INDEX_op_bitsel_vec:
3197 case INDEX_op_rotrv_vec:
3204 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
3205 TCGReg dst, TCGReg src)
3207 tcg_debug_assert(dst >= TCG_REG_V0);
3209 /* Splat from integer reg allowed via constraints for v3.00. */
3210 if (src < TCG_REG_V0) {
3211 tcg_debug_assert(have_isa_3_00);
3214 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
3217 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
3220 /* Fail, so that we fall back on either dupm or mov+dup. */
3226 * Recall we use (or emulate) VSX integer loads, so the integer is
3227 * right justified within the left (zero-index) double-word.
3231 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
3234 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
3237 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
3241 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
3244 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
3245 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
3248 g_assert_not_reached();
3253 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
3254 TCGReg out, TCGReg base, intptr_t offset)
3258 tcg_debug_assert(out >= TCG_REG_V0);
3261 if (have_isa_3_00) {
3262 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
3264 tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
3266 elt = extract32(offset, 0, 4);
3267 #if !HOST_BIG_ENDIAN
3270 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
3273 tcg_debug_assert((offset & 1) == 0);
3274 if (have_isa_3_00) {
3275 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
3277 tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
3279 elt = extract32(offset, 1, 3);
3280 #if !HOST_BIG_ENDIAN
3283 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
3286 if (have_isa_3_00) {
3287 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
3290 tcg_debug_assert((offset & 3) == 0);
3291 tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
3292 elt = extract32(offset, 2, 2);
3293 #if !HOST_BIG_ENDIAN
3296 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
3300 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
3303 tcg_debug_assert((offset & 7) == 0);
3304 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
3305 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
3306 elt = extract32(offset, 3, 1);
3307 #if !HOST_BIG_ENDIAN
3311 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
3313 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
3317 g_assert_not_reached();
3322 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3323 unsigned vecl, unsigned vece,
3324 const TCGArg args[TCG_MAX_OP_ARGS],
3325 const int const_args[TCG_MAX_OP_ARGS])
3327 static const uint32_t
3328 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
3329 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
3330 mul_op[4] = { 0, 0, VMULUWM, VMULLD },
3331 neg_op[4] = { 0, 0, VNEGW, VNEGD },
3332 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
3333 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
3334 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
3335 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
3336 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
3337 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
3338 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
3339 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
3340 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
3341 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
3342 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
3343 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
3344 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
3345 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
3346 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
3347 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
3348 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
3349 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
3350 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
3351 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
3352 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
3354 TCGType type = vecl + TCG_TYPE_V64;
3355 TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
3359 case INDEX_op_ld_vec:
3360 tcg_out_ld(s, type, a0, a1, a2);
3362 case INDEX_op_st_vec:
3363 tcg_out_st(s, type, a0, a1, a2);
3365 case INDEX_op_dupm_vec:
3366 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
3369 case INDEX_op_add_vec:
3370 insn = add_op[vece];
3372 case INDEX_op_sub_vec:
3373 insn = sub_op[vece];
3375 case INDEX_op_neg_vec:
3376 insn = neg_op[vece];
3380 case INDEX_op_mul_vec:
3381 insn = mul_op[vece];
3383 case INDEX_op_ssadd_vec:
3384 insn = ssadd_op[vece];
3386 case INDEX_op_sssub_vec:
3387 insn = sssub_op[vece];
3389 case INDEX_op_usadd_vec:
3390 insn = usadd_op[vece];
3392 case INDEX_op_ussub_vec:
3393 insn = ussub_op[vece];
3395 case INDEX_op_smin_vec:
3396 insn = smin_op[vece];
3398 case INDEX_op_umin_vec:
3399 insn = umin_op[vece];
3401 case INDEX_op_smax_vec:
3402 insn = smax_op[vece];
3404 case INDEX_op_umax_vec:
3405 insn = umax_op[vece];
3407 case INDEX_op_shlv_vec:
3408 insn = shlv_op[vece];
3410 case INDEX_op_shrv_vec:
3411 insn = shrv_op[vece];
3413 case INDEX_op_sarv_vec:
3414 insn = sarv_op[vece];
3416 case INDEX_op_and_vec:
3419 case INDEX_op_or_vec:
3422 case INDEX_op_xor_vec:
3425 case INDEX_op_andc_vec:
3428 case INDEX_op_not_vec:
3432 case INDEX_op_orc_vec:
3435 case INDEX_op_nand_vec:
3438 case INDEX_op_nor_vec:
3441 case INDEX_op_eqv_vec:
3445 case INDEX_op_cmp_vec:
3454 insn = gts_op[vece];
3457 insn = gtu_op[vece];
3460 g_assert_not_reached();
3464 case INDEX_op_bitsel_vec:
3465 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
3468 case INDEX_op_dup2_vec:
3469 assert(TCG_TARGET_REG_BITS == 32);
3470 /* With inputs a1 = xLxx, a2 = xHxx */
3471 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
3472 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
3473 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
3476 case INDEX_op_ppc_mrgh_vec:
3477 insn = mrgh_op[vece];
3479 case INDEX_op_ppc_mrgl_vec:
3480 insn = mrgl_op[vece];
3482 case INDEX_op_ppc_muleu_vec:
3483 insn = muleu_op[vece];
3485 case INDEX_op_ppc_mulou_vec:
3486 insn = mulou_op[vece];
3488 case INDEX_op_ppc_pkum_vec:
3489 insn = pkum_op[vece];
3491 case INDEX_op_rotlv_vec:
3492 insn = rotl_op[vece];
3494 case INDEX_op_ppc_msum_vec:
3495 tcg_debug_assert(vece == MO_16);
3496 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
3499 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
3500 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
3502 g_assert_not_reached();
3505 tcg_debug_assert(insn != 0);
3506 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
3509 static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
3510 TCGv_vec v1, TCGArg imm, TCGOpcode opci)
3514 if (vece == MO_32) {
3516 * Only 5 bits are significant, and VSPLTISB can represent -16..15.
3517 * So using negative numbers gets us the 4th bit easily.
3519 imm = sextract32(imm, 0, 5);
3521 imm &= (8 << vece) - 1;
3524 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */
3525 t1 = tcg_constant_vec(type, MO_8, imm);
3526 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
3527 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
3530 static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
3531 TCGv_vec v1, TCGv_vec v2, TCGCond cond)
3533 bool need_swap = false, need_inv = false;
3535 tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
3543 if (have_isa_3_00 && vece <= MO_32) {
3557 need_swap = need_inv = true;
3560 g_assert_not_reached();
3564 cond = tcg_invert_cond(cond);
3568 t1 = v1, v1 = v2, v2 = t1;
3569 cond = tcg_swap_cond(cond);
3572 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
3573 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
3576 tcg_gen_not_vec(vece, v0, v0);
3580 static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
3581 TCGv_vec v1, TCGv_vec v2)
3583 TCGv_vec t1 = tcg_temp_new_vec(type);
3584 TCGv_vec t2 = tcg_temp_new_vec(type);
3590 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
3591 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3592 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
3593 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3594 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
3595 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3596 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
3597 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3598 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
3599 tcgv_vec_arg(v0), tcgv_vec_arg(t1));
3603 tcg_debug_assert(!have_isa_2_07);
3605 * Only 5 bits are significant, and VSPLTISB can represent -16..15.
3606 * So using -16 is a quick way to represent 16.
3608 c16 = tcg_constant_vec(type, MO_8, -16);
3609 c0 = tcg_constant_vec(type, MO_8, 0);
3611 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
3612 tcgv_vec_arg(v2), tcgv_vec_arg(c16));
3613 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
3614 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3615 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1),
3616 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0));
3617 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1),
3618 tcgv_vec_arg(t1), tcgv_vec_arg(c16));
3619 tcg_gen_add_vec(MO_32, v0, t1, t2);
3623 g_assert_not_reached();
3625 tcg_temp_free_vec(t1);
3626 tcg_temp_free_vec(t2);
3629 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
3633 TCGv_vec v0, v1, v2, t0;
3637 v0 = temp_tcgv_vec(arg_temp(a0));
3638 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
3639 a2 = va_arg(va, TCGArg);
3642 case INDEX_op_shli_vec:
3643 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
3645 case INDEX_op_shri_vec:
3646 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
3648 case INDEX_op_sari_vec:
3649 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
3651 case INDEX_op_rotli_vec:
3652 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
3654 case INDEX_op_cmp_vec:
3655 v2 = temp_tcgv_vec(arg_temp(a2));
3656 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
3658 case INDEX_op_mul_vec:
3659 v2 = temp_tcgv_vec(arg_temp(a2));
3660 expand_vec_mul(type, vece, v0, v1, v2);
3662 case INDEX_op_rotlv_vec:
3663 v2 = temp_tcgv_vec(arg_temp(a2));
3664 t0 = tcg_temp_new_vec(type);
3665 tcg_gen_neg_vec(vece, t0, v2);
3666 tcg_gen_rotlv_vec(vece, v0, v1, t0);
3667 tcg_temp_free_vec(t0);
3670 g_assert_not_reached();
3675 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
3678 case INDEX_op_goto_ptr:
3681 case INDEX_op_ld8u_i32:
3682 case INDEX_op_ld8s_i32:
3683 case INDEX_op_ld16u_i32:
3684 case INDEX_op_ld16s_i32:
3685 case INDEX_op_ld_i32:
3686 case INDEX_op_ctpop_i32:
3687 case INDEX_op_neg_i32:
3688 case INDEX_op_not_i32:
3689 case INDEX_op_ext8s_i32:
3690 case INDEX_op_ext16s_i32:
3691 case INDEX_op_bswap16_i32:
3692 case INDEX_op_bswap32_i32:
3693 case INDEX_op_extract_i32:
3694 case INDEX_op_ld8u_i64:
3695 case INDEX_op_ld8s_i64:
3696 case INDEX_op_ld16u_i64:
3697 case INDEX_op_ld16s_i64:
3698 case INDEX_op_ld32u_i64:
3699 case INDEX_op_ld32s_i64:
3700 case INDEX_op_ld_i64:
3701 case INDEX_op_ctpop_i64:
3702 case INDEX_op_neg_i64:
3703 case INDEX_op_not_i64:
3704 case INDEX_op_ext8s_i64:
3705 case INDEX_op_ext16s_i64:
3706 case INDEX_op_ext32s_i64:
3707 case INDEX_op_ext_i32_i64:
3708 case INDEX_op_extu_i32_i64:
3709 case INDEX_op_bswap16_i64:
3710 case INDEX_op_bswap32_i64:
3711 case INDEX_op_bswap64_i64:
3712 case INDEX_op_extract_i64:
3713 return C_O1_I1(r, r);
3715 case INDEX_op_st8_i32:
3716 case INDEX_op_st16_i32:
3717 case INDEX_op_st_i32:
3718 case INDEX_op_st8_i64:
3719 case INDEX_op_st16_i64:
3720 case INDEX_op_st32_i64:
3721 case INDEX_op_st_i64:
3722 return C_O0_I2(r, r);
3724 case INDEX_op_add_i32:
3725 case INDEX_op_and_i32:
3726 case INDEX_op_or_i32:
3727 case INDEX_op_xor_i32:
3728 case INDEX_op_andc_i32:
3729 case INDEX_op_orc_i32:
3730 case INDEX_op_eqv_i32:
3731 case INDEX_op_shl_i32:
3732 case INDEX_op_shr_i32:
3733 case INDEX_op_sar_i32:
3734 case INDEX_op_rotl_i32:
3735 case INDEX_op_rotr_i32:
3736 case INDEX_op_setcond_i32:
3737 case INDEX_op_and_i64:
3738 case INDEX_op_andc_i64:
3739 case INDEX_op_shl_i64:
3740 case INDEX_op_shr_i64:
3741 case INDEX_op_sar_i64:
3742 case INDEX_op_rotl_i64:
3743 case INDEX_op_rotr_i64:
3744 case INDEX_op_setcond_i64:
3745 return C_O1_I2(r, r, ri);
3747 case INDEX_op_mul_i32:
3748 case INDEX_op_mul_i64:
3749 return C_O1_I2(r, r, rI);
3751 case INDEX_op_div_i32:
3752 case INDEX_op_divu_i32:
3753 case INDEX_op_rem_i32:
3754 case INDEX_op_remu_i32:
3755 case INDEX_op_nand_i32:
3756 case INDEX_op_nor_i32:
3757 case INDEX_op_muluh_i32:
3758 case INDEX_op_mulsh_i32:
3759 case INDEX_op_orc_i64:
3760 case INDEX_op_eqv_i64:
3761 case INDEX_op_nand_i64:
3762 case INDEX_op_nor_i64:
3763 case INDEX_op_div_i64:
3764 case INDEX_op_divu_i64:
3765 case INDEX_op_rem_i64:
3766 case INDEX_op_remu_i64:
3767 case INDEX_op_mulsh_i64:
3768 case INDEX_op_muluh_i64:
3769 return C_O1_I2(r, r, r);
3771 case INDEX_op_sub_i32:
3772 return C_O1_I2(r, rI, ri);
3773 case INDEX_op_add_i64:
3774 return C_O1_I2(r, r, rT);
3775 case INDEX_op_or_i64:
3776 case INDEX_op_xor_i64:
3777 return C_O1_I2(r, r, rU);
3778 case INDEX_op_sub_i64:
3779 return C_O1_I2(r, rI, rT);
3780 case INDEX_op_clz_i32:
3781 case INDEX_op_ctz_i32:
3782 case INDEX_op_clz_i64:
3783 case INDEX_op_ctz_i64:
3784 return C_O1_I2(r, r, rZW);
3786 case INDEX_op_brcond_i32:
3787 case INDEX_op_brcond_i64:
3788 return C_O0_I2(r, ri);
3790 case INDEX_op_movcond_i32:
3791 case INDEX_op_movcond_i64:
3792 return C_O1_I4(r, r, ri, rZ, rZ);
3793 case INDEX_op_deposit_i32:
3794 case INDEX_op_deposit_i64:
3795 return C_O1_I2(r, 0, rZ);
3796 case INDEX_op_brcond2_i32:
3797 return C_O0_I4(r, r, ri, ri);
3798 case INDEX_op_setcond2_i32:
3799 return C_O1_I4(r, r, r, ri, ri);
3800 case INDEX_op_add2_i64:
3801 case INDEX_op_add2_i32:
3802 return C_O2_I4(r, r, r, r, rI, rZM);
3803 case INDEX_op_sub2_i64:
3804 case INDEX_op_sub2_i32:
3805 return C_O2_I4(r, r, rI, rZM, r, r);
3807 case INDEX_op_qemu_ld_i32:
3808 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
3810 : C_O1_I2(r, L, L));
3812 case INDEX_op_qemu_st_i32:
3813 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
3815 : C_O0_I3(S, S, S));
3817 case INDEX_op_qemu_ld_i64:
3818 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
3819 : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
3820 : C_O2_I2(L, L, L, L));
3822 case INDEX_op_qemu_st_i64:
3823 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
3824 : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
3825 : C_O0_I4(S, S, S, S));
3827 case INDEX_op_add_vec:
3828 case INDEX_op_sub_vec:
3829 case INDEX_op_mul_vec:
3830 case INDEX_op_and_vec:
3831 case INDEX_op_or_vec:
3832 case INDEX_op_xor_vec:
3833 case INDEX_op_andc_vec:
3834 case INDEX_op_orc_vec:
3835 case INDEX_op_nor_vec:
3836 case INDEX_op_eqv_vec:
3837 case INDEX_op_nand_vec:
3838 case INDEX_op_cmp_vec:
3839 case INDEX_op_ssadd_vec:
3840 case INDEX_op_sssub_vec:
3841 case INDEX_op_usadd_vec:
3842 case INDEX_op_ussub_vec:
3843 case INDEX_op_smax_vec:
3844 case INDEX_op_smin_vec:
3845 case INDEX_op_umax_vec:
3846 case INDEX_op_umin_vec:
3847 case INDEX_op_shlv_vec:
3848 case INDEX_op_shrv_vec:
3849 case INDEX_op_sarv_vec:
3850 case INDEX_op_rotlv_vec:
3851 case INDEX_op_rotrv_vec:
3852 case INDEX_op_ppc_mrgh_vec:
3853 case INDEX_op_ppc_mrgl_vec:
3854 case INDEX_op_ppc_muleu_vec:
3855 case INDEX_op_ppc_mulou_vec:
3856 case INDEX_op_ppc_pkum_vec:
3857 case INDEX_op_dup2_vec:
3858 return C_O1_I2(v, v, v);
3860 case INDEX_op_not_vec:
3861 case INDEX_op_neg_vec:
3862 return C_O1_I1(v, v);
3864 case INDEX_op_dup_vec:
3865 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
3867 case INDEX_op_ld_vec:
3868 case INDEX_op_dupm_vec:
3869 return C_O1_I1(v, r);
3871 case INDEX_op_st_vec:
3872 return C_O0_I2(v, r);
3874 case INDEX_op_bitsel_vec:
3875 case INDEX_op_ppc_msum_vec:
3876 return C_O1_I3(v, v, v, v);
3879 g_assert_not_reached();
3883 static void tcg_target_init(TCGContext *s)
3885 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
3886 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
3888 have_isa = tcg_isa_base;
3889 if (hwcap & PPC_FEATURE_ARCH_2_06) {
3890 have_isa = tcg_isa_2_06;
3892 #ifdef PPC_FEATURE2_ARCH_2_07
3893 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
3894 have_isa = tcg_isa_2_07;
3897 #ifdef PPC_FEATURE2_ARCH_3_00
3898 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
3899 have_isa = tcg_isa_3_00;
3902 #ifdef PPC_FEATURE2_ARCH_3_10
3903 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
3904 have_isa = tcg_isa_3_10;
3908 #ifdef PPC_FEATURE2_HAS_ISEL
3909 /* Prefer explicit instruction from the kernel. */
3910 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
3912 /* Fall back to knowing Power7 (2.06) has ISEL. */
3913 have_isel = have_isa_2_06;
3916 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
3917 have_altivec = true;
3918 /* We only care about the portion of VSX that overlaps Altivec. */
3919 if (hwcap & PPC_FEATURE_HAS_VSX) {
3924 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
3925 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
3927 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3928 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
3931 tcg_target_call_clobber_regs = 0;
3932 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
3933 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
3934 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
3935 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
3936 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
3937 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
3938 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
3939 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
3940 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
3941 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
3942 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
3943 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
3945 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
3946 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
3947 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
3948 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
3949 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
3950 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
3951 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
3952 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
3953 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
3954 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
3955 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
3956 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
3957 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
3958 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
3959 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
3960 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
3961 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
3962 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
3963 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
3964 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
3966 s->reserved_regs = 0;
3967 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
3968 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
3969 #if defined(_CALL_SYSV)
3970 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
3972 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
3973 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
3975 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
3976 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
3977 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
3979 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
3986 DebugFrameFDEHeader fde;
3987 uint8_t fde_def_cfa[4];
3988 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
3991 /* We're expecting a 2 byte uleb128 encoded value. */
3992 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
3994 #if TCG_TARGET_REG_BITS == 64
3995 # define ELF_HOST_MACHINE EM_PPC64
3997 # define ELF_HOST_MACHINE EM_PPC
4000 static DebugFrame debug_frame = {
4001 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
4004 .cie.code_align = 1,
4005 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
4006 .cie.return_column = 65,
4008 /* Total FDE size does not include the "len" member. */
4009 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
4012 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
4013 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
4017 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
4018 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
4022 void tcg_register_jit(const void *buf, size_t buf_size)
4024 uint8_t *p = &debug_frame.fde_reg_ofs[3];
4027 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
4028 p[0] = 0x80 + tcg_target_callee_save_regs[i];
4029 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
4032 debug_frame.fde.func_start = (uintptr_t)buf;
4033 debug_frame.fde.func_len = buf_size;
4035 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
4037 #endif /* __ELF__ */