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1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_PHYS_ADDR_BITS == 32
32 #define LD_ADDEND LWZ
33 #else
34 #define LD_ADDEND LD
35 #endif
36
37 #if TARGET_LONG_BITS == 32
38 #define LD_ADDR LWZU
39 #define CMP_L 0
40 #else
41 #define LD_ADDR LDU
42 #define CMP_L (1<<21)
43 #endif
44
45 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "r0",
47 "r1",
48 "rp",
49 "r3",
50 "r4",
51 "r5",
52 "r6",
53 "r7",
54 "r8",
55 "r9",
56 "r10",
57 "r11",
58 "r12",
59 "r13",
60 "r14",
61 "r15",
62 "r16",
63 "r17",
64 "r18",
65 "r19",
66 "r20",
67 "r21",
68 "r22",
69 "r23",
70 "r24",
71 "r25",
72 "r26",
73 "r27",
74 "r28",
75 "r29",
76 "r30",
77 "r31"
78 };
79
80 static const int tcg_target_reg_alloc_order[] = {
81 TCG_REG_R14,
82 TCG_REG_R15,
83 TCG_REG_R16,
84 TCG_REG_R17,
85 TCG_REG_R18,
86 TCG_REG_R19,
87 TCG_REG_R20,
88 TCG_REG_R21,
89 TCG_REG_R22,
90 TCG_REG_R23,
91 TCG_REG_R28,
92 TCG_REG_R29,
93 TCG_REG_R30,
94 TCG_REG_R31,
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 TCG_REG_R11,
104 TCG_REG_R12,
105 TCG_REG_R13,
106 TCG_REG_R0,
107 TCG_REG_R1,
108 TCG_REG_R2,
109 TCG_REG_R24,
110 TCG_REG_R25,
111 TCG_REG_R26,
112 TCG_REG_R27
113 };
114
115 static const int tcg_target_call_iarg_regs[] = {
116 TCG_REG_R3,
117 TCG_REG_R4,
118 TCG_REG_R5,
119 TCG_REG_R6,
120 TCG_REG_R7,
121 TCG_REG_R8,
122 TCG_REG_R9,
123 TCG_REG_R10
124 };
125
126 static const int tcg_target_call_oarg_regs[2] = {
127 TCG_REG_R3
128 };
129
130 static const int tcg_target_callee_save_regs[] = {
131 TCG_REG_R14,
132 TCG_REG_R15,
133 TCG_REG_R16,
134 TCG_REG_R17,
135 TCG_REG_R18,
136 TCG_REG_R19,
137 TCG_REG_R20,
138 TCG_REG_R21,
139 TCG_REG_R22,
140 TCG_REG_R23,
141 TCG_REG_R28,
142 TCG_REG_R29,
143 TCG_REG_R30,
144 TCG_REG_R31
145 };
146
147 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
148 {
149 tcg_target_long disp;
150
151 disp = target - (tcg_target_long) pc;
152 if ((disp << 38) >> 38 != disp)
153 tcg_abort ();
154
155 return disp & 0x3fffffc;
156 }
157
158 static void reloc_pc24 (void *pc, tcg_target_long target)
159 {
160 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
161 | reloc_pc24_val (pc, target);
162 }
163
164 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
165 {
166 tcg_target_long disp;
167
168 disp = target - (tcg_target_long) pc;
169 if (disp != (int16_t) disp)
170 tcg_abort ();
171
172 return disp & 0xfffc;
173 }
174
175 static void reloc_pc14 (void *pc, tcg_target_long target)
176 {
177 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
178 | reloc_pc14_val (pc, target);
179 }
180
181 static void patch_reloc (uint8_t *code_ptr, int type,
182 tcg_target_long value, tcg_target_long addend)
183 {
184 value += addend;
185 switch (type) {
186 case R_PPC_REL14:
187 reloc_pc14 (code_ptr, value);
188 break;
189 case R_PPC_REL24:
190 reloc_pc24 (code_ptr, value);
191 break;
192 default:
193 tcg_abort ();
194 }
195 }
196
197 /* maximum number of register used for input function arguments */
198 static int tcg_target_get_call_iarg_regs_count (int flags)
199 {
200 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
201 }
202
203 /* parse target specific constraints */
204 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
205 {
206 const char *ct_str;
207
208 ct_str = *pct_str;
209 switch (ct_str[0]) {
210 case 'A': case 'B': case 'C': case 'D':
211 ct->ct |= TCG_CT_REG;
212 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
213 break;
214 case 'r':
215 ct->ct |= TCG_CT_REG;
216 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
217 break;
218 case 'L': /* qemu_ld constraint */
219 ct->ct |= TCG_CT_REG;
220 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
221 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
222 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
223 break;
224 case 'S': /* qemu_st constraint */
225 ct->ct |= TCG_CT_REG;
226 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
227 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
228 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
229 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
230 break;
231 case 'Z':
232 ct->ct |= TCG_CT_CONST_U32;
233 break;
234 default:
235 return -1;
236 }
237 ct_str++;
238 *pct_str = ct_str;
239 return 0;
240 }
241
242 /* test if a constant matches the constraint */
243 static int tcg_target_const_match (tcg_target_long val,
244 const TCGArgConstraint *arg_ct)
245 {
246 int ct;
247
248 ct = arg_ct->ct;
249 if (ct & TCG_CT_CONST)
250 return 1;
251 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
252 return 1;
253 return 0;
254 }
255
256 #define OPCD(opc) ((opc)<<26)
257 #define XO19(opc) (OPCD(19)|((opc)<<1))
258 #define XO30(opc) (OPCD(30)|((opc)<<2))
259 #define XO31(opc) (OPCD(31)|((opc)<<1))
260 #define XO58(opc) (OPCD(58)|(opc))
261 #define XO62(opc) (OPCD(62)|(opc))
262
263 #define B OPCD( 18)
264 #define BC OPCD( 16)
265 #define LBZ OPCD( 34)
266 #define LHZ OPCD( 40)
267 #define LHA OPCD( 42)
268 #define LWZ OPCD( 32)
269 #define STB OPCD( 38)
270 #define STH OPCD( 44)
271 #define STW OPCD( 36)
272
273 #define STD XO62( 0)
274 #define STDU XO62( 1)
275 #define STDX XO31(149)
276
277 #define LD XO58( 0)
278 #define LDX XO31( 21)
279 #define LDU XO58( 1)
280 #define LWA XO58( 2)
281 #define LWAX XO31(341)
282
283 #define ADDI OPCD( 14)
284 #define ADDIS OPCD( 15)
285 #define ORI OPCD( 24)
286 #define ORIS OPCD( 25)
287 #define XORI OPCD( 26)
288 #define XORIS OPCD( 27)
289 #define ANDI OPCD( 28)
290 #define ANDIS OPCD( 29)
291 #define MULLI OPCD( 7)
292 #define CMPLI OPCD( 10)
293 #define CMPI OPCD( 11)
294
295 #define LWZU OPCD( 33)
296 #define STWU OPCD( 37)
297
298 #define RLWINM OPCD( 21)
299
300 #define RLDICL XO30( 0)
301 #define RLDICR XO30( 1)
302
303 #define BCLR XO19( 16)
304 #define BCCTR XO19(528)
305 #define CRAND XO19(257)
306 #define CRANDC XO19(129)
307 #define CRNAND XO19(225)
308 #define CROR XO19(449)
309
310 #define EXTSB XO31(954)
311 #define EXTSH XO31(922)
312 #define EXTSW XO31(986)
313 #define ADD XO31(266)
314 #define ADDE XO31(138)
315 #define ADDC XO31( 10)
316 #define AND XO31( 28)
317 #define SUBF XO31( 40)
318 #define SUBFC XO31( 8)
319 #define SUBFE XO31(136)
320 #define OR XO31(444)
321 #define XOR XO31(316)
322 #define MULLW XO31(235)
323 #define MULHWU XO31( 11)
324 #define DIVW XO31(491)
325 #define DIVWU XO31(459)
326 #define CMP XO31( 0)
327 #define CMPL XO31( 32)
328 #define LHBRX XO31(790)
329 #define LWBRX XO31(534)
330 #define STHBRX XO31(918)
331 #define STWBRX XO31(662)
332 #define MFSPR XO31(339)
333 #define MTSPR XO31(467)
334 #define SRAWI XO31(824)
335 #define NEG XO31(104)
336
337 #define MULLD XO31(233)
338 #define MULHD XO31( 73)
339 #define MULHDU XO31( 9)
340 #define DIVD XO31(489)
341 #define DIVDU XO31(457)
342
343 #define LBZX XO31( 87)
344 #define LHZX XO31(276)
345 #define LHAX XO31(343)
346 #define LWZX XO31( 23)
347 #define STBX XO31(215)
348 #define STHX XO31(407)
349 #define STWX XO31(151)
350
351 #define SPR(a,b) ((((a)<<5)|(b))<<11)
352 #define LR SPR(8, 0)
353 #define CTR SPR(9, 0)
354
355 #define SLW XO31( 24)
356 #define SRW XO31(536)
357 #define SRAW XO31(792)
358
359 #define SLD XO31( 27)
360 #define SRD XO31(539)
361 #define SRAD XO31(794)
362 #define SRADI XO31(413<<1)
363
364 #define LMW OPCD( 46)
365 #define STMW OPCD( 47)
366
367 #define TW XO31( 4)
368 #define TRAP (TW | TO (31))
369
370 #define RT(r) ((r)<<21)
371 #define RS(r) ((r)<<21)
372 #define RA(r) ((r)<<16)
373 #define RB(r) ((r)<<11)
374 #define TO(t) ((t)<<21)
375 #define SH(s) ((s)<<11)
376 #define MB(b) ((b)<<6)
377 #define ME(e) ((e)<<1)
378 #define BO(o) ((o)<<21)
379 #define MB64(b) ((b)<<5)
380
381 #define LK 1
382
383 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
384 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
385
386 #define BF(n) ((n)<<23)
387 #define BI(n, c) (((c)+((n)*4))<<16)
388 #define BT(n, c) (((c)+((n)*4))<<21)
389 #define BA(n, c) (((c)+((n)*4))<<16)
390 #define BB(n, c) (((c)+((n)*4))<<11)
391
392 #define BO_COND_TRUE BO (12)
393 #define BO_COND_FALSE BO ( 4)
394 #define BO_ALWAYS BO (20)
395
396 enum {
397 CR_LT,
398 CR_GT,
399 CR_EQ,
400 CR_SO
401 };
402
403 static const uint32_t tcg_to_bc[10] = {
404 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
405 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
406 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
407 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
408 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
409 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
410 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
411 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
412 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
413 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
414 };
415
416 static void tcg_out_mov (TCGContext *s, int ret, int arg)
417 {
418 tcg_out32 (s, OR | SAB (arg, ret, arg));
419 }
420
421 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
422 {
423 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
424 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
425 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
426 }
427
428 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
429 {
430 if (arg == (int16_t) arg)
431 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
432 else {
433 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
434 if (arg & 0xffff)
435 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
436 }
437 }
438
439 static void tcg_out_movi (TCGContext *s, TCGType type,
440 int ret, tcg_target_long arg)
441 {
442 int32_t arg32 = arg;
443
444 if (type == TCG_TYPE_I32 || arg == arg32) {
445 tcg_out_movi32 (s, ret, arg32);
446 }
447 else {
448 if ((uint64_t) arg >> 32) {
449 uint16_t h16 = arg >> 16;
450 uint16_t l16 = arg;
451
452 tcg_out_movi32 (s, ret, arg >> 32);
453 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
454 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
455 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
456 }
457 else {
458 tcg_out_movi32 (s, ret, arg32);
459 if (arg32 < 0)
460 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
461 }
462 }
463 }
464
465 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
466 {
467 int reg;
468
469 if (const_arg) {
470 reg = 2;
471 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
472 }
473 else reg = arg;
474
475 tcg_out32 (s, LD | RT (0) | RA (reg));
476 tcg_out32 (s, MTSPR | RA (0) | CTR);
477 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
478 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
479 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
480 }
481
482 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
483 int offset, int op1, int op2)
484 {
485 if (offset == (int16_t) offset)
486 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
487 else {
488 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
489 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
490 }
491 }
492
493 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
494 {
495 tcg_target_long disp;
496
497 disp = target - (tcg_target_long) s->code_ptr;
498 if ((disp << 38) >> 38 == disp)
499 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
500 else {
501 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
502 tcg_out32 (s, MTSPR | RS (0) | CTR);
503 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
504 }
505 }
506
507 #if defined (CONFIG_SOFTMMU)
508 extern void __ldb_mmu(void);
509 extern void __ldw_mmu(void);
510 extern void __ldl_mmu(void);
511 extern void __ldq_mmu(void);
512
513 extern void __stb_mmu(void);
514 extern void __stw_mmu(void);
515 extern void __stl_mmu(void);
516 extern void __stq_mmu(void);
517
518 static void *qemu_ld_helpers[4] = {
519 __ldb_mmu,
520 __ldw_mmu,
521 __ldl_mmu,
522 __ldq_mmu,
523 };
524
525 static void *qemu_st_helpers[4] = {
526 __stb_mmu,
527 __stw_mmu,
528 __stl_mmu,
529 __stq_mmu,
530 };
531 #endif
532
533 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
534 int addr_reg, int s_bits, int offset)
535 {
536 #if TARGET_LONG_BITS == 32
537 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
538
539 tcg_out32 (s, (RLWINM
540 | RA (r0)
541 | RS (addr_reg)
542 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
543 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
544 | ME (31 - CPU_TLB_ENTRY_BITS)
545 )
546 );
547 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
548 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
549 tcg_out32 (s, (RLWINM
550 | RA (r2)
551 | RS (addr_reg)
552 | SH (0)
553 | MB ((32 - s_bits) & 31)
554 | ME (31 - TARGET_PAGE_BITS)
555 )
556 );
557 #else
558 tcg_out_rld (s, RLDICL, r0, addr_reg,
559 64 - TARGET_PAGE_BITS,
560 64 - CPU_TLB_BITS);
561 tcg_out_rld (s, RLDICR, r0, r0,
562 CPU_TLB_ENTRY_BITS,
563 63 - CPU_TLB_ENTRY_BITS);
564
565 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
566 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
567
568 if (!s_bits) {
569 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
570 }
571 else {
572 tcg_out_rld (s, RLDICL, r2, addr_reg,
573 64 - TARGET_PAGE_BITS,
574 TARGET_PAGE_BITS - s_bits);
575 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
576 }
577 #endif
578 }
579
580 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
581 {
582 int addr_reg, data_reg, r0, mem_index, s_bits, bswap;
583 #ifdef CONFIG_SOFTMMU
584 int r1, r2;
585 void *label1_ptr, *label2_ptr;
586 #endif
587
588 data_reg = *args++;
589 addr_reg = *args++;
590 mem_index = *args;
591 s_bits = opc & 3;
592
593 #ifdef CONFIG_SOFTMMU
594 r0 = 3;
595 r1 = 4;
596 r2 = 0;
597
598 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
599 offsetof (CPUState, tlb_table[mem_index][0].addr_read));
600
601 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
602
603 label1_ptr = s->code_ptr;
604 #ifdef FAST_PATH
605 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
606 #endif
607
608 /* slow path */
609 tcg_out_mov (s, 3, addr_reg);
610 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
611
612 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
613
614 switch (opc) {
615 case 0|4:
616 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
617 break;
618 case 1|4:
619 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
620 break;
621 case 2|4:
622 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
623 break;
624 case 0:
625 case 1:
626 case 2:
627 case 3:
628 if (data_reg != 3)
629 tcg_out_mov (s, data_reg, 3);
630 break;
631 }
632 label2_ptr = s->code_ptr;
633 tcg_out32 (s, B);
634
635 /* label1: fast path */
636 #ifdef FAST_PATH
637 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
638 #endif
639
640 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
641 tcg_out32 (s, (LD_ADDEND
642 | RT (r0)
643 | RA (r0)
644 | (offsetof (CPUTLBEntry, addend)
645 - offsetof (CPUTLBEntry, addr_read))
646 ));
647 /* r0 = env->tlb_table[mem_index][index].addend */
648 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
649 /* r0 = env->tlb_table[mem_index][index].addend + addr */
650
651 #else /* !CONFIG_SOFTMMU */
652 r0 = addr_reg;
653 #endif
654
655 #ifdef TARGET_WORDS_BIGENDIAN
656 bswap = 0;
657 #else
658 bswap = 1;
659 #endif
660 switch (opc) {
661 default:
662 case 0:
663 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
664 break;
665 case 0|4:
666 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
667 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
668 break;
669 case 1:
670 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
671 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
672 break;
673 case 1|4:
674 if (bswap) {
675 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
676 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
677 }
678 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
679 break;
680 case 2:
681 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
682 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
683 break;
684 case 2|4:
685 if (bswap) {
686 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
687 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
688 }
689 else tcg_out32 (s, LWA | RT (data_reg)| RA (r0));
690 break;
691 case 3:
692 if (bswap) {
693 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
694 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
695 tcg_out32 (s, LWBRX | RT (r0) | RB (r0));
696 tcg_out_rld (s, RLDICR, r0, r0, 32, 31);
697 tcg_out32 (s, OR | SAB (r0, data_reg, data_reg));
698 }
699 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
700 break;
701 }
702
703 #ifdef CONFIG_SOFTMMU
704 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
705 #endif
706 }
707
708 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
709 {
710 int addr_reg, r0, r1, data_reg, mem_index, bswap;
711 #ifdef CONFIG_SOFTMMU
712 int r2;
713 void *label1_ptr, *label2_ptr;
714 #endif
715
716 data_reg = *args++;
717 addr_reg = *args++;
718 mem_index = *args;
719
720 #ifdef CONFIG_SOFTMMU
721 r0 = 3;
722 r1 = 4;
723 r2 = 0;
724
725 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
726 offsetof (CPUState, tlb_table[mem_index][0].addr_write));
727
728 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
729
730 label1_ptr = s->code_ptr;
731 #ifdef FAST_PATH
732 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
733 #endif
734
735 /* slow path */
736 tcg_out_mov (s, 3, addr_reg);
737 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
738 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
739
740 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
741
742 label2_ptr = s->code_ptr;
743 tcg_out32 (s, B);
744
745 /* label1: fast path */
746 #ifdef FAST_PATH
747 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
748 #endif
749
750 tcg_out32 (s, (LD_ADDEND
751 | RT (r0)
752 | RA (r0)
753 | (offsetof (CPUTLBEntry, addend)
754 - offsetof (CPUTLBEntry, addr_write))
755 ));
756 /* r0 = env->tlb_table[mem_index][index].addend */
757 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
758 /* r0 = env->tlb_table[mem_index][index].addend + addr */
759
760 #else /* !CONFIG_SOFTMMU */
761 r1 = 4;
762 r0 = addr_reg;
763 #endif
764
765 #ifdef TARGET_WORDS_BIGENDIAN
766 bswap = 0;
767 #else
768 bswap = 1;
769 #endif
770 switch (opc) {
771 case 0:
772 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
773 break;
774 case 1:
775 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
776 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
777 break;
778 case 2:
779 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
780 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
781 break;
782 case 3:
783 if (bswap) {
784 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
785 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
786 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
787 tcg_out32 (s, STWBRX | RS (0) | RA (0) | RB (r0));
788 }
789 else tcg_out32 (s, STD | RS (data_reg) | RA (r0));
790 break;
791 }
792
793 #ifdef CONFIG_SOFTMMU
794 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
795 #endif
796 }
797
798 void tcg_target_qemu_prologue (TCGContext *s)
799 {
800 int i, frame_size;
801 uint64_t addr;
802
803 frame_size = 0
804 + 8 /* back chain */
805 + 8 /* CR */
806 + 8 /* LR */
807 + 8 /* compiler doubleword */
808 + 8 /* link editor doubleword */
809 + 8 /* TOC save area */
810 + TCG_STATIC_CALL_ARGS_SIZE
811 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
812 ;
813 frame_size = (frame_size + 15) & ~15;
814
815 /* First emit adhoc function descriptor */
816 addr = (uint64_t) s->code_ptr + 24;
817 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
818 s->code_ptr += 16; /* skip TOC and environment pointer */
819
820 /* Prologue */
821 tcg_out32 (s, MFSPR | RT (0) | LR);
822 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
823 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
824 tcg_out32 (s, (STD
825 | RS (tcg_target_callee_save_regs[i])
826 | RA (1)
827 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
828 )
829 );
830 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
831
832 tcg_out32 (s, MTSPR | RS (3) | CTR);
833 tcg_out32 (s, BCCTR | BO_ALWAYS);
834
835 /* Epilogue */
836 tb_ret_addr = s->code_ptr;
837
838 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
839 tcg_out32 (s, (LD
840 | RT (tcg_target_callee_save_regs[i])
841 | RA (1)
842 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
843 )
844 );
845 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
846 tcg_out32 (s, MTSPR | RS (0) | LR);
847 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
848 tcg_out32 (s, BCLR | BO_ALWAYS);
849 }
850
851 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
852 tcg_target_long arg2)
853 {
854 if (type == TCG_TYPE_I32)
855 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
856 else
857 tcg_out_ldst (s, ret, arg1, arg2, LD, LDX);
858 }
859
860 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
861 tcg_target_long arg2)
862 {
863 if (type == TCG_TYPE_I32)
864 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
865 else
866 tcg_out_ldst (s, arg, arg1, arg2, STD, STDX);
867 }
868
869 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
870 {
871 if (!si && rt == ra)
872 return;
873
874 if (si == (int16_t) si)
875 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
876 else {
877 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
878 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
879 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
880 }
881 }
882
883 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
884 {
885 /* XXX: suboptimal */
886 if (si == (int16_t) si
887 || (((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0)
888 ppc_addi32 (s, rt, ra, si);
889 else {
890 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
891 tcg_out32 (s, ADD | RT (rt) | RA (ra));
892 }
893 }
894
895 static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
896 {
897 ppc_addi64 (s, reg, reg, val);
898 }
899
900 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
901 int const_arg2, int cr, int arch64)
902 {
903 int imm;
904 uint32_t op;
905
906 switch (cond) {
907 case TCG_COND_EQ:
908 case TCG_COND_NE:
909 if (const_arg2) {
910 if ((int16_t) arg2 == arg2) {
911 op = CMPI;
912 imm = 1;
913 break;
914 }
915 else if ((uint16_t) arg2 == arg2) {
916 op = CMPLI;
917 imm = 1;
918 break;
919 }
920 }
921 op = CMPL;
922 imm = 0;
923 break;
924
925 case TCG_COND_LT:
926 case TCG_COND_GE:
927 case TCG_COND_LE:
928 case TCG_COND_GT:
929 if (const_arg2) {
930 if ((int16_t) arg2 == arg2) {
931 op = CMPI;
932 imm = 1;
933 break;
934 }
935 }
936 op = CMP;
937 imm = 0;
938 break;
939
940 case TCG_COND_LTU:
941 case TCG_COND_GEU:
942 case TCG_COND_LEU:
943 case TCG_COND_GTU:
944 if (const_arg2) {
945 if ((uint16_t) arg2 == arg2) {
946 op = CMPLI;
947 imm = 1;
948 break;
949 }
950 }
951 op = CMPL;
952 imm = 0;
953 break;
954
955 default:
956 tcg_abort ();
957 }
958 op |= BF (cr) | (arch64 << 21);
959
960 if (imm)
961 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
962 else {
963 if (const_arg2) {
964 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
965 tcg_out32 (s, op | RA (arg1) | RB (0));
966 }
967 else
968 tcg_out32 (s, op | RA (arg1) | RB (arg2));
969 }
970
971 }
972
973 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
974 {
975 TCGLabel *l = &s->labels[label_index];
976
977 if (l->has_value)
978 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
979 else {
980 uint16_t val = *(uint16_t *) &s->code_ptr[2];
981
982 /* Thanks to Andrzej Zaborowski */
983 tcg_out32 (s, bc | (val & 0xfffc));
984 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
985 }
986 }
987
988 static void tcg_out_brcond (TCGContext *s, int cond,
989 TCGArg arg1, TCGArg arg2, int const_arg2,
990 int label_index, int arch64)
991 {
992 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
993 tcg_out_bc (s, tcg_to_bc[cond], label_index);
994 }
995
996 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
997 {
998 TCGContext s;
999 unsigned long patch_size;
1000
1001 s.code_ptr = (uint8_t *) jmp_addr;
1002 tcg_out_b (&s, 0, addr);
1003 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1004 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1005 }
1006
1007 static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
1008 const int *const_args)
1009 {
1010 int c;
1011
1012 switch (opc) {
1013 case INDEX_op_exit_tb:
1014 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1015 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1016 break;
1017 case INDEX_op_goto_tb:
1018 if (s->tb_jmp_offset) {
1019 /* direct jump method */
1020
1021 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1022 s->code_ptr += 28;
1023 }
1024 else {
1025 tcg_abort ();
1026 }
1027 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1028 break;
1029 case INDEX_op_br:
1030 {
1031 TCGLabel *l = &s->labels[args[0]];
1032
1033 if (l->has_value) {
1034 tcg_out_b (s, 0, l->u.value);
1035 }
1036 else {
1037 uint32_t val = *(uint32_t *) s->code_ptr;
1038
1039 /* Thanks to Andrzej Zaborowski */
1040 tcg_out32 (s, B | (val & 0x3fffffc));
1041 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1042 }
1043 }
1044 break;
1045 case INDEX_op_call:
1046 tcg_out_call (s, args[0], const_args[0]);
1047 break;
1048 case INDEX_op_jmp:
1049 if (const_args[0]) {
1050 tcg_out_b (s, 0, args[0]);
1051 }
1052 else {
1053 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1054 tcg_out32 (s, BCCTR | BO_ALWAYS);
1055 }
1056 break;
1057 case INDEX_op_movi_i32:
1058 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1059 break;
1060 case INDEX_op_movi_i64:
1061 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1062 break;
1063 case INDEX_op_ld8u_i32:
1064 case INDEX_op_ld8u_i64:
1065 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1066 break;
1067 case INDEX_op_ld8s_i32:
1068 case INDEX_op_ld8s_i64:
1069 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1070 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1071 break;
1072 case INDEX_op_ld16u_i32:
1073 case INDEX_op_ld16u_i64:
1074 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1075 break;
1076 case INDEX_op_ld16s_i32:
1077 case INDEX_op_ld16s_i64:
1078 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1079 break;
1080 case INDEX_op_ld_i32:
1081 case INDEX_op_ld32u_i64:
1082 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1083 break;
1084 case INDEX_op_ld32s_i64:
1085 tcg_out_ldst (s, args[0], args[1], args[2], LWA, LWAX);
1086 break;
1087 case INDEX_op_ld_i64:
1088 tcg_out_ldst (s, args[0], args[1], args[2], LD, LDX);
1089 break;
1090 case INDEX_op_st8_i32:
1091 case INDEX_op_st8_i64:
1092 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1093 break;
1094 case INDEX_op_st16_i32:
1095 case INDEX_op_st16_i64:
1096 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1097 break;
1098 case INDEX_op_st_i32:
1099 case INDEX_op_st32_i64:
1100 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1101 break;
1102 case INDEX_op_st_i64:
1103 tcg_out_ldst (s, args[0], args[1], args[2], STD, STDX);
1104 break;
1105
1106 case INDEX_op_add_i32:
1107 if (const_args[2])
1108 ppc_addi32 (s, args[0], args[1], args[2]);
1109 else
1110 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1111 break;
1112 case INDEX_op_sub_i32:
1113 if (const_args[2])
1114 ppc_addi32 (s, args[0], args[1], -args[2]);
1115 else
1116 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1117 break;
1118
1119 case INDEX_op_and_i64:
1120 case INDEX_op_and_i32:
1121 if (const_args[2]) {
1122 if ((args[2] & 0xffff) == args[2])
1123 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1124 else if ((args[2] & 0xffff0000) == args[2])
1125 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1126 | ((args[2] >> 16) & 0xffff));
1127 else {
1128 tcg_out_movi (s, (opc == INDEX_op_and_i32
1129 ? TCG_TYPE_I32
1130 : TCG_TYPE_I64),
1131 0, args[2]);
1132 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1133 }
1134 }
1135 else
1136 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1137 break;
1138 case INDEX_op_or_i64:
1139 case INDEX_op_or_i32:
1140 if (const_args[2]) {
1141 if (args[2] & 0xffff) {
1142 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1143 | (args[2] & 0xffff));
1144 if (args[2] >> 16)
1145 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1146 | ((args[2] >> 16) & 0xffff));
1147 }
1148 else {
1149 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1150 | ((args[2] >> 16) & 0xffff));
1151 }
1152 }
1153 else
1154 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1155 break;
1156 case INDEX_op_xor_i64:
1157 case INDEX_op_xor_i32:
1158 if (const_args[2]) {
1159 if ((args[2] & 0xffff) == args[2])
1160 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1161 | (args[2] & 0xffff));
1162 else if ((args[2] & 0xffff0000) == args[2])
1163 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1164 | ((args[2] >> 16) & 0xffff));
1165 else {
1166 tcg_out_movi (s, (opc == INDEX_op_and_i32
1167 ? TCG_TYPE_I32
1168 : TCG_TYPE_I64),
1169 0, args[2]);
1170 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1171 }
1172 }
1173 else
1174 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1175 break;
1176
1177 case INDEX_op_mul_i32:
1178 if (const_args[2]) {
1179 if (args[2] == (int16_t) args[2])
1180 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1181 | (args[2] & 0xffff));
1182 else {
1183 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1184 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1185 }
1186 }
1187 else
1188 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1189 break;
1190
1191 case INDEX_op_div_i32:
1192 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1193 break;
1194
1195 case INDEX_op_divu_i32:
1196 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1197 break;
1198
1199 case INDEX_op_rem_i32:
1200 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1201 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1202 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1203 break;
1204
1205 case INDEX_op_remu_i32:
1206 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1207 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1208 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1209 break;
1210
1211 case INDEX_op_shl_i32:
1212 if (const_args[2]) {
1213 tcg_out32 (s, (RLWINM
1214 | RA (args[0])
1215 | RS (args[1])
1216 | SH (args[2])
1217 | MB (0)
1218 | ME (31 - args[2])
1219 )
1220 );
1221 }
1222 else
1223 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1224 break;
1225 case INDEX_op_shr_i32:
1226 if (const_args[2]) {
1227 tcg_out32 (s, (RLWINM
1228 | RA (args[0])
1229 | RS (args[1])
1230 | SH (32 - args[2])
1231 | MB (args[2])
1232 | ME (31)
1233 )
1234 );
1235 }
1236 else
1237 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1238 break;
1239 case INDEX_op_sar_i32:
1240 if (const_args[2])
1241 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1242 else
1243 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1244 break;
1245
1246 case INDEX_op_brcond_i32:
1247 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1248 break;
1249
1250 case INDEX_op_brcond_i64:
1251 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1252 break;
1253
1254 case INDEX_op_neg_i32:
1255 case INDEX_op_neg_i64:
1256 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1257 break;
1258
1259 case INDEX_op_add_i64:
1260 if (const_args[2])
1261 ppc_addi64 (s, args[0], args[1], args[2]);
1262 else
1263 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1264 break;
1265 case INDEX_op_sub_i64:
1266 if (const_args[2])
1267 ppc_addi64 (s, args[0], args[1], -args[2]);
1268 else
1269 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1270 break;
1271
1272 case INDEX_op_shl_i64:
1273 if (const_args[2])
1274 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1275 else
1276 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1277 break;
1278 case INDEX_op_shr_i64:
1279 if (const_args[2])
1280 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1281 else
1282 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1283 break;
1284 case INDEX_op_sar_i64:
1285 if (const_args[2]) {
1286 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1287 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1288 }
1289 else
1290 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1291 break;
1292
1293 case INDEX_op_mul_i64:
1294 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1295 break;
1296 case INDEX_op_div_i64:
1297 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1298 break;
1299 case INDEX_op_divu_i64:
1300 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1301 break;
1302 case INDEX_op_rem_i64:
1303 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1304 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1305 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1306 break;
1307 case INDEX_op_remu_i64:
1308 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1309 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1310 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1311 break;
1312
1313 case INDEX_op_qemu_ld8u:
1314 tcg_out_qemu_ld (s, args, 0);
1315 break;
1316 case INDEX_op_qemu_ld8s:
1317 tcg_out_qemu_ld (s, args, 0 | 4);
1318 break;
1319 case INDEX_op_qemu_ld16u:
1320 tcg_out_qemu_ld (s, args, 1);
1321 break;
1322 case INDEX_op_qemu_ld16s:
1323 tcg_out_qemu_ld (s, args, 1 | 4);
1324 break;
1325 case INDEX_op_qemu_ld32u:
1326 tcg_out_qemu_ld (s, args, 2);
1327 break;
1328 case INDEX_op_qemu_ld32s:
1329 tcg_out_qemu_ld (s, args, 2 | 4);
1330 break;
1331 case INDEX_op_qemu_ld64:
1332 tcg_out_qemu_ld (s, args, 3);
1333 break;
1334 case INDEX_op_qemu_st8:
1335 tcg_out_qemu_st (s, args, 0);
1336 break;
1337 case INDEX_op_qemu_st16:
1338 tcg_out_qemu_st (s, args, 1);
1339 break;
1340 case INDEX_op_qemu_st32:
1341 tcg_out_qemu_st (s, args, 2);
1342 break;
1343 case INDEX_op_qemu_st64:
1344 tcg_out_qemu_st (s, args, 3);
1345 break;
1346
1347 case INDEX_op_ext8s_i32:
1348 case INDEX_op_ext8s_i64:
1349 c = EXTSB;
1350 goto gen_ext;
1351 case INDEX_op_ext16s_i32:
1352 case INDEX_op_ext16s_i64:
1353 c = EXTSH;
1354 goto gen_ext;
1355 case INDEX_op_ext32s_i64:
1356 c = EXTSW;
1357 goto gen_ext;
1358 gen_ext:
1359 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1360 break;
1361
1362 default:
1363 tcg_dump_ops (s, stderr);
1364 tcg_abort ();
1365 }
1366 }
1367
1368 static const TCGTargetOpDef ppc_op_defs[] = {
1369 { INDEX_op_exit_tb, { } },
1370 { INDEX_op_goto_tb, { } },
1371 { INDEX_op_call, { "ri" } },
1372 { INDEX_op_jmp, { "ri" } },
1373 { INDEX_op_br, { } },
1374
1375 { INDEX_op_mov_i32, { "r", "r" } },
1376 { INDEX_op_mov_i64, { "r", "r" } },
1377 { INDEX_op_movi_i32, { "r" } },
1378 { INDEX_op_movi_i64, { "r" } },
1379
1380 { INDEX_op_ld8u_i32, { "r", "r" } },
1381 { INDEX_op_ld8s_i32, { "r", "r" } },
1382 { INDEX_op_ld16u_i32, { "r", "r" } },
1383 { INDEX_op_ld16s_i32, { "r", "r" } },
1384 { INDEX_op_ld_i32, { "r", "r" } },
1385 { INDEX_op_ld_i64, { "r", "r" } },
1386 { INDEX_op_st8_i32, { "r", "r" } },
1387 { INDEX_op_st8_i64, { "r", "r" } },
1388 { INDEX_op_st16_i32, { "r", "r" } },
1389 { INDEX_op_st16_i64, { "r", "r" } },
1390 { INDEX_op_st_i32, { "r", "r" } },
1391 { INDEX_op_st_i64, { "r", "r" } },
1392 { INDEX_op_st32_i64, { "r", "r" } },
1393
1394 { INDEX_op_ld8u_i64, { "r", "r" } },
1395 { INDEX_op_ld8s_i64, { "r", "r" } },
1396 { INDEX_op_ld16u_i64, { "r", "r" } },
1397 { INDEX_op_ld16s_i64, { "r", "r" } },
1398 { INDEX_op_ld32u_i64, { "r", "r" } },
1399 { INDEX_op_ld32s_i64, { "r", "r" } },
1400 { INDEX_op_ld_i64, { "r", "r" } },
1401
1402 { INDEX_op_add_i32, { "r", "r", "ri" } },
1403 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1404 { INDEX_op_div_i32, { "r", "r", "r" } },
1405 { INDEX_op_divu_i32, { "r", "r", "r" } },
1406 { INDEX_op_rem_i32, { "r", "r", "r" } },
1407 { INDEX_op_remu_i32, { "r", "r", "r" } },
1408 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1409 { INDEX_op_and_i32, { "r", "r", "ri" } },
1410 { INDEX_op_or_i32, { "r", "r", "ri" } },
1411 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1412
1413 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1414 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1415 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1416
1417 { INDEX_op_brcond_i32, { "r", "ri" } },
1418 { INDEX_op_brcond_i64, { "r", "ri" } },
1419
1420 { INDEX_op_neg_i32, { "r", "r" } },
1421
1422 { INDEX_op_add_i64, { "r", "r", "ri" } },
1423 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1424 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1425 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1426 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1427
1428 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1429 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1430 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1431
1432 { INDEX_op_mul_i64, { "r", "r", "r" } },
1433 { INDEX_op_div_i64, { "r", "r", "r" } },
1434 { INDEX_op_divu_i64, { "r", "r", "r" } },
1435 { INDEX_op_rem_i64, { "r", "r", "r" } },
1436 { INDEX_op_remu_i64, { "r", "r", "r" } },
1437
1438 { INDEX_op_neg_i64, { "r", "r" } },
1439
1440 { INDEX_op_qemu_ld8u, { "r", "L" } },
1441 { INDEX_op_qemu_ld8s, { "r", "L" } },
1442 { INDEX_op_qemu_ld16u, { "r", "L" } },
1443 { INDEX_op_qemu_ld16s, { "r", "L" } },
1444 { INDEX_op_qemu_ld32u, { "r", "L" } },
1445 { INDEX_op_qemu_ld32s, { "r", "L" } },
1446 { INDEX_op_qemu_ld64, { "r", "L" } },
1447
1448 { INDEX_op_qemu_st8, { "S", "S" } },
1449 { INDEX_op_qemu_st16, { "S", "S" } },
1450 { INDEX_op_qemu_st32, { "S", "S" } },
1451 { INDEX_op_qemu_st64, { "S", "S", "S" } },
1452
1453 { INDEX_op_ext8s_i32, { "r", "r" } },
1454 { INDEX_op_ext16s_i32, { "r", "r" } },
1455 { INDEX_op_ext8s_i64, { "r", "r" } },
1456 { INDEX_op_ext16s_i64, { "r", "r" } },
1457 { INDEX_op_ext32s_i64, { "r", "r" } },
1458
1459 { -1 },
1460 };
1461
1462 void tcg_target_init (TCGContext *s)
1463 {
1464 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1465 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1466 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1467 (1 << TCG_REG_R0) |
1468 (1 << TCG_REG_R3) |
1469 (1 << TCG_REG_R4) |
1470 (1 << TCG_REG_R5) |
1471 (1 << TCG_REG_R6) |
1472 (1 << TCG_REG_R7) |
1473 (1 << TCG_REG_R8) |
1474 (1 << TCG_REG_R9) |
1475 (1 << TCG_REG_R10) |
1476 (1 << TCG_REG_R11) |
1477 (1 << TCG_REG_R12)
1478 );
1479
1480 tcg_regset_clear (s->reserved_regs);
1481 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1482 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1483 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1484 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1485
1486 tcg_add_target_add_op_defs (ppc_op_defs);
1487 }
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