2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static uint8_t *tb_ret_addr
;
29 #if TARGET_PHYS_ADDR_BITS == 32
35 #if TARGET_LONG_BITS == 32
43 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
78 static const int tcg_target_reg_alloc_order
[] = {
113 static const int tcg_target_call_iarg_regs
[] = {
124 static const int tcg_target_call_oarg_regs
[2] = {
128 static const int tcg_target_callee_save_regs
[] = {
145 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
147 tcg_target_long disp
;
149 disp
= target
- (tcg_target_long
) pc
;
150 if ((disp
<< 38) >> 38 != disp
)
153 return disp
& 0x3fffffc;
156 static void reloc_pc24 (void *pc
, tcg_target_long target
)
158 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
159 | reloc_pc24_val (pc
, target
);
162 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
164 tcg_target_long disp
;
166 disp
= target
- (tcg_target_long
) pc
;
167 if (disp
!= (int16_t) disp
)
170 return disp
& 0xfffc;
173 static void reloc_pc14 (void *pc
, tcg_target_long target
)
175 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
176 | reloc_pc14_val (pc
, target
);
179 static void patch_reloc (uint8_t *code_ptr
, int type
,
180 tcg_target_long value
, tcg_target_long addend
)
185 reloc_pc14 (code_ptr
, value
);
188 reloc_pc24 (code_ptr
, value
);
195 /* maximum number of register used for input function arguments */
196 static int tcg_target_get_call_iarg_regs_count (int flags
)
198 return sizeof (tcg_target_call_iarg_regs
) / sizeof (tcg_target_call_iarg_regs
[0]);
201 /* parse target specific constraints */
202 static int target_parse_constraint (TCGArgConstraint
*ct
, const char **pct_str
)
208 case 'A': case 'B': case 'C': case 'D':
209 ct
->ct
|= TCG_CT_REG
;
210 tcg_regset_set_reg (ct
->u
.regs
, 3 + ct_str
[0] - 'A');
213 ct
->ct
|= TCG_CT_REG
;
214 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
216 case 'L': /* qemu_ld constraint */
217 ct
->ct
|= TCG_CT_REG
;
218 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
219 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R3
);
220 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R4
);
222 case 'S': /* qemu_st constraint */
223 ct
->ct
|= TCG_CT_REG
;
224 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
225 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R3
);
226 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R4
);
227 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R5
);
237 /* test if a constant matches the constraint */
238 static int tcg_target_const_match (tcg_target_long val
,
239 const TCGArgConstraint
*arg_ct
)
244 if (ct
& TCG_CT_CONST
)
249 #define OPCD(opc) ((opc)<<26)
250 #define XO19(opc) (OPCD(19)|((opc)<<1))
251 #define XO30(opc) (OPCD(30)|((opc)<<2))
252 #define XO31(opc) (OPCD(31)|((opc)<<1))
253 #define XO58(opc) (OPCD(58)|(opc))
254 #define XO62(opc) (OPCD(62)|(opc))
258 #define LBZ OPCD( 34)
259 #define LHZ OPCD( 40)
260 #define LHA OPCD( 42)
261 #define LWZ OPCD( 32)
262 #define STB OPCD( 38)
263 #define STH OPCD( 44)
264 #define STW OPCD( 36)
267 #define STDU XO62( 1)
268 #define STDX XO31(149)
271 #define LDX XO31( 21)
274 #define LWAX XO31(341)
276 #define ADDI OPCD( 14)
277 #define ADDIS OPCD( 15)
278 #define ORI OPCD( 24)
279 #define ORIS OPCD( 25)
280 #define XORI OPCD( 26)
281 #define XORIS OPCD( 27)
282 #define ANDI OPCD( 28)
283 #define ANDIS OPCD( 29)
284 #define MULLI OPCD( 7)
285 #define CMPLI OPCD( 10)
286 #define CMPI OPCD( 11)
288 #define LWZU OPCD( 33)
289 #define STWU OPCD( 37)
291 #define RLWINM OPCD( 21)
293 #define RLDICL XO30( 0)
294 #define RLDICR XO30( 1)
296 #define BCLR XO19( 16)
297 #define BCCTR XO19(528)
298 #define CRAND XO19(257)
299 #define CRANDC XO19(129)
300 #define CRNAND XO19(225)
301 #define CROR XO19(449)
303 #define EXTSB XO31(954)
304 #define EXTSH XO31(922)
305 #define EXTSW XO31(986)
306 #define ADD XO31(266)
307 #define ADDE XO31(138)
308 #define ADDC XO31( 10)
309 #define AND XO31( 28)
310 #define SUBF XO31( 40)
311 #define SUBFC XO31( 8)
312 #define SUBFE XO31(136)
314 #define XOR XO31(316)
315 #define MULLW XO31(235)
316 #define MULHWU XO31( 11)
317 #define DIVW XO31(491)
318 #define DIVWU XO31(459)
320 #define CMPL XO31( 32)
321 #define LHBRX XO31(790)
322 #define LWBRX XO31(534)
323 #define STHBRX XO31(918)
324 #define STWBRX XO31(662)
325 #define MFSPR XO31(339)
326 #define MTSPR XO31(467)
327 #define SRAWI XO31(824)
328 #define NEG XO31(104)
330 #define MULLD XO31(233)
331 #define MULHD XO31( 73)
332 #define MULHDU XO31( 9)
333 #define DIVD XO31(489)
334 #define DIVDU XO31(457)
336 #define LBZX XO31( 87)
337 #define LHZX XO31(276)
338 #define LHAX XO31(343)
339 #define LWZX XO31( 23)
340 #define STBX XO31(215)
341 #define STHX XO31(407)
342 #define STWX XO31(151)
344 #define SPR(a,b) ((((a)<<5)|(b))<<11)
346 #define CTR SPR(9, 0)
348 #define SLW XO31( 24)
349 #define SRW XO31(536)
350 #define SRAW XO31(792)
352 #define SLD XO31( 27)
353 #define SRD XO31(539)
354 #define SRAD XO31(794)
356 #define LMW OPCD( 46)
357 #define STMW OPCD( 47)
360 #define TRAP (TW | TO (31))
362 #define RT(r) ((r)<<21)
363 #define RS(r) ((r)<<21)
364 #define RA(r) ((r)<<16)
365 #define RB(r) ((r)<<11)
366 #define TO(t) ((t)<<21)
367 #define SH(s) ((s)<<11)
368 #define MB(b) ((b)<<6)
369 #define ME(e) ((e)<<1)
370 #define BO(o) ((o)<<21)
371 #define MB64(b) ((b)<<5)
375 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
376 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
378 #define BF(n) ((n)<<23)
379 #define BI(n, c) (((c)+((n)*4))<<16)
380 #define BT(n, c) (((c)+((n)*4))<<21)
381 #define BA(n, c) (((c)+((n)*4))<<16)
382 #define BB(n, c) (((c)+((n)*4))<<11)
384 #define BO_COND_TRUE BO (12)
385 #define BO_COND_FALSE BO ( 4)
386 #define BO_ALWAYS BO (20)
395 static const uint32_t tcg_to_bc
[10] = {
396 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
397 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
398 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
399 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
400 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
401 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
402 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
403 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
404 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
405 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
408 static void tcg_out_mov (TCGContext
*s
, int ret
, int arg
)
410 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
413 static void tcg_out_rld (TCGContext
*s
, int op
, int ra
, int rs
, int sh
, int mb
)
415 sh
= SH (sh
& 0x1f) | (((sh
>> 5) & 1) << 1);
416 mb
= MB64 ((mb
>> 5) | ((mb
<< 1) & 0x3f));
417 tcg_out32 (s
, op
| RA (ra
) | RS (rs
) | sh
| mb
);
420 static void tcg_out_movi32 (TCGContext
*s
, int ret
, int32_t arg
)
422 if (arg
== (int16_t) arg
)
423 tcg_out32 (s
, ADDI
| RT (ret
) | RA (0) | (arg
& 0xffff));
425 tcg_out32 (s
, ADDIS
| RT (ret
) | RA (0) | ((arg
>> 16) & 0xffff));
427 tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | (arg
& 0xffff));
431 static void tcg_out_movi (TCGContext
*s
, TCGType type
,
432 int ret
, tcg_target_long arg
)
436 if (type
== TCG_TYPE_I32
|| arg
== arg32
) {
437 tcg_out_movi32 (s
, ret
, arg32
);
440 if ((uint64_t) arg
>> 32) {
441 uint16_t h16
= arg
>> 16;
444 tcg_out_movi32 (s
, ret
, arg
>> 32);
445 tcg_out_rld (s
, RLDICR
, ret
, ret
, 32, 31);
446 if (h16
) tcg_out32 (s
, ORIS
| RS (ret
) | RA (ret
) | h16
);
447 if (l16
) tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | l16
);
450 tcg_out_movi32 (s
, ret
, arg32
);
452 tcg_out_rld (s
, RLDICL
, ret
, ret
, 0, 32);
457 static void tcg_out_call (TCGContext
*s
, tcg_target_long arg
, int const_arg
)
463 tcg_out_movi (s
, TCG_TYPE_I64
, reg
, arg
);
467 tcg_out32 (s
, LD
| RT (0) | RA (reg
));
468 tcg_out32 (s
, MTSPR
| RA (0) | CTR
);
469 tcg_out32 (s
, LD
| RT (11) | RA (reg
) | 16);
470 tcg_out32 (s
, LD
| RT (2) | RA (reg
) | 8);
471 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| LK
);
474 static void tcg_out_ldst (TCGContext
*s
, int ret
, int addr
,
475 int offset
, int op1
, int op2
)
477 if (offset
== (int16_t) offset
)
478 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
480 tcg_out_movi (s
, TCG_TYPE_I64
, 0, offset
);
481 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
485 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
487 tcg_target_long disp
;
489 disp
= target
- (tcg_target_long
) s
->code_ptr
;
490 if ((disp
<< 38) >> 38 == disp
)
491 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
493 tcg_out_movi (s
, TCG_TYPE_I64
, 0, (tcg_target_long
) target
);
494 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
495 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
499 #if defined (CONFIG_SOFTMMU)
500 extern void __ldb_mmu(void);
501 extern void __ldw_mmu(void);
502 extern void __ldl_mmu(void);
503 extern void __ldq_mmu(void);
505 extern void __stb_mmu(void);
506 extern void __stw_mmu(void);
507 extern void __stl_mmu(void);
508 extern void __stq_mmu(void);
510 static void *qemu_ld_helpers
[4] = {
517 static void *qemu_st_helpers
[4] = {
525 static void tcg_out_tlb_read (TCGContext
*s
, int r0
, int r1
, int r2
,
526 int addr_reg
, int s_bits
, int offset
)
528 #if TARGET_LONG_BITS == 32
529 tcg_out_rld (s
, RLDICL
, addr_reg
, addr_reg
, 0, 32);
531 tcg_out32 (s
, (RLWINM
534 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
535 | MB (32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
))
536 | ME (31 - CPU_TLB_ENTRY_BITS
)
539 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
540 tcg_out32 (s
, (LWZU
| RT (r1
) | RA (r0
) | offset
));
541 tcg_out32 (s
, (RLWINM
545 | MB ((32 - s_bits
) & 31)
546 | ME (31 - TARGET_PAGE_BITS
)
550 tcg_out_rld (s
, RLDICL
, r0
, addr_reg
,
551 64 - TARGET_PAGE_BITS
,
553 tcg_out_rld (s
, RLDICR
, r0
, r0
,
555 63 - CPU_TLB_ENTRY_BITS
);
557 tcg_out32 (s
, ADD
| TAB (r0
, r0
, TCG_AREG0
));
558 tcg_out32 (s
, LD_ADDR
| RT (r1
) | RA (r0
) | offset
);
561 tcg_out_rld (s
, RLDICR
, r2
, addr_reg
, 0, 63 - TARGET_PAGE_BITS
);
564 tcg_out_rld (s
, RLDICL
, r2
, addr_reg
,
565 64 - TARGET_PAGE_BITS
,
566 TARGET_PAGE_BITS
- s_bits
);
567 tcg_out_rld (s
, RLDICL
, r2
, r2
, TARGET_PAGE_BITS
, 0);
572 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
574 int addr_reg
, data_reg
, r0
, mem_index
, s_bits
, bswap
;
575 #ifdef CONFIG_SOFTMMU
577 void *label1_ptr
, *label2_ptr
;
585 #ifdef CONFIG_SOFTMMU
590 tcg_out_tlb_read (s
, r0
, r1
, r2
, addr_reg
, s_bits
,
591 offsetof (CPUState
, tlb_table
[mem_index
][0].addr_read
));
593 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
) | CMP_L
);
595 label1_ptr
= s
->code_ptr
;
597 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
601 tcg_out_mov (s
, 3, addr_reg
);
602 tcg_out_movi (s
, TCG_TYPE_I64
, 4, mem_index
);
604 tcg_out_call (s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
], 1);
608 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (3));
611 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (3));
614 tcg_out32 (s
, EXTSW
| RA (data_reg
) | RS (3));
621 tcg_out_mov (s
, data_reg
, 3);
624 label2_ptr
= s
->code_ptr
;
627 /* label1: fast path */
629 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
632 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
633 tcg_out32 (s
, (LD_ADDEND
636 | (offsetof (CPUTLBEntry
, addend
)
637 - offsetof (CPUTLBEntry
, addr_read
))
639 /* r0 = env->tlb_table[mem_index][index].addend */
640 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
641 /* r0 = env->tlb_table[mem_index][index].addend + addr */
643 #else /* !CONFIG_SOFTMMU */
647 #ifdef TARGET_WORDS_BIGENDIAN
655 tcg_out32 (s
, LBZ
| RT (data_reg
) | RA (r0
));
658 tcg_out32 (s
, LBZ
| RT (data_reg
) | RA (r0
));
659 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (data_reg
));
662 if (bswap
) tcg_out32 (s
, LHBRX
| RT (data_reg
) | RB (r0
));
663 else tcg_out32 (s
, LHZ
| RT (data_reg
) | RA (r0
));
667 tcg_out32 (s
, LHBRX
| RT (data_reg
) | RB (r0
));
668 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (data_reg
));
670 else tcg_out32 (s
, LHA
| RT (data_reg
) | RA (r0
));
673 if (bswap
) tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
674 else tcg_out32 (s
, LWZ
| RT (data_reg
)| RA (r0
));
678 tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
679 tcg_out32 (s
, EXTSW
| RA (data_reg
) | RS (data_reg
));
681 else tcg_out32 (s
, LWA
| RT (data_reg
)| RA (r0
));
685 tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
686 tcg_out32 (s
, ADDI
| RT (r0
) | RA (r0
) | 4);
687 tcg_out32 (s
, LWBRX
| RT (r0
) | RB (r0
));
688 tcg_out_rld (s
, RLDICR
, r0
, r0
, 32, 31);
689 tcg_out32 (s
, OR
| SAB (r0
, data_reg
, data_reg
));
691 else tcg_out32 (s
, LD
| RT (data_reg
) | RA (r0
));
695 #ifdef CONFIG_SOFTMMU
696 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
700 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
702 int addr_reg
, r0
, r1
, data_reg
, mem_index
, bswap
;
703 #ifdef CONFIG_SOFTMMU
705 void *label1_ptr
, *label2_ptr
;
712 #ifdef CONFIG_SOFTMMU
717 tcg_out_tlb_read (s
, r0
, r1
, r2
, addr_reg
, opc
,
718 offsetof (CPUState
, tlb_table
[mem_index
][0].addr_write
));
720 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
) | CMP_L
);
722 label1_ptr
= s
->code_ptr
;
724 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
728 tcg_out_mov (s
, 3, addr_reg
);
729 tcg_out_rld (s
, RLDICL
, 4, data_reg
, 0, 64 - (1 << (3 + opc
)));
730 tcg_out_movi (s
, TCG_TYPE_I64
, 5, mem_index
);
732 tcg_out_call (s
, (tcg_target_long
) qemu_st_helpers
[opc
], 1);
734 label2_ptr
= s
->code_ptr
;
737 /* label1: fast path */
739 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
742 tcg_out32 (s
, (LD_ADDEND
745 | (offsetof (CPUTLBEntry
, addend
)
746 - offsetof (CPUTLBEntry
, addr_write
))
748 /* r0 = env->tlb_table[mem_index][index].addend */
749 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
750 /* r0 = env->tlb_table[mem_index][index].addend + addr */
752 #else /* !CONFIG_SOFTMMU */
757 #ifdef TARGET_WORDS_BIGENDIAN
764 tcg_out32 (s
, STB
| RS (data_reg
) | RA (r0
));
767 if (bswap
) tcg_out32 (s
, STHBRX
| RS (data_reg
) | RA (0) | RB (r0
));
768 else tcg_out32 (s
, STH
| RS (data_reg
) | RA (r0
));
771 if (bswap
) tcg_out32 (s
, STWBRX
| RS (data_reg
) | RA (0) | RB (r0
));
772 else tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
));
776 tcg_out32 (s
, STWBRX
| RS (data_reg
) | RA (0) | RB (r0
));
777 tcg_out32 (s
, ADDI
| RT (r0
) | RA (r0
) | 4);
778 tcg_out_rld (s
, RLDICL
, 0, data_reg
, 32, 0);
779 tcg_out32 (s
, STWBRX
| RS (0) | RA (0) | RB (r0
));
781 else tcg_out32 (s
, STD
| RS (data_reg
) | RA (r0
));
785 #ifdef CONFIG_SOFTMMU
786 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
790 void tcg_target_qemu_prologue (TCGContext
*s
)
799 + 8 /* compiler doubleword */
800 + 8 /* link editor doubleword */
801 + 8 /* TOC save area */
802 + TCG_STATIC_CALL_ARGS_SIZE
803 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 8
805 frame_size
= (frame_size
+ 15) & ~15;
807 /* First emit adhoc function descriptor */
808 addr
= (uint64_t) s
->code_ptr
+ 24;
809 tcg_out32 (s
, addr
>> 32); tcg_out32 (s
, addr
); /* entry point */
810 s
->code_ptr
+= 16; /* skip TOC and environment pointer */
813 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
814 tcg_out32 (s
, STDU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
815 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
817 | RS (tcg_target_callee_save_regs
[i
])
819 | (i
* 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE
)
822 tcg_out32 (s
, STD
| RS (0) | RA (1) | (frame_size
+ 16));
824 tcg_out32 (s
, MTSPR
| RS (3) | CTR
);
825 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
828 tb_ret_addr
= s
->code_ptr
;
830 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
832 | RT (tcg_target_callee_save_regs
[i
])
834 | (i
* 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE
)
837 tcg_out32 (s
, LD
| RT (0) | RA (1) | (frame_size
+ 16));
838 tcg_out32 (s
, MTSPR
| RS (0) | LR
);
839 tcg_out32 (s
, ADDI
| RT (1) | RA (1) | frame_size
);
840 tcg_out32 (s
, BCLR
| BO_ALWAYS
);
843 static void tcg_out_ld (TCGContext
*s
, TCGType type
, int ret
, int arg1
,
844 tcg_target_long arg2
)
846 if (type
== TCG_TYPE_I32
)
847 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
849 tcg_out_ldst (s
, ret
, arg1
, arg2
, LD
, LDX
);
852 static void tcg_out_st (TCGContext
*s
, TCGType type
, int arg
, int arg1
,
853 tcg_target_long arg2
)
855 if (type
== TCG_TYPE_I32
)
856 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
858 tcg_out_ldst (s
, arg
, arg1
, arg2
, STD
, STDX
);
861 static void ppc_addi32 (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
866 if (si
== (int16_t) si
)
867 tcg_out32 (s
, ADDI
| RT (rt
) | RA (ra
) | (si
& 0xffff));
869 uint16_t h
= ((si
>> 16) & 0xffff) + ((uint16_t) si
>> 15);
870 tcg_out32 (s
, ADDIS
| RT (rt
) | RA (ra
) | h
);
871 tcg_out32 (s
, ADDI
| RT (rt
) | RA (rt
) | (si
& 0xffff));
875 static void ppc_addi64 (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
877 tcg_out_movi (s
, TCG_TYPE_I64
, 0, si
);
878 tcg_out32 (s
, ADD
| RT (rt
) | RA (ra
));
881 static void tcg_out_addi (TCGContext
*s
, int reg
, tcg_target_long val
)
883 ppc_addi64 (s
, reg
, reg
, val
);
886 static void tcg_out_cmp (TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
887 int const_arg2
, int cr
, int arch64
)
896 if ((int16_t) arg2
== arg2
) {
901 else if ((uint16_t) arg2
== arg2
) {
916 if ((int16_t) arg2
== arg2
) {
931 if ((uint16_t) arg2
== arg2
) {
944 op
|= BF (cr
) | (arch64
<< 21);
947 tcg_out32 (s
, op
| RA (arg1
) | (arg2
& 0xffff));
950 tcg_out_movi (s
, TCG_TYPE_I64
, 0, arg2
);
951 tcg_out32 (s
, op
| RA (arg1
) | RB (0));
954 tcg_out32 (s
, op
| RA (arg1
) | RB (arg2
));
959 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
961 TCGLabel
*l
= &s
->labels
[label_index
];
964 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
966 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
968 /* Thanks to Andrzej Zaborowski */
969 tcg_out32 (s
, bc
| (val
& 0xfffc));
970 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
974 static void tcg_out_brcond (TCGContext
*s
, int cond
,
975 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
976 int label_index
, int arch64
)
978 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7, arch64
);
979 tcg_out_bc (s
, tcg_to_bc
[cond
], label_index
);
982 void ppc_tb_set_jmp_target (unsigned long jmp_addr
, unsigned long addr
)
985 unsigned long patch_size
;
987 s
.code_ptr
= (uint8_t *) jmp_addr
;
988 tcg_out_b (&s
, 0, addr
);
989 patch_size
= s
.code_ptr
- (uint8_t *) jmp_addr
;
990 flush_icache_range (jmp_addr
, jmp_addr
+ patch_size
);
993 static void tcg_out_op (TCGContext
*s
, int opc
, const TCGArg
*args
,
994 const int *const_args
)
999 case INDEX_op_exit_tb
:
1000 tcg_out_movi (s
, TCG_TYPE_I64
, TCG_REG_R3
, args
[0]);
1001 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1003 case INDEX_op_goto_tb
:
1004 if (s
->tb_jmp_offset
) {
1005 /* direct jump method */
1007 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1013 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1017 TCGLabel
*l
= &s
->labels
[args
[0]];
1020 tcg_out_b (s
, 0, l
->u
.value
);
1023 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1025 /* Thanks to Andrzej Zaborowski */
1026 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1027 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1032 tcg_out_call (s
, args
[0], const_args
[0]);
1035 if (const_args
[0]) {
1036 tcg_out_b (s
, 0, args
[0]);
1039 tcg_out32 (s
, MTSPR
| RS (args
[0]) | CTR
);
1040 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1043 case INDEX_op_movi_i32
:
1044 tcg_out_movi (s
, TCG_TYPE_I32
, args
[0], args
[1]);
1046 case INDEX_op_movi_i64
:
1047 tcg_out_movi (s
, TCG_TYPE_I64
, args
[0], args
[1]);
1049 case INDEX_op_ld8u_i32
:
1050 case INDEX_op_ld8u_i64
:
1051 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1053 case INDEX_op_ld8s_i32
:
1054 case INDEX_op_ld8s_i64
:
1055 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1056 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1058 case INDEX_op_ld16u_i32
:
1059 case INDEX_op_ld16u_i64
:
1060 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1062 case INDEX_op_ld16s_i32
:
1063 case INDEX_op_ld16s_i64
:
1064 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1066 case INDEX_op_ld_i32
:
1067 case INDEX_op_ld32u_i64
:
1068 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1070 case INDEX_op_ld32s_i64
:
1071 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWA
, LWAX
);
1073 case INDEX_op_ld_i64
:
1074 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LD
, LDX
);
1076 case INDEX_op_st8_i32
:
1077 case INDEX_op_st8_i64
:
1078 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1080 case INDEX_op_st16_i32
:
1081 case INDEX_op_st16_i64
:
1082 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1084 case INDEX_op_st_i32
:
1085 case INDEX_op_st32_i64
:
1086 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1088 case INDEX_op_st_i64
:
1089 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STD
, STDX
);
1092 case INDEX_op_add_i32
:
1094 ppc_addi32 (s
, args
[0], args
[1], args
[2]);
1096 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1098 case INDEX_op_sub_i32
:
1100 ppc_addi32 (s
, args
[0], args
[1], -args
[2]);
1102 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1105 case INDEX_op_and_i32
:
1106 if (const_args
[2]) {
1108 tcg_out_movi (s
, TCG_TYPE_I32
, args
[0], 0);
1110 if ((args
[2] & 0xffff) == args
[2])
1111 tcg_out32 (s
, ANDI
| RS (args
[1]) | RA (args
[0]) | args
[2]);
1112 else if ((args
[2] & 0xffff0000) == args
[2])
1113 tcg_out32 (s
, ANDIS
| RS (args
[1]) | RA (args
[0])
1114 | ((args
[2] >> 16) & 0xffff));
1115 else if (args
[2] == 0xffffffff) {
1116 if (args
[0] != args
[1])
1117 tcg_out_mov (s
, args
[0], args
[1]);
1120 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1121 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], 0));
1126 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1128 case INDEX_op_or_i32
:
1129 if (const_args
[2]) {
1131 if (args
[2] & 0xffff) {
1132 tcg_out32 (s
, ORI
| RS (args
[1]) | RA (args
[0])
1133 | (args
[2] & 0xffff));
1135 tcg_out32 (s
, ORIS
| RS (args
[0]) | RA (args
[0])
1136 | ((args
[2] >> 16) & 0xffff));
1139 tcg_out32 (s
, ORIS
| RS (args
[1]) | RA (args
[0])
1140 | ((args
[2] >> 16) & 0xffff));
1144 if (args
[0] != args
[1])
1145 tcg_out_mov (s
, args
[0], args
[1]);
1149 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1151 case INDEX_op_xor_i32
:
1152 if (const_args
[2]) {
1154 if ((args
[2] & 0xffff) == args
[2])
1155 tcg_out32 (s
, XORI
| RS (args
[1]) | RA (args
[0])
1156 | (args
[2] & 0xffff));
1157 else if ((args
[2] & 0xffff0000) == args
[2])
1158 tcg_out32 (s
, XORIS
| RS (args
[1]) | RA (args
[0])
1159 | ((args
[2] >> 16) & 0xffff));
1161 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1162 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], 0));
1166 if (args
[0] != args
[1])
1167 tcg_out_mov (s
, args
[0], args
[1]);
1171 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1174 case INDEX_op_mul_i32
:
1175 if (const_args
[2]) {
1176 if (args
[2] == (int16_t) args
[2])
1177 tcg_out32 (s
, MULLI
| RT (args
[0]) | RA (args
[1])
1178 | (args
[2] & 0xffff));
1180 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1181 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], 0));
1185 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], args
[2]));
1188 case INDEX_op_div_i32
:
1189 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1192 case INDEX_op_divu_i32
:
1193 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1196 case INDEX_op_rem_i32
:
1197 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1198 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1199 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1202 case INDEX_op_remu_i32
:
1203 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1204 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1205 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1208 case INDEX_op_shl_i32
:
1209 if (const_args
[2]) {
1211 tcg_out32 (s
, (RLWINM
1220 tcg_out_mov (s
, args
[0], args
[1]);
1223 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1225 case INDEX_op_shr_i32
:
1226 if (const_args
[2]) {
1228 tcg_out32 (s
, (RLWINM
1237 tcg_out_mov (s
, args
[0], args
[1]);
1240 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1242 case INDEX_op_sar_i32
:
1244 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1246 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1249 case INDEX_op_brcond_i32
:
1250 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3], 0);
1253 case INDEX_op_brcond_i64
:
1254 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3], 1);
1257 case INDEX_op_neg_i32
:
1258 case INDEX_op_neg_i64
:
1259 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1262 case INDEX_op_add_i64
:
1263 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1265 case INDEX_op_sub_i64
:
1266 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1269 case INDEX_op_and_i64
:
1270 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1272 case INDEX_op_or_i64
:
1273 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1275 case INDEX_op_xor_i64
:
1276 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1279 case INDEX_op_shl_i64
:
1280 tcg_out32 (s
, SLD
| SAB (args
[1], args
[0], args
[2]));
1282 case INDEX_op_shr_i64
:
1283 tcg_out32 (s
, SRD
| SAB (args
[1], args
[0], args
[2]));
1285 case INDEX_op_sar_i64
:
1286 tcg_out32 (s
, SRAD
| SAB (args
[1], args
[0], args
[2]));
1289 case INDEX_op_mul_i64
:
1290 tcg_out32 (s
, MULLD
| TAB (args
[0], args
[1], args
[2]));
1292 case INDEX_op_div_i64
:
1293 tcg_out32 (s
, DIVD
| TAB (args
[0], args
[1], args
[2]));
1295 case INDEX_op_divu_i64
:
1296 tcg_out32 (s
, DIVDU
| TAB (args
[0], args
[1], args
[2]));
1298 case INDEX_op_rem_i64
:
1299 tcg_out32 (s
, DIVD
| TAB (0, args
[1], args
[2]));
1300 tcg_out32 (s
, MULLD
| TAB (0, 0, args
[2]));
1301 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1303 case INDEX_op_remu_i64
:
1304 tcg_out32 (s
, DIVDU
| TAB (0, args
[1], args
[2]));
1305 tcg_out32 (s
, MULLD
| TAB (0, 0, args
[2]));
1306 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1309 case INDEX_op_qemu_ld8u
:
1310 tcg_out_qemu_ld (s
, args
, 0);
1312 case INDEX_op_qemu_ld8s
:
1313 tcg_out_qemu_ld (s
, args
, 0 | 4);
1315 case INDEX_op_qemu_ld16u
:
1316 tcg_out_qemu_ld (s
, args
, 1);
1318 case INDEX_op_qemu_ld16s
:
1319 tcg_out_qemu_ld (s
, args
, 1 | 4);
1321 case INDEX_op_qemu_ld32u
:
1322 tcg_out_qemu_ld (s
, args
, 2);
1324 case INDEX_op_qemu_ld32s
:
1325 tcg_out_qemu_ld (s
, args
, 2 | 4);
1327 case INDEX_op_qemu_ld64
:
1328 tcg_out_qemu_ld (s
, args
, 3);
1330 case INDEX_op_qemu_st8
:
1331 tcg_out_qemu_st (s
, args
, 0);
1333 case INDEX_op_qemu_st16
:
1334 tcg_out_qemu_st (s
, args
, 1);
1336 case INDEX_op_qemu_st32
:
1337 tcg_out_qemu_st (s
, args
, 2);
1339 case INDEX_op_qemu_st64
:
1340 tcg_out_qemu_st (s
, args
, 3);
1343 case INDEX_op_ext8s_i32
:
1344 case INDEX_op_ext8s_i64
:
1347 case INDEX_op_ext16s_i32
:
1348 case INDEX_op_ext16s_i64
:
1351 case INDEX_op_ext32s_i64
:
1355 tcg_out32 (s
, c
| RS (args
[1]) | RA (args
[0]));
1359 tcg_dump_ops (s
, stderr
);
1364 static const TCGTargetOpDef ppc_op_defs
[] = {
1365 { INDEX_op_exit_tb
, { } },
1366 { INDEX_op_goto_tb
, { } },
1367 { INDEX_op_call
, { "ri" } },
1368 { INDEX_op_jmp
, { "ri" } },
1369 { INDEX_op_br
, { } },
1371 { INDEX_op_mov_i32
, { "r", "r" } },
1372 { INDEX_op_mov_i64
, { "r", "r" } },
1373 { INDEX_op_movi_i32
, { "r" } },
1374 { INDEX_op_movi_i64
, { "r" } },
1376 { INDEX_op_ld8u_i32
, { "r", "r" } },
1377 { INDEX_op_ld8s_i32
, { "r", "r" } },
1378 { INDEX_op_ld16u_i32
, { "r", "r" } },
1379 { INDEX_op_ld16s_i32
, { "r", "r" } },
1380 { INDEX_op_ld_i32
, { "r", "r" } },
1381 { INDEX_op_ld_i64
, { "r", "r" } },
1382 { INDEX_op_st8_i32
, { "r", "r" } },
1383 { INDEX_op_st8_i64
, { "r", "r" } },
1384 { INDEX_op_st16_i32
, { "r", "r" } },
1385 { INDEX_op_st16_i64
, { "r", "r" } },
1386 { INDEX_op_st_i32
, { "r", "r" } },
1387 { INDEX_op_st_i64
, { "r", "r" } },
1388 { INDEX_op_st32_i64
, { "r", "r" } },
1390 { INDEX_op_ld8u_i64
, { "r", "r" } },
1391 { INDEX_op_ld8s_i64
, { "r", "r" } },
1392 { INDEX_op_ld16u_i64
, { "r", "r" } },
1393 { INDEX_op_ld16s_i64
, { "r", "r" } },
1394 { INDEX_op_ld32u_i64
, { "r", "r" } },
1395 { INDEX_op_ld32s_i64
, { "r", "r" } },
1396 { INDEX_op_ld_i64
, { "r", "r" } },
1398 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1399 { INDEX_op_mul_i32
, { "r", "r", "ri" } },
1400 { INDEX_op_div_i32
, { "r", "r", "r" } },
1401 { INDEX_op_divu_i32
, { "r", "r", "r" } },
1402 { INDEX_op_rem_i32
, { "r", "r", "r" } },
1403 { INDEX_op_remu_i32
, { "r", "r", "r" } },
1404 { INDEX_op_sub_i32
, { "r", "r", "ri" } },
1405 { INDEX_op_and_i32
, { "r", "r", "ri" } },
1406 { INDEX_op_or_i32
, { "r", "r", "ri" } },
1407 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
1409 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1410 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1411 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1413 { INDEX_op_brcond_i32
, { "r", "ri" } },
1414 { INDEX_op_brcond_i64
, { "r", "ri" } },
1416 { INDEX_op_neg_i32
, { "r", "r" } },
1418 { INDEX_op_add_i64
, { "r", "r", "r" } },
1419 { INDEX_op_sub_i64
, { "r", "r", "r" } },
1420 { INDEX_op_and_i64
, { "r", "r", "r" } },
1421 { INDEX_op_or_i64
, { "r", "r", "r" } },
1422 { INDEX_op_xor_i64
, { "r", "r", "r" } },
1424 { INDEX_op_shl_i64
, { "r", "r", "r" } },
1425 { INDEX_op_shr_i64
, { "r", "r", "r" } },
1426 { INDEX_op_sar_i64
, { "r", "r", "r" } },
1428 { INDEX_op_mul_i64
, { "r", "r", "r" } },
1429 { INDEX_op_div_i64
, { "r", "r", "r" } },
1430 { INDEX_op_divu_i64
, { "r", "r", "r" } },
1431 { INDEX_op_rem_i64
, { "r", "r", "r" } },
1432 { INDEX_op_remu_i64
, { "r", "r", "r" } },
1434 { INDEX_op_neg_i64
, { "r", "r" } },
1436 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1437 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1438 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1439 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1440 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1441 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1442 { INDEX_op_qemu_ld64
, { "r", "L" } },
1444 { INDEX_op_qemu_st8
, { "S", "S" } },
1445 { INDEX_op_qemu_st16
, { "S", "S" } },
1446 { INDEX_op_qemu_st32
, { "S", "S" } },
1447 { INDEX_op_qemu_st64
, { "S", "S", "S" } },
1449 { INDEX_op_ext8s_i32
, { "r", "r" } },
1450 { INDEX_op_ext16s_i32
, { "r", "r" } },
1451 { INDEX_op_ext8s_i64
, { "r", "r" } },
1452 { INDEX_op_ext16s_i64
, { "r", "r" } },
1453 { INDEX_op_ext32s_i64
, { "r", "r" } },
1458 void tcg_target_init (TCGContext
*s
)
1460 tcg_regset_set32 (tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1461 tcg_regset_set32 (tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
1462 tcg_regset_set32 (tcg_target_call_clobber_regs
, 0,
1471 (1 << TCG_REG_R10
) |
1472 (1 << TCG_REG_R11
) |
1476 tcg_regset_clear (s
->reserved_regs
);
1477 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R0
);
1478 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R1
);
1479 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R2
);
1480 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R13
);
1482 tcg_add_target_add_op_defs (ppc_op_defs
);