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[qemu.git] / tcg / s390 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 /* We only support generating code for 64-bit mode. */
28 #if TCG_TARGET_REG_BITS != 64
29 #error "unsupported code generation mode"
30 #endif
31
32 /* ??? The translation blocks produced by TCG are generally small enough to
33 be entirely reachable with a 16-bit displacement. Leaving the option for
34 a 32-bit displacement here Just In Case. */
35 #define USE_LONG_BRANCHES 0
36
37 #define TCG_CT_CONST_32 0x0100
38 #define TCG_CT_CONST_NEG 0x0200
39 #define TCG_CT_CONST_ADDI 0x0400
40 #define TCG_CT_CONST_MULI 0x0800
41 #define TCG_CT_CONST_ANDI 0x1000
42 #define TCG_CT_CONST_ORI 0x2000
43 #define TCG_CT_CONST_XORI 0x4000
44 #define TCG_CT_CONST_CMPI 0x8000
45
46 /* Several places within the instruction set 0 means "no register"
47 rather than TCG_REG_R0. */
48 #define TCG_REG_NONE 0
49
50 /* A scratch register that may be be used throughout the backend. */
51 #define TCG_TMP0 TCG_REG_R14
52
53 #ifdef CONFIG_USE_GUEST_BASE
54 #define TCG_GUEST_BASE_REG TCG_REG_R13
55 #else
56 #define TCG_GUEST_BASE_REG TCG_REG_R0
57 #endif
58
59 #ifndef GUEST_BASE
60 #define GUEST_BASE 0
61 #endif
62
63
64 /* All of the following instructions are prefixed with their instruction
65 format, and are defined as 8- or 16-bit quantities, even when the two
66 halves of the 16-bit quantity may appear 32 bits apart in the insn.
67 This makes it easy to copy the values from the tables in Appendix B. */
68 typedef enum S390Opcode {
69 RIL_AFI = 0xc209,
70 RIL_AGFI = 0xc208,
71 RIL_ALFI = 0xc20b,
72 RIL_ALGFI = 0xc20a,
73 RIL_BRASL = 0xc005,
74 RIL_BRCL = 0xc004,
75 RIL_CFI = 0xc20d,
76 RIL_CGFI = 0xc20c,
77 RIL_CLFI = 0xc20f,
78 RIL_CLGFI = 0xc20e,
79 RIL_IIHF = 0xc008,
80 RIL_IILF = 0xc009,
81 RIL_LARL = 0xc000,
82 RIL_LGFI = 0xc001,
83 RIL_LGRL = 0xc408,
84 RIL_LLIHF = 0xc00e,
85 RIL_LLILF = 0xc00f,
86 RIL_LRL = 0xc40d,
87 RIL_MSFI = 0xc201,
88 RIL_MSGFI = 0xc200,
89 RIL_NIHF = 0xc00a,
90 RIL_NILF = 0xc00b,
91 RIL_OIHF = 0xc00c,
92 RIL_OILF = 0xc00d,
93 RIL_SLFI = 0xc205,
94 RIL_XIHF = 0xc006,
95 RIL_XILF = 0xc007,
96
97 RI_AGHI = 0xa70b,
98 RI_AHI = 0xa70a,
99 RI_BRC = 0xa704,
100 RI_IIHH = 0xa500,
101 RI_IIHL = 0xa501,
102 RI_IILH = 0xa502,
103 RI_IILL = 0xa503,
104 RI_LGHI = 0xa709,
105 RI_LLIHH = 0xa50c,
106 RI_LLIHL = 0xa50d,
107 RI_LLILH = 0xa50e,
108 RI_LLILL = 0xa50f,
109 RI_MGHI = 0xa70d,
110 RI_MHI = 0xa70c,
111 RI_NIHH = 0xa504,
112 RI_NIHL = 0xa505,
113 RI_NILH = 0xa506,
114 RI_NILL = 0xa507,
115 RI_OIHH = 0xa508,
116 RI_OIHL = 0xa509,
117 RI_OILH = 0xa50a,
118 RI_OILL = 0xa50b,
119
120 RIE_CGIJ = 0xec7c,
121 RIE_CGRJ = 0xec64,
122 RIE_CIJ = 0xec7e,
123 RIE_CLGRJ = 0xec65,
124 RIE_CLIJ = 0xec7f,
125 RIE_CLGIJ = 0xec7d,
126 RIE_CLRJ = 0xec77,
127 RIE_CRJ = 0xec76,
128
129 RRE_AGR = 0xb908,
130 RRE_ALGR = 0xb90a,
131 RRE_ALCR = 0xb998,
132 RRE_ALCGR = 0xb988,
133 RRE_CGR = 0xb920,
134 RRE_CLGR = 0xb921,
135 RRE_DLGR = 0xb987,
136 RRE_DLR = 0xb997,
137 RRE_DSGFR = 0xb91d,
138 RRE_DSGR = 0xb90d,
139 RRE_LGBR = 0xb906,
140 RRE_LCGR = 0xb903,
141 RRE_LGFR = 0xb914,
142 RRE_LGHR = 0xb907,
143 RRE_LGR = 0xb904,
144 RRE_LLGCR = 0xb984,
145 RRE_LLGFR = 0xb916,
146 RRE_LLGHR = 0xb985,
147 RRE_LRVR = 0xb91f,
148 RRE_LRVGR = 0xb90f,
149 RRE_LTGR = 0xb902,
150 RRE_MSGR = 0xb90c,
151 RRE_MSR = 0xb252,
152 RRE_NGR = 0xb980,
153 RRE_OGR = 0xb981,
154 RRE_SGR = 0xb909,
155 RRE_SLGR = 0xb90b,
156 RRE_SLBR = 0xb999,
157 RRE_SLBGR = 0xb989,
158 RRE_XGR = 0xb982,
159
160 RR_AR = 0x1a,
161 RR_ALR = 0x1e,
162 RR_BASR = 0x0d,
163 RR_BCR = 0x07,
164 RR_CLR = 0x15,
165 RR_CR = 0x19,
166 RR_DR = 0x1d,
167 RR_LCR = 0x13,
168 RR_LR = 0x18,
169 RR_LTR = 0x12,
170 RR_NR = 0x14,
171 RR_OR = 0x16,
172 RR_SR = 0x1b,
173 RR_SLR = 0x1f,
174 RR_XR = 0x17,
175
176 RSY_RLL = 0xeb1d,
177 RSY_RLLG = 0xeb1c,
178 RSY_SLLG = 0xeb0d,
179 RSY_SRAG = 0xeb0a,
180 RSY_SRLG = 0xeb0c,
181
182 RS_SLL = 0x89,
183 RS_SRA = 0x8a,
184 RS_SRL = 0x88,
185
186 RXY_AG = 0xe308,
187 RXY_AY = 0xe35a,
188 RXY_CG = 0xe320,
189 RXY_CY = 0xe359,
190 RXY_LB = 0xe376,
191 RXY_LG = 0xe304,
192 RXY_LGB = 0xe377,
193 RXY_LGF = 0xe314,
194 RXY_LGH = 0xe315,
195 RXY_LHY = 0xe378,
196 RXY_LLGC = 0xe390,
197 RXY_LLGF = 0xe316,
198 RXY_LLGH = 0xe391,
199 RXY_LMG = 0xeb04,
200 RXY_LRV = 0xe31e,
201 RXY_LRVG = 0xe30f,
202 RXY_LRVH = 0xe31f,
203 RXY_LY = 0xe358,
204 RXY_STCY = 0xe372,
205 RXY_STG = 0xe324,
206 RXY_STHY = 0xe370,
207 RXY_STMG = 0xeb24,
208 RXY_STRV = 0xe33e,
209 RXY_STRVG = 0xe32f,
210 RXY_STRVH = 0xe33f,
211 RXY_STY = 0xe350,
212
213 RX_A = 0x5a,
214 RX_C = 0x59,
215 RX_L = 0x58,
216 RX_LH = 0x48,
217 RX_ST = 0x50,
218 RX_STC = 0x42,
219 RX_STH = 0x40,
220 } S390Opcode;
221
222 #define LD_SIGNED 0x04
223 #define LD_UINT8 0x00
224 #define LD_INT8 (LD_UINT8 | LD_SIGNED)
225 #define LD_UINT16 0x01
226 #define LD_INT16 (LD_UINT16 | LD_SIGNED)
227 #define LD_UINT32 0x02
228 #define LD_INT32 (LD_UINT32 | LD_SIGNED)
229 #define LD_UINT64 0x03
230 #define LD_INT64 (LD_UINT64 | LD_SIGNED)
231
232 #ifndef NDEBUG
233 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
234 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
235 "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
236 };
237 #endif
238
239 /* Since R6 is a potential argument register, choose it last of the
240 call-saved registers. Likewise prefer the call-clobbered registers
241 in reverse order to maximize the chance of avoiding the arguments. */
242 static const int tcg_target_reg_alloc_order[] = {
243 TCG_REG_R13,
244 TCG_REG_R12,
245 TCG_REG_R11,
246 TCG_REG_R10,
247 TCG_REG_R9,
248 TCG_REG_R8,
249 TCG_REG_R7,
250 TCG_REG_R6,
251 TCG_REG_R14,
252 TCG_REG_R0,
253 TCG_REG_R1,
254 TCG_REG_R5,
255 TCG_REG_R4,
256 TCG_REG_R3,
257 TCG_REG_R2,
258 };
259
260 static const int tcg_target_call_iarg_regs[] = {
261 TCG_REG_R2,
262 TCG_REG_R3,
263 TCG_REG_R4,
264 TCG_REG_R5,
265 TCG_REG_R6,
266 };
267
268 static const int tcg_target_call_oarg_regs[] = {
269 TCG_REG_R2,
270 };
271
272 #define S390_CC_EQ 8
273 #define S390_CC_LT 4
274 #define S390_CC_GT 2
275 #define S390_CC_OV 1
276 #define S390_CC_NE (S390_CC_LT | S390_CC_GT)
277 #define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
278 #define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
279 #define S390_CC_NEVER 0
280 #define S390_CC_ALWAYS 15
281
282 /* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
283 static const uint8_t tcg_cond_to_s390_cond[] = {
284 [TCG_COND_EQ] = S390_CC_EQ,
285 [TCG_COND_NE] = S390_CC_NE,
286 [TCG_COND_LT] = S390_CC_LT,
287 [TCG_COND_LE] = S390_CC_LE,
288 [TCG_COND_GT] = S390_CC_GT,
289 [TCG_COND_GE] = S390_CC_GE,
290 [TCG_COND_LTU] = S390_CC_LT,
291 [TCG_COND_LEU] = S390_CC_LE,
292 [TCG_COND_GTU] = S390_CC_GT,
293 [TCG_COND_GEU] = S390_CC_GE,
294 };
295
296 /* Condition codes that result from a LOAD AND TEST. Here, we have no
297 unsigned instruction variation, however since the test is vs zero we
298 can re-map the outcomes appropriately. */
299 static const uint8_t tcg_cond_to_ltr_cond[] = {
300 [TCG_COND_EQ] = S390_CC_EQ,
301 [TCG_COND_NE] = S390_CC_NE,
302 [TCG_COND_LT] = S390_CC_LT,
303 [TCG_COND_LE] = S390_CC_LE,
304 [TCG_COND_GT] = S390_CC_GT,
305 [TCG_COND_GE] = S390_CC_GE,
306 [TCG_COND_LTU] = S390_CC_NEVER,
307 [TCG_COND_LEU] = S390_CC_EQ,
308 [TCG_COND_GTU] = S390_CC_NE,
309 [TCG_COND_GEU] = S390_CC_ALWAYS,
310 };
311
312 #ifdef CONFIG_SOFTMMU
313
314 #include "exec/softmmu_defs.h"
315
316 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
317 int mmu_idx) */
318 static const void * const qemu_ld_helpers[4] = {
319 helper_ldb_mmu,
320 helper_ldw_mmu,
321 helper_ldl_mmu,
322 helper_ldq_mmu,
323 };
324
325 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
326 uintxx_t val, int mmu_idx) */
327 static const void * const qemu_st_helpers[4] = {
328 helper_stb_mmu,
329 helper_stw_mmu,
330 helper_stl_mmu,
331 helper_stq_mmu,
332 };
333 #endif
334
335 static uint8_t *tb_ret_addr;
336
337 /* A list of relevant facilities used by this translator. Some of these
338 are required for proper operation, and these are checked at startup. */
339
340 #define FACILITY_ZARCH_ACTIVE (1ULL << (63 - 2))
341 #define FACILITY_LONG_DISP (1ULL << (63 - 18))
342 #define FACILITY_EXT_IMM (1ULL << (63 - 21))
343 #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
344
345 static uint64_t facilities;
346
347 static void patch_reloc(uint8_t *code_ptr, int type,
348 tcg_target_long value, tcg_target_long addend)
349 {
350 tcg_target_long code_ptr_tl = (tcg_target_long)code_ptr;
351 tcg_target_long pcrel2;
352
353 /* ??? Not the usual definition of "addend". */
354 pcrel2 = (value - (code_ptr_tl + addend)) >> 1;
355
356 switch (type) {
357 case R_390_PC16DBL:
358 assert(pcrel2 == (int16_t)pcrel2);
359 *(int16_t *)code_ptr = pcrel2;
360 break;
361 case R_390_PC32DBL:
362 assert(pcrel2 == (int32_t)pcrel2);
363 *(int32_t *)code_ptr = pcrel2;
364 break;
365 default:
366 tcg_abort();
367 break;
368 }
369 }
370
371 /* parse target specific constraints */
372 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
373 {
374 const char *ct_str = *pct_str;
375
376 switch (ct_str[0]) {
377 case 'r': /* all registers */
378 ct->ct |= TCG_CT_REG;
379 tcg_regset_set32(ct->u.regs, 0, 0xffff);
380 break;
381 case 'R': /* not R0 */
382 ct->ct |= TCG_CT_REG;
383 tcg_regset_set32(ct->u.regs, 0, 0xffff);
384 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
385 break;
386 case 'L': /* qemu_ld/st constraint */
387 ct->ct |= TCG_CT_REG;
388 tcg_regset_set32(ct->u.regs, 0, 0xffff);
389 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);
390 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
391 break;
392 case 'a': /* force R2 for division */
393 ct->ct |= TCG_CT_REG;
394 tcg_regset_clear(ct->u.regs);
395 tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
396 break;
397 case 'b': /* force R3 for division */
398 ct->ct |= TCG_CT_REG;
399 tcg_regset_clear(ct->u.regs);
400 tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
401 break;
402 case 'N': /* force immediate negate */
403 ct->ct |= TCG_CT_CONST_NEG;
404 break;
405 case 'W': /* force 32-bit ("word") immediate */
406 ct->ct |= TCG_CT_CONST_32;
407 break;
408 case 'I':
409 ct->ct |= TCG_CT_CONST_ADDI;
410 break;
411 case 'K':
412 ct->ct |= TCG_CT_CONST_MULI;
413 break;
414 case 'A':
415 ct->ct |= TCG_CT_CONST_ANDI;
416 break;
417 case 'O':
418 ct->ct |= TCG_CT_CONST_ORI;
419 break;
420 case 'X':
421 ct->ct |= TCG_CT_CONST_XORI;
422 break;
423 case 'C':
424 ct->ct |= TCG_CT_CONST_CMPI;
425 break;
426 default:
427 return -1;
428 }
429 ct_str++;
430 *pct_str = ct_str;
431
432 return 0;
433 }
434
435 /* Immediates to be used with logical AND. This is an optimization only,
436 since a full 64-bit immediate AND can always be performed with 4 sequential
437 NI[LH][LH] instructions. What we're looking for is immediates that we
438 can load efficiently, and the immediate load plus the reg-reg AND is
439 smaller than the sequential NI's. */
440
441 static int tcg_match_andi(int ct, tcg_target_ulong val)
442 {
443 int i;
444
445 if (facilities & FACILITY_EXT_IMM) {
446 if (ct & TCG_CT_CONST_32) {
447 /* All 32-bit ANDs can be performed with 1 48-bit insn. */
448 return 1;
449 }
450
451 /* Zero-extensions. */
452 if (val == 0xff || val == 0xffff || val == 0xffffffff) {
453 return 1;
454 }
455 } else {
456 if (ct & TCG_CT_CONST_32) {
457 val = (uint32_t)val;
458 } else if (val == 0xffffffff) {
459 return 1;
460 }
461 }
462
463 /* Try all 32-bit insns that can perform it in one go. */
464 for (i = 0; i < 4; i++) {
465 tcg_target_ulong mask = ~(0xffffull << i*16);
466 if ((val & mask) == mask) {
467 return 1;
468 }
469 }
470
471 /* Look for 16-bit values performing the mask. These are better
472 to load with LLI[LH][LH]. */
473 for (i = 0; i < 4; i++) {
474 tcg_target_ulong mask = 0xffffull << i*16;
475 if ((val & mask) == val) {
476 return 0;
477 }
478 }
479
480 /* Look for 32-bit values performing the 64-bit mask. These
481 are better to load with LLI[LH]F, or if extended immediates
482 not available, with a pair of LLI insns. */
483 if ((ct & TCG_CT_CONST_32) == 0) {
484 if (val <= 0xffffffff || (val & 0xffffffff) == 0) {
485 return 0;
486 }
487 }
488
489 return 1;
490 }
491
492 /* Immediates to be used with logical OR. This is an optimization only,
493 since a full 64-bit immediate OR can always be performed with 4 sequential
494 OI[LH][LH] instructions. What we're looking for is immediates that we
495 can load efficiently, and the immediate load plus the reg-reg OR is
496 smaller than the sequential OI's. */
497
498 static int tcg_match_ori(int ct, tcg_target_long val)
499 {
500 if (facilities & FACILITY_EXT_IMM) {
501 if (ct & TCG_CT_CONST_32) {
502 /* All 32-bit ORs can be performed with 1 48-bit insn. */
503 return 1;
504 }
505 }
506
507 /* Look for negative values. These are best to load with LGHI. */
508 if (val < 0) {
509 if (val == (int16_t)val) {
510 return 0;
511 }
512 if (facilities & FACILITY_EXT_IMM) {
513 if (val == (int32_t)val) {
514 return 0;
515 }
516 }
517 }
518
519 return 1;
520 }
521
522 /* Immediates to be used with logical XOR. This is almost, but not quite,
523 only an optimization. XOR with immediate is only supported with the
524 extended-immediate facility. That said, there are a few patterns for
525 which it is better to load the value into a register first. */
526
527 static int tcg_match_xori(int ct, tcg_target_long val)
528 {
529 if ((facilities & FACILITY_EXT_IMM) == 0) {
530 return 0;
531 }
532
533 if (ct & TCG_CT_CONST_32) {
534 /* All 32-bit XORs can be performed with 1 48-bit insn. */
535 return 1;
536 }
537
538 /* Look for negative values. These are best to load with LGHI. */
539 if (val < 0 && val == (int32_t)val) {
540 return 0;
541 }
542
543 return 1;
544 }
545
546 /* Imediates to be used with comparisons. */
547
548 static int tcg_match_cmpi(int ct, tcg_target_long val)
549 {
550 if (facilities & FACILITY_EXT_IMM) {
551 /* The COMPARE IMMEDIATE instruction is available. */
552 if (ct & TCG_CT_CONST_32) {
553 /* We have a 32-bit immediate and can compare against anything. */
554 return 1;
555 } else {
556 /* ??? We have no insight here into whether the comparison is
557 signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit
558 signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses
559 a 32-bit unsigned immediate. If we were to use the (semi)
560 obvious "val == (int32_t)val" we would be enabling unsigned
561 comparisons vs very large numbers. The only solution is to
562 take the intersection of the ranges. */
563 /* ??? Another possible solution is to simply lie and allow all
564 constants here and force the out-of-range values into a temp
565 register in tgen_cmp when we have knowledge of the actual
566 comparison code in use. */
567 return val >= 0 && val <= 0x7fffffff;
568 }
569 } else {
570 /* Only the LOAD AND TEST instruction is available. */
571 return val == 0;
572 }
573 }
574
575 /* Test if a constant matches the constraint. */
576 static int tcg_target_const_match(tcg_target_long val,
577 const TCGArgConstraint *arg_ct)
578 {
579 int ct = arg_ct->ct;
580
581 if (ct & TCG_CT_CONST) {
582 return 1;
583 }
584
585 /* Handle the modifiers. */
586 if (ct & TCG_CT_CONST_NEG) {
587 val = -val;
588 }
589 if (ct & TCG_CT_CONST_32) {
590 val = (int32_t)val;
591 }
592
593 /* The following are mutually exclusive. */
594 if (ct & TCG_CT_CONST_ADDI) {
595 /* Immediates that may be used with add. If we have the
596 extended-immediates facility then we have ADD IMMEDIATE
597 with signed and unsigned 32-bit, otherwise we have only
598 ADD HALFWORD IMMEDIATE with a signed 16-bit. */
599 if (facilities & FACILITY_EXT_IMM) {
600 return val == (int32_t)val || val == (uint32_t)val;
601 } else {
602 return val == (int16_t)val;
603 }
604 } else if (ct & TCG_CT_CONST_MULI) {
605 /* Immediates that may be used with multiply. If we have the
606 general-instruction-extensions, then we have MULTIPLY SINGLE
607 IMMEDIATE with a signed 32-bit, otherwise we have only
608 MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
609 if (facilities & FACILITY_GEN_INST_EXT) {
610 return val == (int32_t)val;
611 } else {
612 return val == (int16_t)val;
613 }
614 } else if (ct & TCG_CT_CONST_ANDI) {
615 return tcg_match_andi(ct, val);
616 } else if (ct & TCG_CT_CONST_ORI) {
617 return tcg_match_ori(ct, val);
618 } else if (ct & TCG_CT_CONST_XORI) {
619 return tcg_match_xori(ct, val);
620 } else if (ct & TCG_CT_CONST_CMPI) {
621 return tcg_match_cmpi(ct, val);
622 }
623
624 return 0;
625 }
626
627 /* Emit instructions according to the given instruction format. */
628
629 static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
630 {
631 tcg_out16(s, (op << 8) | (r1 << 4) | r2);
632 }
633
634 static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
635 TCGReg r1, TCGReg r2)
636 {
637 tcg_out32(s, (op << 16) | (r1 << 4) | r2);
638 }
639
640 static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
641 {
642 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
643 }
644
645 static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
646 {
647 tcg_out16(s, op | (r1 << 4));
648 tcg_out32(s, i2);
649 }
650
651 static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
652 TCGReg b2, TCGReg r3, int disp)
653 {
654 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
655 | (disp & 0xfff));
656 }
657
658 static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
659 TCGReg b2, TCGReg r3, int disp)
660 {
661 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
662 tcg_out32(s, (op & 0xff) | (b2 << 28)
663 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
664 }
665
666 #define tcg_out_insn_RX tcg_out_insn_RS
667 #define tcg_out_insn_RXY tcg_out_insn_RSY
668
669 /* Emit an opcode with "type-checking" of the format. */
670 #define tcg_out_insn(S, FMT, OP, ...) \
671 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
672
673
674 /* emit 64-bit shifts */
675 static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
676 TCGReg src, TCGReg sh_reg, int sh_imm)
677 {
678 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
679 }
680
681 /* emit 32-bit shifts */
682 static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
683 TCGReg sh_reg, int sh_imm)
684 {
685 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
686 }
687
688 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
689 {
690 if (src != dst) {
691 if (type == TCG_TYPE_I32) {
692 tcg_out_insn(s, RR, LR, dst, src);
693 } else {
694 tcg_out_insn(s, RRE, LGR, dst, src);
695 }
696 }
697 }
698
699 /* load a register with an immediate value */
700 static void tcg_out_movi(TCGContext *s, TCGType type,
701 TCGReg ret, tcg_target_long sval)
702 {
703 static const S390Opcode lli_insns[4] = {
704 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
705 };
706
707 tcg_target_ulong uval = sval;
708 int i;
709
710 if (type == TCG_TYPE_I32) {
711 uval = (uint32_t)sval;
712 sval = (int32_t)sval;
713 }
714
715 /* Try all 32-bit insns that can load it in one go. */
716 if (sval >= -0x8000 && sval < 0x8000) {
717 tcg_out_insn(s, RI, LGHI, ret, sval);
718 return;
719 }
720
721 for (i = 0; i < 4; i++) {
722 tcg_target_long mask = 0xffffull << i*16;
723 if ((uval & mask) == uval) {
724 tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
725 return;
726 }
727 }
728
729 /* Try all 48-bit insns that can load it in one go. */
730 if (facilities & FACILITY_EXT_IMM) {
731 if (sval == (int32_t)sval) {
732 tcg_out_insn(s, RIL, LGFI, ret, sval);
733 return;
734 }
735 if (uval <= 0xffffffff) {
736 tcg_out_insn(s, RIL, LLILF, ret, uval);
737 return;
738 }
739 if ((uval & 0xffffffff) == 0) {
740 tcg_out_insn(s, RIL, LLIHF, ret, uval >> 31 >> 1);
741 return;
742 }
743 }
744
745 /* Try for PC-relative address load. */
746 if ((sval & 1) == 0) {
747 intptr_t off = (sval - (intptr_t)s->code_ptr) >> 1;
748 if (off == (int32_t)off) {
749 tcg_out_insn(s, RIL, LARL, ret, off);
750 return;
751 }
752 }
753
754 /* If extended immediates are not present, then we may have to issue
755 several instructions to load the low 32 bits. */
756 if (!(facilities & FACILITY_EXT_IMM)) {
757 /* A 32-bit unsigned value can be loaded in 2 insns. And given
758 that the lli_insns loop above did not succeed, we know that
759 both insns are required. */
760 if (uval <= 0xffffffff) {
761 tcg_out_insn(s, RI, LLILL, ret, uval);
762 tcg_out_insn(s, RI, IILH, ret, uval >> 16);
763 return;
764 }
765
766 /* If all high bits are set, the value can be loaded in 2 or 3 insns.
767 We first want to make sure that all the high bits get set. With
768 luck the low 16-bits can be considered negative to perform that for
769 free, otherwise we load an explicit -1. */
770 if (sval >> 31 >> 1 == -1) {
771 if (uval & 0x8000) {
772 tcg_out_insn(s, RI, LGHI, ret, uval);
773 } else {
774 tcg_out_insn(s, RI, LGHI, ret, -1);
775 tcg_out_insn(s, RI, IILL, ret, uval);
776 }
777 tcg_out_insn(s, RI, IILH, ret, uval >> 16);
778 return;
779 }
780 }
781
782 /* If we get here, both the high and low parts have non-zero bits. */
783
784 /* Recurse to load the lower 32-bits. */
785 tcg_out_movi(s, TCG_TYPE_I64, ret, uval & 0xffffffff);
786
787 /* Insert data into the high 32-bits. */
788 uval = uval >> 31 >> 1;
789 if (facilities & FACILITY_EXT_IMM) {
790 if (uval < 0x10000) {
791 tcg_out_insn(s, RI, IIHL, ret, uval);
792 } else if ((uval & 0xffff) == 0) {
793 tcg_out_insn(s, RI, IIHH, ret, uval >> 16);
794 } else {
795 tcg_out_insn(s, RIL, IIHF, ret, uval);
796 }
797 } else {
798 if (uval & 0xffff) {
799 tcg_out_insn(s, RI, IIHL, ret, uval);
800 }
801 if (uval & 0xffff0000) {
802 tcg_out_insn(s, RI, IIHH, ret, uval >> 16);
803 }
804 }
805 }
806
807
808 /* Emit a load/store type instruction. Inputs are:
809 DATA: The register to be loaded or stored.
810 BASE+OFS: The effective address.
811 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
812 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
813
814 static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
815 TCGReg data, TCGReg base, TCGReg index,
816 tcg_target_long ofs)
817 {
818 if (ofs < -0x80000 || ofs >= 0x80000) {
819 /* Combine the low 16 bits of the offset with the actual load insn;
820 the high 48 bits must come from an immediate load. */
821 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs & ~0xffff);
822 ofs &= 0xffff;
823
824 /* If we were already given an index register, add it in. */
825 if (index != TCG_REG_NONE) {
826 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
827 }
828 index = TCG_TMP0;
829 }
830
831 if (opc_rx && ofs >= 0 && ofs < 0x1000) {
832 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
833 } else {
834 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
835 }
836 }
837
838
839 /* load data without address translation or endianness conversion */
840 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
841 TCGReg base, tcg_target_long ofs)
842 {
843 if (type == TCG_TYPE_I32) {
844 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
845 } else {
846 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
847 }
848 }
849
850 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
851 TCGReg base, tcg_target_long ofs)
852 {
853 if (type == TCG_TYPE_I32) {
854 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
855 } else {
856 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
857 }
858 }
859
860 /* load data from an absolute host address */
861 static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
862 {
863 tcg_target_long addr = (tcg_target_long)abs;
864
865 if (facilities & FACILITY_GEN_INST_EXT) {
866 tcg_target_long disp = (addr - (tcg_target_long)s->code_ptr) >> 1;
867 if (disp == (int32_t)disp) {
868 if (type == TCG_TYPE_I32) {
869 tcg_out_insn(s, RIL, LRL, dest, disp);
870 } else {
871 tcg_out_insn(s, RIL, LGRL, dest, disp);
872 }
873 return;
874 }
875 }
876
877 tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
878 tcg_out_ld(s, type, dest, dest, addr & 0xffff);
879 }
880
881 static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
882 {
883 if (facilities & FACILITY_EXT_IMM) {
884 tcg_out_insn(s, RRE, LGBR, dest, src);
885 return;
886 }
887
888 if (type == TCG_TYPE_I32) {
889 if (dest == src) {
890 tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
891 } else {
892 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
893 }
894 tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
895 } else {
896 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
897 tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
898 }
899 }
900
901 static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
902 {
903 if (facilities & FACILITY_EXT_IMM) {
904 tcg_out_insn(s, RRE, LLGCR, dest, src);
905 return;
906 }
907
908 if (dest == src) {
909 tcg_out_movi(s, type, TCG_TMP0, 0xff);
910 src = TCG_TMP0;
911 } else {
912 tcg_out_movi(s, type, dest, 0xff);
913 }
914 if (type == TCG_TYPE_I32) {
915 tcg_out_insn(s, RR, NR, dest, src);
916 } else {
917 tcg_out_insn(s, RRE, NGR, dest, src);
918 }
919 }
920
921 static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
922 {
923 if (facilities & FACILITY_EXT_IMM) {
924 tcg_out_insn(s, RRE, LGHR, dest, src);
925 return;
926 }
927
928 if (type == TCG_TYPE_I32) {
929 if (dest == src) {
930 tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
931 } else {
932 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
933 }
934 tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
935 } else {
936 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
937 tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
938 }
939 }
940
941 static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
942 {
943 if (facilities & FACILITY_EXT_IMM) {
944 tcg_out_insn(s, RRE, LLGHR, dest, src);
945 return;
946 }
947
948 if (dest == src) {
949 tcg_out_movi(s, type, TCG_TMP0, 0xffff);
950 src = TCG_TMP0;
951 } else {
952 tcg_out_movi(s, type, dest, 0xffff);
953 }
954 if (type == TCG_TYPE_I32) {
955 tcg_out_insn(s, RR, NR, dest, src);
956 } else {
957 tcg_out_insn(s, RRE, NGR, dest, src);
958 }
959 }
960
961 static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
962 {
963 tcg_out_insn(s, RRE, LGFR, dest, src);
964 }
965
966 static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
967 {
968 tcg_out_insn(s, RRE, LLGFR, dest, src);
969 }
970
971 static inline void tgen32_addi(TCGContext *s, TCGReg dest, int32_t val)
972 {
973 if (val == (int16_t)val) {
974 tcg_out_insn(s, RI, AHI, dest, val);
975 } else {
976 tcg_out_insn(s, RIL, AFI, dest, val);
977 }
978 }
979
980 static inline void tgen64_addi(TCGContext *s, TCGReg dest, int64_t val)
981 {
982 if (val == (int16_t)val) {
983 tcg_out_insn(s, RI, AGHI, dest, val);
984 } else if (val == (int32_t)val) {
985 tcg_out_insn(s, RIL, AGFI, dest, val);
986 } else if (val == (uint32_t)val) {
987 tcg_out_insn(s, RIL, ALGFI, dest, val);
988 } else {
989 tcg_abort();
990 }
991
992 }
993
994 static void tgen64_andi(TCGContext *s, TCGReg dest, tcg_target_ulong val)
995 {
996 static const S390Opcode ni_insns[4] = {
997 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
998 };
999 static const S390Opcode nif_insns[2] = {
1000 RIL_NILF, RIL_NIHF
1001 };
1002
1003 int i;
1004
1005 /* Look for no-op. */
1006 if (val == -1) {
1007 return;
1008 }
1009
1010 /* Look for the zero-extensions. */
1011 if (val == 0xffffffff) {
1012 tgen_ext32u(s, dest, dest);
1013 return;
1014 }
1015
1016 if (facilities & FACILITY_EXT_IMM) {
1017 if (val == 0xff) {
1018 tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
1019 return;
1020 }
1021 if (val == 0xffff) {
1022 tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
1023 return;
1024 }
1025
1026 /* Try all 32-bit insns that can perform it in one go. */
1027 for (i = 0; i < 4; i++) {
1028 tcg_target_ulong mask = ~(0xffffull << i*16);
1029 if ((val & mask) == mask) {
1030 tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
1031 return;
1032 }
1033 }
1034
1035 /* Try all 48-bit insns that can perform it in one go. */
1036 if (facilities & FACILITY_EXT_IMM) {
1037 for (i = 0; i < 2; i++) {
1038 tcg_target_ulong mask = ~(0xffffffffull << i*32);
1039 if ((val & mask) == mask) {
1040 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
1041 return;
1042 }
1043 }
1044 }
1045
1046 /* Perform the AND via sequential modifications to the high and low
1047 parts. Do this via recursion to handle 16-bit vs 32-bit masks in
1048 each half. */
1049 tgen64_andi(s, dest, val | 0xffffffff00000000ull);
1050 tgen64_andi(s, dest, val | 0x00000000ffffffffull);
1051 } else {
1052 /* With no extended-immediate facility, just emit the sequence. */
1053 for (i = 0; i < 4; i++) {
1054 tcg_target_ulong mask = 0xffffull << i*16;
1055 if ((val & mask) != mask) {
1056 tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
1057 }
1058 }
1059 }
1060 }
1061
1062 static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
1063 {
1064 static const S390Opcode oi_insns[4] = {
1065 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
1066 };
1067 static const S390Opcode nif_insns[2] = {
1068 RIL_OILF, RIL_OIHF
1069 };
1070
1071 int i;
1072
1073 /* Look for no-op. */
1074 if (val == 0) {
1075 return;
1076 }
1077
1078 if (facilities & FACILITY_EXT_IMM) {
1079 /* Try all 32-bit insns that can perform it in one go. */
1080 for (i = 0; i < 4; i++) {
1081 tcg_target_ulong mask = (0xffffull << i*16);
1082 if ((val & mask) != 0 && (val & ~mask) == 0) {
1083 tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
1084 return;
1085 }
1086 }
1087
1088 /* Try all 48-bit insns that can perform it in one go. */
1089 for (i = 0; i < 2; i++) {
1090 tcg_target_ulong mask = (0xffffffffull << i*32);
1091 if ((val & mask) != 0 && (val & ~mask) == 0) {
1092 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
1093 return;
1094 }
1095 }
1096
1097 /* Perform the OR via sequential modifications to the high and
1098 low parts. Do this via recursion to handle 16-bit vs 32-bit
1099 masks in each half. */
1100 tgen64_ori(s, dest, val & 0x00000000ffffffffull);
1101 tgen64_ori(s, dest, val & 0xffffffff00000000ull);
1102 } else {
1103 /* With no extended-immediate facility, we don't need to be so
1104 clever. Just iterate over the insns and mask in the constant. */
1105 for (i = 0; i < 4; i++) {
1106 tcg_target_ulong mask = (0xffffull << i*16);
1107 if ((val & mask) != 0) {
1108 tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
1109 }
1110 }
1111 }
1112 }
1113
1114 static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
1115 {
1116 /* Perform the xor by parts. */
1117 if (val & 0xffffffff) {
1118 tcg_out_insn(s, RIL, XILF, dest, val);
1119 }
1120 if (val > 0xffffffff) {
1121 tcg_out_insn(s, RIL, XIHF, dest, val >> 31 >> 1);
1122 }
1123 }
1124
1125 static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
1126 TCGArg c2, int c2const)
1127 {
1128 bool is_unsigned = is_unsigned_cond(c);
1129 if (c2const) {
1130 if (c2 == 0) {
1131 if (type == TCG_TYPE_I32) {
1132 tcg_out_insn(s, RR, LTR, r1, r1);
1133 } else {
1134 tcg_out_insn(s, RRE, LTGR, r1, r1);
1135 }
1136 return tcg_cond_to_ltr_cond[c];
1137 } else {
1138 if (is_unsigned) {
1139 if (type == TCG_TYPE_I32) {
1140 tcg_out_insn(s, RIL, CLFI, r1, c2);
1141 } else {
1142 tcg_out_insn(s, RIL, CLGFI, r1, c2);
1143 }
1144 } else {
1145 if (type == TCG_TYPE_I32) {
1146 tcg_out_insn(s, RIL, CFI, r1, c2);
1147 } else {
1148 tcg_out_insn(s, RIL, CGFI, r1, c2);
1149 }
1150 }
1151 }
1152 } else {
1153 if (is_unsigned) {
1154 if (type == TCG_TYPE_I32) {
1155 tcg_out_insn(s, RR, CLR, r1, c2);
1156 } else {
1157 tcg_out_insn(s, RRE, CLGR, r1, c2);
1158 }
1159 } else {
1160 if (type == TCG_TYPE_I32) {
1161 tcg_out_insn(s, RR, CR, r1, c2);
1162 } else {
1163 tcg_out_insn(s, RRE, CGR, r1, c2);
1164 }
1165 }
1166 }
1167 return tcg_cond_to_s390_cond[c];
1168 }
1169
1170 static void tgen_setcond(TCGContext *s, TCGType type, TCGCond c,
1171 TCGReg dest, TCGReg r1, TCGArg c2, int c2const)
1172 {
1173 int cc = tgen_cmp(s, type, c, r1, c2, c2const);
1174
1175 /* Emit: r1 = 1; if (cc) goto over; r1 = 0; over: */
1176 tcg_out_movi(s, type, dest, 1);
1177 tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
1178 tcg_out_movi(s, type, dest, 0);
1179 }
1180
1181 static void tgen_gotoi(TCGContext *s, int cc, tcg_target_long dest)
1182 {
1183 tcg_target_long off = (dest - (tcg_target_long)s->code_ptr) >> 1;
1184 if (off > -0x8000 && off < 0x7fff) {
1185 tcg_out_insn(s, RI, BRC, cc, off);
1186 } else if (off == (int32_t)off) {
1187 tcg_out_insn(s, RIL, BRCL, cc, off);
1188 } else {
1189 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, dest);
1190 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
1191 }
1192 }
1193
1194 static void tgen_branch(TCGContext *s, int cc, int labelno)
1195 {
1196 TCGLabel* l = &s->labels[labelno];
1197 if (l->has_value) {
1198 tgen_gotoi(s, cc, l->u.value);
1199 } else if (USE_LONG_BRANCHES) {
1200 tcg_out16(s, RIL_BRCL | (cc << 4));
1201 tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, labelno, -2);
1202 s->code_ptr += 4;
1203 } else {
1204 tcg_out16(s, RI_BRC | (cc << 4));
1205 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, labelno, -2);
1206 s->code_ptr += 2;
1207 }
1208 }
1209
1210 static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
1211 TCGReg r1, TCGReg r2, int labelno)
1212 {
1213 TCGLabel* l = &s->labels[labelno];
1214 tcg_target_long off;
1215
1216 if (l->has_value) {
1217 off = (l->u.value - (tcg_target_long)s->code_ptr) >> 1;
1218 } else {
1219 /* We need to keep the offset unchanged for retranslation. */
1220 off = ((int16_t *)s->code_ptr)[1];
1221 tcg_out_reloc(s, s->code_ptr + 2, R_390_PC16DBL, labelno, -2);
1222 }
1223
1224 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
1225 tcg_out16(s, off);
1226 tcg_out16(s, cc << 12 | (opc & 0xff));
1227 }
1228
1229 static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
1230 TCGReg r1, int i2, int labelno)
1231 {
1232 TCGLabel* l = &s->labels[labelno];
1233 tcg_target_long off;
1234
1235 if (l->has_value) {
1236 off = (l->u.value - (tcg_target_long)s->code_ptr) >> 1;
1237 } else {
1238 /* We need to keep the offset unchanged for retranslation. */
1239 off = ((int16_t *)s->code_ptr)[1];
1240 tcg_out_reloc(s, s->code_ptr + 2, R_390_PC16DBL, labelno, -2);
1241 }
1242
1243 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
1244 tcg_out16(s, off);
1245 tcg_out16(s, (i2 << 8) | (opc & 0xff));
1246 }
1247
1248 static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
1249 TCGReg r1, TCGArg c2, int c2const, int labelno)
1250 {
1251 int cc;
1252
1253 if (facilities & FACILITY_GEN_INST_EXT) {
1254 bool is_unsigned = (c > TCG_COND_GT);
1255 bool in_range;
1256 S390Opcode opc;
1257
1258 cc = tcg_cond_to_s390_cond[c];
1259
1260 if (!c2const) {
1261 opc = (type == TCG_TYPE_I32
1262 ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
1263 : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
1264 tgen_compare_branch(s, opc, cc, r1, c2, labelno);
1265 return;
1266 }
1267
1268 /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
1269 If the immediate we've been given does not fit that range, we'll
1270 fall back to separate compare and branch instructions using the
1271 larger comparison range afforded by COMPARE IMMEDIATE. */
1272 if (type == TCG_TYPE_I32) {
1273 if (is_unsigned) {
1274 opc = RIE_CLIJ;
1275 in_range = (uint32_t)c2 == (uint8_t)c2;
1276 } else {
1277 opc = RIE_CIJ;
1278 in_range = (int32_t)c2 == (int8_t)c2;
1279 }
1280 } else {
1281 if (is_unsigned) {
1282 opc = RIE_CLGIJ;
1283 in_range = (uint64_t)c2 == (uint8_t)c2;
1284 } else {
1285 opc = RIE_CGIJ;
1286 in_range = (int64_t)c2 == (int8_t)c2;
1287 }
1288 }
1289 if (in_range) {
1290 tgen_compare_imm_branch(s, opc, cc, r1, c2, labelno);
1291 return;
1292 }
1293 }
1294
1295 cc = tgen_cmp(s, type, c, r1, c2, c2const);
1296 tgen_branch(s, cc, labelno);
1297 }
1298
1299 static void tgen_calli(TCGContext *s, tcg_target_long dest)
1300 {
1301 tcg_target_long off = (dest - (tcg_target_long)s->code_ptr) >> 1;
1302 if (off == (int32_t)off) {
1303 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
1304 } else {
1305 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, dest);
1306 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
1307 }
1308 }
1309
1310 static void tcg_out_qemu_ld_direct(TCGContext *s, int opc, TCGReg data,
1311 TCGReg base, TCGReg index, int disp)
1312 {
1313 #ifdef TARGET_WORDS_BIGENDIAN
1314 const int bswap = 0;
1315 #else
1316 const int bswap = 1;
1317 #endif
1318 switch (opc) {
1319 case LD_UINT8:
1320 tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
1321 break;
1322 case LD_INT8:
1323 tcg_out_insn(s, RXY, LGB, data, base, index, disp);
1324 break;
1325 case LD_UINT16:
1326 if (bswap) {
1327 /* swapped unsigned halfword load with upper bits zeroed */
1328 tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
1329 tgen_ext16u(s, TCG_TYPE_I64, data, data);
1330 } else {
1331 tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
1332 }
1333 break;
1334 case LD_INT16:
1335 if (bswap) {
1336 /* swapped sign-extended halfword load */
1337 tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
1338 tgen_ext16s(s, TCG_TYPE_I64, data, data);
1339 } else {
1340 tcg_out_insn(s, RXY, LGH, data, base, index, disp);
1341 }
1342 break;
1343 case LD_UINT32:
1344 if (bswap) {
1345 /* swapped unsigned int load with upper bits zeroed */
1346 tcg_out_insn(s, RXY, LRV, data, base, index, disp);
1347 tgen_ext32u(s, data, data);
1348 } else {
1349 tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
1350 }
1351 break;
1352 case LD_INT32:
1353 if (bswap) {
1354 /* swapped sign-extended int load */
1355 tcg_out_insn(s, RXY, LRV, data, base, index, disp);
1356 tgen_ext32s(s, data, data);
1357 } else {
1358 tcg_out_insn(s, RXY, LGF, data, base, index, disp);
1359 }
1360 break;
1361 case LD_UINT64:
1362 if (bswap) {
1363 tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
1364 } else {
1365 tcg_out_insn(s, RXY, LG, data, base, index, disp);
1366 }
1367 break;
1368 default:
1369 tcg_abort();
1370 }
1371 }
1372
1373 static void tcg_out_qemu_st_direct(TCGContext *s, int opc, TCGReg data,
1374 TCGReg base, TCGReg index, int disp)
1375 {
1376 #ifdef TARGET_WORDS_BIGENDIAN
1377 const int bswap = 0;
1378 #else
1379 const int bswap = 1;
1380 #endif
1381 switch (opc) {
1382 case LD_UINT8:
1383 if (disp >= 0 && disp < 0x1000) {
1384 tcg_out_insn(s, RX, STC, data, base, index, disp);
1385 } else {
1386 tcg_out_insn(s, RXY, STCY, data, base, index, disp);
1387 }
1388 break;
1389 case LD_UINT16:
1390 if (bswap) {
1391 tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
1392 } else if (disp >= 0 && disp < 0x1000) {
1393 tcg_out_insn(s, RX, STH, data, base, index, disp);
1394 } else {
1395 tcg_out_insn(s, RXY, STHY, data, base, index, disp);
1396 }
1397 break;
1398 case LD_UINT32:
1399 if (bswap) {
1400 tcg_out_insn(s, RXY, STRV, data, base, index, disp);
1401 } else if (disp >= 0 && disp < 0x1000) {
1402 tcg_out_insn(s, RX, ST, data, base, index, disp);
1403 } else {
1404 tcg_out_insn(s, RXY, STY, data, base, index, disp);
1405 }
1406 break;
1407 case LD_UINT64:
1408 if (bswap) {
1409 tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
1410 } else {
1411 tcg_out_insn(s, RXY, STG, data, base, index, disp);
1412 }
1413 break;
1414 default:
1415 tcg_abort();
1416 }
1417 }
1418
1419 #if defined(CONFIG_SOFTMMU)
1420 static void tgen64_andi_tmp(TCGContext *s, TCGReg dest, tcg_target_ulong val)
1421 {
1422 if (tcg_match_andi(0, val)) {
1423 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, val);
1424 tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
1425 } else {
1426 tgen64_andi(s, dest, val);
1427 }
1428 }
1429
1430 static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
1431 TCGReg addr_reg, int mem_index, int opc,
1432 uint16_t **label2_ptr_p, int is_store)
1433 {
1434 const TCGReg arg0 = TCG_REG_R2;
1435 const TCGReg arg1 = TCG_REG_R3;
1436 int s_bits = opc & 3;
1437 uint16_t *label1_ptr;
1438 tcg_target_long ofs;
1439
1440 if (TARGET_LONG_BITS == 32) {
1441 tgen_ext32u(s, arg0, addr_reg);
1442 } else {
1443 tcg_out_mov(s, TCG_TYPE_I64, arg0, addr_reg);
1444 }
1445
1446 tcg_out_sh64(s, RSY_SRLG, arg1, addr_reg, TCG_REG_NONE,
1447 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1448
1449 tgen64_andi_tmp(s, arg0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
1450 tgen64_andi_tmp(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1451
1452 if (is_store) {
1453 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
1454 } else {
1455 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
1456 }
1457 assert(ofs < 0x80000);
1458
1459 if (TARGET_LONG_BITS == 32) {
1460 tcg_out_mem(s, RX_C, RXY_CY, arg0, arg1, TCG_AREG0, ofs);
1461 } else {
1462 tcg_out_mem(s, 0, RXY_CG, arg0, arg1, TCG_AREG0, ofs);
1463 }
1464
1465 if (TARGET_LONG_BITS == 32) {
1466 tgen_ext32u(s, arg0, addr_reg);
1467 } else {
1468 tcg_out_mov(s, TCG_TYPE_I64, arg0, addr_reg);
1469 }
1470
1471 label1_ptr = (uint16_t*)s->code_ptr;
1472
1473 /* je label1 (offset will be patched in later) */
1474 tcg_out_insn(s, RI, BRC, S390_CC_EQ, 0);
1475
1476 /* call load/store helper */
1477 if (is_store) {
1478 /* Make sure to zero-extend the value to the full register
1479 for the calling convention. */
1480 switch (opc) {
1481 case LD_UINT8:
1482 tgen_ext8u(s, TCG_TYPE_I64, arg1, data_reg);
1483 break;
1484 case LD_UINT16:
1485 tgen_ext16u(s, TCG_TYPE_I64, arg1, data_reg);
1486 break;
1487 case LD_UINT32:
1488 tgen_ext32u(s, arg1, data_reg);
1489 break;
1490 case LD_UINT64:
1491 tcg_out_mov(s, TCG_TYPE_I64, arg1, data_reg);
1492 break;
1493 default:
1494 tcg_abort();
1495 }
1496 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
1497 /* XXX/FIXME: suboptimal */
1498 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
1499 tcg_target_call_iarg_regs[2]);
1500 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
1501 tcg_target_call_iarg_regs[1]);
1502 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
1503 tcg_target_call_iarg_regs[0]);
1504 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
1505 TCG_AREG0);
1506 tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
1507 } else {
1508 tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
1509 /* XXX/FIXME: suboptimal */
1510 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
1511 tcg_target_call_iarg_regs[1]);
1512 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
1513 tcg_target_call_iarg_regs[0]);
1514 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
1515 TCG_AREG0);
1516 tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
1517
1518 /* sign extension */
1519 switch (opc) {
1520 case LD_INT8:
1521 tgen_ext8s(s, TCG_TYPE_I64, data_reg, arg0);
1522 break;
1523 case LD_INT16:
1524 tgen_ext16s(s, TCG_TYPE_I64, data_reg, arg0);
1525 break;
1526 case LD_INT32:
1527 tgen_ext32s(s, data_reg, arg0);
1528 break;
1529 default:
1530 /* unsigned -> just copy */
1531 tcg_out_mov(s, TCG_TYPE_I64, data_reg, arg0);
1532 break;
1533 }
1534 }
1535
1536 /* jump to label2 (end) */
1537 *label2_ptr_p = (uint16_t*)s->code_ptr;
1538
1539 tcg_out_insn(s, RI, BRC, S390_CC_ALWAYS, 0);
1540
1541 /* this is label1, patch branch */
1542 *(label1_ptr + 1) = ((unsigned long)s->code_ptr -
1543 (unsigned long)label1_ptr) >> 1;
1544
1545 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1546 assert(ofs < 0x80000);
1547
1548 tcg_out_mem(s, 0, RXY_AG, arg0, arg1, TCG_AREG0, ofs);
1549 }
1550
1551 static void tcg_finish_qemu_ldst(TCGContext* s, uint16_t *label2_ptr)
1552 {
1553 /* patch branch */
1554 *(label2_ptr + 1) = ((unsigned long)s->code_ptr -
1555 (unsigned long)label2_ptr) >> 1;
1556 }
1557 #else
1558 static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
1559 TCGReg *index_reg, tcg_target_long *disp)
1560 {
1561 if (TARGET_LONG_BITS == 32) {
1562 tgen_ext32u(s, TCG_TMP0, *addr_reg);
1563 *addr_reg = TCG_TMP0;
1564 }
1565 if (GUEST_BASE < 0x80000) {
1566 *index_reg = TCG_REG_NONE;
1567 *disp = GUEST_BASE;
1568 } else {
1569 *index_reg = TCG_GUEST_BASE_REG;
1570 *disp = 0;
1571 }
1572 }
1573 #endif /* CONFIG_SOFTMMU */
1574
1575 /* load data with address translation (if applicable)
1576 and endianness conversion */
1577 static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
1578 {
1579 TCGReg addr_reg, data_reg;
1580 #if defined(CONFIG_SOFTMMU)
1581 int mem_index;
1582 uint16_t *label2_ptr;
1583 #else
1584 TCGReg index_reg;
1585 tcg_target_long disp;
1586 #endif
1587
1588 data_reg = *args++;
1589 addr_reg = *args++;
1590
1591 #if defined(CONFIG_SOFTMMU)
1592 mem_index = *args;
1593
1594 tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
1595 opc, &label2_ptr, 0);
1596
1597 tcg_out_qemu_ld_direct(s, opc, data_reg, TCG_REG_R2, TCG_REG_NONE, 0);
1598
1599 tcg_finish_qemu_ldst(s, label2_ptr);
1600 #else
1601 tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
1602 tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
1603 #endif
1604 }
1605
1606 static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, int opc)
1607 {
1608 TCGReg addr_reg, data_reg;
1609 #if defined(CONFIG_SOFTMMU)
1610 int mem_index;
1611 uint16_t *label2_ptr;
1612 #else
1613 TCGReg index_reg;
1614 tcg_target_long disp;
1615 #endif
1616
1617 data_reg = *args++;
1618 addr_reg = *args++;
1619
1620 #if defined(CONFIG_SOFTMMU)
1621 mem_index = *args;
1622
1623 tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
1624 opc, &label2_ptr, 1);
1625
1626 tcg_out_qemu_st_direct(s, opc, data_reg, TCG_REG_R2, TCG_REG_NONE, 0);
1627
1628 tcg_finish_qemu_ldst(s, label2_ptr);
1629 #else
1630 tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
1631 tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
1632 #endif
1633 }
1634
1635 # define OP_32_64(x) \
1636 case glue(glue(INDEX_op_,x),_i32): \
1637 case glue(glue(INDEX_op_,x),_i64)
1638
1639 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1640 const TCGArg *args, const int *const_args)
1641 {
1642 S390Opcode op;
1643
1644 switch (opc) {
1645 case INDEX_op_exit_tb:
1646 /* return value */
1647 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, args[0]);
1648 tgen_gotoi(s, S390_CC_ALWAYS, (unsigned long)tb_ret_addr);
1649 break;
1650
1651 case INDEX_op_goto_tb:
1652 if (s->tb_jmp_offset) {
1653 tcg_abort();
1654 } else {
1655 /* load address stored at s->tb_next + args[0] */
1656 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0, s->tb_next + args[0]);
1657 /* and go there */
1658 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0);
1659 }
1660 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1661 break;
1662
1663 case INDEX_op_call:
1664 if (const_args[0]) {
1665 tgen_calli(s, args[0]);
1666 } else {
1667 tcg_out_insn(s, RR, BASR, TCG_REG_R14, args[0]);
1668 }
1669 break;
1670
1671 case INDEX_op_mov_i32:
1672 tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
1673 break;
1674 case INDEX_op_movi_i32:
1675 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1676 break;
1677
1678 OP_32_64(ld8u):
1679 /* ??? LLC (RXY format) is only present with the extended-immediate
1680 facility, whereas LLGC is always present. */
1681 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
1682 break;
1683
1684 OP_32_64(ld8s):
1685 /* ??? LB is no smaller than LGB, so no point to using it. */
1686 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
1687 break;
1688
1689 OP_32_64(ld16u):
1690 /* ??? LLH (RXY format) is only present with the extended-immediate
1691 facility, whereas LLGH is always present. */
1692 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
1693 break;
1694
1695 case INDEX_op_ld16s_i32:
1696 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
1697 break;
1698
1699 case INDEX_op_ld_i32:
1700 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1701 break;
1702
1703 OP_32_64(st8):
1704 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
1705 TCG_REG_NONE, args[2]);
1706 break;
1707
1708 OP_32_64(st16):
1709 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
1710 TCG_REG_NONE, args[2]);
1711 break;
1712
1713 case INDEX_op_st_i32:
1714 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1715 break;
1716
1717 case INDEX_op_add_i32:
1718 if (const_args[2]) {
1719 tgen32_addi(s, args[0], args[2]);
1720 } else {
1721 tcg_out_insn(s, RR, AR, args[0], args[2]);
1722 }
1723 break;
1724 case INDEX_op_sub_i32:
1725 if (const_args[2]) {
1726 tgen32_addi(s, args[0], -args[2]);
1727 } else {
1728 tcg_out_insn(s, RR, SR, args[0], args[2]);
1729 }
1730 break;
1731
1732 case INDEX_op_and_i32:
1733 if (const_args[2]) {
1734 tgen64_andi(s, args[0], args[2] | 0xffffffff00000000ull);
1735 } else {
1736 tcg_out_insn(s, RR, NR, args[0], args[2]);
1737 }
1738 break;
1739 case INDEX_op_or_i32:
1740 if (const_args[2]) {
1741 tgen64_ori(s, args[0], args[2] & 0xffffffff);
1742 } else {
1743 tcg_out_insn(s, RR, OR, args[0], args[2]);
1744 }
1745 break;
1746 case INDEX_op_xor_i32:
1747 if (const_args[2]) {
1748 tgen64_xori(s, args[0], args[2] & 0xffffffff);
1749 } else {
1750 tcg_out_insn(s, RR, XR, args[0], args[2]);
1751 }
1752 break;
1753
1754 case INDEX_op_neg_i32:
1755 tcg_out_insn(s, RR, LCR, args[0], args[1]);
1756 break;
1757
1758 case INDEX_op_mul_i32:
1759 if (const_args[2]) {
1760 if ((int32_t)args[2] == (int16_t)args[2]) {
1761 tcg_out_insn(s, RI, MHI, args[0], args[2]);
1762 } else {
1763 tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
1764 }
1765 } else {
1766 tcg_out_insn(s, RRE, MSR, args[0], args[2]);
1767 }
1768 break;
1769
1770 case INDEX_op_div2_i32:
1771 tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
1772 break;
1773 case INDEX_op_divu2_i32:
1774 tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
1775 break;
1776
1777 case INDEX_op_shl_i32:
1778 op = RS_SLL;
1779 do_shift32:
1780 if (const_args[2]) {
1781 tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]);
1782 } else {
1783 tcg_out_sh32(s, op, args[0], args[2], 0);
1784 }
1785 break;
1786 case INDEX_op_shr_i32:
1787 op = RS_SRL;
1788 goto do_shift32;
1789 case INDEX_op_sar_i32:
1790 op = RS_SRA;
1791 goto do_shift32;
1792
1793 case INDEX_op_rotl_i32:
1794 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
1795 if (const_args[2]) {
1796 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
1797 } else {
1798 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
1799 }
1800 break;
1801 case INDEX_op_rotr_i32:
1802 if (const_args[2]) {
1803 tcg_out_sh64(s, RSY_RLL, args[0], args[1],
1804 TCG_REG_NONE, (32 - args[2]) & 31);
1805 } else {
1806 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
1807 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
1808 }
1809 break;
1810
1811 case INDEX_op_ext8s_i32:
1812 tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
1813 break;
1814 case INDEX_op_ext16s_i32:
1815 tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
1816 break;
1817 case INDEX_op_ext8u_i32:
1818 tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
1819 break;
1820 case INDEX_op_ext16u_i32:
1821 tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
1822 break;
1823
1824 OP_32_64(bswap16):
1825 /* The TCG bswap definition requires bits 0-47 already be zero.
1826 Thus we don't need the G-type insns to implement bswap16_i64. */
1827 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
1828 tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
1829 break;
1830 OP_32_64(bswap32):
1831 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
1832 break;
1833
1834 case INDEX_op_add2_i32:
1835 /* ??? Make use of ALFI. */
1836 tcg_out_insn(s, RR, ALR, args[0], args[4]);
1837 tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
1838 break;
1839 case INDEX_op_sub2_i32:
1840 /* ??? Make use of SLFI. */
1841 tcg_out_insn(s, RR, SLR, args[0], args[4]);
1842 tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
1843 break;
1844
1845 case INDEX_op_br:
1846 tgen_branch(s, S390_CC_ALWAYS, args[0]);
1847 break;
1848
1849 case INDEX_op_brcond_i32:
1850 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
1851 args[1], const_args[1], args[3]);
1852 break;
1853 case INDEX_op_setcond_i32:
1854 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
1855 args[2], const_args[2]);
1856 break;
1857
1858 case INDEX_op_qemu_ld8u:
1859 tcg_out_qemu_ld(s, args, LD_UINT8);
1860 break;
1861 case INDEX_op_qemu_ld8s:
1862 tcg_out_qemu_ld(s, args, LD_INT8);
1863 break;
1864 case INDEX_op_qemu_ld16u:
1865 tcg_out_qemu_ld(s, args, LD_UINT16);
1866 break;
1867 case INDEX_op_qemu_ld16s:
1868 tcg_out_qemu_ld(s, args, LD_INT16);
1869 break;
1870 case INDEX_op_qemu_ld32:
1871 /* ??? Technically we can use a non-extending instruction. */
1872 tcg_out_qemu_ld(s, args, LD_UINT32);
1873 break;
1874 case INDEX_op_qemu_ld64:
1875 tcg_out_qemu_ld(s, args, LD_UINT64);
1876 break;
1877
1878 case INDEX_op_qemu_st8:
1879 tcg_out_qemu_st(s, args, LD_UINT8);
1880 break;
1881 case INDEX_op_qemu_st16:
1882 tcg_out_qemu_st(s, args, LD_UINT16);
1883 break;
1884 case INDEX_op_qemu_st32:
1885 tcg_out_qemu_st(s, args, LD_UINT32);
1886 break;
1887 case INDEX_op_qemu_st64:
1888 tcg_out_qemu_st(s, args, LD_UINT64);
1889 break;
1890
1891 case INDEX_op_mov_i64:
1892 tcg_out_mov(s, TCG_TYPE_I64, args[0], args[1]);
1893 break;
1894 case INDEX_op_movi_i64:
1895 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1896 break;
1897
1898 case INDEX_op_ld16s_i64:
1899 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
1900 break;
1901 case INDEX_op_ld32u_i64:
1902 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
1903 break;
1904 case INDEX_op_ld32s_i64:
1905 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
1906 break;
1907 case INDEX_op_ld_i64:
1908 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
1909 break;
1910
1911 case INDEX_op_st32_i64:
1912 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1913 break;
1914 case INDEX_op_st_i64:
1915 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
1916 break;
1917
1918 case INDEX_op_add_i64:
1919 if (const_args[2]) {
1920 tgen64_addi(s, args[0], args[2]);
1921 } else {
1922 tcg_out_insn(s, RRE, AGR, args[0], args[2]);
1923 }
1924 break;
1925 case INDEX_op_sub_i64:
1926 if (const_args[2]) {
1927 tgen64_addi(s, args[0], -args[2]);
1928 } else {
1929 tcg_out_insn(s, RRE, SGR, args[0], args[2]);
1930 }
1931 break;
1932
1933 case INDEX_op_and_i64:
1934 if (const_args[2]) {
1935 tgen64_andi(s, args[0], args[2]);
1936 } else {
1937 tcg_out_insn(s, RRE, NGR, args[0], args[2]);
1938 }
1939 break;
1940 case INDEX_op_or_i64:
1941 if (const_args[2]) {
1942 tgen64_ori(s, args[0], args[2]);
1943 } else {
1944 tcg_out_insn(s, RRE, OGR, args[0], args[2]);
1945 }
1946 break;
1947 case INDEX_op_xor_i64:
1948 if (const_args[2]) {
1949 tgen64_xori(s, args[0], args[2]);
1950 } else {
1951 tcg_out_insn(s, RRE, XGR, args[0], args[2]);
1952 }
1953 break;
1954
1955 case INDEX_op_neg_i64:
1956 tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
1957 break;
1958 case INDEX_op_bswap64_i64:
1959 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
1960 break;
1961
1962 case INDEX_op_mul_i64:
1963 if (const_args[2]) {
1964 if (args[2] == (int16_t)args[2]) {
1965 tcg_out_insn(s, RI, MGHI, args[0], args[2]);
1966 } else {
1967 tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
1968 }
1969 } else {
1970 tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
1971 }
1972 break;
1973
1974 case INDEX_op_div2_i64:
1975 /* ??? We get an unnecessary sign-extension of the dividend
1976 into R3 with this definition, but as we do in fact always
1977 produce both quotient and remainder using INDEX_op_div_i64
1978 instead requires jumping through even more hoops. */
1979 tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
1980 break;
1981 case INDEX_op_divu2_i64:
1982 tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
1983 break;
1984
1985 case INDEX_op_shl_i64:
1986 op = RSY_SLLG;
1987 do_shift64:
1988 if (const_args[2]) {
1989 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
1990 } else {
1991 tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
1992 }
1993 break;
1994 case INDEX_op_shr_i64:
1995 op = RSY_SRLG;
1996 goto do_shift64;
1997 case INDEX_op_sar_i64:
1998 op = RSY_SRAG;
1999 goto do_shift64;
2000
2001 case INDEX_op_rotl_i64:
2002 if (const_args[2]) {
2003 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2004 TCG_REG_NONE, args[2]);
2005 } else {
2006 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
2007 }
2008 break;
2009 case INDEX_op_rotr_i64:
2010 if (const_args[2]) {
2011 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2012 TCG_REG_NONE, (64 - args[2]) & 63);
2013 } else {
2014 /* We can use the smaller 32-bit negate because only the
2015 low 6 bits are examined for the rotate. */
2016 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
2017 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
2018 }
2019 break;
2020
2021 case INDEX_op_ext8s_i64:
2022 tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
2023 break;
2024 case INDEX_op_ext16s_i64:
2025 tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
2026 break;
2027 case INDEX_op_ext32s_i64:
2028 tgen_ext32s(s, args[0], args[1]);
2029 break;
2030 case INDEX_op_ext8u_i64:
2031 tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
2032 break;
2033 case INDEX_op_ext16u_i64:
2034 tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
2035 break;
2036 case INDEX_op_ext32u_i64:
2037 tgen_ext32u(s, args[0], args[1]);
2038 break;
2039
2040 case INDEX_op_add2_i64:
2041 /* ??? Make use of ALGFI and SLGFI. */
2042 tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
2043 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
2044 break;
2045 case INDEX_op_sub2_i64:
2046 /* ??? Make use of ALGFI and SLGFI. */
2047 tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
2048 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
2049 break;
2050
2051 case INDEX_op_brcond_i64:
2052 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
2053 args[1], const_args[1], args[3]);
2054 break;
2055 case INDEX_op_setcond_i64:
2056 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
2057 args[2], const_args[2]);
2058 break;
2059
2060 case INDEX_op_qemu_ld32u:
2061 tcg_out_qemu_ld(s, args, LD_UINT32);
2062 break;
2063 case INDEX_op_qemu_ld32s:
2064 tcg_out_qemu_ld(s, args, LD_INT32);
2065 break;
2066
2067 default:
2068 fprintf(stderr,"unimplemented opc 0x%x\n",opc);
2069 tcg_abort();
2070 }
2071 }
2072
2073 static const TCGTargetOpDef s390_op_defs[] = {
2074 { INDEX_op_exit_tb, { } },
2075 { INDEX_op_goto_tb, { } },
2076 { INDEX_op_call, { "ri" } },
2077 { INDEX_op_br, { } },
2078
2079 { INDEX_op_mov_i32, { "r", "r" } },
2080 { INDEX_op_movi_i32, { "r" } },
2081
2082 { INDEX_op_ld8u_i32, { "r", "r" } },
2083 { INDEX_op_ld8s_i32, { "r", "r" } },
2084 { INDEX_op_ld16u_i32, { "r", "r" } },
2085 { INDEX_op_ld16s_i32, { "r", "r" } },
2086 { INDEX_op_ld_i32, { "r", "r" } },
2087 { INDEX_op_st8_i32, { "r", "r" } },
2088 { INDEX_op_st16_i32, { "r", "r" } },
2089 { INDEX_op_st_i32, { "r", "r" } },
2090
2091 { INDEX_op_add_i32, { "r", "0", "rWI" } },
2092 { INDEX_op_sub_i32, { "r", "0", "rWNI" } },
2093 { INDEX_op_mul_i32, { "r", "0", "rK" } },
2094
2095 { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
2096 { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } },
2097
2098 { INDEX_op_and_i32, { "r", "0", "rWA" } },
2099 { INDEX_op_or_i32, { "r", "0", "rWO" } },
2100 { INDEX_op_xor_i32, { "r", "0", "rWX" } },
2101
2102 { INDEX_op_neg_i32, { "r", "r" } },
2103
2104 { INDEX_op_shl_i32, { "r", "0", "Ri" } },
2105 { INDEX_op_shr_i32, { "r", "0", "Ri" } },
2106 { INDEX_op_sar_i32, { "r", "0", "Ri" } },
2107
2108 { INDEX_op_rotl_i32, { "r", "r", "Ri" } },
2109 { INDEX_op_rotr_i32, { "r", "r", "Ri" } },
2110
2111 { INDEX_op_ext8s_i32, { "r", "r" } },
2112 { INDEX_op_ext8u_i32, { "r", "r" } },
2113 { INDEX_op_ext16s_i32, { "r", "r" } },
2114 { INDEX_op_ext16u_i32, { "r", "r" } },
2115
2116 { INDEX_op_bswap16_i32, { "r", "r" } },
2117 { INDEX_op_bswap32_i32, { "r", "r" } },
2118
2119 { INDEX_op_add2_i32, { "r", "r", "0", "1", "r", "r" } },
2120 { INDEX_op_sub2_i32, { "r", "r", "0", "1", "r", "r" } },
2121
2122 { INDEX_op_brcond_i32, { "r", "rWC" } },
2123 { INDEX_op_setcond_i32, { "r", "r", "rWC" } },
2124
2125 { INDEX_op_qemu_ld8u, { "r", "L" } },
2126 { INDEX_op_qemu_ld8s, { "r", "L" } },
2127 { INDEX_op_qemu_ld16u, { "r", "L" } },
2128 { INDEX_op_qemu_ld16s, { "r", "L" } },
2129 { INDEX_op_qemu_ld32, { "r", "L" } },
2130 { INDEX_op_qemu_ld64, { "r", "L" } },
2131
2132 { INDEX_op_qemu_st8, { "L", "L" } },
2133 { INDEX_op_qemu_st16, { "L", "L" } },
2134 { INDEX_op_qemu_st32, { "L", "L" } },
2135 { INDEX_op_qemu_st64, { "L", "L" } },
2136
2137 { INDEX_op_mov_i64, { "r", "r" } },
2138 { INDEX_op_movi_i64, { "r" } },
2139
2140 { INDEX_op_ld8u_i64, { "r", "r" } },
2141 { INDEX_op_ld8s_i64, { "r", "r" } },
2142 { INDEX_op_ld16u_i64, { "r", "r" } },
2143 { INDEX_op_ld16s_i64, { "r", "r" } },
2144 { INDEX_op_ld32u_i64, { "r", "r" } },
2145 { INDEX_op_ld32s_i64, { "r", "r" } },
2146 { INDEX_op_ld_i64, { "r", "r" } },
2147
2148 { INDEX_op_st8_i64, { "r", "r" } },
2149 { INDEX_op_st16_i64, { "r", "r" } },
2150 { INDEX_op_st32_i64, { "r", "r" } },
2151 { INDEX_op_st_i64, { "r", "r" } },
2152
2153 { INDEX_op_add_i64, { "r", "0", "rI" } },
2154 { INDEX_op_sub_i64, { "r", "0", "rNI" } },
2155 { INDEX_op_mul_i64, { "r", "0", "rK" } },
2156
2157 { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
2158 { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
2159
2160 { INDEX_op_and_i64, { "r", "0", "rA" } },
2161 { INDEX_op_or_i64, { "r", "0", "rO" } },
2162 { INDEX_op_xor_i64, { "r", "0", "rX" } },
2163
2164 { INDEX_op_neg_i64, { "r", "r" } },
2165
2166 { INDEX_op_shl_i64, { "r", "r", "Ri" } },
2167 { INDEX_op_shr_i64, { "r", "r", "Ri" } },
2168 { INDEX_op_sar_i64, { "r", "r", "Ri" } },
2169
2170 { INDEX_op_rotl_i64, { "r", "r", "Ri" } },
2171 { INDEX_op_rotr_i64, { "r", "r", "Ri" } },
2172
2173 { INDEX_op_ext8s_i64, { "r", "r" } },
2174 { INDEX_op_ext8u_i64, { "r", "r" } },
2175 { INDEX_op_ext16s_i64, { "r", "r" } },
2176 { INDEX_op_ext16u_i64, { "r", "r" } },
2177 { INDEX_op_ext32s_i64, { "r", "r" } },
2178 { INDEX_op_ext32u_i64, { "r", "r" } },
2179
2180 { INDEX_op_bswap16_i64, { "r", "r" } },
2181 { INDEX_op_bswap32_i64, { "r", "r" } },
2182 { INDEX_op_bswap64_i64, { "r", "r" } },
2183
2184 { INDEX_op_add2_i64, { "r", "r", "0", "1", "r", "r" } },
2185 { INDEX_op_sub2_i64, { "r", "r", "0", "1", "r", "r" } },
2186
2187 { INDEX_op_brcond_i64, { "r", "rC" } },
2188 { INDEX_op_setcond_i64, { "r", "r", "rC" } },
2189
2190 { INDEX_op_qemu_ld32u, { "r", "L" } },
2191 { INDEX_op_qemu_ld32s, { "r", "L" } },
2192
2193 { -1 },
2194 };
2195
2196 /* ??? Linux kernels provide an AUXV entry AT_HWCAP that provides most of
2197 this information. However, getting at that entry is not easy this far
2198 away from main. Our options are: start searching from environ, but
2199 that fails as soon as someone does a setenv in between. Read the data
2200 from /proc/self/auxv. Or do the probing ourselves. The only thing
2201 extra that AT_HWCAP gives us is HWCAP_S390_HIGH_GPRS, which indicates
2202 that the kernel saves all 64-bits of the registers around traps while
2203 in 31-bit mode. But this is true of all "recent" kernels (ought to dig
2204 back and see from when this might not be true). */
2205
2206 #include <signal.h>
2207
2208 static volatile sig_atomic_t got_sigill;
2209
2210 static void sigill_handler(int sig)
2211 {
2212 got_sigill = 1;
2213 }
2214
2215 static void query_facilities(void)
2216 {
2217 struct sigaction sa_old, sa_new;
2218 register int r0 __asm__("0");
2219 register void *r1 __asm__("1");
2220 int fail;
2221
2222 memset(&sa_new, 0, sizeof(sa_new));
2223 sa_new.sa_handler = sigill_handler;
2224 sigaction(SIGILL, &sa_new, &sa_old);
2225
2226 /* First, try STORE FACILITY LIST EXTENDED. If this is present, then
2227 we need not do any more probing. Unfortunately, this itself is an
2228 extension and the original STORE FACILITY LIST instruction is
2229 kernel-only, storing its results at absolute address 200. */
2230 /* stfle 0(%r1) */
2231 r1 = &facilities;
2232 asm volatile(".word 0xb2b0,0x1000"
2233 : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
2234
2235 if (got_sigill) {
2236 /* STORE FACILITY EXTENDED is not available. Probe for one of each
2237 kind of instruction that we're interested in. */
2238 /* ??? Possibly some of these are in practice never present unless
2239 the store-facility-extended facility is also present. But since
2240 that isn't documented it's just better to probe for each. */
2241
2242 /* Test for z/Architecture. Required even in 31-bit mode. */
2243 got_sigill = 0;
2244 /* agr %r0,%r0 */
2245 asm volatile(".word 0xb908,0x0000" : "=r"(r0) : : "cc");
2246 if (!got_sigill) {
2247 facilities |= FACILITY_ZARCH_ACTIVE;
2248 }
2249
2250 /* Test for long displacement. */
2251 got_sigill = 0;
2252 /* ly %r0,0(%r1) */
2253 r1 = &facilities;
2254 asm volatile(".word 0xe300,0x1000,0x0058"
2255 : "=r"(r0) : "r"(r1) : "cc");
2256 if (!got_sigill) {
2257 facilities |= FACILITY_LONG_DISP;
2258 }
2259
2260 /* Test for extended immediates. */
2261 got_sigill = 0;
2262 /* afi %r0,0 */
2263 asm volatile(".word 0xc209,0x0000,0x0000" : : : "cc");
2264 if (!got_sigill) {
2265 facilities |= FACILITY_EXT_IMM;
2266 }
2267
2268 /* Test for general-instructions-extension. */
2269 got_sigill = 0;
2270 /* msfi %r0,1 */
2271 asm volatile(".word 0xc201,0x0000,0x0001");
2272 if (!got_sigill) {
2273 facilities |= FACILITY_GEN_INST_EXT;
2274 }
2275 }
2276
2277 sigaction(SIGILL, &sa_old, NULL);
2278
2279 /* The translator currently uses these extensions unconditionally.
2280 Pruning this back to the base ESA/390 architecture doesn't seem
2281 worthwhile, since even the KVM target requires z/Arch. */
2282 fail = 0;
2283 if ((facilities & FACILITY_ZARCH_ACTIVE) == 0) {
2284 fprintf(stderr, "TCG: z/Arch facility is required.\n");
2285 fprintf(stderr, "TCG: Boot with a 64-bit enabled kernel.\n");
2286 fail = 1;
2287 }
2288 if ((facilities & FACILITY_LONG_DISP) == 0) {
2289 fprintf(stderr, "TCG: long-displacement facility is required.\n");
2290 fail = 1;
2291 }
2292
2293 /* So far there's just enough support for 31-bit mode to let the
2294 compile succeed. This is good enough to run QEMU with KVM. */
2295 if (sizeof(void *) != 8) {
2296 fprintf(stderr, "TCG: 31-bit mode is not supported.\n");
2297 fail = 1;
2298 }
2299
2300 if (fail) {
2301 exit(-1);
2302 }
2303 }
2304
2305 static void tcg_target_init(TCGContext *s)
2306 {
2307 #if !defined(CONFIG_USER_ONLY)
2308 /* fail safe */
2309 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) {
2310 tcg_abort();
2311 }
2312 #endif
2313
2314 query_facilities();
2315
2316 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
2317 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
2318
2319 tcg_regset_clear(tcg_target_call_clobber_regs);
2320 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2321 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
2322 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2323 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2324 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
2325 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
2326 /* The return register can be considered call-clobbered. */
2327 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2328
2329 tcg_regset_clear(s->reserved_regs);
2330 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
2331 /* XXX many insns can't be used with R0, so we better avoid it for now */
2332 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
2333 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
2334
2335 tcg_add_target_add_op_defs(s390_op_defs);
2336 }
2337
2338 static void tcg_target_qemu_prologue(TCGContext *s)
2339 {
2340 tcg_target_long frame_size;
2341
2342 /* stmg %r6,%r15,48(%r15) (save registers) */
2343 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
2344
2345 /* aghi %r15,-frame_size */
2346 frame_size = TCG_TARGET_CALL_STACK_OFFSET;
2347 frame_size += TCG_STATIC_CALL_ARGS_SIZE;
2348 frame_size += CPU_TEMP_BUF_NLONGS * sizeof(long);
2349 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -frame_size);
2350
2351 tcg_set_frame(s, TCG_REG_CALL_STACK,
2352 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
2353 CPU_TEMP_BUF_NLONGS * sizeof(long));
2354
2355 if (GUEST_BASE >= 0x80000) {
2356 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
2357 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2358 }
2359
2360 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2361 /* br %r3 (go to TB) */
2362 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
2363
2364 tb_ret_addr = s->code_ptr;
2365
2366 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
2367 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
2368 frame_size + 48);
2369
2370 /* br %r14 (return) */
2371 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
2372 }
Qemu copy for testing