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1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "tcg/tcg.h"
27 #include "tcg/tcg-temp-internal.h"
28 #include "tcg/tcg-op-common.h"
29 #include "exec/translation-block.h"
30 #include "exec/plugin-gen.h"
31 #include "tcg-internal.h"
32
33
34 void tcg_gen_op1(TCGOpcode opc, TCGArg a1)
35 {
36 TCGOp *op = tcg_emit_op(opc, 1);
37 op->args[0] = a1;
38 }
39
40 void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
41 {
42 TCGOp *op = tcg_emit_op(opc, 2);
43 op->args[0] = a1;
44 op->args[1] = a2;
45 }
46
47 void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
48 {
49 TCGOp *op = tcg_emit_op(opc, 3);
50 op->args[0] = a1;
51 op->args[1] = a2;
52 op->args[2] = a3;
53 }
54
55 void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
56 {
57 TCGOp *op = tcg_emit_op(opc, 4);
58 op->args[0] = a1;
59 op->args[1] = a2;
60 op->args[2] = a3;
61 op->args[3] = a4;
62 }
63
64 void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
65 TCGArg a4, TCGArg a5)
66 {
67 TCGOp *op = tcg_emit_op(opc, 5);
68 op->args[0] = a1;
69 op->args[1] = a2;
70 op->args[2] = a3;
71 op->args[3] = a4;
72 op->args[4] = a5;
73 }
74
75 void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
76 TCGArg a4, TCGArg a5, TCGArg a6)
77 {
78 TCGOp *op = tcg_emit_op(opc, 6);
79 op->args[0] = a1;
80 op->args[1] = a2;
81 op->args[2] = a3;
82 op->args[3] = a4;
83 op->args[4] = a5;
84 op->args[5] = a6;
85 }
86
87 /* Generic ops. */
88
89 static void add_last_as_label_use(TCGLabel *l)
90 {
91 TCGLabelUse *u = tcg_malloc(sizeof(TCGLabelUse));
92
93 u->op = tcg_last_op();
94 QSIMPLEQ_INSERT_TAIL(&l->branches, u, next);
95 }
96
97 void tcg_gen_br(TCGLabel *l)
98 {
99 tcg_gen_op1(INDEX_op_br, label_arg(l));
100 add_last_as_label_use(l);
101 }
102
103 void tcg_gen_mb(TCGBar mb_type)
104 {
105 #ifdef CONFIG_USER_ONLY
106 bool parallel = tcg_ctx->gen_tb->cflags & CF_PARALLEL;
107 #else
108 /*
109 * It is tempting to elide the barrier in a uniprocessor context.
110 * However, even with a single cpu we have i/o threads running in
111 * parallel, and lack of memory order can result in e.g. virtio
112 * queue entries being read incorrectly.
113 */
114 bool parallel = true;
115 #endif
116
117 if (parallel) {
118 tcg_gen_op1(INDEX_op_mb, mb_type);
119 }
120 }
121
122 /* 32 bit ops */
123
124 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
125 {
126 tcg_gen_mov_i32(ret, tcg_constant_i32(arg));
127 }
128
129 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
130 {
131 /* some cases can be optimized here */
132 if (arg2 == 0) {
133 tcg_gen_mov_i32(ret, arg1);
134 } else {
135 tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2));
136 }
137 }
138
139 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
140 {
141 if (arg1 == 0 && TCG_TARGET_HAS_neg_i32) {
142 /* Don't recurse with tcg_gen_neg_i32. */
143 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2);
144 } else {
145 tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2);
146 }
147 }
148
149 void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
150 {
151 /* some cases can be optimized here */
152 if (arg2 == 0) {
153 tcg_gen_mov_i32(ret, arg1);
154 } else {
155 tcg_gen_sub_i32(ret, arg1, tcg_constant_i32(arg2));
156 }
157 }
158
159 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
160 {
161 /* Some cases can be optimized here. */
162 switch (arg2) {
163 case 0:
164 tcg_gen_movi_i32(ret, 0);
165 return;
166 case -1:
167 tcg_gen_mov_i32(ret, arg1);
168 return;
169 case 0xff:
170 /* Don't recurse with tcg_gen_ext8u_i32. */
171 if (TCG_TARGET_HAS_ext8u_i32) {
172 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
173 return;
174 }
175 break;
176 case 0xffff:
177 if (TCG_TARGET_HAS_ext16u_i32) {
178 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
179 return;
180 }
181 break;
182 }
183
184 tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2));
185 }
186
187 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
188 {
189 /* Some cases can be optimized here. */
190 if (arg2 == -1) {
191 tcg_gen_movi_i32(ret, -1);
192 } else if (arg2 == 0) {
193 tcg_gen_mov_i32(ret, arg1);
194 } else {
195 tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2));
196 }
197 }
198
199 void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
200 {
201 /* Some cases can be optimized here. */
202 if (arg2 == 0) {
203 tcg_gen_mov_i32(ret, arg1);
204 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
205 /* Don't recurse with tcg_gen_not_i32. */
206 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
207 } else {
208 tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2));
209 }
210 }
211
212 void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
213 {
214 tcg_debug_assert(arg2 >= 0 && arg2 < 32);
215 if (arg2 == 0) {
216 tcg_gen_mov_i32(ret, arg1);
217 } else {
218 tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2));
219 }
220 }
221
222 void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
223 {
224 tcg_debug_assert(arg2 >= 0 && arg2 < 32);
225 if (arg2 == 0) {
226 tcg_gen_mov_i32(ret, arg1);
227 } else {
228 tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2));
229 }
230 }
231
232 void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
233 {
234 tcg_debug_assert(arg2 >= 0 && arg2 < 32);
235 if (arg2 == 0) {
236 tcg_gen_mov_i32(ret, arg1);
237 } else {
238 tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2));
239 }
240 }
241
242 void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l)
243 {
244 if (cond == TCG_COND_ALWAYS) {
245 tcg_gen_br(l);
246 } else if (cond != TCG_COND_NEVER) {
247 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_arg(l));
248 add_last_as_label_use(l);
249 }
250 }
251
252 void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l)
253 {
254 if (cond == TCG_COND_ALWAYS) {
255 tcg_gen_br(l);
256 } else if (cond != TCG_COND_NEVER) {
257 tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l);
258 }
259 }
260
261 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
262 TCGv_i32 arg1, TCGv_i32 arg2)
263 {
264 if (cond == TCG_COND_ALWAYS) {
265 tcg_gen_movi_i32(ret, 1);
266 } else if (cond == TCG_COND_NEVER) {
267 tcg_gen_movi_i32(ret, 0);
268 } else {
269 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
270 }
271 }
272
273 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
274 TCGv_i32 arg1, int32_t arg2)
275 {
276 tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2));
277 }
278
279 void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret,
280 TCGv_i32 arg1, TCGv_i32 arg2)
281 {
282 if (cond == TCG_COND_ALWAYS) {
283 tcg_gen_movi_i32(ret, -1);
284 } else if (cond == TCG_COND_NEVER) {
285 tcg_gen_movi_i32(ret, 0);
286 } else if (TCG_TARGET_HAS_negsetcond_i32) {
287 tcg_gen_op4i_i32(INDEX_op_negsetcond_i32, ret, arg1, arg2, cond);
288 } else {
289 tcg_gen_setcond_i32(cond, ret, arg1, arg2);
290 tcg_gen_neg_i32(ret, ret);
291 }
292 }
293
294 void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
295 {
296 if (arg2 == 0) {
297 tcg_gen_movi_i32(ret, 0);
298 } else if (is_power_of_2(arg2)) {
299 tcg_gen_shli_i32(ret, arg1, ctz32(arg2));
300 } else {
301 tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2));
302 }
303 }
304
305 void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
306 {
307 if (TCG_TARGET_HAS_div_i32) {
308 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
309 } else if (TCG_TARGET_HAS_div2_i32) {
310 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
311 tcg_gen_sari_i32(t0, arg1, 31);
312 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
313 tcg_temp_free_i32(t0);
314 } else {
315 gen_helper_div_i32(ret, arg1, arg2);
316 }
317 }
318
319 void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
320 {
321 if (TCG_TARGET_HAS_rem_i32) {
322 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
323 } else if (TCG_TARGET_HAS_div_i32) {
324 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
325 tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
326 tcg_gen_mul_i32(t0, t0, arg2);
327 tcg_gen_sub_i32(ret, arg1, t0);
328 tcg_temp_free_i32(t0);
329 } else if (TCG_TARGET_HAS_div2_i32) {
330 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
331 tcg_gen_sari_i32(t0, arg1, 31);
332 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
333 tcg_temp_free_i32(t0);
334 } else {
335 gen_helper_rem_i32(ret, arg1, arg2);
336 }
337 }
338
339 void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
340 {
341 if (TCG_TARGET_HAS_div_i32) {
342 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
343 } else if (TCG_TARGET_HAS_div2_i32) {
344 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
345 tcg_gen_movi_i32(t0, 0);
346 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
347 tcg_temp_free_i32(t0);
348 } else {
349 gen_helper_divu_i32(ret, arg1, arg2);
350 }
351 }
352
353 void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
354 {
355 if (TCG_TARGET_HAS_rem_i32) {
356 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
357 } else if (TCG_TARGET_HAS_div_i32) {
358 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
359 tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
360 tcg_gen_mul_i32(t0, t0, arg2);
361 tcg_gen_sub_i32(ret, arg1, t0);
362 tcg_temp_free_i32(t0);
363 } else if (TCG_TARGET_HAS_div2_i32) {
364 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
365 tcg_gen_movi_i32(t0, 0);
366 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
367 tcg_temp_free_i32(t0);
368 } else {
369 gen_helper_remu_i32(ret, arg1, arg2);
370 }
371 }
372
373 void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
374 {
375 if (TCG_TARGET_HAS_andc_i32) {
376 tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
377 } else {
378 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
379 tcg_gen_not_i32(t0, arg2);
380 tcg_gen_and_i32(ret, arg1, t0);
381 tcg_temp_free_i32(t0);
382 }
383 }
384
385 void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
386 {
387 if (TCG_TARGET_HAS_eqv_i32) {
388 tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
389 } else {
390 tcg_gen_xor_i32(ret, arg1, arg2);
391 tcg_gen_not_i32(ret, ret);
392 }
393 }
394
395 void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
396 {
397 if (TCG_TARGET_HAS_nand_i32) {
398 tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
399 } else {
400 tcg_gen_and_i32(ret, arg1, arg2);
401 tcg_gen_not_i32(ret, ret);
402 }
403 }
404
405 void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
406 {
407 if (TCG_TARGET_HAS_nor_i32) {
408 tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
409 } else {
410 tcg_gen_or_i32(ret, arg1, arg2);
411 tcg_gen_not_i32(ret, ret);
412 }
413 }
414
415 void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
416 {
417 if (TCG_TARGET_HAS_orc_i32) {
418 tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
419 } else {
420 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
421 tcg_gen_not_i32(t0, arg2);
422 tcg_gen_or_i32(ret, arg1, t0);
423 tcg_temp_free_i32(t0);
424 }
425 }
426
427 void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
428 {
429 if (TCG_TARGET_HAS_clz_i32) {
430 tcg_gen_op3_i32(INDEX_op_clz_i32, ret, arg1, arg2);
431 } else if (TCG_TARGET_HAS_clz_i64) {
432 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
433 TCGv_i64 t2 = tcg_temp_ebb_new_i64();
434 tcg_gen_extu_i32_i64(t1, arg1);
435 tcg_gen_extu_i32_i64(t2, arg2);
436 tcg_gen_addi_i64(t2, t2, 32);
437 tcg_gen_clz_i64(t1, t1, t2);
438 tcg_gen_extrl_i64_i32(ret, t1);
439 tcg_temp_free_i64(t1);
440 tcg_temp_free_i64(t2);
441 tcg_gen_subi_i32(ret, ret, 32);
442 } else {
443 gen_helper_clz_i32(ret, arg1, arg2);
444 }
445 }
446
447 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
448 {
449 tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2));
450 }
451
452 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
453 {
454 if (TCG_TARGET_HAS_ctz_i32) {
455 tcg_gen_op3_i32(INDEX_op_ctz_i32, ret, arg1, arg2);
456 } else if (TCG_TARGET_HAS_ctz_i64) {
457 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
458 TCGv_i64 t2 = tcg_temp_ebb_new_i64();
459 tcg_gen_extu_i32_i64(t1, arg1);
460 tcg_gen_extu_i32_i64(t2, arg2);
461 tcg_gen_ctz_i64(t1, t1, t2);
462 tcg_gen_extrl_i64_i32(ret, t1);
463 tcg_temp_free_i64(t1);
464 tcg_temp_free_i64(t2);
465 } else if (TCG_TARGET_HAS_ctpop_i32
466 || TCG_TARGET_HAS_ctpop_i64
467 || TCG_TARGET_HAS_clz_i32
468 || TCG_TARGET_HAS_clz_i64) {
469 TCGv_i32 z, t = tcg_temp_ebb_new_i32();
470
471 if (TCG_TARGET_HAS_ctpop_i32 || TCG_TARGET_HAS_ctpop_i64) {
472 tcg_gen_subi_i32(t, arg1, 1);
473 tcg_gen_andc_i32(t, t, arg1);
474 tcg_gen_ctpop_i32(t, t);
475 } else {
476 /* Since all non-x86 hosts have clz(0) == 32, don't fight it. */
477 tcg_gen_neg_i32(t, arg1);
478 tcg_gen_and_i32(t, t, arg1);
479 tcg_gen_clzi_i32(t, t, 32);
480 tcg_gen_xori_i32(t, t, 31);
481 }
482 z = tcg_constant_i32(0);
483 tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t);
484 tcg_temp_free_i32(t);
485 } else {
486 gen_helper_ctz_i32(ret, arg1, arg2);
487 }
488 }
489
490 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
491 {
492 if (!TCG_TARGET_HAS_ctz_i32 && TCG_TARGET_HAS_ctpop_i32 && arg2 == 32) {
493 /* This equivalence has the advantage of not requiring a fixup. */
494 TCGv_i32 t = tcg_temp_ebb_new_i32();
495 tcg_gen_subi_i32(t, arg1, 1);
496 tcg_gen_andc_i32(t, t, arg1);
497 tcg_gen_ctpop_i32(ret, t);
498 tcg_temp_free_i32(t);
499 } else {
500 tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2));
501 }
502 }
503
504 void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg)
505 {
506 if (TCG_TARGET_HAS_clz_i32) {
507 TCGv_i32 t = tcg_temp_ebb_new_i32();
508 tcg_gen_sari_i32(t, arg, 31);
509 tcg_gen_xor_i32(t, t, arg);
510 tcg_gen_clzi_i32(t, t, 32);
511 tcg_gen_subi_i32(ret, t, 1);
512 tcg_temp_free_i32(t);
513 } else {
514 gen_helper_clrsb_i32(ret, arg);
515 }
516 }
517
518 void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1)
519 {
520 if (TCG_TARGET_HAS_ctpop_i32) {
521 tcg_gen_op2_i32(INDEX_op_ctpop_i32, ret, arg1);
522 } else if (TCG_TARGET_HAS_ctpop_i64) {
523 TCGv_i64 t = tcg_temp_ebb_new_i64();
524 tcg_gen_extu_i32_i64(t, arg1);
525 tcg_gen_ctpop_i64(t, t);
526 tcg_gen_extrl_i64_i32(ret, t);
527 tcg_temp_free_i64(t);
528 } else {
529 gen_helper_ctpop_i32(ret, arg1);
530 }
531 }
532
533 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
534 {
535 if (TCG_TARGET_HAS_rot_i32) {
536 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
537 } else {
538 TCGv_i32 t0, t1;
539
540 t0 = tcg_temp_ebb_new_i32();
541 t1 = tcg_temp_ebb_new_i32();
542 tcg_gen_shl_i32(t0, arg1, arg2);
543 tcg_gen_subfi_i32(t1, 32, arg2);
544 tcg_gen_shr_i32(t1, arg1, t1);
545 tcg_gen_or_i32(ret, t0, t1);
546 tcg_temp_free_i32(t0);
547 tcg_temp_free_i32(t1);
548 }
549 }
550
551 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
552 {
553 tcg_debug_assert(arg2 >= 0 && arg2 < 32);
554 /* some cases can be optimized here */
555 if (arg2 == 0) {
556 tcg_gen_mov_i32(ret, arg1);
557 } else if (TCG_TARGET_HAS_rot_i32) {
558 tcg_gen_rotl_i32(ret, arg1, tcg_constant_i32(arg2));
559 } else {
560 TCGv_i32 t0, t1;
561 t0 = tcg_temp_ebb_new_i32();
562 t1 = tcg_temp_ebb_new_i32();
563 tcg_gen_shli_i32(t0, arg1, arg2);
564 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
565 tcg_gen_or_i32(ret, t0, t1);
566 tcg_temp_free_i32(t0);
567 tcg_temp_free_i32(t1);
568 }
569 }
570
571 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
572 {
573 if (TCG_TARGET_HAS_rot_i32) {
574 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
575 } else {
576 TCGv_i32 t0, t1;
577
578 t0 = tcg_temp_ebb_new_i32();
579 t1 = tcg_temp_ebb_new_i32();
580 tcg_gen_shr_i32(t0, arg1, arg2);
581 tcg_gen_subfi_i32(t1, 32, arg2);
582 tcg_gen_shl_i32(t1, arg1, t1);
583 tcg_gen_or_i32(ret, t0, t1);
584 tcg_temp_free_i32(t0);
585 tcg_temp_free_i32(t1);
586 }
587 }
588
589 void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
590 {
591 tcg_debug_assert(arg2 >= 0 && arg2 < 32);
592 /* some cases can be optimized here */
593 if (arg2 == 0) {
594 tcg_gen_mov_i32(ret, arg1);
595 } else {
596 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
597 }
598 }
599
600 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
601 unsigned int ofs, unsigned int len)
602 {
603 uint32_t mask;
604 TCGv_i32 t1;
605
606 tcg_debug_assert(ofs < 32);
607 tcg_debug_assert(len > 0);
608 tcg_debug_assert(len <= 32);
609 tcg_debug_assert(ofs + len <= 32);
610
611 if (len == 32) {
612 tcg_gen_mov_i32(ret, arg2);
613 return;
614 }
615 if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
616 tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
617 return;
618 }
619
620 t1 = tcg_temp_ebb_new_i32();
621
622 if (TCG_TARGET_HAS_extract2_i32) {
623 if (ofs + len == 32) {
624 tcg_gen_shli_i32(t1, arg1, len);
625 tcg_gen_extract2_i32(ret, t1, arg2, len);
626 goto done;
627 }
628 if (ofs == 0) {
629 tcg_gen_extract2_i32(ret, arg1, arg2, len);
630 tcg_gen_rotli_i32(ret, ret, len);
631 goto done;
632 }
633 }
634
635 mask = (1u << len) - 1;
636 if (ofs + len < 32) {
637 tcg_gen_andi_i32(t1, arg2, mask);
638 tcg_gen_shli_i32(t1, t1, ofs);
639 } else {
640 tcg_gen_shli_i32(t1, arg2, ofs);
641 }
642 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
643 tcg_gen_or_i32(ret, ret, t1);
644 done:
645 tcg_temp_free_i32(t1);
646 }
647
648 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
649 unsigned int ofs, unsigned int len)
650 {
651 tcg_debug_assert(ofs < 32);
652 tcg_debug_assert(len > 0);
653 tcg_debug_assert(len <= 32);
654 tcg_debug_assert(ofs + len <= 32);
655
656 if (ofs + len == 32) {
657 tcg_gen_shli_i32(ret, arg, ofs);
658 } else if (ofs == 0) {
659 tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
660 } else if (TCG_TARGET_HAS_deposit_i32
661 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
662 TCGv_i32 zero = tcg_constant_i32(0);
663 tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len);
664 } else {
665 /* To help two-operand hosts we prefer to zero-extend first,
666 which allows ARG to stay live. */
667 switch (len) {
668 case 16:
669 if (TCG_TARGET_HAS_ext16u_i32) {
670 tcg_gen_ext16u_i32(ret, arg);
671 tcg_gen_shli_i32(ret, ret, ofs);
672 return;
673 }
674 break;
675 case 8:
676 if (TCG_TARGET_HAS_ext8u_i32) {
677 tcg_gen_ext8u_i32(ret, arg);
678 tcg_gen_shli_i32(ret, ret, ofs);
679 return;
680 }
681 break;
682 }
683 /* Otherwise prefer zero-extension over AND for code size. */
684 switch (ofs + len) {
685 case 16:
686 if (TCG_TARGET_HAS_ext16u_i32) {
687 tcg_gen_shli_i32(ret, arg, ofs);
688 tcg_gen_ext16u_i32(ret, ret);
689 return;
690 }
691 break;
692 case 8:
693 if (TCG_TARGET_HAS_ext8u_i32) {
694 tcg_gen_shli_i32(ret, arg, ofs);
695 tcg_gen_ext8u_i32(ret, ret);
696 return;
697 }
698 break;
699 }
700 tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
701 tcg_gen_shli_i32(ret, ret, ofs);
702 }
703 }
704
705 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
706 unsigned int ofs, unsigned int len)
707 {
708 tcg_debug_assert(ofs < 32);
709 tcg_debug_assert(len > 0);
710 tcg_debug_assert(len <= 32);
711 tcg_debug_assert(ofs + len <= 32);
712
713 /* Canonicalize certain special cases, even if extract is supported. */
714 if (ofs + len == 32) {
715 tcg_gen_shri_i32(ret, arg, 32 - len);
716 return;
717 }
718 if (ofs == 0) {
719 tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
720 return;
721 }
722
723 if (TCG_TARGET_HAS_extract_i32
724 && TCG_TARGET_extract_i32_valid(ofs, len)) {
725 tcg_gen_op4ii_i32(INDEX_op_extract_i32, ret, arg, ofs, len);
726 return;
727 }
728
729 /* Assume that zero-extension, if available, is cheaper than a shift. */
730 switch (ofs + len) {
731 case 16:
732 if (TCG_TARGET_HAS_ext16u_i32) {
733 tcg_gen_ext16u_i32(ret, arg);
734 tcg_gen_shri_i32(ret, ret, ofs);
735 return;
736 }
737 break;
738 case 8:
739 if (TCG_TARGET_HAS_ext8u_i32) {
740 tcg_gen_ext8u_i32(ret, arg);
741 tcg_gen_shri_i32(ret, ret, ofs);
742 return;
743 }
744 break;
745 }
746
747 /* ??? Ideally we'd know what values are available for immediate AND.
748 Assume that 8 bits are available, plus the special case of 16,
749 so that we get ext8u, ext16u. */
750 switch (len) {
751 case 1 ... 8: case 16:
752 tcg_gen_shri_i32(ret, arg, ofs);
753 tcg_gen_andi_i32(ret, ret, (1u << len) - 1);
754 break;
755 default:
756 tcg_gen_shli_i32(ret, arg, 32 - len - ofs);
757 tcg_gen_shri_i32(ret, ret, 32 - len);
758 break;
759 }
760 }
761
762 void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
763 unsigned int ofs, unsigned int len)
764 {
765 tcg_debug_assert(ofs < 32);
766 tcg_debug_assert(len > 0);
767 tcg_debug_assert(len <= 32);
768 tcg_debug_assert(ofs + len <= 32);
769
770 /* Canonicalize certain special cases, even if extract is supported. */
771 if (ofs + len == 32) {
772 tcg_gen_sari_i32(ret, arg, 32 - len);
773 return;
774 }
775 if (ofs == 0) {
776 switch (len) {
777 case 16:
778 tcg_gen_ext16s_i32(ret, arg);
779 return;
780 case 8:
781 tcg_gen_ext8s_i32(ret, arg);
782 return;
783 }
784 }
785
786 if (TCG_TARGET_HAS_sextract_i32
787 && TCG_TARGET_extract_i32_valid(ofs, len)) {
788 tcg_gen_op4ii_i32(INDEX_op_sextract_i32, ret, arg, ofs, len);
789 return;
790 }
791
792 /* Assume that sign-extension, if available, is cheaper than a shift. */
793 switch (ofs + len) {
794 case 16:
795 if (TCG_TARGET_HAS_ext16s_i32) {
796 tcg_gen_ext16s_i32(ret, arg);
797 tcg_gen_sari_i32(ret, ret, ofs);
798 return;
799 }
800 break;
801 case 8:
802 if (TCG_TARGET_HAS_ext8s_i32) {
803 tcg_gen_ext8s_i32(ret, arg);
804 tcg_gen_sari_i32(ret, ret, ofs);
805 return;
806 }
807 break;
808 }
809 switch (len) {
810 case 16:
811 if (TCG_TARGET_HAS_ext16s_i32) {
812 tcg_gen_shri_i32(ret, arg, ofs);
813 tcg_gen_ext16s_i32(ret, ret);
814 return;
815 }
816 break;
817 case 8:
818 if (TCG_TARGET_HAS_ext8s_i32) {
819 tcg_gen_shri_i32(ret, arg, ofs);
820 tcg_gen_ext8s_i32(ret, ret);
821 return;
822 }
823 break;
824 }
825
826 tcg_gen_shli_i32(ret, arg, 32 - len - ofs);
827 tcg_gen_sari_i32(ret, ret, 32 - len);
828 }
829
830 /*
831 * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
832 * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
833 */
834 void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
835 unsigned int ofs)
836 {
837 tcg_debug_assert(ofs <= 32);
838 if (ofs == 0) {
839 tcg_gen_mov_i32(ret, al);
840 } else if (ofs == 32) {
841 tcg_gen_mov_i32(ret, ah);
842 } else if (al == ah) {
843 tcg_gen_rotri_i32(ret, al, ofs);
844 } else if (TCG_TARGET_HAS_extract2_i32) {
845 tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
846 } else {
847 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
848 tcg_gen_shri_i32(t0, al, ofs);
849 tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
850 tcg_temp_free_i32(t0);
851 }
852 }
853
854 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
855 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
856 {
857 if (cond == TCG_COND_ALWAYS) {
858 tcg_gen_mov_i32(ret, v1);
859 } else if (cond == TCG_COND_NEVER) {
860 tcg_gen_mov_i32(ret, v2);
861 } else if (TCG_TARGET_HAS_movcond_i32) {
862 tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
863 } else {
864 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
865 TCGv_i32 t1 = tcg_temp_ebb_new_i32();
866 tcg_gen_negsetcond_i32(cond, t0, c1, c2);
867 tcg_gen_and_i32(t1, v1, t0);
868 tcg_gen_andc_i32(ret, v2, t0);
869 tcg_gen_or_i32(ret, ret, t1);
870 tcg_temp_free_i32(t0);
871 tcg_temp_free_i32(t1);
872 }
873 }
874
875 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
876 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
877 {
878 if (TCG_TARGET_HAS_add2_i32) {
879 tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh);
880 } else {
881 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
882 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
883 tcg_gen_concat_i32_i64(t0, al, ah);
884 tcg_gen_concat_i32_i64(t1, bl, bh);
885 tcg_gen_add_i64(t0, t0, t1);
886 tcg_gen_extr_i64_i32(rl, rh, t0);
887 tcg_temp_free_i64(t0);
888 tcg_temp_free_i64(t1);
889 }
890 }
891
892 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
893 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
894 {
895 if (TCG_TARGET_HAS_sub2_i32) {
896 tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh);
897 } else {
898 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
899 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
900 tcg_gen_concat_i32_i64(t0, al, ah);
901 tcg_gen_concat_i32_i64(t1, bl, bh);
902 tcg_gen_sub_i64(t0, t0, t1);
903 tcg_gen_extr_i64_i32(rl, rh, t0);
904 tcg_temp_free_i64(t0);
905 tcg_temp_free_i64(t1);
906 }
907 }
908
909 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
910 {
911 if (TCG_TARGET_HAS_mulu2_i32) {
912 tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
913 } else if (TCG_TARGET_HAS_muluh_i32) {
914 TCGv_i32 t = tcg_temp_ebb_new_i32();
915 tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
916 tcg_gen_op3_i32(INDEX_op_muluh_i32, rh, arg1, arg2);
917 tcg_gen_mov_i32(rl, t);
918 tcg_temp_free_i32(t);
919 } else if (TCG_TARGET_REG_BITS == 64) {
920 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
921 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
922 tcg_gen_extu_i32_i64(t0, arg1);
923 tcg_gen_extu_i32_i64(t1, arg2);
924 tcg_gen_mul_i64(t0, t0, t1);
925 tcg_gen_extr_i64_i32(rl, rh, t0);
926 tcg_temp_free_i64(t0);
927 tcg_temp_free_i64(t1);
928 } else {
929 qemu_build_not_reached();
930 }
931 }
932
933 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
934 {
935 if (TCG_TARGET_HAS_muls2_i32) {
936 tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
937 } else if (TCG_TARGET_HAS_mulsh_i32) {
938 TCGv_i32 t = tcg_temp_ebb_new_i32();
939 tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
940 tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
941 tcg_gen_mov_i32(rl, t);
942 tcg_temp_free_i32(t);
943 } else if (TCG_TARGET_REG_BITS == 32) {
944 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
945 TCGv_i32 t1 = tcg_temp_ebb_new_i32();
946 TCGv_i32 t2 = tcg_temp_ebb_new_i32();
947 TCGv_i32 t3 = tcg_temp_ebb_new_i32();
948 tcg_gen_mulu2_i32(t0, t1, arg1, arg2);
949 /* Adjust for negative inputs. */
950 tcg_gen_sari_i32(t2, arg1, 31);
951 tcg_gen_sari_i32(t3, arg2, 31);
952 tcg_gen_and_i32(t2, t2, arg2);
953 tcg_gen_and_i32(t3, t3, arg1);
954 tcg_gen_sub_i32(rh, t1, t2);
955 tcg_gen_sub_i32(rh, rh, t3);
956 tcg_gen_mov_i32(rl, t0);
957 tcg_temp_free_i32(t0);
958 tcg_temp_free_i32(t1);
959 tcg_temp_free_i32(t2);
960 tcg_temp_free_i32(t3);
961 } else {
962 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
963 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
964 tcg_gen_ext_i32_i64(t0, arg1);
965 tcg_gen_ext_i32_i64(t1, arg2);
966 tcg_gen_mul_i64(t0, t0, t1);
967 tcg_gen_extr_i64_i32(rl, rh, t0);
968 tcg_temp_free_i64(t0);
969 tcg_temp_free_i64(t1);
970 }
971 }
972
973 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
974 {
975 if (TCG_TARGET_REG_BITS == 32) {
976 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
977 TCGv_i32 t1 = tcg_temp_ebb_new_i32();
978 TCGv_i32 t2 = tcg_temp_ebb_new_i32();
979 tcg_gen_mulu2_i32(t0, t1, arg1, arg2);
980 /* Adjust for negative input for the signed arg1. */
981 tcg_gen_sari_i32(t2, arg1, 31);
982 tcg_gen_and_i32(t2, t2, arg2);
983 tcg_gen_sub_i32(rh, t1, t2);
984 tcg_gen_mov_i32(rl, t0);
985 tcg_temp_free_i32(t0);
986 tcg_temp_free_i32(t1);
987 tcg_temp_free_i32(t2);
988 } else {
989 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
990 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
991 tcg_gen_ext_i32_i64(t0, arg1);
992 tcg_gen_extu_i32_i64(t1, arg2);
993 tcg_gen_mul_i64(t0, t0, t1);
994 tcg_gen_extr_i64_i32(rl, rh, t0);
995 tcg_temp_free_i64(t0);
996 tcg_temp_free_i64(t1);
997 }
998 }
999
1000 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1001 {
1002 if (TCG_TARGET_HAS_ext8s_i32) {
1003 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1004 } else {
1005 tcg_gen_shli_i32(ret, arg, 24);
1006 tcg_gen_sari_i32(ret, ret, 24);
1007 }
1008 }
1009
1010 void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1011 {
1012 if (TCG_TARGET_HAS_ext16s_i32) {
1013 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1014 } else {
1015 tcg_gen_shli_i32(ret, arg, 16);
1016 tcg_gen_sari_i32(ret, ret, 16);
1017 }
1018 }
1019
1020 void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1021 {
1022 if (TCG_TARGET_HAS_ext8u_i32) {
1023 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1024 } else {
1025 tcg_gen_andi_i32(ret, arg, 0xffu);
1026 }
1027 }
1028
1029 void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1030 {
1031 if (TCG_TARGET_HAS_ext16u_i32) {
1032 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1033 } else {
1034 tcg_gen_andi_i32(ret, arg, 0xffffu);
1035 }
1036 }
1037
1038 /*
1039 * bswap16_i32: 16-bit byte swap on the low bits of a 32-bit value.
1040 *
1041 * Byte pattern: xxab -> yyba
1042 *
1043 * With TCG_BSWAP_IZ, x == zero, else undefined.
1044 * With TCG_BSWAP_OZ, y == zero, with TCG_BSWAP_OS y == sign, else undefined.
1045 */
1046 void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
1047 {
1048 /* Only one extension flag may be present. */
1049 tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
1050
1051 if (TCG_TARGET_HAS_bswap16_i32) {
1052 tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg, flags);
1053 } else {
1054 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
1055 TCGv_i32 t1 = tcg_temp_ebb_new_i32();
1056
1057 /* arg = ..ab (IZ) xxab (!IZ) */
1058 tcg_gen_shri_i32(t0, arg, 8); /* t0 = ...a (IZ) .xxa (!IZ) */
1059 if (!(flags & TCG_BSWAP_IZ)) {
1060 tcg_gen_ext8u_i32(t0, t0); /* t0 = ...a */
1061 }
1062
1063 if (flags & TCG_BSWAP_OS) {
1064 tcg_gen_shli_i32(t1, arg, 24); /* t1 = b... */
1065 tcg_gen_sari_i32(t1, t1, 16); /* t1 = ssb. */
1066 } else if (flags & TCG_BSWAP_OZ) {
1067 tcg_gen_ext8u_i32(t1, arg); /* t1 = ...b */
1068 tcg_gen_shli_i32(t1, t1, 8); /* t1 = ..b. */
1069 } else {
1070 tcg_gen_shli_i32(t1, arg, 8); /* t1 = xab. */
1071 }
1072
1073 tcg_gen_or_i32(ret, t0, t1); /* ret = ..ba (OZ) */
1074 /* = ssba (OS) */
1075 /* = xaba (no flag) */
1076 tcg_temp_free_i32(t0);
1077 tcg_temp_free_i32(t1);
1078 }
1079 }
1080
1081 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1082 {
1083 if (TCG_TARGET_HAS_bswap32_i32) {
1084 tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
1085 } else {
1086 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
1087 TCGv_i32 t1 = tcg_temp_ebb_new_i32();
1088 TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff);
1089
1090 /* arg = abcd */
1091 tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */
1092 tcg_gen_and_i32(t1, arg, t2); /* t1 = .b.d */
1093 tcg_gen_and_i32(t0, t0, t2); /* t0 = .a.c */
1094 tcg_gen_shli_i32(t1, t1, 8); /* t1 = b.d. */
1095 tcg_gen_or_i32(ret, t0, t1); /* ret = badc */
1096
1097 tcg_gen_shri_i32(t0, ret, 16); /* t0 = ..ba */
1098 tcg_gen_shli_i32(t1, ret, 16); /* t1 = dc.. */
1099 tcg_gen_or_i32(ret, t0, t1); /* ret = dcba */
1100
1101 tcg_temp_free_i32(t0);
1102 tcg_temp_free_i32(t1);
1103 }
1104 }
1105
1106 void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg)
1107 {
1108 /* Swapping 2 16-bit elements is a rotate. */
1109 tcg_gen_rotli_i32(ret, arg, 16);
1110 }
1111
1112 void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
1113 {
1114 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b);
1115 }
1116
1117 void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
1118 {
1119 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b);
1120 }
1121
1122 void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
1123 {
1124 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a);
1125 }
1126
1127 void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
1128 {
1129 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a);
1130 }
1131
1132 void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a)
1133 {
1134 TCGv_i32 t = tcg_temp_ebb_new_i32();
1135
1136 tcg_gen_sari_i32(t, a, 31);
1137 tcg_gen_xor_i32(ret, a, t);
1138 tcg_gen_sub_i32(ret, ret, t);
1139 tcg_temp_free_i32(t);
1140 }
1141
1142 /* 64-bit ops */
1143
1144 #if TCG_TARGET_REG_BITS == 32
1145 /* These are all inline for TCG_TARGET_REG_BITS == 64. */
1146
1147 void tcg_gen_discard_i64(TCGv_i64 arg)
1148 {
1149 tcg_gen_discard_i32(TCGV_LOW(arg));
1150 tcg_gen_discard_i32(TCGV_HIGH(arg));
1151 }
1152
1153 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1154 {
1155 TCGTemp *ts = tcgv_i64_temp(arg);
1156
1157 /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */
1158 if (ts->kind == TEMP_CONST) {
1159 tcg_gen_movi_i64(ret, ts->val);
1160 } else {
1161 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1162 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1163 }
1164 }
1165
1166 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1167 {
1168 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
1169 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
1170 }
1171
1172 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1173 {
1174 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
1175 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1176 }
1177
1178 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1179 {
1180 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
1181 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1182 }
1183
1184 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1185 {
1186 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
1187 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1188 }
1189
1190 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1191 {
1192 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
1193 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1194 }
1195
1196 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1197 {
1198 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
1199 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1200 }
1201
1202 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1203 {
1204 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
1205 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1206 }
1207
1208 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1209 {
1210 /* Since arg2 and ret have different types,
1211 they cannot be the same temporary */
1212 #if HOST_BIG_ENDIAN
1213 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
1214 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
1215 #else
1216 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
1217 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
1218 #endif
1219 }
1220
1221 void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1222 {
1223 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
1224 }
1225
1226 void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1227 {
1228 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
1229 }
1230
1231 void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1232 {
1233 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
1234 }
1235
1236 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1237 {
1238 #if HOST_BIG_ENDIAN
1239 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
1240 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
1241 #else
1242 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
1243 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
1244 #endif
1245 }
1246
1247 void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1248 {
1249 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
1250 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
1251 }
1252
1253 void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1254 {
1255 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
1256 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
1257 }
1258
1259 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1260 {
1261 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1262 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1263 }
1264
1265 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1266 {
1267 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1268 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1269 }
1270
1271 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1272 {
1273 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1274 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1275 }
1276
1277 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1278 {
1279 gen_helper_shl_i64(ret, arg1, arg2);
1280 }
1281
1282 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1283 {
1284 gen_helper_shr_i64(ret, arg1, arg2);
1285 }
1286
1287 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1288 {
1289 gen_helper_sar_i64(ret, arg1, arg2);
1290 }
1291
1292 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1293 {
1294 TCGv_i64 t0;
1295 TCGv_i32 t1;
1296
1297 t0 = tcg_temp_ebb_new_i64();
1298 t1 = tcg_temp_ebb_new_i32();
1299
1300 tcg_gen_mulu2_i32(TCGV_LOW(t0), TCGV_HIGH(t0),
1301 TCGV_LOW(arg1), TCGV_LOW(arg2));
1302
1303 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1304 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1305 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1306 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1307
1308 tcg_gen_mov_i64(ret, t0);
1309 tcg_temp_free_i64(t0);
1310 tcg_temp_free_i32(t1);
1311 }
1312
1313 #else
1314
1315 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1316 {
1317 tcg_gen_mov_i64(ret, tcg_constant_i64(arg));
1318 }
1319
1320 #endif /* TCG_TARGET_REG_SIZE == 32 */
1321
1322 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1323 {
1324 /* some cases can be optimized here */
1325 if (arg2 == 0) {
1326 tcg_gen_mov_i64(ret, arg1);
1327 } else if (TCG_TARGET_REG_BITS == 64) {
1328 tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2));
1329 } else {
1330 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
1331 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1332 tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32));
1333 }
1334 }
1335
1336 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1337 {
1338 if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) {
1339 /* Don't recurse with tcg_gen_neg_i64. */
1340 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2);
1341 } else if (TCG_TARGET_REG_BITS == 64) {
1342 tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2);
1343 } else {
1344 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
1345 tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> 32),
1346 TCGV_LOW(arg2), TCGV_HIGH(arg2));
1347 }
1348 }
1349
1350 void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1351 {
1352 /* some cases can be optimized here */
1353 if (arg2 == 0) {
1354 tcg_gen_mov_i64(ret, arg1);
1355 } else if (TCG_TARGET_REG_BITS == 64) {
1356 tcg_gen_sub_i64(ret, arg1, tcg_constant_i64(arg2));
1357 } else {
1358 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
1359 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1360 tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32));
1361 }
1362 }
1363
1364 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1365 {
1366 if (TCG_TARGET_REG_BITS == 32) {
1367 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
1368 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
1369 return;
1370 }
1371
1372 /* Some cases can be optimized here. */
1373 switch (arg2) {
1374 case 0:
1375 tcg_gen_movi_i64(ret, 0);
1376 return;
1377 case -1:
1378 tcg_gen_mov_i64(ret, arg1);
1379 return;
1380 case 0xff:
1381 /* Don't recurse with tcg_gen_ext8u_i64. */
1382 if (TCG_TARGET_HAS_ext8u_i64) {
1383 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
1384 return;
1385 }
1386 break;
1387 case 0xffff:
1388 if (TCG_TARGET_HAS_ext16u_i64) {
1389 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
1390 return;
1391 }
1392 break;
1393 case 0xffffffffu:
1394 if (TCG_TARGET_HAS_ext32u_i64) {
1395 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
1396 return;
1397 }
1398 break;
1399 }
1400
1401 tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2));
1402 }
1403
1404 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1405 {
1406 if (TCG_TARGET_REG_BITS == 32) {
1407 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
1408 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
1409 return;
1410 }
1411 /* Some cases can be optimized here. */
1412 if (arg2 == -1) {
1413 tcg_gen_movi_i64(ret, -1);
1414 } else if (arg2 == 0) {
1415 tcg_gen_mov_i64(ret, arg1);
1416 } else {
1417 tcg_gen_or_i64(ret, arg1, tcg_constant_i64(arg2));
1418 }
1419 }
1420
1421 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1422 {
1423 if (TCG_TARGET_REG_BITS == 32) {
1424 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
1425 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
1426 return;
1427 }
1428 /* Some cases can be optimized here. */
1429 if (arg2 == 0) {
1430 tcg_gen_mov_i64(ret, arg1);
1431 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
1432 /* Don't recurse with tcg_gen_not_i64. */
1433 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
1434 } else {
1435 tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2));
1436 }
1437 }
1438
1439 static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
1440 unsigned c, bool right, bool arith)
1441 {
1442 tcg_debug_assert(c < 64);
1443 if (c == 0) {
1444 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
1445 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
1446 } else if (c >= 32) {
1447 c -= 32;
1448 if (right) {
1449 if (arith) {
1450 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
1451 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
1452 } else {
1453 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
1454 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1455 }
1456 } else {
1457 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
1458 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
1459 }
1460 } else if (right) {
1461 if (TCG_TARGET_HAS_extract2_i32) {
1462 tcg_gen_extract2_i32(TCGV_LOW(ret),
1463 TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
1464 } else {
1465 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
1466 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
1467 TCGV_HIGH(arg1), 32 - c, c);
1468 }
1469 if (arith) {
1470 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
1471 } else {
1472 tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
1473 }
1474 } else {
1475 if (TCG_TARGET_HAS_extract2_i32) {
1476 tcg_gen_extract2_i32(TCGV_HIGH(ret),
1477 TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
1478 } else {
1479 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
1480 tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
1481 tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
1482 TCGV_HIGH(arg1), c, 32 - c);
1483 tcg_temp_free_i32(t0);
1484 }
1485 tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
1486 }
1487 }
1488
1489 void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1490 {
1491 tcg_debug_assert(arg2 >= 0 && arg2 < 64);
1492 if (TCG_TARGET_REG_BITS == 32) {
1493 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
1494 } else if (arg2 == 0) {
1495 tcg_gen_mov_i64(ret, arg1);
1496 } else {
1497 tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2));
1498 }
1499 }
1500
1501 void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1502 {
1503 tcg_debug_assert(arg2 >= 0 && arg2 < 64);
1504 if (TCG_TARGET_REG_BITS == 32) {
1505 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
1506 } else if (arg2 == 0) {
1507 tcg_gen_mov_i64(ret, arg1);
1508 } else {
1509 tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2));
1510 }
1511 }
1512
1513 void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1514 {
1515 tcg_debug_assert(arg2 >= 0 && arg2 < 64);
1516 if (TCG_TARGET_REG_BITS == 32) {
1517 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
1518 } else if (arg2 == 0) {
1519 tcg_gen_mov_i64(ret, arg1);
1520 } else {
1521 tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2));
1522 }
1523 }
1524
1525 void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l)
1526 {
1527 if (cond == TCG_COND_ALWAYS) {
1528 tcg_gen_br(l);
1529 } else if (cond != TCG_COND_NEVER) {
1530 if (TCG_TARGET_REG_BITS == 32) {
1531 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1),
1532 TCGV_HIGH(arg1), TCGV_LOW(arg2),
1533 TCGV_HIGH(arg2), cond, label_arg(l));
1534 } else {
1535 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond,
1536 label_arg(l));
1537 }
1538 add_last_as_label_use(l);
1539 }
1540 }
1541
1542 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l)
1543 {
1544 if (TCG_TARGET_REG_BITS == 64) {
1545 tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l);
1546 } else if (cond == TCG_COND_ALWAYS) {
1547 tcg_gen_br(l);
1548 } else if (cond != TCG_COND_NEVER) {
1549 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
1550 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1551 tcg_constant_i32(arg2),
1552 tcg_constant_i32(arg2 >> 32),
1553 cond, label_arg(l));
1554 add_last_as_label_use(l);
1555 }
1556 }
1557
1558 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1559 TCGv_i64 arg1, TCGv_i64 arg2)
1560 {
1561 if (cond == TCG_COND_ALWAYS) {
1562 tcg_gen_movi_i64(ret, 1);
1563 } else if (cond == TCG_COND_NEVER) {
1564 tcg_gen_movi_i64(ret, 0);
1565 } else {
1566 if (TCG_TARGET_REG_BITS == 32) {
1567 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1568 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1569 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1570 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1571 } else {
1572 tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1573 }
1574 }
1575 }
1576
1577 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1578 TCGv_i64 arg1, int64_t arg2)
1579 {
1580 if (TCG_TARGET_REG_BITS == 64) {
1581 tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2));
1582 } else if (cond == TCG_COND_ALWAYS) {
1583 tcg_gen_movi_i64(ret, 1);
1584 } else if (cond == TCG_COND_NEVER) {
1585 tcg_gen_movi_i64(ret, 0);
1586 } else {
1587 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1588 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1589 tcg_constant_i32(arg2),
1590 tcg_constant_i32(arg2 >> 32), cond);
1591 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1592 }
1593 }
1594
1595 void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret,
1596 TCGv_i64 arg1, TCGv_i64 arg2)
1597 {
1598 if (cond == TCG_COND_ALWAYS) {
1599 tcg_gen_movi_i64(ret, -1);
1600 } else if (cond == TCG_COND_NEVER) {
1601 tcg_gen_movi_i64(ret, 0);
1602 } else if (TCG_TARGET_HAS_negsetcond_i64) {
1603 tcg_gen_op4i_i64(INDEX_op_negsetcond_i64, ret, arg1, arg2, cond);
1604 } else if (TCG_TARGET_REG_BITS == 32) {
1605 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1606 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1607 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1608 tcg_gen_neg_i32(TCGV_LOW(ret), TCGV_LOW(ret));
1609 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_LOW(ret));
1610 } else {
1611 tcg_gen_setcond_i64(cond, ret, arg1, arg2);
1612 tcg_gen_neg_i64(ret, ret);
1613 }
1614 }
1615
1616 void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1617 {
1618 if (arg2 == 0) {
1619 tcg_gen_movi_i64(ret, 0);
1620 } else if (is_power_of_2(arg2)) {
1621 tcg_gen_shli_i64(ret, arg1, ctz64(arg2));
1622 } else {
1623 tcg_gen_mul_i64(ret, arg1, tcg_constant_i64(arg2));
1624 }
1625 }
1626
1627 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1628 {
1629 if (TCG_TARGET_HAS_div_i64) {
1630 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1631 } else if (TCG_TARGET_HAS_div2_i64) {
1632 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1633 tcg_gen_sari_i64(t0, arg1, 63);
1634 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1635 tcg_temp_free_i64(t0);
1636 } else {
1637 gen_helper_div_i64(ret, arg1, arg2);
1638 }
1639 }
1640
1641 void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1642 {
1643 if (TCG_TARGET_HAS_rem_i64) {
1644 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1645 } else if (TCG_TARGET_HAS_div_i64) {
1646 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1647 tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
1648 tcg_gen_mul_i64(t0, t0, arg2);
1649 tcg_gen_sub_i64(ret, arg1, t0);
1650 tcg_temp_free_i64(t0);
1651 } else if (TCG_TARGET_HAS_div2_i64) {
1652 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1653 tcg_gen_sari_i64(t0, arg1, 63);
1654 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1655 tcg_temp_free_i64(t0);
1656 } else {
1657 gen_helper_rem_i64(ret, arg1, arg2);
1658 }
1659 }
1660
1661 void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1662 {
1663 if (TCG_TARGET_HAS_div_i64) {
1664 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1665 } else if (TCG_TARGET_HAS_div2_i64) {
1666 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1667 tcg_gen_movi_i64(t0, 0);
1668 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1669 tcg_temp_free_i64(t0);
1670 } else {
1671 gen_helper_divu_i64(ret, arg1, arg2);
1672 }
1673 }
1674
1675 void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1676 {
1677 if (TCG_TARGET_HAS_rem_i64) {
1678 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1679 } else if (TCG_TARGET_HAS_div_i64) {
1680 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1681 tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
1682 tcg_gen_mul_i64(t0, t0, arg2);
1683 tcg_gen_sub_i64(ret, arg1, t0);
1684 tcg_temp_free_i64(t0);
1685 } else if (TCG_TARGET_HAS_div2_i64) {
1686 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1687 tcg_gen_movi_i64(t0, 0);
1688 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1689 tcg_temp_free_i64(t0);
1690 } else {
1691 gen_helper_remu_i64(ret, arg1, arg2);
1692 }
1693 }
1694
1695 void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1696 {
1697 if (TCG_TARGET_REG_BITS == 32) {
1698 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1699 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1700 } else if (TCG_TARGET_HAS_ext8s_i64) {
1701 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1702 } else {
1703 tcg_gen_shli_i64(ret, arg, 56);
1704 tcg_gen_sari_i64(ret, ret, 56);
1705 }
1706 }
1707
1708 void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1709 {
1710 if (TCG_TARGET_REG_BITS == 32) {
1711 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1712 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1713 } else if (TCG_TARGET_HAS_ext16s_i64) {
1714 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1715 } else {
1716 tcg_gen_shli_i64(ret, arg, 48);
1717 tcg_gen_sari_i64(ret, ret, 48);
1718 }
1719 }
1720
1721 void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1722 {
1723 if (TCG_TARGET_REG_BITS == 32) {
1724 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1725 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1726 } else if (TCG_TARGET_HAS_ext32s_i64) {
1727 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1728 } else {
1729 tcg_gen_shli_i64(ret, arg, 32);
1730 tcg_gen_sari_i64(ret, ret, 32);
1731 }
1732 }
1733
1734 void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1735 {
1736 if (TCG_TARGET_REG_BITS == 32) {
1737 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1738 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1739 } else if (TCG_TARGET_HAS_ext8u_i64) {
1740 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1741 } else {
1742 tcg_gen_andi_i64(ret, arg, 0xffu);
1743 }
1744 }
1745
1746 void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1747 {
1748 if (TCG_TARGET_REG_BITS == 32) {
1749 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1750 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1751 } else if (TCG_TARGET_HAS_ext16u_i64) {
1752 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1753 } else {
1754 tcg_gen_andi_i64(ret, arg, 0xffffu);
1755 }
1756 }
1757
1758 void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1759 {
1760 if (TCG_TARGET_REG_BITS == 32) {
1761 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1762 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1763 } else if (TCG_TARGET_HAS_ext32u_i64) {
1764 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1765 } else {
1766 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1767 }
1768 }
1769
1770 /*
1771 * bswap16_i64: 16-bit byte swap on the low bits of a 64-bit value.
1772 *
1773 * Byte pattern: xxxxxxxxab -> yyyyyyyyba
1774 *
1775 * With TCG_BSWAP_IZ, x == zero, else undefined.
1776 * With TCG_BSWAP_OZ, y == zero, with TCG_BSWAP_OS y == sign, else undefined.
1777 */
1778 void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
1779 {
1780 /* Only one extension flag may be present. */
1781 tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
1782
1783 if (TCG_TARGET_REG_BITS == 32) {
1784 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg), flags);
1785 if (flags & TCG_BSWAP_OS) {
1786 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1787 } else {
1788 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1789 }
1790 } else if (TCG_TARGET_HAS_bswap16_i64) {
1791 tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg, flags);
1792 } else {
1793 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1794 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
1795
1796 /* arg = ......ab or xxxxxxab */
1797 tcg_gen_shri_i64(t0, arg, 8); /* t0 = .......a or .xxxxxxa */
1798 if (!(flags & TCG_BSWAP_IZ)) {
1799 tcg_gen_ext8u_i64(t0, t0); /* t0 = .......a */
1800 }
1801
1802 if (flags & TCG_BSWAP_OS) {
1803 tcg_gen_shli_i64(t1, arg, 56); /* t1 = b....... */
1804 tcg_gen_sari_i64(t1, t1, 48); /* t1 = ssssssb. */
1805 } else if (flags & TCG_BSWAP_OZ) {
1806 tcg_gen_ext8u_i64(t1, arg); /* t1 = .......b */
1807 tcg_gen_shli_i64(t1, t1, 8); /* t1 = ......b. */
1808 } else {
1809 tcg_gen_shli_i64(t1, arg, 8); /* t1 = xxxxxab. */
1810 }
1811
1812 tcg_gen_or_i64(ret, t0, t1); /* ret = ......ba (OZ) */
1813 /* ssssssba (OS) */
1814 /* xxxxxaba (no flag) */
1815 tcg_temp_free_i64(t0);
1816 tcg_temp_free_i64(t1);
1817 }
1818 }
1819
1820 void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
1821 {
1822 /* Only one extension flag may be present. */
1823 tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
1824
1825 if (TCG_TARGET_REG_BITS == 32) {
1826 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1827 if (flags & TCG_BSWAP_OS) {
1828 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1829 } else {
1830 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1831 }
1832 } else if (TCG_TARGET_HAS_bswap32_i64) {
1833 tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
1834 } else {
1835 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1836 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
1837 TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff);
1838
1839 /* arg = xxxxabcd */
1840 tcg_gen_shri_i64(t0, arg, 8); /* t0 = .xxxxabc */
1841 tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */
1842 tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */
1843 tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */
1844 tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */
1845
1846 tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */
1847 tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */
1848 if (flags & TCG_BSWAP_OS) {
1849 tcg_gen_sari_i64(t1, t1, 32); /* t1 = ssssdc.. */
1850 } else {
1851 tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */
1852 }
1853 tcg_gen_or_i64(ret, t0, t1); /* ret = ssssdcba */
1854
1855 tcg_temp_free_i64(t0);
1856 tcg_temp_free_i64(t1);
1857 }
1858 }
1859
1860 void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1861 {
1862 if (TCG_TARGET_REG_BITS == 32) {
1863 TCGv_i32 t0, t1;
1864 t0 = tcg_temp_ebb_new_i32();
1865 t1 = tcg_temp_ebb_new_i32();
1866
1867 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1868 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1869 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1870 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1871 tcg_temp_free_i32(t0);
1872 tcg_temp_free_i32(t1);
1873 } else if (TCG_TARGET_HAS_bswap64_i64) {
1874 tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
1875 } else {
1876 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1877 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
1878 TCGv_i64 t2 = tcg_temp_ebb_new_i64();
1879
1880 /* arg = abcdefgh */
1881 tcg_gen_movi_i64(t2, 0x00ff00ff00ff00ffull);
1882 tcg_gen_shri_i64(t0, arg, 8); /* t0 = .abcdefg */
1883 tcg_gen_and_i64(t1, arg, t2); /* t1 = .b.d.f.h */
1884 tcg_gen_and_i64(t0, t0, t2); /* t0 = .a.c.e.g */
1885 tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */
1886 tcg_gen_or_i64(ret, t0, t1); /* ret = badcfehg */
1887
1888 tcg_gen_movi_i64(t2, 0x0000ffff0000ffffull);
1889 tcg_gen_shri_i64(t0, ret, 16); /* t0 = ..badcfe */
1890 tcg_gen_and_i64(t1, ret, t2); /* t1 = ..dc..hg */
1891 tcg_gen_and_i64(t0, t0, t2); /* t0 = ..ba..fe */
1892 tcg_gen_shli_i64(t1, t1, 16); /* t1 = dc..hg.. */
1893 tcg_gen_or_i64(ret, t0, t1); /* ret = dcbahgfe */
1894
1895 tcg_gen_shri_i64(t0, ret, 32); /* t0 = ....dcba */
1896 tcg_gen_shli_i64(t1, ret, 32); /* t1 = hgfe.... */
1897 tcg_gen_or_i64(ret, t0, t1); /* ret = hgfedcba */
1898
1899 tcg_temp_free_i64(t0);
1900 tcg_temp_free_i64(t1);
1901 tcg_temp_free_i64(t2);
1902 }
1903 }
1904
1905 void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg)
1906 {
1907 uint64_t m = 0x0000ffff0000ffffull;
1908 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1909 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
1910
1911 /* See include/qemu/bitops.h, hswap64. */
1912 tcg_gen_rotli_i64(t1, arg, 32);
1913 tcg_gen_andi_i64(t0, t1, m);
1914 tcg_gen_shli_i64(t0, t0, 16);
1915 tcg_gen_shri_i64(t1, t1, 16);
1916 tcg_gen_andi_i64(t1, t1, m);
1917 tcg_gen_or_i64(ret, t0, t1);
1918
1919 tcg_temp_free_i64(t0);
1920 tcg_temp_free_i64(t1);
1921 }
1922
1923 void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg)
1924 {
1925 /* Swapping 2 32-bit elements is a rotate. */
1926 tcg_gen_rotli_i64(ret, arg, 32);
1927 }
1928
1929 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1930 {
1931 if (TCG_TARGET_REG_BITS == 32) {
1932 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1933 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1934 } else if (TCG_TARGET_HAS_not_i64) {
1935 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1936 } else {
1937 tcg_gen_xori_i64(ret, arg, -1);
1938 }
1939 }
1940
1941 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1942 {
1943 if (TCG_TARGET_REG_BITS == 32) {
1944 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1945 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1946 } else if (TCG_TARGET_HAS_andc_i64) {
1947 tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1948 } else {
1949 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
1950 tcg_gen_not_i64(t0, arg2);
1951 tcg_gen_and_i64(ret, arg1, t0);
1952 tcg_temp_free_i64(t0);
1953 }
1954 }
1955
1956 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1957 {
1958 if (TCG_TARGET_REG_BITS == 32) {
1959 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1960 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1961 } else if (TCG_TARGET_HAS_eqv_i64) {
1962 tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1963 } else {
1964 tcg_gen_xor_i64(ret, arg1, arg2);
1965 tcg_gen_not_i64(ret, ret);
1966 }
1967 }
1968
1969 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1970 {
1971 if (TCG_TARGET_REG_BITS == 32) {
1972 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1973 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1974 } else if (TCG_TARGET_HAS_nand_i64) {
1975 tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1976 } else {
1977 tcg_gen_and_i64(ret, arg1, arg2);
1978 tcg_gen_not_i64(ret, ret);
1979 }
1980 }
1981
1982 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1983 {
1984 if (TCG_TARGET_REG_BITS == 32) {
1985 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1986 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1987 } else if (TCG_TARGET_HAS_nor_i64) {
1988 tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1989 } else {
1990 tcg_gen_or_i64(ret, arg1, arg2);
1991 tcg_gen_not_i64(ret, ret);
1992 }
1993 }
1994
1995 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1996 {
1997 if (TCG_TARGET_REG_BITS == 32) {
1998 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1999 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
2000 } else if (TCG_TARGET_HAS_orc_i64) {
2001 tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
2002 } else {
2003 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2004 tcg_gen_not_i64(t0, arg2);
2005 tcg_gen_or_i64(ret, arg1, t0);
2006 tcg_temp_free_i64(t0);
2007 }
2008 }
2009
2010 void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2011 {
2012 if (TCG_TARGET_HAS_clz_i64) {
2013 tcg_gen_op3_i64(INDEX_op_clz_i64, ret, arg1, arg2);
2014 } else {
2015 gen_helper_clz_i64(ret, arg1, arg2);
2016 }
2017 }
2018
2019 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
2020 {
2021 if (TCG_TARGET_REG_BITS == 32
2022 && TCG_TARGET_HAS_clz_i32
2023 && arg2 <= 0xffffffffu) {
2024 TCGv_i32 t = tcg_temp_ebb_new_i32();
2025 tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32);
2026 tcg_gen_addi_i32(t, t, 32);
2027 tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t);
2028 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2029 tcg_temp_free_i32(t);
2030 } else {
2031 tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2));
2032 }
2033 }
2034
2035 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2036 {
2037 if (TCG_TARGET_HAS_ctz_i64) {
2038 tcg_gen_op3_i64(INDEX_op_ctz_i64, ret, arg1, arg2);
2039 } else if (TCG_TARGET_HAS_ctpop_i64 || TCG_TARGET_HAS_clz_i64) {
2040 TCGv_i64 z, t = tcg_temp_ebb_new_i64();
2041
2042 if (TCG_TARGET_HAS_ctpop_i64) {
2043 tcg_gen_subi_i64(t, arg1, 1);
2044 tcg_gen_andc_i64(t, t, arg1);
2045 tcg_gen_ctpop_i64(t, t);
2046 } else {
2047 /* Since all non-x86 hosts have clz(0) == 64, don't fight it. */
2048 tcg_gen_neg_i64(t, arg1);
2049 tcg_gen_and_i64(t, t, arg1);
2050 tcg_gen_clzi_i64(t, t, 64);
2051 tcg_gen_xori_i64(t, t, 63);
2052 }
2053 z = tcg_constant_i64(0);
2054 tcg_gen_movcond_i64(TCG_COND_EQ, ret, arg1, z, arg2, t);
2055 tcg_temp_free_i64(t);
2056 tcg_temp_free_i64(z);
2057 } else {
2058 gen_helper_ctz_i64(ret, arg1, arg2);
2059 }
2060 }
2061
2062 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
2063 {
2064 if (TCG_TARGET_REG_BITS == 32
2065 && TCG_TARGET_HAS_ctz_i32
2066 && arg2 <= 0xffffffffu) {
2067 TCGv_i32 t32 = tcg_temp_ebb_new_i32();
2068 tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32);
2069 tcg_gen_addi_i32(t32, t32, 32);
2070 tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32);
2071 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2072 tcg_temp_free_i32(t32);
2073 } else if (!TCG_TARGET_HAS_ctz_i64
2074 && TCG_TARGET_HAS_ctpop_i64
2075 && arg2 == 64) {
2076 /* This equivalence has the advantage of not requiring a fixup. */
2077 TCGv_i64 t = tcg_temp_ebb_new_i64();
2078 tcg_gen_subi_i64(t, arg1, 1);
2079 tcg_gen_andc_i64(t, t, arg1);
2080 tcg_gen_ctpop_i64(ret, t);
2081 tcg_temp_free_i64(t);
2082 } else {
2083 tcg_gen_ctz_i64(ret, arg1, tcg_constant_i64(arg2));
2084 }
2085 }
2086
2087 void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg)
2088 {
2089 if (TCG_TARGET_HAS_clz_i64 || TCG_TARGET_HAS_clz_i32) {
2090 TCGv_i64 t = tcg_temp_ebb_new_i64();
2091 tcg_gen_sari_i64(t, arg, 63);
2092 tcg_gen_xor_i64(t, t, arg);
2093 tcg_gen_clzi_i64(t, t, 64);
2094 tcg_gen_subi_i64(ret, t, 1);
2095 tcg_temp_free_i64(t);
2096 } else {
2097 gen_helper_clrsb_i64(ret, arg);
2098 }
2099 }
2100
2101 void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1)
2102 {
2103 if (TCG_TARGET_HAS_ctpop_i64) {
2104 tcg_gen_op2_i64(INDEX_op_ctpop_i64, ret, arg1);
2105 } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_ctpop_i32) {
2106 tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
2107 tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
2108 tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret));
2109 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2110 } else {
2111 gen_helper_ctpop_i64(ret, arg1);
2112 }
2113 }
2114
2115 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2116 {
2117 if (TCG_TARGET_HAS_rot_i64) {
2118 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
2119 } else {
2120 TCGv_i64 t0, t1;
2121 t0 = tcg_temp_ebb_new_i64();
2122 t1 = tcg_temp_ebb_new_i64();
2123 tcg_gen_shl_i64(t0, arg1, arg2);
2124 tcg_gen_subfi_i64(t1, 64, arg2);
2125 tcg_gen_shr_i64(t1, arg1, t1);
2126 tcg_gen_or_i64(ret, t0, t1);
2127 tcg_temp_free_i64(t0);
2128 tcg_temp_free_i64(t1);
2129 }
2130 }
2131
2132 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2133 {
2134 tcg_debug_assert(arg2 >= 0 && arg2 < 64);
2135 /* some cases can be optimized here */
2136 if (arg2 == 0) {
2137 tcg_gen_mov_i64(ret, arg1);
2138 } else if (TCG_TARGET_HAS_rot_i64) {
2139 tcg_gen_rotl_i64(ret, arg1, tcg_constant_i64(arg2));
2140 } else {
2141 TCGv_i64 t0, t1;
2142 t0 = tcg_temp_ebb_new_i64();
2143 t1 = tcg_temp_ebb_new_i64();
2144 tcg_gen_shli_i64(t0, arg1, arg2);
2145 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2146 tcg_gen_or_i64(ret, t0, t1);
2147 tcg_temp_free_i64(t0);
2148 tcg_temp_free_i64(t1);
2149 }
2150 }
2151
2152 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2153 {
2154 if (TCG_TARGET_HAS_rot_i64) {
2155 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2156 } else {
2157 TCGv_i64 t0, t1;
2158 t0 = tcg_temp_ebb_new_i64();
2159 t1 = tcg_temp_ebb_new_i64();
2160 tcg_gen_shr_i64(t0, arg1, arg2);
2161 tcg_gen_subfi_i64(t1, 64, arg2);
2162 tcg_gen_shl_i64(t1, arg1, t1);
2163 tcg_gen_or_i64(ret, t0, t1);
2164 tcg_temp_free_i64(t0);
2165 tcg_temp_free_i64(t1);
2166 }
2167 }
2168
2169 void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2170 {
2171 tcg_debug_assert(arg2 >= 0 && arg2 < 64);
2172 /* some cases can be optimized here */
2173 if (arg2 == 0) {
2174 tcg_gen_mov_i64(ret, arg1);
2175 } else {
2176 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2177 }
2178 }
2179
2180 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
2181 unsigned int ofs, unsigned int len)
2182 {
2183 uint64_t mask;
2184 TCGv_i64 t1;
2185
2186 tcg_debug_assert(ofs < 64);
2187 tcg_debug_assert(len > 0);
2188 tcg_debug_assert(len <= 64);
2189 tcg_debug_assert(ofs + len <= 64);
2190
2191 if (len == 64) {
2192 tcg_gen_mov_i64(ret, arg2);
2193 return;
2194 }
2195 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
2196 tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
2197 return;
2198 }
2199
2200 if (TCG_TARGET_REG_BITS == 32) {
2201 if (ofs >= 32) {
2202 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2203 TCGV_LOW(arg2), ofs - 32, len);
2204 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
2205 return;
2206 }
2207 if (ofs + len <= 32) {
2208 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2209 TCGV_LOW(arg2), ofs, len);
2210 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
2211 return;
2212 }
2213 }
2214
2215 t1 = tcg_temp_ebb_new_i64();
2216
2217 if (TCG_TARGET_HAS_extract2_i64) {
2218 if (ofs + len == 64) {
2219 tcg_gen_shli_i64(t1, arg1, len);
2220 tcg_gen_extract2_i64(ret, t1, arg2, len);
2221 goto done;
2222 }
2223 if (ofs == 0) {
2224 tcg_gen_extract2_i64(ret, arg1, arg2, len);
2225 tcg_gen_rotli_i64(ret, ret, len);
2226 goto done;
2227 }
2228 }
2229
2230 mask = (1ull << len) - 1;
2231 if (ofs + len < 64) {
2232 tcg_gen_andi_i64(t1, arg2, mask);
2233 tcg_gen_shli_i64(t1, t1, ofs);
2234 } else {
2235 tcg_gen_shli_i64(t1, arg2, ofs);
2236 }
2237 tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2238 tcg_gen_or_i64(ret, ret, t1);
2239 done:
2240 tcg_temp_free_i64(t1);
2241 }
2242
2243 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
2244 unsigned int ofs, unsigned int len)
2245 {
2246 tcg_debug_assert(ofs < 64);
2247 tcg_debug_assert(len > 0);
2248 tcg_debug_assert(len <= 64);
2249 tcg_debug_assert(ofs + len <= 64);
2250
2251 if (ofs + len == 64) {
2252 tcg_gen_shli_i64(ret, arg, ofs);
2253 } else if (ofs == 0) {
2254 tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
2255 } else if (TCG_TARGET_HAS_deposit_i64
2256 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
2257 TCGv_i64 zero = tcg_constant_i64(0);
2258 tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len);
2259 } else {
2260 if (TCG_TARGET_REG_BITS == 32) {
2261 if (ofs >= 32) {
2262 tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg),
2263 ofs - 32, len);
2264 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
2265 return;
2266 }
2267 if (ofs + len <= 32) {
2268 tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
2269 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2270 return;
2271 }
2272 }
2273 /* To help two-operand hosts we prefer to zero-extend first,
2274 which allows ARG to stay live. */
2275 switch (len) {
2276 case 32:
2277 if (TCG_TARGET_HAS_ext32u_i64) {
2278 tcg_gen_ext32u_i64(ret, arg);
2279 tcg_gen_shli_i64(ret, ret, ofs);
2280 return;
2281 }
2282 break;
2283 case 16:
2284 if (TCG_TARGET_HAS_ext16u_i64) {
2285 tcg_gen_ext16u_i64(ret, arg);
2286 tcg_gen_shli_i64(ret, ret, ofs);
2287 return;
2288 }
2289 break;
2290 case 8:
2291 if (TCG_TARGET_HAS_ext8u_i64) {
2292 tcg_gen_ext8u_i64(ret, arg);
2293 tcg_gen_shli_i64(ret, ret, ofs);
2294 return;
2295 }
2296 break;
2297 }
2298 /* Otherwise prefer zero-extension over AND for code size. */
2299 switch (ofs + len) {
2300 case 32:
2301 if (TCG_TARGET_HAS_ext32u_i64) {
2302 tcg_gen_shli_i64(ret, arg, ofs);
2303 tcg_gen_ext32u_i64(ret, ret);
2304 return;
2305 }
2306 break;
2307 case 16:
2308 if (TCG_TARGET_HAS_ext16u_i64) {
2309 tcg_gen_shli_i64(ret, arg, ofs);
2310 tcg_gen_ext16u_i64(ret, ret);
2311 return;
2312 }
2313 break;
2314 case 8:
2315 if (TCG_TARGET_HAS_ext8u_i64) {
2316 tcg_gen_shli_i64(ret, arg, ofs);
2317 tcg_gen_ext8u_i64(ret, ret);
2318 return;
2319 }
2320 break;
2321 }
2322 tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
2323 tcg_gen_shli_i64(ret, ret, ofs);
2324 }
2325 }
2326
2327 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
2328 unsigned int ofs, unsigned int len)
2329 {
2330 tcg_debug_assert(ofs < 64);
2331 tcg_debug_assert(len > 0);
2332 tcg_debug_assert(len <= 64);
2333 tcg_debug_assert(ofs + len <= 64);
2334
2335 /* Canonicalize certain special cases, even if extract is supported. */
2336 if (ofs + len == 64) {
2337 tcg_gen_shri_i64(ret, arg, 64 - len);
2338 return;
2339 }
2340 if (ofs == 0) {
2341 tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
2342 return;
2343 }
2344
2345 if (TCG_TARGET_REG_BITS == 32) {
2346 /* Look for a 32-bit extract within one of the two words. */
2347 if (ofs >= 32) {
2348 tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, len);
2349 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2350 return;
2351 }
2352 if (ofs + len <= 32) {
2353 tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
2354 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2355 return;
2356 }
2357 /* The field is split across two words. One double-word
2358 shift is better than two double-word shifts. */
2359 goto do_shift_and;
2360 }
2361
2362 if (TCG_TARGET_HAS_extract_i64
2363 && TCG_TARGET_extract_i64_valid(ofs, len)) {
2364 tcg_gen_op4ii_i64(INDEX_op_extract_i64, ret, arg, ofs, len);
2365 return;
2366 }
2367
2368 /* Assume that zero-extension, if available, is cheaper than a shift. */
2369 switch (ofs + len) {
2370 case 32:
2371 if (TCG_TARGET_HAS_ext32u_i64) {
2372 tcg_gen_ext32u_i64(ret, arg);
2373 tcg_gen_shri_i64(ret, ret, ofs);
2374 return;
2375 }
2376 break;
2377 case 16:
2378 if (TCG_TARGET_HAS_ext16u_i64) {
2379 tcg_gen_ext16u_i64(ret, arg);
2380 tcg_gen_shri_i64(ret, ret, ofs);
2381 return;
2382 }
2383 break;
2384 case 8:
2385 if (TCG_TARGET_HAS_ext8u_i64) {
2386 tcg_gen_ext8u_i64(ret, arg);
2387 tcg_gen_shri_i64(ret, ret, ofs);
2388 return;
2389 }
2390 break;
2391 }
2392
2393 /* ??? Ideally we'd know what values are available for immediate AND.
2394 Assume that 8 bits are available, plus the special cases of 16 and 32,
2395 so that we get ext8u, ext16u, and ext32u. */
2396 switch (len) {
2397 case 1 ... 8: case 16: case 32:
2398 do_shift_and:
2399 tcg_gen_shri_i64(ret, arg, ofs);
2400 tcg_gen_andi_i64(ret, ret, (1ull << len) - 1);
2401 break;
2402 default:
2403 tcg_gen_shli_i64(ret, arg, 64 - len - ofs);
2404 tcg_gen_shri_i64(ret, ret, 64 - len);
2405 break;
2406 }
2407 }
2408
2409 void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
2410 unsigned int ofs, unsigned int len)
2411 {
2412 tcg_debug_assert(ofs < 64);
2413 tcg_debug_assert(len > 0);
2414 tcg_debug_assert(len <= 64);
2415 tcg_debug_assert(ofs + len <= 64);
2416
2417 /* Canonicalize certain special cases, even if sextract is supported. */
2418 if (ofs + len == 64) {
2419 tcg_gen_sari_i64(ret, arg, 64 - len);
2420 return;
2421 }
2422 if (ofs == 0) {
2423 switch (len) {
2424 case 32:
2425 tcg_gen_ext32s_i64(ret, arg);
2426 return;
2427 case 16:
2428 tcg_gen_ext16s_i64(ret, arg);
2429 return;
2430 case 8:
2431 tcg_gen_ext8s_i64(ret, arg);
2432 return;
2433 }
2434 }
2435
2436 if (TCG_TARGET_REG_BITS == 32) {
2437 /* Look for a 32-bit extract within one of the two words. */
2438 if (ofs >= 32) {
2439 tcg_gen_sextract_i32(TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, len);
2440 } else if (ofs + len <= 32) {
2441 tcg_gen_sextract_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
2442 } else if (ofs == 0) {
2443 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
2444 tcg_gen_sextract_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - 32);
2445 return;
2446 } else if (len > 32) {
2447 TCGv_i32 t = tcg_temp_ebb_new_i32();
2448 /* Extract the bits for the high word normally. */
2449 tcg_gen_sextract_i32(t, TCGV_HIGH(arg), ofs + 32, len - 32);
2450 /* Shift the field down for the low part. */
2451 tcg_gen_shri_i64(ret, arg, ofs);
2452 /* Overwrite the shift into the high part. */
2453 tcg_gen_mov_i32(TCGV_HIGH(ret), t);
2454 tcg_temp_free_i32(t);
2455 return;
2456 } else {
2457 /* Shift the field down for the low part, such that the
2458 field sits at the MSB. */
2459 tcg_gen_shri_i64(ret, arg, ofs + len - 32);
2460 /* Shift the field down from the MSB, sign extending. */
2461 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_LOW(ret), 32 - len);
2462 }
2463 /* Sign-extend the field from 32 bits. */
2464 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2465 return;
2466 }
2467
2468 if (TCG_TARGET_HAS_sextract_i64
2469 && TCG_TARGET_extract_i64_valid(ofs, len)) {
2470 tcg_gen_op4ii_i64(INDEX_op_sextract_i64, ret, arg, ofs, len);
2471 return;
2472 }
2473
2474 /* Assume that sign-extension, if available, is cheaper than a shift. */
2475 switch (ofs + len) {
2476 case 32:
2477 if (TCG_TARGET_HAS_ext32s_i64) {
2478 tcg_gen_ext32s_i64(ret, arg);
2479 tcg_gen_sari_i64(ret, ret, ofs);
2480 return;
2481 }
2482 break;
2483 case 16:
2484 if (TCG_TARGET_HAS_ext16s_i64) {
2485 tcg_gen_ext16s_i64(ret, arg);
2486 tcg_gen_sari_i64(ret, ret, ofs);
2487 return;
2488 }
2489 break;
2490 case 8:
2491 if (TCG_TARGET_HAS_ext8s_i64) {
2492 tcg_gen_ext8s_i64(ret, arg);
2493 tcg_gen_sari_i64(ret, ret, ofs);
2494 return;
2495 }
2496 break;
2497 }
2498 switch (len) {
2499 case 32:
2500 if (TCG_TARGET_HAS_ext32s_i64) {
2501 tcg_gen_shri_i64(ret, arg, ofs);
2502 tcg_gen_ext32s_i64(ret, ret);
2503 return;
2504 }
2505 break;
2506 case 16:
2507 if (TCG_TARGET_HAS_ext16s_i64) {
2508 tcg_gen_shri_i64(ret, arg, ofs);
2509 tcg_gen_ext16s_i64(ret, ret);
2510 return;
2511 }
2512 break;
2513 case 8:
2514 if (TCG_TARGET_HAS_ext8s_i64) {
2515 tcg_gen_shri_i64(ret, arg, ofs);
2516 tcg_gen_ext8s_i64(ret, ret);
2517 return;
2518 }
2519 break;
2520 }
2521 tcg_gen_shli_i64(ret, arg, 64 - len - ofs);
2522 tcg_gen_sari_i64(ret, ret, 64 - len);
2523 }
2524
2525 /*
2526 * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
2527 * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
2528 */
2529 void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
2530 unsigned int ofs)
2531 {
2532 tcg_debug_assert(ofs <= 64);
2533 if (ofs == 0) {
2534 tcg_gen_mov_i64(ret, al);
2535 } else if (ofs == 64) {
2536 tcg_gen_mov_i64(ret, ah);
2537 } else if (al == ah) {
2538 tcg_gen_rotri_i64(ret, al, ofs);
2539 } else if (TCG_TARGET_HAS_extract2_i64) {
2540 tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
2541 } else {
2542 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2543 tcg_gen_shri_i64(t0, al, ofs);
2544 tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
2545 tcg_temp_free_i64(t0);
2546 }
2547 }
2548
2549 void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
2550 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
2551 {
2552 if (cond == TCG_COND_ALWAYS) {
2553 tcg_gen_mov_i64(ret, v1);
2554 } else if (cond == TCG_COND_NEVER) {
2555 tcg_gen_mov_i64(ret, v2);
2556 } else if (TCG_TARGET_REG_BITS == 32) {
2557 TCGv_i32 t0 = tcg_temp_ebb_new_i32();
2558 TCGv_i32 t1 = tcg_temp_ebb_new_i32();
2559 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
2560 TCGV_LOW(c1), TCGV_HIGH(c1),
2561 TCGV_LOW(c2), TCGV_HIGH(c2), cond);
2562
2563 if (TCG_TARGET_HAS_movcond_i32) {
2564 tcg_gen_movi_i32(t1, 0);
2565 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1,
2566 TCGV_LOW(v1), TCGV_LOW(v2));
2567 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1,
2568 TCGV_HIGH(v1), TCGV_HIGH(v2));
2569 } else {
2570 tcg_gen_neg_i32(t0, t0);
2571
2572 tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
2573 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
2574 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
2575
2576 tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
2577 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
2578 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
2579 }
2580 tcg_temp_free_i32(t0);
2581 tcg_temp_free_i32(t1);
2582 } else if (TCG_TARGET_HAS_movcond_i64) {
2583 tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
2584 } else {
2585 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2586 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
2587 tcg_gen_negsetcond_i64(cond, t0, c1, c2);
2588 tcg_gen_and_i64(t1, v1, t0);
2589 tcg_gen_andc_i64(ret, v2, t0);
2590 tcg_gen_or_i64(ret, ret, t1);
2591 tcg_temp_free_i64(t0);
2592 tcg_temp_free_i64(t1);
2593 }
2594 }
2595
2596 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2597 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2598 {
2599 if (TCG_TARGET_HAS_add2_i64) {
2600 tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh);
2601 } else {
2602 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2603 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
2604 tcg_gen_add_i64(t0, al, bl);
2605 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al);
2606 tcg_gen_add_i64(rh, ah, bh);
2607 tcg_gen_add_i64(rh, rh, t1);
2608 tcg_gen_mov_i64(rl, t0);
2609 tcg_temp_free_i64(t0);
2610 tcg_temp_free_i64(t1);
2611 }
2612 }
2613
2614 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2615 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2616 {
2617 if (TCG_TARGET_HAS_sub2_i64) {
2618 tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh);
2619 } else {
2620 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2621 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
2622 tcg_gen_sub_i64(t0, al, bl);
2623 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl);
2624 tcg_gen_sub_i64(rh, ah, bh);
2625 tcg_gen_sub_i64(rh, rh, t1);
2626 tcg_gen_mov_i64(rl, t0);
2627 tcg_temp_free_i64(t0);
2628 tcg_temp_free_i64(t1);
2629 }
2630 }
2631
2632 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
2633 {
2634 if (TCG_TARGET_HAS_mulu2_i64) {
2635 tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
2636 } else if (TCG_TARGET_HAS_muluh_i64) {
2637 TCGv_i64 t = tcg_temp_ebb_new_i64();
2638 tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
2639 tcg_gen_op3_i64(INDEX_op_muluh_i64, rh, arg1, arg2);
2640 tcg_gen_mov_i64(rl, t);
2641 tcg_temp_free_i64(t);
2642 } else {
2643 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2644 tcg_gen_mul_i64(t0, arg1, arg2);
2645 gen_helper_muluh_i64(rh, arg1, arg2);
2646 tcg_gen_mov_i64(rl, t0);
2647 tcg_temp_free_i64(t0);
2648 }
2649 }
2650
2651 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
2652 {
2653 if (TCG_TARGET_HAS_muls2_i64) {
2654 tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
2655 } else if (TCG_TARGET_HAS_mulsh_i64) {
2656 TCGv_i64 t = tcg_temp_ebb_new_i64();
2657 tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
2658 tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);
2659 tcg_gen_mov_i64(rl, t);
2660 tcg_temp_free_i64(t);
2661 } else if (TCG_TARGET_HAS_mulu2_i64 || TCG_TARGET_HAS_muluh_i64) {
2662 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2663 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
2664 TCGv_i64 t2 = tcg_temp_ebb_new_i64();
2665 TCGv_i64 t3 = tcg_temp_ebb_new_i64();
2666 tcg_gen_mulu2_i64(t0, t1, arg1, arg2);
2667 /* Adjust for negative inputs. */
2668 tcg_gen_sari_i64(t2, arg1, 63);
2669 tcg_gen_sari_i64(t3, arg2, 63);
2670 tcg_gen_and_i64(t2, t2, arg2);
2671 tcg_gen_and_i64(t3, t3, arg1);
2672 tcg_gen_sub_i64(rh, t1, t2);
2673 tcg_gen_sub_i64(rh, rh, t3);
2674 tcg_gen_mov_i64(rl, t0);
2675 tcg_temp_free_i64(t0);
2676 tcg_temp_free_i64(t1);
2677 tcg_temp_free_i64(t2);
2678 tcg_temp_free_i64(t3);
2679 } else {
2680 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2681 tcg_gen_mul_i64(t0, arg1, arg2);
2682 gen_helper_mulsh_i64(rh, arg1, arg2);
2683 tcg_gen_mov_i64(rl, t0);
2684 tcg_temp_free_i64(t0);
2685 }
2686 }
2687
2688 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
2689 {
2690 TCGv_i64 t0 = tcg_temp_ebb_new_i64();
2691 TCGv_i64 t1 = tcg_temp_ebb_new_i64();
2692 TCGv_i64 t2 = tcg_temp_ebb_new_i64();
2693 tcg_gen_mulu2_i64(t0, t1, arg1, arg2);
2694 /* Adjust for negative input for the signed arg1. */
2695 tcg_gen_sari_i64(t2, arg1, 63);
2696 tcg_gen_and_i64(t2, t2, arg2);
2697 tcg_gen_sub_i64(rh, t1, t2);
2698 tcg_gen_mov_i64(rl, t0);
2699 tcg_temp_free_i64(t0);
2700 tcg_temp_free_i64(t1);
2701 tcg_temp_free_i64(t2);
2702 }
2703
2704 void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
2705 {
2706 tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b);
2707 }
2708
2709 void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
2710 {
2711 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b);
2712 }
2713
2714 void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
2715 {
2716 tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a);
2717 }
2718
2719 void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
2720 {
2721 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a);
2722 }
2723
2724 void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a)
2725 {
2726 TCGv_i64 t = tcg_temp_ebb_new_i64();
2727
2728 tcg_gen_sari_i64(t, a, 63);
2729 tcg_gen_xor_i64(ret, a, t);
2730 tcg_gen_sub_i64(ret, ret, t);
2731 tcg_temp_free_i64(t);
2732 }
2733
2734 /* Size changing operations. */
2735
2736 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
2737 {
2738 if (TCG_TARGET_REG_BITS == 32) {
2739 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
2740 } else if (TCG_TARGET_HAS_extr_i64_i32) {
2741 tcg_gen_op2(INDEX_op_extrl_i64_i32,
2742 tcgv_i32_arg(ret), tcgv_i64_arg(arg));
2743 } else {
2744 tcg_gen_mov_i32(ret, (TCGv_i32)arg);
2745 }
2746 }
2747
2748 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
2749 {
2750 if (TCG_TARGET_REG_BITS == 32) {
2751 tcg_gen_mov_i32(ret, TCGV_HIGH(arg));
2752 } else if (TCG_TARGET_HAS_extr_i64_i32) {
2753 tcg_gen_op2(INDEX_op_extrh_i64_i32,
2754 tcgv_i32_arg(ret), tcgv_i64_arg(arg));
2755 } else {
2756 TCGv_i64 t = tcg_temp_ebb_new_i64();
2757 tcg_gen_shri_i64(t, arg, 32);
2758 tcg_gen_mov_i32(ret, (TCGv_i32)t);
2759 tcg_temp_free_i64(t);
2760 }
2761 }
2762
2763 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
2764 {
2765 if (TCG_TARGET_REG_BITS == 32) {
2766 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
2767 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2768 } else {
2769 tcg_gen_op2(INDEX_op_extu_i32_i64,
2770 tcgv_i64_arg(ret), tcgv_i32_arg(arg));
2771 }
2772 }
2773
2774 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
2775 {
2776 if (TCG_TARGET_REG_BITS == 32) {
2777 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
2778 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2779 } else {
2780 tcg_gen_op2(INDEX_op_ext_i32_i64,
2781 tcgv_i64_arg(ret), tcgv_i32_arg(arg));
2782 }
2783 }
2784
2785 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
2786 {
2787 TCGv_i64 tmp;
2788
2789 if (TCG_TARGET_REG_BITS == 32) {
2790 tcg_gen_mov_i32(TCGV_LOW(dest), low);
2791 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
2792 return;
2793 }
2794
2795 tmp = tcg_temp_ebb_new_i64();
2796 /* These extensions are only needed for type correctness.
2797 We may be able to do better given target specific information. */
2798 tcg_gen_extu_i32_i64(tmp, high);
2799 tcg_gen_extu_i32_i64(dest, low);
2800 /* If deposit is available, use it. Otherwise use the extra
2801 knowledge that we have of the zero-extensions above. */
2802 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
2803 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
2804 } else {
2805 tcg_gen_shli_i64(tmp, tmp, 32);
2806 tcg_gen_or_i64(dest, dest, tmp);
2807 }
2808 tcg_temp_free_i64(tmp);
2809 }
2810
2811 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg)
2812 {
2813 if (TCG_TARGET_REG_BITS == 32) {
2814 tcg_gen_mov_i32(lo, TCGV_LOW(arg));
2815 tcg_gen_mov_i32(hi, TCGV_HIGH(arg));
2816 } else {
2817 tcg_gen_extrl_i64_i32(lo, arg);
2818 tcg_gen_extrh_i64_i32(hi, arg);
2819 }
2820 }
2821
2822 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)
2823 {
2824 tcg_gen_ext32u_i64(lo, arg);
2825 tcg_gen_shri_i64(hi, arg, 32);
2826 }
2827
2828 void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg)
2829 {
2830 tcg_gen_mov_i64(lo, TCGV128_LOW(arg));
2831 tcg_gen_mov_i64(hi, TCGV128_HIGH(arg));
2832 }
2833
2834 void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi)
2835 {
2836 tcg_gen_mov_i64(TCGV128_LOW(ret), lo);
2837 tcg_gen_mov_i64(TCGV128_HIGH(ret), hi);
2838 }
2839
2840 void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src)
2841 {
2842 if (dst != src) {
2843 tcg_gen_mov_i64(TCGV128_LOW(dst), TCGV128_LOW(src));
2844 tcg_gen_mov_i64(TCGV128_HIGH(dst), TCGV128_HIGH(src));
2845 }
2846 }
2847
2848 /* QEMU specific operations. */
2849
2850 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx)
2851 {
2852 /*
2853 * Let the jit code return the read-only version of the
2854 * TranslationBlock, so that we minimize the pc-relative
2855 * distance of the address of the exit_tb code to TB.
2856 * This will improve utilization of pc-relative address loads.
2857 *
2858 * TODO: Move this to translator_loop, so that all const
2859 * TranslationBlock pointers refer to read-only memory.
2860 * This requires coordination with targets that do not use
2861 * the translator_loop.
2862 */
2863 uintptr_t val = (uintptr_t)tcg_splitwx_to_rx((void *)tb) + idx;
2864
2865 if (tb == NULL) {
2866 tcg_debug_assert(idx == 0);
2867 } else if (idx <= TB_EXIT_IDXMAX) {
2868 #ifdef CONFIG_DEBUG_TCG
2869 /* This is an exit following a goto_tb. Verify that we have
2870 seen this numbered exit before, via tcg_gen_goto_tb. */
2871 tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx));
2872 #endif
2873 } else {
2874 /* This is an exit via the exitreq label. */
2875 tcg_debug_assert(idx == TB_EXIT_REQUESTED);
2876 }
2877
2878 tcg_gen_op1i(INDEX_op_exit_tb, val);
2879 }
2880
2881 void tcg_gen_goto_tb(unsigned idx)
2882 {
2883 /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */
2884 tcg_debug_assert(!(tcg_ctx->gen_tb->cflags & CF_NO_GOTO_TB));
2885 /* We only support two chained exits. */
2886 tcg_debug_assert(idx <= TB_EXIT_IDXMAX);
2887 #ifdef CONFIG_DEBUG_TCG
2888 /* Verify that we haven't seen this numbered exit before. */
2889 tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0);
2890 tcg_ctx->goto_tb_issue_mask |= 1 << idx;
2891 #endif
2892 plugin_gen_disable_mem_helpers();
2893 tcg_gen_op1i(INDEX_op_goto_tb, idx);
2894 }
2895
2896 void tcg_gen_lookup_and_goto_ptr(void)
2897 {
2898 TCGv_ptr ptr;
2899
2900 if (tcg_ctx->gen_tb->cflags & CF_NO_GOTO_PTR) {
2901 tcg_gen_exit_tb(NULL, 0);
2902 return;
2903 }
2904
2905 plugin_gen_disable_mem_helpers();
2906 ptr = tcg_temp_ebb_new_ptr();
2907 gen_helper_lookup_tb_ptr(ptr, cpu_env);
2908 tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
2909 tcg_temp_free_ptr(ptr);
2910 }