2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 /* Define to jump the ELF file used to communicate with GDB. */
30 #include "qemu/error-report.h"
31 #include "qemu/cutils.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/qemu-print.h"
34 #include "qemu/cacheflush.h"
35 #include "qemu/cacheinfo.h"
36 #include "qemu/timer.h"
38 /* Note: the long term plan is to reduce the dependencies on the QEMU
39 CPU definitions. Currently they are used for qemu_ld/st
41 #define NO_CPU_IO_DEFS
43 #include "exec/exec-all.h"
44 #include "exec/tlb-common.h"
45 #include "tcg/tcg-op-common.h"
47 #if UINTPTR_MAX == UINT32_MAX
48 # define ELF_CLASS ELFCLASS32
50 # define ELF_CLASS ELFCLASS64
53 # define ELF_DATA ELFDATA2MSB
55 # define ELF_DATA ELFDATA2LSB
60 #include "tcg/tcg-ldst.h"
61 #include "tcg/tcg-temp-internal.h"
62 #include "tcg-internal.h"
63 #include "accel/tcg/perf.h"
64 #ifdef CONFIG_USER_ONLY
65 #include "exec/user/guest-base.h"
68 /* Forward declarations for functions declared in tcg-target.c.inc and
70 static void tcg_target_init(TCGContext
*s
);
71 static void tcg_target_qemu_prologue(TCGContext
*s
);
72 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
73 intptr_t value
, intptr_t addend
);
75 /* The CIE and FDE header definitions will be common to all hosts. */
77 uint32_t len
__attribute__((aligned((sizeof(void *)))));
83 uint8_t return_column
;
86 typedef struct QEMU_PACKED
{
87 uint32_t len
__attribute__((aligned((sizeof(void *)))));
91 } DebugFrameFDEHeader
;
93 typedef struct QEMU_PACKED
{
95 DebugFrameFDEHeader fde
;
98 typedef struct TCGLabelQemuLdst
{
99 bool is_ld
; /* qemu_ld: true, qemu_st: false */
101 TCGType type
; /* result type of a load */
102 TCGReg addrlo_reg
; /* reg index for low word of guest virtual addr */
103 TCGReg addrhi_reg
; /* reg index for high word of guest virtual addr */
104 TCGReg datalo_reg
; /* reg index for low word to be loaded or stored */
105 TCGReg datahi_reg
; /* reg index for high word to be loaded or stored */
106 const tcg_insn_unit
*raddr
; /* addr of the next IR of qemu_ld/st IR */
107 tcg_insn_unit
*label_ptr
[2]; /* label pointers to be updated */
108 QSIMPLEQ_ENTRY(TCGLabelQemuLdst
) next
;
111 static void tcg_register_jit_int(const void *buf
, size_t size
,
112 const void *debug_frame
,
113 size_t debug_frame_size
)
114 __attribute__((unused
));
116 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
117 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
119 static bool tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
120 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
121 TCGReg ret
, tcg_target_long arg
);
122 static void tcg_out_ext8s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
123 static void tcg_out_ext16s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
124 static void tcg_out_ext8u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
125 static void tcg_out_ext16u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
126 static void tcg_out_ext32s(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
127 static void tcg_out_ext32u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
128 static void tcg_out_exts_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
129 static void tcg_out_extu_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
130 static void tcg_out_extrl_i64_i32(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
131 static void tcg_out_addi_ptr(TCGContext
*s
, TCGReg
, TCGReg
, tcg_target_long
);
132 static bool tcg_out_xchg(TCGContext
*s
, TCGType type
, TCGReg r1
, TCGReg r2
);
133 static void tcg_out_exit_tb(TCGContext
*s
, uintptr_t arg
);
134 static void tcg_out_goto_tb(TCGContext
*s
, int which
);
135 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
136 const TCGArg args
[TCG_MAX_OP_ARGS
],
137 const int const_args
[TCG_MAX_OP_ARGS
]);
138 #if TCG_TARGET_MAYBE_vec
139 static bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
140 TCGReg dst
, TCGReg src
);
141 static bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
142 TCGReg dst
, TCGReg base
, intptr_t offset
);
143 static void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
144 TCGReg dst
, int64_t arg
);
145 static void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
146 unsigned vecl
, unsigned vece
,
147 const TCGArg args
[TCG_MAX_OP_ARGS
],
148 const int const_args
[TCG_MAX_OP_ARGS
]);
150 static inline bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
151 TCGReg dst
, TCGReg src
)
153 g_assert_not_reached();
155 static inline bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
156 TCGReg dst
, TCGReg base
, intptr_t offset
)
158 g_assert_not_reached();
160 static inline void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
161 TCGReg dst
, int64_t arg
)
163 g_assert_not_reached();
165 static inline void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
166 unsigned vecl
, unsigned vece
,
167 const TCGArg args
[TCG_MAX_OP_ARGS
],
168 const int const_args
[TCG_MAX_OP_ARGS
])
170 g_assert_not_reached();
173 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
175 static bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
176 TCGReg base
, intptr_t ofs
);
177 static void tcg_out_call(TCGContext
*s
, const tcg_insn_unit
*target
,
178 const TCGHelperInfo
*info
);
179 static TCGReg
tcg_target_call_oarg_reg(TCGCallReturnKind kind
, int slot
);
180 static bool tcg_target_const_match(int64_t val
, TCGType type
, int ct
);
181 #ifdef TCG_TARGET_NEED_LDST_LABELS
182 static int tcg_out_ldst_finalize(TCGContext
*s
);
185 typedef struct TCGLdstHelperParam
{
186 TCGReg (*ra_gen
)(TCGContext
*s
, const TCGLabelQemuLdst
*l
, int arg_reg
);
189 } TCGLdstHelperParam
;
191 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
192 const TCGLdstHelperParam
*p
)
193 __attribute__((unused
));
194 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
195 bool load_sign
, const TCGLdstHelperParam
*p
)
196 __attribute__((unused
));
197 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
198 const TCGLdstHelperParam
*p
)
199 __attribute__((unused
));
201 static void * const qemu_ld_helpers
[MO_SSIZE
+ 1] __attribute__((unused
)) = {
202 [MO_UB
] = helper_ldub_mmu
,
203 [MO_SB
] = helper_ldsb_mmu
,
204 [MO_UW
] = helper_lduw_mmu
,
205 [MO_SW
] = helper_ldsw_mmu
,
206 [MO_UL
] = helper_ldul_mmu
,
207 [MO_UQ
] = helper_ldq_mmu
,
208 #if TCG_TARGET_REG_BITS == 64
209 [MO_SL
] = helper_ldsl_mmu
,
210 [MO_128
] = helper_ld16_mmu
,
214 static void * const qemu_st_helpers
[MO_SIZE
+ 1] __attribute__((unused
)) = {
215 [MO_8
] = helper_stb_mmu
,
216 [MO_16
] = helper_stw_mmu
,
217 [MO_32
] = helper_stl_mmu
,
218 [MO_64
] = helper_stq_mmu
,
219 #if TCG_TARGET_REG_BITS == 64
220 [MO_128
] = helper_st16_mmu
,
225 MemOp atom
; /* lg2 bits of atomicity required */
226 MemOp align
; /* lg2 bits of alignment to use */
229 static TCGAtomAlign
atom_and_align_for_opc(TCGContext
*s
, MemOp opc
,
230 MemOp host_atom
, bool allow_two_ops
)
231 __attribute__((unused
));
233 TCGContext tcg_init_ctx
;
234 __thread TCGContext
*tcg_ctx
;
236 TCGContext
**tcg_ctxs
;
237 unsigned int tcg_cur_ctxs
;
238 unsigned int tcg_max_ctxs
;
239 TCGv_env cpu_env
= 0;
240 const void *tcg_code_gen_epilogue
;
241 uintptr_t tcg_splitwx_diff
;
243 #ifndef CONFIG_TCG_INTERPRETER
244 tcg_prologue_fn
*tcg_qemu_tb_exec
;
247 static TCGRegSet tcg_target_available_regs
[TCG_TYPE_COUNT
];
248 static TCGRegSet tcg_target_call_clobber_regs
;
250 #if TCG_TARGET_INSN_UNIT_SIZE == 1
251 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
256 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
263 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
264 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
266 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
269 tcg_insn_unit
*p
= s
->code_ptr
;
270 memcpy(p
, &v
, sizeof(v
));
271 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
275 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
278 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
281 memcpy(p
, &v
, sizeof(v
));
286 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
287 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
289 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
292 tcg_insn_unit
*p
= s
->code_ptr
;
293 memcpy(p
, &v
, sizeof(v
));
294 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
298 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
301 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
304 memcpy(p
, &v
, sizeof(v
));
309 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
310 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
312 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
315 tcg_insn_unit
*p
= s
->code_ptr
;
316 memcpy(p
, &v
, sizeof(v
));
317 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
321 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
324 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
327 memcpy(p
, &v
, sizeof(v
));
332 /* label relocation processing */
334 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
335 TCGLabel
*l
, intptr_t addend
)
337 TCGRelocation
*r
= tcg_malloc(sizeof(TCGRelocation
));
342 QSIMPLEQ_INSERT_TAIL(&l
->relocs
, r
, next
);
345 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
)
347 tcg_debug_assert(!l
->has_value
);
349 l
->u
.value_ptr
= tcg_splitwx_to_rx(s
->code_ptr
);
352 TCGLabel
*gen_new_label(void)
354 TCGContext
*s
= tcg_ctx
;
355 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
357 memset(l
, 0, sizeof(TCGLabel
));
358 l
->id
= s
->nb_labels
++;
359 QSIMPLEQ_INIT(&l
->branches
);
360 QSIMPLEQ_INIT(&l
->relocs
);
362 QSIMPLEQ_INSERT_TAIL(&s
->labels
, l
, next
);
367 static bool tcg_resolve_relocs(TCGContext
*s
)
371 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
373 uintptr_t value
= l
->u
.value
;
375 QSIMPLEQ_FOREACH(r
, &l
->relocs
, next
) {
376 if (!patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
)) {
384 static void set_jmp_reset_offset(TCGContext
*s
, int which
)
387 * We will check for overflow at the end of the opcode loop in
388 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
390 s
->gen_tb
->jmp_reset_offset
[which
] = tcg_current_code_size(s
);
393 static void G_GNUC_UNUSED
set_jmp_insn_offset(TCGContext
*s
, int which
)
396 * We will check for overflow at the end of the opcode loop in
397 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
399 s
->gen_tb
->jmp_insn_offset
[which
] = tcg_current_code_size(s
);
402 static uintptr_t G_GNUC_UNUSED
get_jmp_target_addr(TCGContext
*s
, int which
)
405 * Return the read-execute version of the pointer, for the benefit
406 * of any pc-relative addressing mode.
408 return (uintptr_t)tcg_splitwx_to_rx(&s
->gen_tb
->jmp_target_addr
[which
]);
411 #if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER)
412 static int tlb_mask_table_ofs(TCGContext
*s
, int which
)
414 return s
->tlb_fast_offset
+ which
* sizeof(CPUTLBDescFast
);
418 /* Signal overflow, starting over with fewer guest insns. */
420 void tcg_raise_tb_overflow(TCGContext
*s
)
422 siglongjmp(s
->jmp_trans
, -2);
426 * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext.
427 * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg.
429 * However, tcg_out_helper_load_slots reuses this field to hold an
430 * argument slot number (which may designate a argument register or an
431 * argument stack slot), converting to TCGReg once all arguments that
432 * are destined for the stack are processed.
434 typedef struct TCGMovExtend
{
443 * tcg_out_movext -- move and extend
445 * @dst_type: integral type for destination
446 * @dst: destination register
447 * @src_type: integral type for source
448 * @src_ext: extension to apply to source
449 * @src: source register
451 * Move or extend @src into @dst, depending on @src_ext and the types.
453 static void tcg_out_movext(TCGContext
*s
, TCGType dst_type
, TCGReg dst
,
454 TCGType src_type
, MemOp src_ext
, TCGReg src
)
458 tcg_out_ext8u(s
, dst
, src
);
461 tcg_out_ext8s(s
, dst_type
, dst
, src
);
464 tcg_out_ext16u(s
, dst
, src
);
467 tcg_out_ext16s(s
, dst_type
, dst
, src
);
471 if (dst_type
== TCG_TYPE_I32
) {
472 if (src_type
== TCG_TYPE_I32
) {
473 tcg_out_mov(s
, TCG_TYPE_I32
, dst
, src
);
475 tcg_out_extrl_i64_i32(s
, dst
, src
);
477 } else if (src_type
== TCG_TYPE_I32
) {
478 if (src_ext
& MO_SIGN
) {
479 tcg_out_exts_i32_i64(s
, dst
, src
);
481 tcg_out_extu_i32_i64(s
, dst
, src
);
484 if (src_ext
& MO_SIGN
) {
485 tcg_out_ext32s(s
, dst
, src
);
487 tcg_out_ext32u(s
, dst
, src
);
492 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
493 if (dst_type
== TCG_TYPE_I32
) {
494 tcg_out_extrl_i64_i32(s
, dst
, src
);
496 tcg_out_mov(s
, TCG_TYPE_I64
, dst
, src
);
500 g_assert_not_reached();
504 /* Minor variations on a theme, using a structure. */
505 static void tcg_out_movext1_new_src(TCGContext
*s
, const TCGMovExtend
*i
,
508 tcg_out_movext(s
, i
->dst_type
, i
->dst
, i
->src_type
, i
->src_ext
, src
);
511 static void tcg_out_movext1(TCGContext
*s
, const TCGMovExtend
*i
)
513 tcg_out_movext1_new_src(s
, i
, i
->src
);
517 * tcg_out_movext2 -- move and extend two pair
519 * @i1: first move description
520 * @i2: second move description
521 * @scratch: temporary register, or -1 for none
523 * As tcg_out_movext, for both @i1 and @i2, caring for overlap
524 * between the sources and destinations.
527 static void tcg_out_movext2(TCGContext
*s
, const TCGMovExtend
*i1
,
528 const TCGMovExtend
*i2
, int scratch
)
530 TCGReg src1
= i1
->src
;
531 TCGReg src2
= i2
->src
;
533 if (i1
->dst
!= src2
) {
534 tcg_out_movext1(s
, i1
);
535 tcg_out_movext1(s
, i2
);
538 if (i2
->dst
== src1
) {
539 TCGType src1_type
= i1
->src_type
;
540 TCGType src2_type
= i2
->src_type
;
542 if (tcg_out_xchg(s
, MAX(src1_type
, src2_type
), src1
, src2
)) {
543 /* The data is now in the correct registers, now extend. */
547 tcg_debug_assert(scratch
>= 0);
548 tcg_out_mov(s
, src1_type
, scratch
, src1
);
552 tcg_out_movext1_new_src(s
, i2
, src2
);
553 tcg_out_movext1_new_src(s
, i1
, src1
);
557 * tcg_out_movext3 -- move and extend three pair
559 * @i1: first move description
560 * @i2: second move description
561 * @i3: third move description
562 * @scratch: temporary register, or -1 for none
564 * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap
565 * between the sources and destinations.
568 static void tcg_out_movext3(TCGContext
*s
, const TCGMovExtend
*i1
,
569 const TCGMovExtend
*i2
, const TCGMovExtend
*i3
,
572 TCGReg src1
= i1
->src
;
573 TCGReg src2
= i2
->src
;
574 TCGReg src3
= i3
->src
;
576 if (i1
->dst
!= src2
&& i1
->dst
!= src3
) {
577 tcg_out_movext1(s
, i1
);
578 tcg_out_movext2(s
, i2
, i3
, scratch
);
581 if (i2
->dst
!= src1
&& i2
->dst
!= src3
) {
582 tcg_out_movext1(s
, i2
);
583 tcg_out_movext2(s
, i1
, i3
, scratch
);
586 if (i3
->dst
!= src1
&& i3
->dst
!= src2
) {
587 tcg_out_movext1(s
, i3
);
588 tcg_out_movext2(s
, i1
, i2
, scratch
);
593 * There is a cycle. Since there are only 3 nodes, the cycle is
594 * either "clockwise" or "anti-clockwise", and can be solved with
595 * a single scratch or two xchg.
597 if (i1
->dst
== src2
&& i2
->dst
== src3
&& i3
->dst
== src1
) {
599 if (tcg_out_xchg(s
, MAX(i1
->src_type
, i2
->src_type
), src1
, src2
)) {
600 tcg_out_xchg(s
, MAX(i2
->src_type
, i3
->src_type
), src2
, src3
);
601 /* The data is now in the correct registers, now extend. */
602 tcg_out_movext1_new_src(s
, i1
, i1
->dst
);
603 tcg_out_movext1_new_src(s
, i2
, i2
->dst
);
604 tcg_out_movext1_new_src(s
, i3
, i3
->dst
);
606 tcg_debug_assert(scratch
>= 0);
607 tcg_out_mov(s
, i1
->src_type
, scratch
, src1
);
608 tcg_out_movext1(s
, i3
);
609 tcg_out_movext1(s
, i2
);
610 tcg_out_movext1_new_src(s
, i1
, scratch
);
612 } else if (i1
->dst
== src3
&& i2
->dst
== src1
&& i3
->dst
== src2
) {
613 /* "Anti-clockwise" */
614 if (tcg_out_xchg(s
, MAX(i2
->src_type
, i3
->src_type
), src2
, src3
)) {
615 tcg_out_xchg(s
, MAX(i1
->src_type
, i2
->src_type
), src1
, src2
);
616 /* The data is now in the correct registers, now extend. */
617 tcg_out_movext1_new_src(s
, i1
, i1
->dst
);
618 tcg_out_movext1_new_src(s
, i2
, i2
->dst
);
619 tcg_out_movext1_new_src(s
, i3
, i3
->dst
);
621 tcg_debug_assert(scratch
>= 0);
622 tcg_out_mov(s
, i1
->src_type
, scratch
, src1
);
623 tcg_out_movext1(s
, i2
);
624 tcg_out_movext1(s
, i3
);
625 tcg_out_movext1_new_src(s
, i1
, scratch
);
628 g_assert_not_reached();
632 #define C_PFX1(P, A) P##A
633 #define C_PFX2(P, A, B) P##A##_##B
634 #define C_PFX3(P, A, B, C) P##A##_##B##_##C
635 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
636 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
637 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
639 /* Define an enumeration for the various combinations. */
641 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
642 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
643 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
644 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
646 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
647 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
648 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
649 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
651 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
653 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
654 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
655 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
656 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
659 #include "tcg-target-con-set.h"
660 } TCGConstraintSetIndex
;
662 static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode
);
678 /* Put all of the constraint sets into an array, indexed by the enum. */
680 #define C_O0_I1(I1) { .args_ct_str = { #I1 } },
681 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
682 #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
683 #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
685 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
686 #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
687 #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
688 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
690 #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
692 #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
693 #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
694 #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
695 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
697 static const TCGTargetOpDef constraint_sets
[] = {
698 #include "tcg-target-con-set.h"
716 /* Expand the enumerator to be returned from tcg_target_op_def(). */
718 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
719 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
720 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
721 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
723 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
724 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
725 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
726 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
728 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
730 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
731 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
732 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
733 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
735 #include "tcg-target.c.inc"
737 static void alloc_tcg_plugin_context(TCGContext
*s
)
740 s
->plugin_tb
= g_new0(struct qemu_plugin_tb
, 1);
741 s
->plugin_tb
->insns
=
742 g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn
);
747 * All TCG threads except the parent (i.e. the one that called tcg_context_init
748 * and registered the target's TCG globals) must register with this function
749 * before initiating translation.
751 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation
752 * of tcg_region_init() for the reasoning behind this.
754 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in
755 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context
756 * is not used anymore for translation once this function is called.
758 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates
759 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode.
761 #ifdef CONFIG_USER_ONLY
762 void tcg_register_thread(void)
764 tcg_ctx
= &tcg_init_ctx
;
767 void tcg_register_thread(void)
769 TCGContext
*s
= g_malloc(sizeof(*s
));
774 /* Relink mem_base. */
775 for (i
= 0, n
= tcg_init_ctx
.nb_globals
; i
< n
; ++i
) {
776 if (tcg_init_ctx
.temps
[i
].mem_base
) {
777 ptrdiff_t b
= tcg_init_ctx
.temps
[i
].mem_base
- tcg_init_ctx
.temps
;
778 tcg_debug_assert(b
>= 0 && b
< n
);
779 s
->temps
[i
].mem_base
= &s
->temps
[b
];
783 /* Claim an entry in tcg_ctxs */
784 n
= qatomic_fetch_inc(&tcg_cur_ctxs
);
785 g_assert(n
< tcg_max_ctxs
);
786 qatomic_set(&tcg_ctxs
[n
], s
);
789 alloc_tcg_plugin_context(s
);
790 tcg_region_initial_alloc(s
);
795 #endif /* !CONFIG_USER_ONLY */
797 /* pool based memory allocation */
798 void *tcg_malloc_internal(TCGContext
*s
, int size
)
803 if (size
> TCG_POOL_CHUNK_SIZE
) {
804 /* big malloc: insert a new pool (XXX: could optimize) */
805 p
= g_malloc(sizeof(TCGPool
) + size
);
807 p
->next
= s
->pool_first_large
;
808 s
->pool_first_large
= p
;
819 pool_size
= TCG_POOL_CHUNK_SIZE
;
820 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
823 if (s
->pool_current
) {
824 s
->pool_current
->next
= p
;
834 s
->pool_cur
= p
->data
+ size
;
835 s
->pool_end
= p
->data
+ p
->size
;
839 void tcg_pool_reset(TCGContext
*s
)
842 for (p
= s
->pool_first_large
; p
; p
= t
) {
846 s
->pool_first_large
= NULL
;
847 s
->pool_cur
= s
->pool_end
= NULL
;
848 s
->pool_current
= NULL
;
852 * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions,
853 * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N.
854 * We only use these for layout in tcg_out_ld_helper_ret and
855 * tcg_out_st_helper_args, and share them between several of
856 * the helpers, with the end result that it's easier to build manually.
859 #if TCG_TARGET_REG_BITS == 32
860 # define dh_typecode_ttl dh_typecode_i32
862 # define dh_typecode_ttl dh_typecode_i64
865 static TCGHelperInfo info_helper_ld32_mmu
= {
866 .flags
= TCG_CALL_NO_WG
,
867 .typemask
= dh_typemask(ttl
, 0) /* return tcg_target_ulong */
868 | dh_typemask(env
, 1)
869 | dh_typemask(i64
, 2) /* uint64_t addr */
870 | dh_typemask(i32
, 3) /* unsigned oi */
871 | dh_typemask(ptr
, 4) /* uintptr_t ra */
874 static TCGHelperInfo info_helper_ld64_mmu
= {
875 .flags
= TCG_CALL_NO_WG
,
876 .typemask
= dh_typemask(i64
, 0) /* return uint64_t */
877 | dh_typemask(env
, 1)
878 | dh_typemask(i64
, 2) /* uint64_t addr */
879 | dh_typemask(i32
, 3) /* unsigned oi */
880 | dh_typemask(ptr
, 4) /* uintptr_t ra */
883 static TCGHelperInfo info_helper_ld128_mmu
= {
884 .flags
= TCG_CALL_NO_WG
,
885 .typemask
= dh_typemask(i128
, 0) /* return Int128 */
886 | dh_typemask(env
, 1)
887 | dh_typemask(i64
, 2) /* uint64_t addr */
888 | dh_typemask(i32
, 3) /* unsigned oi */
889 | dh_typemask(ptr
, 4) /* uintptr_t ra */
892 static TCGHelperInfo info_helper_st32_mmu
= {
893 .flags
= TCG_CALL_NO_WG
,
894 .typemask
= dh_typemask(void, 0)
895 | dh_typemask(env
, 1)
896 | dh_typemask(i64
, 2) /* uint64_t addr */
897 | dh_typemask(i32
, 3) /* uint32_t data */
898 | dh_typemask(i32
, 4) /* unsigned oi */
899 | dh_typemask(ptr
, 5) /* uintptr_t ra */
902 static TCGHelperInfo info_helper_st64_mmu
= {
903 .flags
= TCG_CALL_NO_WG
,
904 .typemask
= dh_typemask(void, 0)
905 | dh_typemask(env
, 1)
906 | dh_typemask(i64
, 2) /* uint64_t addr */
907 | dh_typemask(i64
, 3) /* uint64_t data */
908 | dh_typemask(i32
, 4) /* unsigned oi */
909 | dh_typemask(ptr
, 5) /* uintptr_t ra */
912 static TCGHelperInfo info_helper_st128_mmu
= {
913 .flags
= TCG_CALL_NO_WG
,
914 .typemask
= dh_typemask(void, 0)
915 | dh_typemask(env
, 1)
916 | dh_typemask(i64
, 2) /* uint64_t addr */
917 | dh_typemask(i128
, 3) /* Int128 data */
918 | dh_typemask(i32
, 4) /* unsigned oi */
919 | dh_typemask(ptr
, 5) /* uintptr_t ra */
922 #ifdef CONFIG_TCG_INTERPRETER
923 static ffi_type
*typecode_to_ffi(int argmask
)
926 * libffi does not support __int128_t, so we have forced Int128
927 * to use the structure definition instead of the builtin type.
929 static ffi_type
*ffi_type_i128_elements
[3] = {
934 static ffi_type ffi_type_i128
= {
936 .alignment
= __alignof__(Int128
),
937 .type
= FFI_TYPE_STRUCT
,
938 .elements
= ffi_type_i128_elements
,
942 case dh_typecode_void
:
943 return &ffi_type_void
;
944 case dh_typecode_i32
:
945 return &ffi_type_uint32
;
946 case dh_typecode_s32
:
947 return &ffi_type_sint32
;
948 case dh_typecode_i64
:
949 return &ffi_type_uint64
;
950 case dh_typecode_s64
:
951 return &ffi_type_sint64
;
952 case dh_typecode_ptr
:
953 return &ffi_type_pointer
;
954 case dh_typecode_i128
:
955 return &ffi_type_i128
;
957 g_assert_not_reached();
960 static ffi_cif
*init_ffi_layout(TCGHelperInfo
*info
)
962 unsigned typemask
= info
->typemask
;
970 /* Ignoring the return type, find the last non-zero field. */
971 nargs
= 32 - clz32(typemask
>> 3);
972 nargs
= DIV_ROUND_UP(nargs
, 3);
973 assert(nargs
<= MAX_CALL_IARGS
);
975 ca
= g_malloc0(sizeof(*ca
) + nargs
* sizeof(ffi_type
*));
976 ca
->cif
.rtype
= typecode_to_ffi(typemask
& 7);
977 ca
->cif
.nargs
= nargs
;
980 ca
->cif
.arg_types
= ca
->args
;
981 for (int j
= 0; j
< nargs
; ++j
) {
982 int typecode
= extract32(typemask
, (j
+ 1) * 3, 3);
983 ca
->args
[j
] = typecode_to_ffi(typecode
);
987 status
= ffi_prep_cif(&ca
->cif
, FFI_DEFAULT_ABI
, nargs
,
988 ca
->cif
.rtype
, ca
->cif
.arg_types
);
989 assert(status
== FFI_OK
);
994 #define HELPER_INFO_INIT(I) (&(I)->cif)
995 #define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I)
997 #define HELPER_INFO_INIT(I) (&(I)->init)
998 #define HELPER_INFO_INIT_VAL(I) 1
999 #endif /* CONFIG_TCG_INTERPRETER */
1001 static inline bool arg_slot_reg_p(unsigned arg_slot
)
1004 * Split the sizeof away from the comparison to avoid Werror from
1005 * "unsigned < 0 is always false", when iarg_regs is empty.
1007 unsigned nreg
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
1008 return arg_slot
< nreg
;
1011 static inline int arg_slot_stk_ofs(unsigned arg_slot
)
1013 unsigned max
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
1014 unsigned stk_slot
= arg_slot
- ARRAY_SIZE(tcg_target_call_iarg_regs
);
1016 tcg_debug_assert(stk_slot
< max
);
1017 return TCG_TARGET_CALL_STACK_OFFSET
+ stk_slot
* sizeof(tcg_target_long
);
1020 typedef struct TCGCumulativeArgs
{
1021 int arg_idx
; /* tcg_gen_callN args[] */
1022 int info_in_idx
; /* TCGHelperInfo in[] */
1023 int arg_slot
; /* regs+stack slot */
1024 int ref_slot
; /* stack slots for references */
1025 } TCGCumulativeArgs
;
1027 static void layout_arg_even(TCGCumulativeArgs
*cum
)
1029 cum
->arg_slot
+= cum
->arg_slot
& 1;
1032 static void layout_arg_1(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
,
1033 TCGCallArgumentKind kind
)
1035 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1037 *loc
= (TCGCallArgumentLoc
){
1039 .arg_idx
= cum
->arg_idx
,
1040 .arg_slot
= cum
->arg_slot
,
1046 static void layout_arg_normal_n(TCGCumulativeArgs
*cum
,
1047 TCGHelperInfo
*info
, int n
)
1049 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1051 for (int i
= 0; i
< n
; ++i
) {
1052 /* Layout all using the same arg_idx, adjusting the subindex. */
1053 loc
[i
] = (TCGCallArgumentLoc
){
1054 .kind
= TCG_CALL_ARG_NORMAL
,
1055 .arg_idx
= cum
->arg_idx
,
1057 .arg_slot
= cum
->arg_slot
+ i
,
1060 cum
->info_in_idx
+= n
;
1064 static void layout_arg_by_ref(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
)
1066 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1067 int n
= 128 / TCG_TARGET_REG_BITS
;
1069 /* The first subindex carries the pointer. */
1070 layout_arg_1(cum
, info
, TCG_CALL_ARG_BY_REF
);
1073 * The callee is allowed to clobber memory associated with
1074 * structure pass by-reference. Therefore we must make copies.
1075 * Allocate space from "ref_slot", which will be adjusted to
1076 * follow the parameters on the stack.
1078 loc
[0].ref_slot
= cum
->ref_slot
;
1081 * Subsequent words also go into the reference slot, but
1082 * do not accumulate into the regular arguments.
1084 for (int i
= 1; i
< n
; ++i
) {
1085 loc
[i
] = (TCGCallArgumentLoc
){
1086 .kind
= TCG_CALL_ARG_BY_REF_N
,
1087 .arg_idx
= cum
->arg_idx
,
1089 .ref_slot
= cum
->ref_slot
+ i
,
1092 cum
->info_in_idx
+= n
;
1096 static void init_call_layout(TCGHelperInfo
*info
)
1098 int max_reg_slots
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
1099 int max_stk_slots
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
1100 unsigned typemask
= info
->typemask
;
1102 TCGCumulativeArgs cum
= { };
1105 * Parse and place any function return value.
1107 typecode
= typemask
& 7;
1109 case dh_typecode_void
:
1112 case dh_typecode_i32
:
1113 case dh_typecode_s32
:
1114 case dh_typecode_ptr
:
1116 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1118 case dh_typecode_i64
:
1119 case dh_typecode_s64
:
1120 info
->nr_out
= 64 / TCG_TARGET_REG_BITS
;
1121 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1122 /* Query the last register now to trigger any assert early. */
1123 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1125 case dh_typecode_i128
:
1126 info
->nr_out
= 128 / TCG_TARGET_REG_BITS
;
1127 info
->out_kind
= TCG_TARGET_CALL_RET_I128
;
1128 switch (TCG_TARGET_CALL_RET_I128
) {
1129 case TCG_CALL_RET_NORMAL
:
1130 /* Query the last register now to trigger any assert early. */
1131 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1133 case TCG_CALL_RET_BY_VEC
:
1134 /* Query the single register now to trigger any assert early. */
1135 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0);
1137 case TCG_CALL_RET_BY_REF
:
1139 * Allocate the first argument to the output.
1140 * We don't need to store this anywhere, just make it
1141 * unavailable for use in the input loop below.
1146 qemu_build_not_reached();
1150 g_assert_not_reached();
1154 * Parse and place function arguments.
1156 for (typemask
>>= 3; typemask
; typemask
>>= 3, cum
.arg_idx
++) {
1157 TCGCallArgumentKind kind
;
1160 typecode
= typemask
& 7;
1162 case dh_typecode_i32
:
1163 case dh_typecode_s32
:
1164 type
= TCG_TYPE_I32
;
1166 case dh_typecode_i64
:
1167 case dh_typecode_s64
:
1168 type
= TCG_TYPE_I64
;
1170 case dh_typecode_ptr
:
1171 type
= TCG_TYPE_PTR
;
1173 case dh_typecode_i128
:
1174 type
= TCG_TYPE_I128
;
1177 g_assert_not_reached();
1182 switch (TCG_TARGET_CALL_ARG_I32
) {
1183 case TCG_CALL_ARG_EVEN
:
1184 layout_arg_even(&cum
);
1186 case TCG_CALL_ARG_NORMAL
:
1187 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1189 case TCG_CALL_ARG_EXTEND
:
1190 kind
= TCG_CALL_ARG_EXTEND_U
+ (typecode
& 1);
1191 layout_arg_1(&cum
, info
, kind
);
1194 qemu_build_not_reached();
1199 switch (TCG_TARGET_CALL_ARG_I64
) {
1200 case TCG_CALL_ARG_EVEN
:
1201 layout_arg_even(&cum
);
1203 case TCG_CALL_ARG_NORMAL
:
1204 if (TCG_TARGET_REG_BITS
== 32) {
1205 layout_arg_normal_n(&cum
, info
, 2);
1207 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1211 qemu_build_not_reached();
1216 switch (TCG_TARGET_CALL_ARG_I128
) {
1217 case TCG_CALL_ARG_EVEN
:
1218 layout_arg_even(&cum
);
1220 case TCG_CALL_ARG_NORMAL
:
1221 layout_arg_normal_n(&cum
, info
, 128 / TCG_TARGET_REG_BITS
);
1223 case TCG_CALL_ARG_BY_REF
:
1224 layout_arg_by_ref(&cum
, info
);
1227 qemu_build_not_reached();
1232 g_assert_not_reached();
1235 info
->nr_in
= cum
.info_in_idx
;
1237 /* Validate that we didn't overrun the input array. */
1238 assert(cum
.info_in_idx
<= ARRAY_SIZE(info
->in
));
1239 /* Validate the backend has enough argument space. */
1240 assert(cum
.arg_slot
<= max_reg_slots
+ max_stk_slots
);
1243 * Relocate the "ref_slot" area to the end of the parameters.
1244 * Minimizing this stack offset helps code size for x86,
1245 * which has a signed 8-bit offset encoding.
1247 if (cum
.ref_slot
!= 0) {
1250 if (cum
.arg_slot
> max_reg_slots
) {
1251 int align
= __alignof(Int128
) / sizeof(tcg_target_long
);
1253 ref_base
= cum
.arg_slot
- max_reg_slots
;
1255 ref_base
= ROUND_UP(ref_base
, align
);
1258 assert(ref_base
+ cum
.ref_slot
<= max_stk_slots
);
1259 ref_base
+= max_reg_slots
;
1261 if (ref_base
!= 0) {
1262 for (int i
= cum
.info_in_idx
- 1; i
>= 0; --i
) {
1263 TCGCallArgumentLoc
*loc
= &info
->in
[i
];
1264 switch (loc
->kind
) {
1265 case TCG_CALL_ARG_BY_REF
:
1266 case TCG_CALL_ARG_BY_REF_N
:
1267 loc
->ref_slot
+= ref_base
;
1277 static int indirect_reg_alloc_order
[ARRAY_SIZE(tcg_target_reg_alloc_order
)];
1278 static void process_op_defs(TCGContext
*s
);
1279 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1280 TCGReg reg
, const char *name
);
1282 static void tcg_context_init(unsigned max_cpus
)
1284 TCGContext
*s
= &tcg_init_ctx
;
1285 int op
, total_args
, n
, i
;
1287 TCGArgConstraint
*args_ct
;
1290 memset(s
, 0, sizeof(*s
));
1293 /* Count total number of arguments and allocate the corresponding
1296 for(op
= 0; op
< NB_OPS
; op
++) {
1297 def
= &tcg_op_defs
[op
];
1298 n
= def
->nb_iargs
+ def
->nb_oargs
;
1302 args_ct
= g_new0(TCGArgConstraint
, total_args
);
1304 for(op
= 0; op
< NB_OPS
; op
++) {
1305 def
= &tcg_op_defs
[op
];
1306 def
->args_ct
= args_ct
;
1307 n
= def
->nb_iargs
+ def
->nb_oargs
;
1311 init_call_layout(&info_helper_ld32_mmu
);
1312 init_call_layout(&info_helper_ld64_mmu
);
1313 init_call_layout(&info_helper_ld128_mmu
);
1314 init_call_layout(&info_helper_st32_mmu
);
1315 init_call_layout(&info_helper_st64_mmu
);
1316 init_call_layout(&info_helper_st128_mmu
);
1321 /* Reverse the order of the saved registers, assuming they're all at
1322 the start of tcg_target_reg_alloc_order. */
1323 for (n
= 0; n
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++n
) {
1324 int r
= tcg_target_reg_alloc_order
[n
];
1325 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, r
)) {
1329 for (i
= 0; i
< n
; ++i
) {
1330 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[n
- 1 - i
];
1332 for (; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++i
) {
1333 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[i
];
1336 alloc_tcg_plugin_context(s
);
1340 * In user-mode we simply share the init context among threads, since we
1341 * use a single region. See the documentation tcg_region_init() for the
1342 * reasoning behind this.
1343 * In softmmu we will have at most max_cpus TCG threads.
1345 #ifdef CONFIG_USER_ONLY
1346 tcg_ctxs
= &tcg_ctx
;
1350 tcg_max_ctxs
= max_cpus
;
1351 tcg_ctxs
= g_new0(TCGContext
*, max_cpus
);
1354 tcg_debug_assert(!tcg_regset_test_reg(s
->reserved_regs
, TCG_AREG0
));
1355 ts
= tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, TCG_AREG0
, "env");
1356 cpu_env
= temp_tcgv_ptr(ts
);
1359 void tcg_init(size_t tb_size
, int splitwx
, unsigned max_cpus
)
1361 tcg_context_init(max_cpus
);
1362 tcg_region_init(tb_size
, splitwx
, max_cpus
);
1366 * Allocate TBs right before their corresponding translated code, making
1367 * sure that TBs and code are on different cache lines.
1369 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
)
1371 uintptr_t align
= qemu_icache_linesize
;
1372 TranslationBlock
*tb
;
1376 tb
= (void *)ROUND_UP((uintptr_t)s
->code_gen_ptr
, align
);
1377 next
= (void *)ROUND_UP((uintptr_t)(tb
+ 1), align
);
1379 if (unlikely(next
> s
->code_gen_highwater
)) {
1380 if (tcg_region_alloc(s
)) {
1385 qatomic_set(&s
->code_gen_ptr
, next
);
1386 s
->data_gen_ptr
= NULL
;
1390 void tcg_prologue_init(TCGContext
*s
)
1392 size_t prologue_size
;
1394 s
->code_ptr
= s
->code_gen_ptr
;
1395 s
->code_buf
= s
->code_gen_ptr
;
1396 s
->data_gen_ptr
= NULL
;
1398 #ifndef CONFIG_TCG_INTERPRETER
1399 tcg_qemu_tb_exec
= (tcg_prologue_fn
*)tcg_splitwx_to_rx(s
->code_ptr
);
1402 #ifdef TCG_TARGET_NEED_POOL_LABELS
1403 s
->pool_labels
= NULL
;
1406 qemu_thread_jit_write();
1407 /* Generate the prologue. */
1408 tcg_target_qemu_prologue(s
);
1410 #ifdef TCG_TARGET_NEED_POOL_LABELS
1411 /* Allow the prologue to put e.g. guest_base into a pool entry. */
1413 int result
= tcg_out_pool_finalize(s
);
1414 tcg_debug_assert(result
== 0);
1418 prologue_size
= tcg_current_code_size(s
);
1419 perf_report_prologue(s
->code_gen_ptr
, prologue_size
);
1421 #ifndef CONFIG_TCG_INTERPRETER
1422 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
1423 (uintptr_t)s
->code_buf
, prologue_size
);
1426 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
1427 FILE *logfile
= qemu_log_trylock();
1429 fprintf(logfile
, "PROLOGUE: [size=%zu]\n", prologue_size
);
1430 if (s
->data_gen_ptr
) {
1431 size_t code_size
= s
->data_gen_ptr
- s
->code_gen_ptr
;
1432 size_t data_size
= prologue_size
- code_size
;
1435 disas(logfile
, s
->code_gen_ptr
, code_size
);
1437 for (i
= 0; i
< data_size
; i
+= sizeof(tcg_target_ulong
)) {
1438 if (sizeof(tcg_target_ulong
) == 8) {
1440 "0x%08" PRIxPTR
": .quad 0x%016" PRIx64
"\n",
1441 (uintptr_t)s
->data_gen_ptr
+ i
,
1442 *(uint64_t *)(s
->data_gen_ptr
+ i
));
1445 "0x%08" PRIxPTR
": .long 0x%08x\n",
1446 (uintptr_t)s
->data_gen_ptr
+ i
,
1447 *(uint32_t *)(s
->data_gen_ptr
+ i
));
1451 disas(logfile
, s
->code_gen_ptr
, prologue_size
);
1453 fprintf(logfile
, "\n");
1454 qemu_log_unlock(logfile
);
1458 #ifndef CONFIG_TCG_INTERPRETER
1460 * Assert that goto_ptr is implemented completely, setting an epilogue.
1461 * For tci, we use NULL as the signal to return from the interpreter,
1462 * so skip this check.
1464 tcg_debug_assert(tcg_code_gen_epilogue
!= NULL
);
1467 tcg_region_prologue_set(s
);
1470 void tcg_func_start(TCGContext
*s
)
1473 s
->nb_temps
= s
->nb_globals
;
1475 /* No temps have been previously allocated for size or locality. */
1476 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
1478 /* No constant temps have been previously allocated. */
1479 for (int i
= 0; i
< TCG_TYPE_COUNT
; ++i
) {
1480 if (s
->const_table
[i
]) {
1481 g_hash_table_remove_all(s
->const_table
[i
]);
1487 s
->current_frame_offset
= s
->frame_start
;
1489 #ifdef CONFIG_DEBUG_TCG
1490 s
->goto_tb_issue_mask
= 0;
1493 QTAILQ_INIT(&s
->ops
);
1494 QTAILQ_INIT(&s
->free_ops
);
1495 QSIMPLEQ_INIT(&s
->labels
);
1497 tcg_debug_assert(s
->addr_type
== TCG_TYPE_I32
||
1498 s
->addr_type
== TCG_TYPE_I64
);
1500 #if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER)
1501 tcg_debug_assert(s
->tlb_fast_offset
< 0);
1502 tcg_debug_assert(s
->tlb_fast_offset
>= MIN_TLB_MASK_TABLE_OFS
);
1506 static TCGTemp
*tcg_temp_alloc(TCGContext
*s
)
1508 int n
= s
->nb_temps
++;
1510 if (n
>= TCG_MAX_TEMPS
) {
1511 tcg_raise_tb_overflow(s
);
1513 return memset(&s
->temps
[n
], 0, sizeof(TCGTemp
));
1516 static TCGTemp
*tcg_global_alloc(TCGContext
*s
)
1520 tcg_debug_assert(s
->nb_globals
== s
->nb_temps
);
1521 tcg_debug_assert(s
->nb_globals
< TCG_MAX_TEMPS
);
1523 ts
= tcg_temp_alloc(s
);
1524 ts
->kind
= TEMP_GLOBAL
;
1529 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1530 TCGReg reg
, const char *name
)
1534 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
1536 ts
= tcg_global_alloc(s
);
1537 ts
->base_type
= type
;
1539 ts
->kind
= TEMP_FIXED
;
1542 tcg_regset_set_reg(s
->reserved_regs
, reg
);
1547 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
)
1549 s
->frame_start
= start
;
1550 s
->frame_end
= start
+ size
;
1552 = tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, reg
, "_frame");
1555 TCGTemp
*tcg_global_mem_new_internal(TCGType type
, TCGv_ptr base
,
1556 intptr_t offset
, const char *name
)
1558 TCGContext
*s
= tcg_ctx
;
1559 TCGTemp
*base_ts
= tcgv_ptr_temp(base
);
1560 TCGTemp
*ts
= tcg_global_alloc(s
);
1561 int indirect_reg
= 0;
1563 switch (base_ts
->kind
) {
1567 /* We do not support double-indirect registers. */
1568 tcg_debug_assert(!base_ts
->indirect_reg
);
1569 base_ts
->indirect_base
= 1;
1570 s
->nb_indirects
+= (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
1575 g_assert_not_reached();
1578 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1579 TCGTemp
*ts2
= tcg_global_alloc(s
);
1582 ts
->base_type
= TCG_TYPE_I64
;
1583 ts
->type
= TCG_TYPE_I32
;
1584 ts
->indirect_reg
= indirect_reg
;
1585 ts
->mem_allocated
= 1;
1586 ts
->mem_base
= base_ts
;
1587 ts
->mem_offset
= offset
;
1588 pstrcpy(buf
, sizeof(buf
), name
);
1589 pstrcat(buf
, sizeof(buf
), "_0");
1590 ts
->name
= strdup(buf
);
1592 tcg_debug_assert(ts2
== ts
+ 1);
1593 ts2
->base_type
= TCG_TYPE_I64
;
1594 ts2
->type
= TCG_TYPE_I32
;
1595 ts2
->indirect_reg
= indirect_reg
;
1596 ts2
->mem_allocated
= 1;
1597 ts2
->mem_base
= base_ts
;
1598 ts2
->mem_offset
= offset
+ 4;
1599 ts2
->temp_subindex
= 1;
1600 pstrcpy(buf
, sizeof(buf
), name
);
1601 pstrcat(buf
, sizeof(buf
), "_1");
1602 ts2
->name
= strdup(buf
);
1604 ts
->base_type
= type
;
1606 ts
->indirect_reg
= indirect_reg
;
1607 ts
->mem_allocated
= 1;
1608 ts
->mem_base
= base_ts
;
1609 ts
->mem_offset
= offset
;
1615 TCGTemp
*tcg_temp_new_internal(TCGType type
, TCGTempKind kind
)
1617 TCGContext
*s
= tcg_ctx
;
1621 if (kind
== TEMP_EBB
) {
1622 int idx
= find_first_bit(s
->free_temps
[type
].l
, TCG_MAX_TEMPS
);
1624 if (idx
< TCG_MAX_TEMPS
) {
1625 /* There is already an available temp with the right type. */
1626 clear_bit(idx
, s
->free_temps
[type
].l
);
1628 ts
= &s
->temps
[idx
];
1629 ts
->temp_allocated
= 1;
1630 tcg_debug_assert(ts
->base_type
== type
);
1631 tcg_debug_assert(ts
->kind
== kind
);
1635 tcg_debug_assert(kind
== TEMP_TB
);
1646 n
= 64 / TCG_TARGET_REG_BITS
;
1649 n
= 128 / TCG_TARGET_REG_BITS
;
1652 g_assert_not_reached();
1655 ts
= tcg_temp_alloc(s
);
1656 ts
->base_type
= type
;
1657 ts
->temp_allocated
= 1;
1663 ts
->type
= TCG_TYPE_REG
;
1665 for (int i
= 1; i
< n
; ++i
) {
1666 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1668 tcg_debug_assert(ts2
== ts
+ i
);
1669 ts2
->base_type
= type
;
1670 ts2
->type
= TCG_TYPE_REG
;
1671 ts2
->temp_allocated
= 1;
1672 ts2
->temp_subindex
= i
;
1679 TCGv_vec
tcg_temp_new_vec(TCGType type
)
1683 #ifdef CONFIG_DEBUG_TCG
1686 assert(TCG_TARGET_HAS_v64
);
1689 assert(TCG_TARGET_HAS_v128
);
1692 assert(TCG_TARGET_HAS_v256
);
1695 g_assert_not_reached();
1699 t
= tcg_temp_new_internal(type
, TEMP_EBB
);
1700 return temp_tcgv_vec(t
);
1703 /* Create a new temp of the same type as an existing temp. */
1704 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
)
1706 TCGTemp
*t
= tcgv_vec_temp(match
);
1708 tcg_debug_assert(t
->temp_allocated
!= 0);
1710 t
= tcg_temp_new_internal(t
->base_type
, TEMP_EBB
);
1711 return temp_tcgv_vec(t
);
1714 void tcg_temp_free_internal(TCGTemp
*ts
)
1716 TCGContext
*s
= tcg_ctx
;
1721 /* Silently ignore free. */
1724 tcg_debug_assert(ts
->temp_allocated
!= 0);
1725 ts
->temp_allocated
= 0;
1726 set_bit(temp_idx(ts
), s
->free_temps
[ts
->base_type
].l
);
1729 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */
1730 g_assert_not_reached();
1734 TCGTemp
*tcg_constant_internal(TCGType type
, int64_t val
)
1736 TCGContext
*s
= tcg_ctx
;
1737 GHashTable
*h
= s
->const_table
[type
];
1741 h
= g_hash_table_new(g_int64_hash
, g_int64_equal
);
1742 s
->const_table
[type
] = h
;
1745 ts
= g_hash_table_lookup(h
, &val
);
1749 ts
= tcg_temp_alloc(s
);
1751 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1752 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1754 tcg_debug_assert(ts2
== ts
+ 1);
1756 ts
->base_type
= TCG_TYPE_I64
;
1757 ts
->type
= TCG_TYPE_I32
;
1758 ts
->kind
= TEMP_CONST
;
1759 ts
->temp_allocated
= 1;
1761 ts2
->base_type
= TCG_TYPE_I64
;
1762 ts2
->type
= TCG_TYPE_I32
;
1763 ts2
->kind
= TEMP_CONST
;
1764 ts2
->temp_allocated
= 1;
1765 ts2
->temp_subindex
= 1;
1768 * Retain the full value of the 64-bit constant in the low
1769 * part, so that the hash table works. Actual uses will
1770 * truncate the value to the low part.
1772 ts
[HOST_BIG_ENDIAN
].val
= val
;
1773 ts
[!HOST_BIG_ENDIAN
].val
= val
>> 32;
1774 val_ptr
= &ts
[HOST_BIG_ENDIAN
].val
;
1776 ts
->base_type
= type
;
1778 ts
->kind
= TEMP_CONST
;
1779 ts
->temp_allocated
= 1;
1783 g_hash_table_insert(h
, val_ptr
, ts
);
1789 TCGv_vec
tcg_constant_vec(TCGType type
, unsigned vece
, int64_t val
)
1791 val
= dup_const(vece
, val
);
1792 return temp_tcgv_vec(tcg_constant_internal(type
, val
));
1795 TCGv_vec
tcg_constant_vec_matching(TCGv_vec match
, unsigned vece
, int64_t val
)
1797 TCGTemp
*t
= tcgv_vec_temp(match
);
1799 tcg_debug_assert(t
->temp_allocated
!= 0);
1800 return tcg_constant_vec(t
->base_type
, vece
, val
);
1803 #ifdef CONFIG_DEBUG_TCG
1804 size_t temp_idx(TCGTemp
*ts
)
1806 ptrdiff_t n
= ts
- tcg_ctx
->temps
;
1807 assert(n
>= 0 && n
< tcg_ctx
->nb_temps
);
1811 TCGTemp
*tcgv_i32_temp(TCGv_i32 v
)
1813 uintptr_t o
= (uintptr_t)v
- offsetof(TCGContext
, temps
);
1815 assert(o
< sizeof(TCGTemp
) * tcg_ctx
->nb_temps
);
1816 assert(o
% sizeof(TCGTemp
) == 0);
1818 return (void *)tcg_ctx
+ (uintptr_t)v
;
1820 #endif /* CONFIG_DEBUG_TCG */
1822 /* Return true if OP may appear in the opcode stream.
1823 Test the runtime variable that controls each opcode. */
1824 bool tcg_op_supported(TCGOpcode op
)
1827 = TCG_TARGET_HAS_v64
| TCG_TARGET_HAS_v128
| TCG_TARGET_HAS_v256
;
1830 case INDEX_op_discard
:
1831 case INDEX_op_set_label
:
1835 case INDEX_op_insn_start
:
1836 case INDEX_op_exit_tb
:
1837 case INDEX_op_goto_tb
:
1838 case INDEX_op_goto_ptr
:
1839 case INDEX_op_qemu_ld_a32_i32
:
1840 case INDEX_op_qemu_ld_a64_i32
:
1841 case INDEX_op_qemu_st_a32_i32
:
1842 case INDEX_op_qemu_st_a64_i32
:
1843 case INDEX_op_qemu_ld_a32_i64
:
1844 case INDEX_op_qemu_ld_a64_i64
:
1845 case INDEX_op_qemu_st_a32_i64
:
1846 case INDEX_op_qemu_st_a64_i64
:
1849 case INDEX_op_qemu_st8_a32_i32
:
1850 case INDEX_op_qemu_st8_a64_i32
:
1851 return TCG_TARGET_HAS_qemu_st8_i32
;
1853 case INDEX_op_qemu_ld_a32_i128
:
1854 case INDEX_op_qemu_ld_a64_i128
:
1855 case INDEX_op_qemu_st_a32_i128
:
1856 case INDEX_op_qemu_st_a64_i128
:
1857 return TCG_TARGET_HAS_qemu_ldst_i128
;
1859 case INDEX_op_mov_i32
:
1860 case INDEX_op_setcond_i32
:
1861 case INDEX_op_brcond_i32
:
1862 case INDEX_op_ld8u_i32
:
1863 case INDEX_op_ld8s_i32
:
1864 case INDEX_op_ld16u_i32
:
1865 case INDEX_op_ld16s_i32
:
1866 case INDEX_op_ld_i32
:
1867 case INDEX_op_st8_i32
:
1868 case INDEX_op_st16_i32
:
1869 case INDEX_op_st_i32
:
1870 case INDEX_op_add_i32
:
1871 case INDEX_op_sub_i32
:
1872 case INDEX_op_mul_i32
:
1873 case INDEX_op_and_i32
:
1874 case INDEX_op_or_i32
:
1875 case INDEX_op_xor_i32
:
1876 case INDEX_op_shl_i32
:
1877 case INDEX_op_shr_i32
:
1878 case INDEX_op_sar_i32
:
1881 case INDEX_op_movcond_i32
:
1882 return TCG_TARGET_HAS_movcond_i32
;
1883 case INDEX_op_div_i32
:
1884 case INDEX_op_divu_i32
:
1885 return TCG_TARGET_HAS_div_i32
;
1886 case INDEX_op_rem_i32
:
1887 case INDEX_op_remu_i32
:
1888 return TCG_TARGET_HAS_rem_i32
;
1889 case INDEX_op_div2_i32
:
1890 case INDEX_op_divu2_i32
:
1891 return TCG_TARGET_HAS_div2_i32
;
1892 case INDEX_op_rotl_i32
:
1893 case INDEX_op_rotr_i32
:
1894 return TCG_TARGET_HAS_rot_i32
;
1895 case INDEX_op_deposit_i32
:
1896 return TCG_TARGET_HAS_deposit_i32
;
1897 case INDEX_op_extract_i32
:
1898 return TCG_TARGET_HAS_extract_i32
;
1899 case INDEX_op_sextract_i32
:
1900 return TCG_TARGET_HAS_sextract_i32
;
1901 case INDEX_op_extract2_i32
:
1902 return TCG_TARGET_HAS_extract2_i32
;
1903 case INDEX_op_add2_i32
:
1904 return TCG_TARGET_HAS_add2_i32
;
1905 case INDEX_op_sub2_i32
:
1906 return TCG_TARGET_HAS_sub2_i32
;
1907 case INDEX_op_mulu2_i32
:
1908 return TCG_TARGET_HAS_mulu2_i32
;
1909 case INDEX_op_muls2_i32
:
1910 return TCG_TARGET_HAS_muls2_i32
;
1911 case INDEX_op_muluh_i32
:
1912 return TCG_TARGET_HAS_muluh_i32
;
1913 case INDEX_op_mulsh_i32
:
1914 return TCG_TARGET_HAS_mulsh_i32
;
1915 case INDEX_op_ext8s_i32
:
1916 return TCG_TARGET_HAS_ext8s_i32
;
1917 case INDEX_op_ext16s_i32
:
1918 return TCG_TARGET_HAS_ext16s_i32
;
1919 case INDEX_op_ext8u_i32
:
1920 return TCG_TARGET_HAS_ext8u_i32
;
1921 case INDEX_op_ext16u_i32
:
1922 return TCG_TARGET_HAS_ext16u_i32
;
1923 case INDEX_op_bswap16_i32
:
1924 return TCG_TARGET_HAS_bswap16_i32
;
1925 case INDEX_op_bswap32_i32
:
1926 return TCG_TARGET_HAS_bswap32_i32
;
1927 case INDEX_op_not_i32
:
1928 return TCG_TARGET_HAS_not_i32
;
1929 case INDEX_op_neg_i32
:
1930 return TCG_TARGET_HAS_neg_i32
;
1931 case INDEX_op_andc_i32
:
1932 return TCG_TARGET_HAS_andc_i32
;
1933 case INDEX_op_orc_i32
:
1934 return TCG_TARGET_HAS_orc_i32
;
1935 case INDEX_op_eqv_i32
:
1936 return TCG_TARGET_HAS_eqv_i32
;
1937 case INDEX_op_nand_i32
:
1938 return TCG_TARGET_HAS_nand_i32
;
1939 case INDEX_op_nor_i32
:
1940 return TCG_TARGET_HAS_nor_i32
;
1941 case INDEX_op_clz_i32
:
1942 return TCG_TARGET_HAS_clz_i32
;
1943 case INDEX_op_ctz_i32
:
1944 return TCG_TARGET_HAS_ctz_i32
;
1945 case INDEX_op_ctpop_i32
:
1946 return TCG_TARGET_HAS_ctpop_i32
;
1948 case INDEX_op_brcond2_i32
:
1949 case INDEX_op_setcond2_i32
:
1950 return TCG_TARGET_REG_BITS
== 32;
1952 case INDEX_op_mov_i64
:
1953 case INDEX_op_setcond_i64
:
1954 case INDEX_op_brcond_i64
:
1955 case INDEX_op_ld8u_i64
:
1956 case INDEX_op_ld8s_i64
:
1957 case INDEX_op_ld16u_i64
:
1958 case INDEX_op_ld16s_i64
:
1959 case INDEX_op_ld32u_i64
:
1960 case INDEX_op_ld32s_i64
:
1961 case INDEX_op_ld_i64
:
1962 case INDEX_op_st8_i64
:
1963 case INDEX_op_st16_i64
:
1964 case INDEX_op_st32_i64
:
1965 case INDEX_op_st_i64
:
1966 case INDEX_op_add_i64
:
1967 case INDEX_op_sub_i64
:
1968 case INDEX_op_mul_i64
:
1969 case INDEX_op_and_i64
:
1970 case INDEX_op_or_i64
:
1971 case INDEX_op_xor_i64
:
1972 case INDEX_op_shl_i64
:
1973 case INDEX_op_shr_i64
:
1974 case INDEX_op_sar_i64
:
1975 case INDEX_op_ext_i32_i64
:
1976 case INDEX_op_extu_i32_i64
:
1977 return TCG_TARGET_REG_BITS
== 64;
1979 case INDEX_op_movcond_i64
:
1980 return TCG_TARGET_HAS_movcond_i64
;
1981 case INDEX_op_div_i64
:
1982 case INDEX_op_divu_i64
:
1983 return TCG_TARGET_HAS_div_i64
;
1984 case INDEX_op_rem_i64
:
1985 case INDEX_op_remu_i64
:
1986 return TCG_TARGET_HAS_rem_i64
;
1987 case INDEX_op_div2_i64
:
1988 case INDEX_op_divu2_i64
:
1989 return TCG_TARGET_HAS_div2_i64
;
1990 case INDEX_op_rotl_i64
:
1991 case INDEX_op_rotr_i64
:
1992 return TCG_TARGET_HAS_rot_i64
;
1993 case INDEX_op_deposit_i64
:
1994 return TCG_TARGET_HAS_deposit_i64
;
1995 case INDEX_op_extract_i64
:
1996 return TCG_TARGET_HAS_extract_i64
;
1997 case INDEX_op_sextract_i64
:
1998 return TCG_TARGET_HAS_sextract_i64
;
1999 case INDEX_op_extract2_i64
:
2000 return TCG_TARGET_HAS_extract2_i64
;
2001 case INDEX_op_extrl_i64_i32
:
2002 return TCG_TARGET_HAS_extrl_i64_i32
;
2003 case INDEX_op_extrh_i64_i32
:
2004 return TCG_TARGET_HAS_extrh_i64_i32
;
2005 case INDEX_op_ext8s_i64
:
2006 return TCG_TARGET_HAS_ext8s_i64
;
2007 case INDEX_op_ext16s_i64
:
2008 return TCG_TARGET_HAS_ext16s_i64
;
2009 case INDEX_op_ext32s_i64
:
2010 return TCG_TARGET_HAS_ext32s_i64
;
2011 case INDEX_op_ext8u_i64
:
2012 return TCG_TARGET_HAS_ext8u_i64
;
2013 case INDEX_op_ext16u_i64
:
2014 return TCG_TARGET_HAS_ext16u_i64
;
2015 case INDEX_op_ext32u_i64
:
2016 return TCG_TARGET_HAS_ext32u_i64
;
2017 case INDEX_op_bswap16_i64
:
2018 return TCG_TARGET_HAS_bswap16_i64
;
2019 case INDEX_op_bswap32_i64
:
2020 return TCG_TARGET_HAS_bswap32_i64
;
2021 case INDEX_op_bswap64_i64
:
2022 return TCG_TARGET_HAS_bswap64_i64
;
2023 case INDEX_op_not_i64
:
2024 return TCG_TARGET_HAS_not_i64
;
2025 case INDEX_op_neg_i64
:
2026 return TCG_TARGET_HAS_neg_i64
;
2027 case INDEX_op_andc_i64
:
2028 return TCG_TARGET_HAS_andc_i64
;
2029 case INDEX_op_orc_i64
:
2030 return TCG_TARGET_HAS_orc_i64
;
2031 case INDEX_op_eqv_i64
:
2032 return TCG_TARGET_HAS_eqv_i64
;
2033 case INDEX_op_nand_i64
:
2034 return TCG_TARGET_HAS_nand_i64
;
2035 case INDEX_op_nor_i64
:
2036 return TCG_TARGET_HAS_nor_i64
;
2037 case INDEX_op_clz_i64
:
2038 return TCG_TARGET_HAS_clz_i64
;
2039 case INDEX_op_ctz_i64
:
2040 return TCG_TARGET_HAS_ctz_i64
;
2041 case INDEX_op_ctpop_i64
:
2042 return TCG_TARGET_HAS_ctpop_i64
;
2043 case INDEX_op_add2_i64
:
2044 return TCG_TARGET_HAS_add2_i64
;
2045 case INDEX_op_sub2_i64
:
2046 return TCG_TARGET_HAS_sub2_i64
;
2047 case INDEX_op_mulu2_i64
:
2048 return TCG_TARGET_HAS_mulu2_i64
;
2049 case INDEX_op_muls2_i64
:
2050 return TCG_TARGET_HAS_muls2_i64
;
2051 case INDEX_op_muluh_i64
:
2052 return TCG_TARGET_HAS_muluh_i64
;
2053 case INDEX_op_mulsh_i64
:
2054 return TCG_TARGET_HAS_mulsh_i64
;
2056 case INDEX_op_mov_vec
:
2057 case INDEX_op_dup_vec
:
2058 case INDEX_op_dupm_vec
:
2059 case INDEX_op_ld_vec
:
2060 case INDEX_op_st_vec
:
2061 case INDEX_op_add_vec
:
2062 case INDEX_op_sub_vec
:
2063 case INDEX_op_and_vec
:
2064 case INDEX_op_or_vec
:
2065 case INDEX_op_xor_vec
:
2066 case INDEX_op_cmp_vec
:
2068 case INDEX_op_dup2_vec
:
2069 return have_vec
&& TCG_TARGET_REG_BITS
== 32;
2070 case INDEX_op_not_vec
:
2071 return have_vec
&& TCG_TARGET_HAS_not_vec
;
2072 case INDEX_op_neg_vec
:
2073 return have_vec
&& TCG_TARGET_HAS_neg_vec
;
2074 case INDEX_op_abs_vec
:
2075 return have_vec
&& TCG_TARGET_HAS_abs_vec
;
2076 case INDEX_op_andc_vec
:
2077 return have_vec
&& TCG_TARGET_HAS_andc_vec
;
2078 case INDEX_op_orc_vec
:
2079 return have_vec
&& TCG_TARGET_HAS_orc_vec
;
2080 case INDEX_op_nand_vec
:
2081 return have_vec
&& TCG_TARGET_HAS_nand_vec
;
2082 case INDEX_op_nor_vec
:
2083 return have_vec
&& TCG_TARGET_HAS_nor_vec
;
2084 case INDEX_op_eqv_vec
:
2085 return have_vec
&& TCG_TARGET_HAS_eqv_vec
;
2086 case INDEX_op_mul_vec
:
2087 return have_vec
&& TCG_TARGET_HAS_mul_vec
;
2088 case INDEX_op_shli_vec
:
2089 case INDEX_op_shri_vec
:
2090 case INDEX_op_sari_vec
:
2091 return have_vec
&& TCG_TARGET_HAS_shi_vec
;
2092 case INDEX_op_shls_vec
:
2093 case INDEX_op_shrs_vec
:
2094 case INDEX_op_sars_vec
:
2095 return have_vec
&& TCG_TARGET_HAS_shs_vec
;
2096 case INDEX_op_shlv_vec
:
2097 case INDEX_op_shrv_vec
:
2098 case INDEX_op_sarv_vec
:
2099 return have_vec
&& TCG_TARGET_HAS_shv_vec
;
2100 case INDEX_op_rotli_vec
:
2101 return have_vec
&& TCG_TARGET_HAS_roti_vec
;
2102 case INDEX_op_rotls_vec
:
2103 return have_vec
&& TCG_TARGET_HAS_rots_vec
;
2104 case INDEX_op_rotlv_vec
:
2105 case INDEX_op_rotrv_vec
:
2106 return have_vec
&& TCG_TARGET_HAS_rotv_vec
;
2107 case INDEX_op_ssadd_vec
:
2108 case INDEX_op_usadd_vec
:
2109 case INDEX_op_sssub_vec
:
2110 case INDEX_op_ussub_vec
:
2111 return have_vec
&& TCG_TARGET_HAS_sat_vec
;
2112 case INDEX_op_smin_vec
:
2113 case INDEX_op_umin_vec
:
2114 case INDEX_op_smax_vec
:
2115 case INDEX_op_umax_vec
:
2116 return have_vec
&& TCG_TARGET_HAS_minmax_vec
;
2117 case INDEX_op_bitsel_vec
:
2118 return have_vec
&& TCG_TARGET_HAS_bitsel_vec
;
2119 case INDEX_op_cmpsel_vec
:
2120 return have_vec
&& TCG_TARGET_HAS_cmpsel_vec
;
2123 tcg_debug_assert(op
> INDEX_op_last_generic
&& op
< NB_OPS
);
2128 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
);
2130 void tcg_gen_callN(TCGHelperInfo
*info
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
)
2132 TCGv_i64 extend_free
[MAX_CALL_IARGS
];
2135 int i
, n
, pi
= 0, total_args
;
2137 if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info
)))) {
2138 init_call_layout(info
);
2139 g_once_init_leave(HELPER_INFO_INIT(info
), HELPER_INFO_INIT_VAL(info
));
2142 total_args
= info
->nr_out
+ info
->nr_in
+ 2;
2143 op
= tcg_op_alloc(INDEX_op_call
, total_args
);
2145 #ifdef CONFIG_PLUGIN
2146 /* Flag helpers that may affect guest state */
2147 if (tcg_ctx
->plugin_insn
&&
2148 !(info
->flags
& TCG_CALL_PLUGIN
) &&
2149 !(info
->flags
& TCG_CALL_NO_SIDE_EFFECTS
)) {
2150 tcg_ctx
->plugin_insn
->calls_helpers
= true;
2154 TCGOP_CALLO(op
) = n
= info
->nr_out
;
2157 tcg_debug_assert(ret
== NULL
);
2160 tcg_debug_assert(ret
!= NULL
);
2161 op
->args
[pi
++] = temp_arg(ret
);
2165 tcg_debug_assert(ret
!= NULL
);
2166 tcg_debug_assert(ret
->base_type
== ret
->type
+ ctz32(n
));
2167 tcg_debug_assert(ret
->temp_subindex
== 0);
2168 for (i
= 0; i
< n
; ++i
) {
2169 op
->args
[pi
++] = temp_arg(ret
+ i
);
2173 g_assert_not_reached();
2176 TCGOP_CALLI(op
) = n
= info
->nr_in
;
2177 for (i
= 0; i
< n
; i
++) {
2178 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
2179 TCGTemp
*ts
= args
[loc
->arg_idx
] + loc
->tmp_subindex
;
2181 switch (loc
->kind
) {
2182 case TCG_CALL_ARG_NORMAL
:
2183 case TCG_CALL_ARG_BY_REF
:
2184 case TCG_CALL_ARG_BY_REF_N
:
2185 op
->args
[pi
++] = temp_arg(ts
);
2188 case TCG_CALL_ARG_EXTEND_U
:
2189 case TCG_CALL_ARG_EXTEND_S
:
2191 TCGv_i64 temp
= tcg_temp_ebb_new_i64();
2192 TCGv_i32 orig
= temp_tcgv_i32(ts
);
2194 if (loc
->kind
== TCG_CALL_ARG_EXTEND_S
) {
2195 tcg_gen_ext_i32_i64(temp
, orig
);
2197 tcg_gen_extu_i32_i64(temp
, orig
);
2199 op
->args
[pi
++] = tcgv_i64_arg(temp
);
2200 extend_free
[n_extend
++] = temp
;
2205 g_assert_not_reached();
2208 op
->args
[pi
++] = (uintptr_t)info
->func
;
2209 op
->args
[pi
++] = (uintptr_t)info
;
2210 tcg_debug_assert(pi
== total_args
);
2212 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2214 tcg_debug_assert(n_extend
< ARRAY_SIZE(extend_free
));
2215 for (i
= 0; i
< n_extend
; ++i
) {
2216 tcg_temp_free_i64(extend_free
[i
]);
2220 static void tcg_reg_alloc_start(TCGContext
*s
)
2224 for (i
= 0, n
= s
->nb_temps
; i
< n
; i
++) {
2225 TCGTemp
*ts
= &s
->temps
[i
];
2226 TCGTempVal val
= TEMP_VAL_MEM
;
2230 val
= TEMP_VAL_CONST
;
2238 val
= TEMP_VAL_DEAD
;
2241 ts
->mem_allocated
= 0;
2244 g_assert_not_reached();
2249 memset(s
->reg_to_temp
, 0, sizeof(s
->reg_to_temp
));
2252 static char *tcg_get_arg_str_ptr(TCGContext
*s
, char *buf
, int buf_size
,
2255 int idx
= temp_idx(ts
);
2260 pstrcpy(buf
, buf_size
, ts
->name
);
2263 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
2266 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
2271 snprintf(buf
, buf_size
, "$0x%x", (int32_t)ts
->val
);
2273 #if TCG_TARGET_REG_BITS > 32
2275 snprintf(buf
, buf_size
, "$0x%" PRIx64
, ts
->val
);
2281 snprintf(buf
, buf_size
, "v%d$0x%" PRIx64
,
2282 64 << (ts
->type
- TCG_TYPE_V64
), ts
->val
);
2285 g_assert_not_reached();
2292 static char *tcg_get_arg_str(TCGContext
*s
, char *buf
,
2293 int buf_size
, TCGArg arg
)
2295 return tcg_get_arg_str_ptr(s
, buf
, buf_size
, arg_temp(arg
));
2298 static const char * const cond_name
[] =
2300 [TCG_COND_NEVER
] = "never",
2301 [TCG_COND_ALWAYS
] = "always",
2302 [TCG_COND_EQ
] = "eq",
2303 [TCG_COND_NE
] = "ne",
2304 [TCG_COND_LT
] = "lt",
2305 [TCG_COND_GE
] = "ge",
2306 [TCG_COND_LE
] = "le",
2307 [TCG_COND_GT
] = "gt",
2308 [TCG_COND_LTU
] = "ltu",
2309 [TCG_COND_GEU
] = "geu",
2310 [TCG_COND_LEU
] = "leu",
2311 [TCG_COND_GTU
] = "gtu"
2314 static const char * const ldst_name
[(MO_BSWAP
| MO_SSIZE
) + 1] =
2328 [MO_128
+ MO_BE
] = "beo",
2329 [MO_128
+ MO_LE
] = "leo",
2332 static const char * const alignment_name
[(MO_AMASK
>> MO_ASHIFT
) + 1] = {
2333 [MO_UNALN
>> MO_ASHIFT
] = "un+",
2334 [MO_ALIGN
>> MO_ASHIFT
] = "al+",
2335 [MO_ALIGN_2
>> MO_ASHIFT
] = "al2+",
2336 [MO_ALIGN_4
>> MO_ASHIFT
] = "al4+",
2337 [MO_ALIGN_8
>> MO_ASHIFT
] = "al8+",
2338 [MO_ALIGN_16
>> MO_ASHIFT
] = "al16+",
2339 [MO_ALIGN_32
>> MO_ASHIFT
] = "al32+",
2340 [MO_ALIGN_64
>> MO_ASHIFT
] = "al64+",
2343 static const char * const atom_name
[(MO_ATOM_MASK
>> MO_ATOM_SHIFT
) + 1] = {
2344 [MO_ATOM_IFALIGN
>> MO_ATOM_SHIFT
] = "",
2345 [MO_ATOM_IFALIGN_PAIR
>> MO_ATOM_SHIFT
] = "pair+",
2346 [MO_ATOM_WITHIN16
>> MO_ATOM_SHIFT
] = "w16+",
2347 [MO_ATOM_WITHIN16_PAIR
>> MO_ATOM_SHIFT
] = "w16p+",
2348 [MO_ATOM_SUBALIGN
>> MO_ATOM_SHIFT
] = "sub+",
2349 [MO_ATOM_NONE
>> MO_ATOM_SHIFT
] = "noat+",
2352 static const char bswap_flag_name
[][6] = {
2353 [TCG_BSWAP_IZ
] = "iz",
2354 [TCG_BSWAP_OZ
] = "oz",
2355 [TCG_BSWAP_OS
] = "os",
2356 [TCG_BSWAP_IZ
| TCG_BSWAP_OZ
] = "iz,oz",
2357 [TCG_BSWAP_IZ
| TCG_BSWAP_OS
] = "iz,os",
2360 static inline bool tcg_regset_single(TCGRegSet d
)
2362 return (d
& (d
- 1)) == 0;
2365 static inline TCGReg
tcg_regset_first(TCGRegSet d
)
2367 if (TCG_TARGET_NB_REGS
<= 32) {
2374 /* Return only the number of characters output -- no error return. */
2375 #define ne_fprintf(...) \
2376 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; })
2378 static void tcg_dump_ops(TCGContext
*s
, FILE *f
, bool have_prefs
)
2383 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
2384 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
2385 const TCGOpDef
*def
;
2390 def
= &tcg_op_defs
[c
];
2392 if (c
== INDEX_op_insn_start
) {
2394 col
+= ne_fprintf(f
, "\n ----");
2396 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
2397 col
+= ne_fprintf(f
, " %016" PRIx64
,
2398 tcg_get_insn_start_param(op
, i
));
2400 } else if (c
== INDEX_op_call
) {
2401 const TCGHelperInfo
*info
= tcg_call_info(op
);
2402 void *func
= tcg_call_func(op
);
2404 /* variable number of arguments */
2405 nb_oargs
= TCGOP_CALLO(op
);
2406 nb_iargs
= TCGOP_CALLI(op
);
2407 nb_cargs
= def
->nb_cargs
;
2409 col
+= ne_fprintf(f
, " %s ", def
->name
);
2412 * Print the function name from TCGHelperInfo, if available.
2413 * Note that plugins have a template function for the info,
2414 * but the actual function pointer comes from the plugin.
2416 if (func
== info
->func
) {
2417 col
+= ne_fprintf(f
, "%s", info
->name
);
2419 col
+= ne_fprintf(f
, "plugin(%p)", func
);
2422 col
+= ne_fprintf(f
, ",$0x%x,$%d", info
->flags
, nb_oargs
);
2423 for (i
= 0; i
< nb_oargs
; i
++) {
2424 col
+= ne_fprintf(f
, ",%s", tcg_get_arg_str(s
, buf
, sizeof(buf
),
2427 for (i
= 0; i
< nb_iargs
; i
++) {
2428 TCGArg arg
= op
->args
[nb_oargs
+ i
];
2429 const char *t
= tcg_get_arg_str(s
, buf
, sizeof(buf
), arg
);
2430 col
+= ne_fprintf(f
, ",%s", t
);
2433 col
+= ne_fprintf(f
, " %s ", def
->name
);
2435 nb_oargs
= def
->nb_oargs
;
2436 nb_iargs
= def
->nb_iargs
;
2437 nb_cargs
= def
->nb_cargs
;
2439 if (def
->flags
& TCG_OPF_VECTOR
) {
2440 col
+= ne_fprintf(f
, "v%d,e%d,", 64 << TCGOP_VECL(op
),
2441 8 << TCGOP_VECE(op
));
2445 for (i
= 0; i
< nb_oargs
; i
++) {
2446 const char *sep
= k
? "," : "";
2447 col
+= ne_fprintf(f
, "%s%s", sep
,
2448 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2451 for (i
= 0; i
< nb_iargs
; i
++) {
2452 const char *sep
= k
? "," : "";
2453 col
+= ne_fprintf(f
, "%s%s", sep
,
2454 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2458 case INDEX_op_brcond_i32
:
2459 case INDEX_op_setcond_i32
:
2460 case INDEX_op_movcond_i32
:
2461 case INDEX_op_brcond2_i32
:
2462 case INDEX_op_setcond2_i32
:
2463 case INDEX_op_brcond_i64
:
2464 case INDEX_op_setcond_i64
:
2465 case INDEX_op_movcond_i64
:
2466 case INDEX_op_cmp_vec
:
2467 case INDEX_op_cmpsel_vec
:
2468 if (op
->args
[k
] < ARRAY_SIZE(cond_name
)
2469 && cond_name
[op
->args
[k
]]) {
2470 col
+= ne_fprintf(f
, ",%s", cond_name
[op
->args
[k
++]]);
2472 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, op
->args
[k
++]);
2476 case INDEX_op_qemu_ld_a32_i32
:
2477 case INDEX_op_qemu_ld_a64_i32
:
2478 case INDEX_op_qemu_st_a32_i32
:
2479 case INDEX_op_qemu_st_a64_i32
:
2480 case INDEX_op_qemu_st8_a32_i32
:
2481 case INDEX_op_qemu_st8_a64_i32
:
2482 case INDEX_op_qemu_ld_a32_i64
:
2483 case INDEX_op_qemu_ld_a64_i64
:
2484 case INDEX_op_qemu_st_a32_i64
:
2485 case INDEX_op_qemu_st_a64_i64
:
2486 case INDEX_op_qemu_ld_a32_i128
:
2487 case INDEX_op_qemu_ld_a64_i128
:
2488 case INDEX_op_qemu_st_a32_i128
:
2489 case INDEX_op_qemu_st_a64_i128
:
2491 const char *s_al
, *s_op
, *s_at
;
2492 MemOpIdx oi
= op
->args
[k
++];
2493 MemOp op
= get_memop(oi
);
2494 unsigned ix
= get_mmuidx(oi
);
2496 s_al
= alignment_name
[(op
& MO_AMASK
) >> MO_ASHIFT
];
2497 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
2498 s_at
= atom_name
[(op
& MO_ATOM_MASK
) >> MO_ATOM_SHIFT
];
2499 op
&= ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
| MO_ATOM_MASK
);
2501 /* If all fields are accounted for, print symbolically. */
2502 if (!op
&& s_al
&& s_op
&& s_at
) {
2503 col
+= ne_fprintf(f
, ",%s%s%s,%u",
2504 s_at
, s_al
, s_op
, ix
);
2507 col
+= ne_fprintf(f
, ",$0x%x,%u", op
, ix
);
2512 case INDEX_op_bswap16_i32
:
2513 case INDEX_op_bswap16_i64
:
2514 case INDEX_op_bswap32_i32
:
2515 case INDEX_op_bswap32_i64
:
2516 case INDEX_op_bswap64_i64
:
2518 TCGArg flags
= op
->args
[k
];
2519 const char *name
= NULL
;
2521 if (flags
< ARRAY_SIZE(bswap_flag_name
)) {
2522 name
= bswap_flag_name
[flags
];
2525 col
+= ne_fprintf(f
, ",%s", name
);
2527 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, flags
);
2537 case INDEX_op_set_label
:
2539 case INDEX_op_brcond_i32
:
2540 case INDEX_op_brcond_i64
:
2541 case INDEX_op_brcond2_i32
:
2542 col
+= ne_fprintf(f
, "%s$L%d", k
? "," : "",
2543 arg_label(op
->args
[k
])->id
);
2548 TCGBar membar
= op
->args
[k
];
2549 const char *b_op
, *m_op
;
2551 switch (membar
& TCG_BAR_SC
) {
2565 g_assert_not_reached();
2568 switch (membar
& TCG_MO_ALL
) {
2584 case TCG_MO_LD_LD
| TCG_MO_LD_ST
:
2587 case TCG_MO_LD_LD
| TCG_MO_ST_LD
:
2590 case TCG_MO_LD_LD
| TCG_MO_ST_ST
:
2593 case TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2596 case TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2599 case TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2602 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2605 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2608 case TCG_MO_LD_LD
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2611 case TCG_MO_LD_ST
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2618 g_assert_not_reached();
2621 col
+= ne_fprintf(f
, "%s%s:%s", (k
? "," : ""), b_op
, m_op
);
2628 for (; i
< nb_cargs
; i
++, k
++) {
2629 col
+= ne_fprintf(f
, "%s$0x%" TCG_PRIlx
, k
? "," : "",
2634 if (have_prefs
|| op
->life
) {
2635 for (; col
< 40; ++col
) {
2641 unsigned life
= op
->life
;
2643 if (life
& (SYNC_ARG
* 3)) {
2644 ne_fprintf(f
, " sync:");
2645 for (i
= 0; i
< 2; ++i
) {
2646 if (life
& (SYNC_ARG
<< i
)) {
2647 ne_fprintf(f
, " %d", i
);
2653 ne_fprintf(f
, " dead:");
2654 for (i
= 0; life
; ++i
, life
>>= 1) {
2656 ne_fprintf(f
, " %d", i
);
2663 for (i
= 0; i
< nb_oargs
; ++i
) {
2664 TCGRegSet set
= output_pref(op
, i
);
2667 ne_fprintf(f
, " pref=");
2672 ne_fprintf(f
, "none");
2673 } else if (set
== MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS
)) {
2674 ne_fprintf(f
, "all");
2675 #ifdef CONFIG_DEBUG_TCG
2676 } else if (tcg_regset_single(set
)) {
2677 TCGReg reg
= tcg_regset_first(set
);
2678 ne_fprintf(f
, "%s", tcg_target_reg_names
[reg
]);
2680 } else if (TCG_TARGET_NB_REGS
<= 32) {
2681 ne_fprintf(f
, "0x%x", (uint32_t)set
);
2683 ne_fprintf(f
, "0x%" PRIx64
, (uint64_t)set
);
2692 /* we give more priority to constraints with less registers */
2693 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
2695 const TCGArgConstraint
*arg_ct
= &def
->args_ct
[k
];
2696 int n
= ctpop64(arg_ct
->regs
);
2699 * Sort constraints of a single register first, which includes output
2700 * aliases (which must exactly match the input already allocated).
2702 if (n
== 1 || arg_ct
->oalias
) {
2707 * Sort register pairs next, first then second immediately after.
2708 * Arbitrarily sort multiple pairs by the index of the first reg;
2709 * there shouldn't be many pairs.
2711 switch (arg_ct
->pair
) {
2716 return (arg_ct
->pair_index
+ 1) * 2 - 1;
2719 /* Finally, sort by decreasing register count. */
2724 /* sort from highest priority to lowest */
2725 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
2728 TCGArgConstraint
*a
= def
->args_ct
;
2730 for (i
= 0; i
< n
; i
++) {
2731 a
[start
+ i
].sort_index
= start
+ i
;
2736 for (i
= 0; i
< n
- 1; i
++) {
2737 for (j
= i
+ 1; j
< n
; j
++) {
2738 int p1
= get_constraint_priority(def
, a
[start
+ i
].sort_index
);
2739 int p2
= get_constraint_priority(def
, a
[start
+ j
].sort_index
);
2741 int tmp
= a
[start
+ i
].sort_index
;
2742 a
[start
+ i
].sort_index
= a
[start
+ j
].sort_index
;
2743 a
[start
+ j
].sort_index
= tmp
;
2749 static void process_op_defs(TCGContext
*s
)
2753 for (op
= 0; op
< NB_OPS
; op
++) {
2754 TCGOpDef
*def
= &tcg_op_defs
[op
];
2755 const TCGTargetOpDef
*tdefs
;
2756 bool saw_alias_pair
= false;
2757 int i
, o
, i2
, o2
, nb_args
;
2759 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2763 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
2769 * Macro magic should make it impossible, but double-check that
2770 * the array index is in range. Since the signness of an enum
2771 * is implementation defined, force the result to unsigned.
2773 unsigned con_set
= tcg_target_op_def(op
);
2774 tcg_debug_assert(con_set
< ARRAY_SIZE(constraint_sets
));
2775 tdefs
= &constraint_sets
[con_set
];
2777 for (i
= 0; i
< nb_args
; i
++) {
2778 const char *ct_str
= tdefs
->args_ct_str
[i
];
2779 bool input_p
= i
>= def
->nb_oargs
;
2781 /* Incomplete TCGTargetOpDef entry. */
2782 tcg_debug_assert(ct_str
!= NULL
);
2787 tcg_debug_assert(input_p
);
2788 tcg_debug_assert(o
< def
->nb_oargs
);
2789 tcg_debug_assert(def
->args_ct
[o
].regs
!= 0);
2790 tcg_debug_assert(!def
->args_ct
[o
].oalias
);
2791 def
->args_ct
[i
] = def
->args_ct
[o
];
2792 /* The output sets oalias. */
2793 def
->args_ct
[o
].oalias
= 1;
2794 def
->args_ct
[o
].alias_index
= i
;
2795 /* The input sets ialias. */
2796 def
->args_ct
[i
].ialias
= 1;
2797 def
->args_ct
[i
].alias_index
= o
;
2798 if (def
->args_ct
[i
].pair
) {
2799 saw_alias_pair
= true;
2801 tcg_debug_assert(ct_str
[1] == '\0');
2805 tcg_debug_assert(!input_p
);
2806 def
->args_ct
[i
].newreg
= true;
2810 case 'p': /* plus */
2811 /* Allocate to the register after the previous. */
2812 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2814 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2815 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2816 def
->args_ct
[i
] = (TCGArgConstraint
){
2819 .regs
= def
->args_ct
[o
].regs
<< 1,
2821 def
->args_ct
[o
].pair
= 1;
2822 def
->args_ct
[o
].pair_index
= i
;
2823 tcg_debug_assert(ct_str
[1] == '\0');
2826 case 'm': /* minus */
2827 /* Allocate to the register before the previous. */
2828 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2830 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2831 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2832 def
->args_ct
[i
] = (TCGArgConstraint
){
2835 .regs
= def
->args_ct
[o
].regs
>> 1,
2837 def
->args_ct
[o
].pair
= 2;
2838 def
->args_ct
[o
].pair_index
= i
;
2839 tcg_debug_assert(ct_str
[1] == '\0');
2846 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
2849 /* Include all of the target-specific constraints. */
2852 #define CONST(CASE, MASK) \
2853 case CASE: def->args_ct[i].ct |= MASK; break;
2854 #define REGS(CASE, MASK) \
2855 case CASE: def->args_ct[i].regs |= MASK; break;
2857 #include "tcg-target-con-str.h"
2866 /* Typo in TCGTargetOpDef constraint. */
2867 g_assert_not_reached();
2869 } while (*++ct_str
!= '\0');
2872 /* TCGTargetOpDef entry with too much information? */
2873 tcg_debug_assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
2876 * Fix up output pairs that are aliased with inputs.
2877 * When we created the alias, we copied pair from the output.
2878 * There are three cases:
2879 * (1a) Pairs of inputs alias pairs of outputs.
2880 * (1b) One input aliases the first of a pair of outputs.
2881 * (2) One input aliases the second of a pair of outputs.
2883 * Case 1a is handled by making sure that the pair_index'es are
2884 * properly updated so that they appear the same as a pair of inputs.
2886 * Case 1b is handled by setting the pair_index of the input to
2887 * itself, simply so it doesn't point to an unrelated argument.
2888 * Since we don't encounter the "second" during the input allocation
2889 * phase, nothing happens with the second half of the input pair.
2891 * Case 2 is handled by setting the second input to pair=3, the
2892 * first output to pair=3, and the pair_index'es to match.
2894 if (saw_alias_pair
) {
2895 for (i
= def
->nb_oargs
; i
< nb_args
; i
++) {
2897 * Since [0-9pm] must be alone in the constraint string,
2898 * the only way they can both be set is if the pair comes
2899 * from the output alias.
2901 if (!def
->args_ct
[i
].ialias
) {
2904 switch (def
->args_ct
[i
].pair
) {
2908 o
= def
->args_ct
[i
].alias_index
;
2909 o2
= def
->args_ct
[o
].pair_index
;
2910 tcg_debug_assert(def
->args_ct
[o
].pair
== 1);
2911 tcg_debug_assert(def
->args_ct
[o2
].pair
== 2);
2912 if (def
->args_ct
[o2
].oalias
) {
2914 i2
= def
->args_ct
[o2
].alias_index
;
2915 tcg_debug_assert(def
->args_ct
[i2
].pair
== 2);
2916 def
->args_ct
[i2
].pair_index
= i
;
2917 def
->args_ct
[i
].pair_index
= i2
;
2920 def
->args_ct
[i
].pair_index
= i
;
2924 o
= def
->args_ct
[i
].alias_index
;
2925 o2
= def
->args_ct
[o
].pair_index
;
2926 tcg_debug_assert(def
->args_ct
[o
].pair
== 2);
2927 tcg_debug_assert(def
->args_ct
[o2
].pair
== 1);
2928 if (def
->args_ct
[o2
].oalias
) {
2930 i2
= def
->args_ct
[o2
].alias_index
;
2931 tcg_debug_assert(def
->args_ct
[i2
].pair
== 1);
2932 def
->args_ct
[i2
].pair_index
= i
;
2933 def
->args_ct
[i
].pair_index
= i2
;
2936 def
->args_ct
[i
].pair
= 3;
2937 def
->args_ct
[o2
].pair
= 3;
2938 def
->args_ct
[i
].pair_index
= o2
;
2939 def
->args_ct
[o2
].pair_index
= i
;
2943 g_assert_not_reached();
2948 /* sort the constraints (XXX: this is just an heuristic) */
2949 sort_constraints(def
, 0, def
->nb_oargs
);
2950 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
2954 static void remove_label_use(TCGOp
*op
, int idx
)
2956 TCGLabel
*label
= arg_label(op
->args
[idx
]);
2959 QSIMPLEQ_FOREACH(use
, &label
->branches
, next
) {
2960 if (use
->op
== op
) {
2961 QSIMPLEQ_REMOVE(&label
->branches
, use
, TCGLabelUse
, next
);
2965 g_assert_not_reached();
2968 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
2972 remove_label_use(op
, 0);
2974 case INDEX_op_brcond_i32
:
2975 case INDEX_op_brcond_i64
:
2976 remove_label_use(op
, 3);
2978 case INDEX_op_brcond2_i32
:
2979 remove_label_use(op
, 5);
2985 QTAILQ_REMOVE(&s
->ops
, op
, link
);
2986 QTAILQ_INSERT_TAIL(&s
->free_ops
, op
, link
);
2989 #ifdef CONFIG_PROFILER
2990 qatomic_set(&s
->prof
.del_op_count
, s
->prof
.del_op_count
+ 1);
2994 void tcg_remove_ops_after(TCGOp
*op
)
2996 TCGContext
*s
= tcg_ctx
;
2999 TCGOp
*last
= tcg_last_op();
3003 tcg_op_remove(s
, last
);
3007 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
)
3009 TCGContext
*s
= tcg_ctx
;
3012 if (unlikely(!QTAILQ_EMPTY(&s
->free_ops
))) {
3013 QTAILQ_FOREACH(op
, &s
->free_ops
, link
) {
3014 if (nargs
<= op
->nargs
) {
3015 QTAILQ_REMOVE(&s
->free_ops
, op
, link
);
3022 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */
3023 nargs
= MAX(4, nargs
);
3024 op
= tcg_malloc(sizeof(TCGOp
) + sizeof(TCGArg
) * nargs
);
3027 memset(op
, 0, offsetof(TCGOp
, link
));
3031 /* Check for bitfield overflow. */
3032 tcg_debug_assert(op
->nargs
== nargs
);
3038 TCGOp
*tcg_emit_op(TCGOpcode opc
, unsigned nargs
)
3040 TCGOp
*op
= tcg_op_alloc(opc
, nargs
);
3041 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
3045 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*old_op
,
3046 TCGOpcode opc
, unsigned nargs
)
3048 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
3049 QTAILQ_INSERT_BEFORE(old_op
, new_op
, link
);
3053 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*old_op
,
3054 TCGOpcode opc
, unsigned nargs
)
3056 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
3057 QTAILQ_INSERT_AFTER(&s
->ops
, old_op
, new_op
, link
);
3061 static void move_label_uses(TCGLabel
*to
, TCGLabel
*from
)
3065 QSIMPLEQ_FOREACH(u
, &from
->branches
, next
) {
3069 op
->args
[0] = label_arg(to
);
3071 case INDEX_op_brcond_i32
:
3072 case INDEX_op_brcond_i64
:
3073 op
->args
[3] = label_arg(to
);
3075 case INDEX_op_brcond2_i32
:
3076 op
->args
[5] = label_arg(to
);
3079 g_assert_not_reached();
3083 QSIMPLEQ_CONCAT(&to
->branches
, &from
->branches
);
3086 /* Reachable analysis : remove unreachable code. */
3087 static void __attribute__((noinline
))
3088 reachable_code_pass(TCGContext
*s
)
3090 TCGOp
*op
, *op_next
, *op_prev
;
3093 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3098 case INDEX_op_set_label
:
3099 label
= arg_label(op
->args
[0]);
3102 * Note that the first op in the TB is always a load,
3103 * so there is always something before a label.
3105 op_prev
= QTAILQ_PREV(op
, link
);
3108 * If we find two sequential labels, move all branches to
3109 * reference the second label and remove the first label.
3110 * Do this before branch to next optimization, so that the
3111 * middle label is out of the way.
3113 if (op_prev
->opc
== INDEX_op_set_label
) {
3114 move_label_uses(label
, arg_label(op_prev
->args
[0]));
3115 tcg_op_remove(s
, op_prev
);
3116 op_prev
= QTAILQ_PREV(op
, link
);
3120 * Optimization can fold conditional branches to unconditional.
3121 * If we find a label which is preceded by an unconditional
3122 * branch to next, remove the branch. We couldn't do this when
3123 * processing the branch because any dead code between the branch
3124 * and label had not yet been removed.
3126 if (op_prev
->opc
== INDEX_op_br
&&
3127 label
== arg_label(op_prev
->args
[0])) {
3128 tcg_op_remove(s
, op_prev
);
3129 /* Fall through means insns become live again. */
3133 if (QSIMPLEQ_EMPTY(&label
->branches
)) {
3135 * While there is an occasional backward branch, virtually
3136 * all branches generated by the translators are forward.
3137 * Which means that generally we will have already removed
3138 * all references to the label that will be, and there is
3139 * little to be gained by iterating.
3143 /* Once we see a label, insns become live again. */
3150 case INDEX_op_exit_tb
:
3151 case INDEX_op_goto_ptr
:
3152 /* Unconditional branches; everything following is dead. */
3157 /* Notice noreturn helper calls, raising exceptions. */
3158 if (tcg_call_flags(op
) & TCG_CALL_NO_RETURN
) {
3163 case INDEX_op_insn_start
:
3164 /* Never remove -- we need to keep these for unwind. */
3173 tcg_op_remove(s
, op
);
3181 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
3182 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
3184 /* For liveness_pass_1, the register preferences for a given temp. */
3185 static inline TCGRegSet
*la_temp_pref(TCGTemp
*ts
)
3187 return ts
->state_ptr
;
3190 /* For liveness_pass_1, reset the preferences for a given temp to the
3191 * maximal regset for its type.
3193 static inline void la_reset_pref(TCGTemp
*ts
)
3196 = (ts
->state
== TS_DEAD
? 0 : tcg_target_available_regs
[ts
->type
]);
3199 /* liveness analysis: end of function: all temps are dead, and globals
3200 should be in memory. */
3201 static void la_func_end(TCGContext
*s
, int ng
, int nt
)
3205 for (i
= 0; i
< ng
; ++i
) {
3206 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3207 la_reset_pref(&s
->temps
[i
]);
3209 for (i
= ng
; i
< nt
; ++i
) {
3210 s
->temps
[i
].state
= TS_DEAD
;
3211 la_reset_pref(&s
->temps
[i
]);
3215 /* liveness analysis: end of basic block: all temps are dead, globals
3216 and local temps should be in memory. */
3217 static void la_bb_end(TCGContext
*s
, int ng
, int nt
)
3221 for (i
= 0; i
< nt
; ++i
) {
3222 TCGTemp
*ts
= &s
->temps
[i
];
3229 state
= TS_DEAD
| TS_MEM
;
3236 g_assert_not_reached();
3243 /* liveness analysis: sync globals back to memory. */
3244 static void la_global_sync(TCGContext
*s
, int ng
)
3248 for (i
= 0; i
< ng
; ++i
) {
3249 int state
= s
->temps
[i
].state
;
3250 s
->temps
[i
].state
= state
| TS_MEM
;
3251 if (state
== TS_DEAD
) {
3252 /* If the global was previously dead, reset prefs. */
3253 la_reset_pref(&s
->temps
[i
]);
3259 * liveness analysis: conditional branch: all temps are dead unless
3260 * explicitly live-across-conditional-branch, globals and local temps
3263 static void la_bb_sync(TCGContext
*s
, int ng
, int nt
)
3265 la_global_sync(s
, ng
);
3267 for (int i
= ng
; i
< nt
; ++i
) {
3268 TCGTemp
*ts
= &s
->temps
[i
];
3274 ts
->state
= state
| TS_MEM
;
3275 if (state
!= TS_DEAD
) {
3283 g_assert_not_reached();
3285 la_reset_pref(&s
->temps
[i
]);
3289 /* liveness analysis: sync globals back to memory and kill. */
3290 static void la_global_kill(TCGContext
*s
, int ng
)
3294 for (i
= 0; i
< ng
; i
++) {
3295 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3296 la_reset_pref(&s
->temps
[i
]);
3300 /* liveness analysis: note live globals crossing calls. */
3301 static void la_cross_call(TCGContext
*s
, int nt
)
3303 TCGRegSet mask
= ~tcg_target_call_clobber_regs
;
3306 for (i
= 0; i
< nt
; i
++) {
3307 TCGTemp
*ts
= &s
->temps
[i
];
3308 if (!(ts
->state
& TS_DEAD
)) {
3309 TCGRegSet
*pset
= la_temp_pref(ts
);
3310 TCGRegSet set
= *pset
;
3313 /* If the combination is not possible, restart. */
3315 set
= tcg_target_available_regs
[ts
->type
] & mask
;
3323 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce
3324 * to TEMP_EBB, if possible.
3326 static void __attribute__((noinline
))
3327 liveness_pass_0(TCGContext
*s
)
3329 void * const multiple_ebb
= (void *)(uintptr_t)-1;
3330 int nb_temps
= s
->nb_temps
;
3333 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3334 s
->temps
[i
].state_ptr
= NULL
;
3338 * Represent each EBB by the op at which it begins. In the case of
3339 * the first EBB, this is the first op, otherwise it is a label.
3340 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use
3341 * within a single EBB, else MULTIPLE_EBB.
3343 ebb
= QTAILQ_FIRST(&s
->ops
);
3344 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
3345 const TCGOpDef
*def
;
3346 int nb_oargs
, nb_iargs
;
3349 case INDEX_op_set_label
:
3352 case INDEX_op_discard
:
3355 nb_oargs
= TCGOP_CALLO(op
);
3356 nb_iargs
= TCGOP_CALLI(op
);
3359 def
= &tcg_op_defs
[op
->opc
];
3360 nb_oargs
= def
->nb_oargs
;
3361 nb_iargs
= def
->nb_iargs
;
3365 for (int i
= 0; i
< nb_oargs
+ nb_iargs
; ++i
) {
3366 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
3368 if (ts
->kind
!= TEMP_TB
) {
3371 if (ts
->state_ptr
== NULL
) {
3372 ts
->state_ptr
= ebb
;
3373 } else if (ts
->state_ptr
!= ebb
) {
3374 ts
->state_ptr
= multiple_ebb
;
3380 * For TEMP_TB that turned out not to be used beyond one EBB,
3381 * reduce the liveness to TEMP_EBB.
3383 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3384 TCGTemp
*ts
= &s
->temps
[i
];
3385 if (ts
->kind
== TEMP_TB
&& ts
->state_ptr
!= multiple_ebb
) {
3386 ts
->kind
= TEMP_EBB
;
3391 /* Liveness analysis : update the opc_arg_life array to tell if a
3392 given input arguments is dead. Instructions updating dead
3393 temporaries are removed. */
3394 static void __attribute__((noinline
))
3395 liveness_pass_1(TCGContext
*s
)
3397 int nb_globals
= s
->nb_globals
;
3398 int nb_temps
= s
->nb_temps
;
3399 TCGOp
*op
, *op_prev
;
3403 prefs
= tcg_malloc(sizeof(TCGRegSet
) * nb_temps
);
3404 for (i
= 0; i
< nb_temps
; ++i
) {
3405 s
->temps
[i
].state_ptr
= prefs
+ i
;
3408 /* ??? Should be redundant with the exit_tb that ends the TB. */
3409 la_func_end(s
, nb_globals
, nb_temps
);
3411 QTAILQ_FOREACH_REVERSE_SAFE(op
, &s
->ops
, link
, op_prev
) {
3412 int nb_iargs
, nb_oargs
;
3413 TCGOpcode opc_new
, opc_new2
;
3415 TCGLifeData arg_life
= 0;
3417 TCGOpcode opc
= op
->opc
;
3418 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3423 const TCGHelperInfo
*info
= tcg_call_info(op
);
3424 int call_flags
= tcg_call_flags(op
);
3426 nb_oargs
= TCGOP_CALLO(op
);
3427 nb_iargs
= TCGOP_CALLI(op
);
3429 /* pure functions can be removed if their result is unused */
3430 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
3431 for (i
= 0; i
< nb_oargs
; i
++) {
3432 ts
= arg_temp(op
->args
[i
]);
3433 if (ts
->state
!= TS_DEAD
) {
3434 goto do_not_remove_call
;
3441 /* Output args are dead. */
3442 for (i
= 0; i
< nb_oargs
; i
++) {
3443 ts
= arg_temp(op
->args
[i
]);
3444 if (ts
->state
& TS_DEAD
) {
3445 arg_life
|= DEAD_ARG
<< i
;
3447 if (ts
->state
& TS_MEM
) {
3448 arg_life
|= SYNC_ARG
<< i
;
3450 ts
->state
= TS_DEAD
;
3454 /* Not used -- it will be tcg_target_call_oarg_reg(). */
3455 memset(op
->output_pref
, 0, sizeof(op
->output_pref
));
3457 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
3458 TCG_CALL_NO_READ_GLOBALS
))) {
3459 la_global_kill(s
, nb_globals
);
3460 } else if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
3461 la_global_sync(s
, nb_globals
);
3464 /* Record arguments that die in this helper. */
3465 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3466 ts
= arg_temp(op
->args
[i
]);
3467 if (ts
->state
& TS_DEAD
) {
3468 arg_life
|= DEAD_ARG
<< i
;
3472 /* For all live registers, remove call-clobbered prefs. */
3473 la_cross_call(s
, nb_temps
);
3476 * Input arguments are live for preceding opcodes.
3478 * For those arguments that die, and will be allocated in
3479 * registers, clear the register set for that arg, to be
3480 * filled in below. For args that will be on the stack,
3481 * reset to any available reg. Process arguments in reverse
3482 * order so that if a temp is used more than once, the stack
3483 * reset to max happens before the register reset to 0.
3485 for (i
= nb_iargs
- 1; i
>= 0; i
--) {
3486 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3487 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3489 if (ts
->state
& TS_DEAD
) {
3490 switch (loc
->kind
) {
3491 case TCG_CALL_ARG_NORMAL
:
3492 case TCG_CALL_ARG_EXTEND_U
:
3493 case TCG_CALL_ARG_EXTEND_S
:
3494 if (arg_slot_reg_p(loc
->arg_slot
)) {
3495 *la_temp_pref(ts
) = 0;
3501 tcg_target_available_regs
[ts
->type
];
3504 ts
->state
&= ~TS_DEAD
;
3509 * For each input argument, add its input register to prefs.
3510 * If a temp is used once, this produces a single set bit;
3511 * if a temp is used multiple times, this produces a set.
3513 for (i
= 0; i
< nb_iargs
; i
++) {
3514 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3515 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3517 switch (loc
->kind
) {
3518 case TCG_CALL_ARG_NORMAL
:
3519 case TCG_CALL_ARG_EXTEND_U
:
3520 case TCG_CALL_ARG_EXTEND_S
:
3521 if (arg_slot_reg_p(loc
->arg_slot
)) {
3522 tcg_regset_set_reg(*la_temp_pref(ts
),
3523 tcg_target_call_iarg_regs
[loc
->arg_slot
]);
3532 case INDEX_op_insn_start
:
3534 case INDEX_op_discard
:
3535 /* mark the temporary as dead */
3536 ts
= arg_temp(op
->args
[0]);
3537 ts
->state
= TS_DEAD
;
3541 case INDEX_op_add2_i32
:
3542 opc_new
= INDEX_op_add_i32
;
3544 case INDEX_op_sub2_i32
:
3545 opc_new
= INDEX_op_sub_i32
;
3547 case INDEX_op_add2_i64
:
3548 opc_new
= INDEX_op_add_i64
;
3550 case INDEX_op_sub2_i64
:
3551 opc_new
= INDEX_op_sub_i64
;
3555 /* Test if the high part of the operation is dead, but not
3556 the low part. The result can be optimized to a simple
3557 add or sub. This happens often for x86_64 guest when the
3558 cpu mode is set to 32 bit. */
3559 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3560 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3563 /* Replace the opcode and adjust the args in place,
3564 leaving 3 unused args at the end. */
3565 op
->opc
= opc
= opc_new
;
3566 op
->args
[1] = op
->args
[2];
3567 op
->args
[2] = op
->args
[4];
3568 /* Fall through and mark the single-word operation live. */
3574 case INDEX_op_mulu2_i32
:
3575 opc_new
= INDEX_op_mul_i32
;
3576 opc_new2
= INDEX_op_muluh_i32
;
3577 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
3579 case INDEX_op_muls2_i32
:
3580 opc_new
= INDEX_op_mul_i32
;
3581 opc_new2
= INDEX_op_mulsh_i32
;
3582 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
3584 case INDEX_op_mulu2_i64
:
3585 opc_new
= INDEX_op_mul_i64
;
3586 opc_new2
= INDEX_op_muluh_i64
;
3587 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
3589 case INDEX_op_muls2_i64
:
3590 opc_new
= INDEX_op_mul_i64
;
3591 opc_new2
= INDEX_op_mulsh_i64
;
3592 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
3597 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3598 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3599 /* Both parts of the operation are dead. */
3602 /* The high part of the operation is dead; generate the low. */
3603 op
->opc
= opc
= opc_new
;
3604 op
->args
[1] = op
->args
[2];
3605 op
->args
[2] = op
->args
[3];
3606 } else if (arg_temp(op
->args
[0])->state
== TS_DEAD
&& have_opc_new2
) {
3607 /* The low part of the operation is dead; generate the high. */
3608 op
->opc
= opc
= opc_new2
;
3609 op
->args
[0] = op
->args
[1];
3610 op
->args
[1] = op
->args
[2];
3611 op
->args
[2] = op
->args
[3];
3615 /* Mark the single-word operation live. */
3620 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
3621 nb_iargs
= def
->nb_iargs
;
3622 nb_oargs
= def
->nb_oargs
;
3624 /* Test if the operation can be removed because all
3625 its outputs are dead. We assume that nb_oargs == 0
3626 implies side effects */
3627 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
3628 for (i
= 0; i
< nb_oargs
; i
++) {
3629 if (arg_temp(op
->args
[i
])->state
!= TS_DEAD
) {
3638 tcg_op_remove(s
, op
);
3642 for (i
= 0; i
< nb_oargs
; i
++) {
3643 ts
= arg_temp(op
->args
[i
]);
3645 /* Remember the preference of the uses that followed. */
3646 if (i
< ARRAY_SIZE(op
->output_pref
)) {
3647 op
->output_pref
[i
] = *la_temp_pref(ts
);
3650 /* Output args are dead. */
3651 if (ts
->state
& TS_DEAD
) {
3652 arg_life
|= DEAD_ARG
<< i
;
3654 if (ts
->state
& TS_MEM
) {
3655 arg_life
|= SYNC_ARG
<< i
;
3657 ts
->state
= TS_DEAD
;
3661 /* If end of basic block, update. */
3662 if (def
->flags
& TCG_OPF_BB_EXIT
) {
3663 la_func_end(s
, nb_globals
, nb_temps
);
3664 } else if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3665 la_bb_sync(s
, nb_globals
, nb_temps
);
3666 } else if (def
->flags
& TCG_OPF_BB_END
) {
3667 la_bb_end(s
, nb_globals
, nb_temps
);
3668 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3669 la_global_sync(s
, nb_globals
);
3670 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
3671 la_cross_call(s
, nb_temps
);
3675 /* Record arguments that die in this opcode. */
3676 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3677 ts
= arg_temp(op
->args
[i
]);
3678 if (ts
->state
& TS_DEAD
) {
3679 arg_life
|= DEAD_ARG
<< i
;
3683 /* Input arguments are live for preceding opcodes. */
3684 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3685 ts
= arg_temp(op
->args
[i
]);
3686 if (ts
->state
& TS_DEAD
) {
3687 /* For operands that were dead, initially allow
3688 all regs for the type. */
3689 *la_temp_pref(ts
) = tcg_target_available_regs
[ts
->type
];
3690 ts
->state
&= ~TS_DEAD
;
3694 /* Incorporate constraints for this operand. */
3696 case INDEX_op_mov_i32
:
3697 case INDEX_op_mov_i64
:
3698 /* Note that these are TCG_OPF_NOT_PRESENT and do not
3699 have proper constraints. That said, special case
3700 moves to propagate preferences backward. */
3701 if (IS_DEAD_ARG(1)) {
3702 *la_temp_pref(arg_temp(op
->args
[0]))
3703 = *la_temp_pref(arg_temp(op
->args
[1]));
3708 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3709 const TCGArgConstraint
*ct
= &def
->args_ct
[i
];
3710 TCGRegSet set
, *pset
;
3712 ts
= arg_temp(op
->args
[i
]);
3713 pset
= la_temp_pref(ts
);
3718 set
&= output_pref(op
, ct
->alias_index
);
3720 /* If the combination is not possible, restart. */
3730 op
->life
= arg_life
;
3734 /* Liveness analysis: Convert indirect regs to direct temporaries. */
3735 static bool __attribute__((noinline
))
3736 liveness_pass_2(TCGContext
*s
)
3738 int nb_globals
= s
->nb_globals
;
3740 bool changes
= false;
3741 TCGOp
*op
, *op_next
;
3743 /* Create a temporary for each indirect global. */
3744 for (i
= 0; i
< nb_globals
; ++i
) {
3745 TCGTemp
*its
= &s
->temps
[i
];
3746 if (its
->indirect_reg
) {
3747 TCGTemp
*dts
= tcg_temp_alloc(s
);
3748 dts
->type
= its
->type
;
3749 dts
->base_type
= its
->base_type
;
3750 dts
->temp_subindex
= its
->temp_subindex
;
3751 dts
->kind
= TEMP_EBB
;
3752 its
->state_ptr
= dts
;
3754 its
->state_ptr
= NULL
;
3756 /* All globals begin dead. */
3757 its
->state
= TS_DEAD
;
3759 for (nb_temps
= s
->nb_temps
; i
< nb_temps
; ++i
) {
3760 TCGTemp
*its
= &s
->temps
[i
];
3761 its
->state_ptr
= NULL
;
3762 its
->state
= TS_DEAD
;
3765 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3766 TCGOpcode opc
= op
->opc
;
3767 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3768 TCGLifeData arg_life
= op
->life
;
3769 int nb_iargs
, nb_oargs
, call_flags
;
3770 TCGTemp
*arg_ts
, *dir_ts
;
3772 if (opc
== INDEX_op_call
) {
3773 nb_oargs
= TCGOP_CALLO(op
);
3774 nb_iargs
= TCGOP_CALLI(op
);
3775 call_flags
= tcg_call_flags(op
);
3777 nb_iargs
= def
->nb_iargs
;
3778 nb_oargs
= def
->nb_oargs
;
3780 /* Set flags similar to how calls require. */
3781 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3782 /* Like reading globals: sync_globals */
3783 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3784 } else if (def
->flags
& TCG_OPF_BB_END
) {
3785 /* Like writing globals: save_globals */
3787 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3788 /* Like reading globals: sync_globals */
3789 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3791 /* No effect on globals. */
3792 call_flags
= (TCG_CALL_NO_READ_GLOBALS
|
3793 TCG_CALL_NO_WRITE_GLOBALS
);
3797 /* Make sure that input arguments are available. */
3798 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3799 arg_ts
= arg_temp(op
->args
[i
]);
3800 dir_ts
= arg_ts
->state_ptr
;
3801 if (dir_ts
&& arg_ts
->state
== TS_DEAD
) {
3802 TCGOpcode lopc
= (arg_ts
->type
== TCG_TYPE_I32
3805 TCGOp
*lop
= tcg_op_insert_before(s
, op
, lopc
, 3);
3807 lop
->args
[0] = temp_arg(dir_ts
);
3808 lop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3809 lop
->args
[2] = arg_ts
->mem_offset
;
3811 /* Loaded, but synced with memory. */
3812 arg_ts
->state
= TS_MEM
;
3816 /* Perform input replacement, and mark inputs that became dead.
3817 No action is required except keeping temp_state up to date
3818 so that we reload when needed. */
3819 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3820 arg_ts
= arg_temp(op
->args
[i
]);
3821 dir_ts
= arg_ts
->state_ptr
;
3823 op
->args
[i
] = temp_arg(dir_ts
);
3825 if (IS_DEAD_ARG(i
)) {
3826 arg_ts
->state
= TS_DEAD
;
3831 /* Liveness analysis should ensure that the following are
3832 all correct, for call sites and basic block end points. */
3833 if (call_flags
& TCG_CALL_NO_READ_GLOBALS
) {
3835 } else if (call_flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
3836 for (i
= 0; i
< nb_globals
; ++i
) {
3837 /* Liveness should see that globals are synced back,
3838 that is, either TS_DEAD or TS_MEM. */
3839 arg_ts
= &s
->temps
[i
];
3840 tcg_debug_assert(arg_ts
->state_ptr
== 0
3841 || arg_ts
->state
!= 0);
3844 for (i
= 0; i
< nb_globals
; ++i
) {
3845 /* Liveness should see that globals are saved back,
3846 that is, TS_DEAD, waiting to be reloaded. */
3847 arg_ts
= &s
->temps
[i
];
3848 tcg_debug_assert(arg_ts
->state_ptr
== 0
3849 || arg_ts
->state
== TS_DEAD
);
3853 /* Outputs become available. */
3854 if (opc
== INDEX_op_mov_i32
|| opc
== INDEX_op_mov_i64
) {
3855 arg_ts
= arg_temp(op
->args
[0]);
3856 dir_ts
= arg_ts
->state_ptr
;
3858 op
->args
[0] = temp_arg(dir_ts
);
3861 /* The output is now live and modified. */
3864 if (NEED_SYNC_ARG(0)) {
3865 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3868 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3869 TCGTemp
*out_ts
= dir_ts
;
3871 if (IS_DEAD_ARG(0)) {
3872 out_ts
= arg_temp(op
->args
[1]);
3873 arg_ts
->state
= TS_DEAD
;
3874 tcg_op_remove(s
, op
);
3876 arg_ts
->state
= TS_MEM
;
3879 sop
->args
[0] = temp_arg(out_ts
);
3880 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3881 sop
->args
[2] = arg_ts
->mem_offset
;
3883 tcg_debug_assert(!IS_DEAD_ARG(0));
3887 for (i
= 0; i
< nb_oargs
; i
++) {
3888 arg_ts
= arg_temp(op
->args
[i
]);
3889 dir_ts
= arg_ts
->state_ptr
;
3893 op
->args
[i
] = temp_arg(dir_ts
);
3896 /* The output is now live and modified. */
3899 /* Sync outputs upon their last write. */
3900 if (NEED_SYNC_ARG(i
)) {
3901 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3904 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3906 sop
->args
[0] = temp_arg(dir_ts
);
3907 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3908 sop
->args
[2] = arg_ts
->mem_offset
;
3910 arg_ts
->state
= TS_MEM
;
3912 /* Drop outputs that are dead. */
3913 if (IS_DEAD_ARG(i
)) {
3914 arg_ts
->state
= TS_DEAD
;
3923 static void temp_allocate_frame(TCGContext
*s
, TCGTemp
*ts
)
3928 /* When allocating an object, look at the full type. */
3929 size
= tcg_type_size(ts
->base_type
);
3930 switch (ts
->base_type
) {
3942 * Note that we do not require aligned storage for V256,
3943 * and that we provide alignment for I128 to match V128,
3944 * even if that's above what the host ABI requires.
3949 g_assert_not_reached();
3953 * Assume the stack is sufficiently aligned.
3954 * This affects e.g. ARM NEON, where we have 8 byte stack alignment
3955 * and do not require 16 byte vector alignment. This seems slightly
3956 * easier than fully parameterizing the above switch statement.
3958 align
= MIN(TCG_TARGET_STACK_ALIGN
, align
);
3959 off
= ROUND_UP(s
->current_frame_offset
, align
);
3961 /* If we've exhausted the stack frame, restart with a smaller TB. */
3962 if (off
+ size
> s
->frame_end
) {
3963 tcg_raise_tb_overflow(s
);
3965 s
->current_frame_offset
= off
+ size
;
3966 #if defined(__sparc__)
3967 off
+= TCG_TARGET_STACK_BIAS
;
3970 /* If the object was subdivided, assign memory to all the parts. */
3971 if (ts
->base_type
!= ts
->type
) {
3972 int part_size
= tcg_type_size(ts
->type
);
3973 int part_count
= size
/ part_size
;
3976 * Each part is allocated sequentially in tcg_temp_new_internal.
3977 * Jump back to the first part by subtracting the current index.
3979 ts
-= ts
->temp_subindex
;
3980 for (int i
= 0; i
< part_count
; ++i
) {
3981 ts
[i
].mem_offset
= off
+ i
* part_size
;
3982 ts
[i
].mem_base
= s
->frame_temp
;
3983 ts
[i
].mem_allocated
= 1;
3986 ts
->mem_offset
= off
;
3987 ts
->mem_base
= s
->frame_temp
;
3988 ts
->mem_allocated
= 1;
3992 /* Assign @reg to @ts, and update reg_to_temp[]. */
3993 static void set_temp_val_reg(TCGContext
*s
, TCGTemp
*ts
, TCGReg reg
)
3995 if (ts
->val_type
== TEMP_VAL_REG
) {
3996 TCGReg old
= ts
->reg
;
3997 tcg_debug_assert(s
->reg_to_temp
[old
] == ts
);
4001 s
->reg_to_temp
[old
] = NULL
;
4003 tcg_debug_assert(s
->reg_to_temp
[reg
] == NULL
);
4004 s
->reg_to_temp
[reg
] = ts
;
4005 ts
->val_type
= TEMP_VAL_REG
;
4009 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */
4010 static void set_temp_val_nonreg(TCGContext
*s
, TCGTemp
*ts
, TCGTempVal type
)
4012 tcg_debug_assert(type
!= TEMP_VAL_REG
);
4013 if (ts
->val_type
== TEMP_VAL_REG
) {
4014 TCGReg reg
= ts
->reg
;
4015 tcg_debug_assert(s
->reg_to_temp
[reg
] == ts
);
4016 s
->reg_to_temp
[reg
] = NULL
;
4018 ts
->val_type
= type
;
4021 static void temp_load(TCGContext
*, TCGTemp
*, TCGRegSet
, TCGRegSet
, TCGRegSet
);
4023 /* Mark a temporary as free or dead. If 'free_or_dead' is negative,
4024 mark it free; otherwise mark it dead. */
4025 static void temp_free_or_dead(TCGContext
*s
, TCGTemp
*ts
, int free_or_dead
)
4027 TCGTempVal new_type
;
4034 new_type
= TEMP_VAL_MEM
;
4037 new_type
= free_or_dead
< 0 ? TEMP_VAL_MEM
: TEMP_VAL_DEAD
;
4040 new_type
= TEMP_VAL_CONST
;
4043 g_assert_not_reached();
4045 set_temp_val_nonreg(s
, ts
, new_type
);
4048 /* Mark a temporary as dead. */
4049 static inline void temp_dead(TCGContext
*s
, TCGTemp
*ts
)
4051 temp_free_or_dead(s
, ts
, 1);
4054 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
4055 registers needs to be allocated to store a constant. If 'free_or_dead'
4056 is non-zero, subsequently release the temporary; if it is positive, the
4057 temp is dead; if it is negative, the temp is free. */
4058 static void temp_sync(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
,
4059 TCGRegSet preferred_regs
, int free_or_dead
)
4061 if (!temp_readonly(ts
) && !ts
->mem_coherent
) {
4062 if (!ts
->mem_allocated
) {
4063 temp_allocate_frame(s
, ts
);
4065 switch (ts
->val_type
) {
4066 case TEMP_VAL_CONST
:
4067 /* If we're going to free the temp immediately, then we won't
4068 require it later in a register, so attempt to store the
4069 constant to memory directly. */
4071 && tcg_out_sti(s
, ts
->type
, ts
->val
,
4072 ts
->mem_base
->reg
, ts
->mem_offset
)) {
4075 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4076 allocated_regs
, preferred_regs
);
4080 tcg_out_st(s
, ts
->type
, ts
->reg
,
4081 ts
->mem_base
->reg
, ts
->mem_offset
);
4089 g_assert_not_reached();
4091 ts
->mem_coherent
= 1;
4094 temp_free_or_dead(s
, ts
, free_or_dead
);
4098 /* free register 'reg' by spilling the corresponding temporary if necessary */
4099 static void tcg_reg_free(TCGContext
*s
, TCGReg reg
, TCGRegSet allocated_regs
)
4101 TCGTemp
*ts
= s
->reg_to_temp
[reg
];
4103 temp_sync(s
, ts
, allocated_regs
, 0, -1);
4109 * @required_regs: Set of registers in which we must allocate.
4110 * @allocated_regs: Set of registers which must be avoided.
4111 * @preferred_regs: Set of registers we should prefer.
4112 * @rev: True if we search the registers in "indirect" order.
4114 * The allocated register must be in @required_regs & ~@allocated_regs,
4115 * but if we can put it in @preferred_regs we may save a move later.
4117 static TCGReg
tcg_reg_alloc(TCGContext
*s
, TCGRegSet required_regs
,
4118 TCGRegSet allocated_regs
,
4119 TCGRegSet preferred_regs
, bool rev
)
4121 int i
, j
, f
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4122 TCGRegSet reg_ct
[2];
4125 reg_ct
[1] = required_regs
& ~allocated_regs
;
4126 tcg_debug_assert(reg_ct
[1] != 0);
4127 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4129 /* Skip the preferred_regs option if it cannot be satisfied,
4130 or if the preference made no difference. */
4131 f
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4133 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4135 /* Try free registers, preferences first. */
4136 for (j
= f
; j
< 2; j
++) {
4137 TCGRegSet set
= reg_ct
[j
];
4139 if (tcg_regset_single(set
)) {
4140 /* One register in the set. */
4141 TCGReg reg
= tcg_regset_first(set
);
4142 if (s
->reg_to_temp
[reg
] == NULL
) {
4146 for (i
= 0; i
< n
; i
++) {
4147 TCGReg reg
= order
[i
];
4148 if (s
->reg_to_temp
[reg
] == NULL
&&
4149 tcg_regset_test_reg(set
, reg
)) {
4156 /* We must spill something. */
4157 for (j
= f
; j
< 2; j
++) {
4158 TCGRegSet set
= reg_ct
[j
];
4160 if (tcg_regset_single(set
)) {
4161 /* One register in the set. */
4162 TCGReg reg
= tcg_regset_first(set
);
4163 tcg_reg_free(s
, reg
, allocated_regs
);
4166 for (i
= 0; i
< n
; i
++) {
4167 TCGReg reg
= order
[i
];
4168 if (tcg_regset_test_reg(set
, reg
)) {
4169 tcg_reg_free(s
, reg
, allocated_regs
);
4176 g_assert_not_reached();
4179 static TCGReg
tcg_reg_alloc_pair(TCGContext
*s
, TCGRegSet required_regs
,
4180 TCGRegSet allocated_regs
,
4181 TCGRegSet preferred_regs
, bool rev
)
4183 int i
, j
, k
, fmin
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4184 TCGRegSet reg_ct
[2];
4187 /* Ensure that if I is not in allocated_regs, I+1 is not either. */
4188 reg_ct
[1] = required_regs
& ~(allocated_regs
| (allocated_regs
>> 1));
4189 tcg_debug_assert(reg_ct
[1] != 0);
4190 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4192 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4195 * Skip the preferred_regs option if it cannot be satisfied,
4196 * or if the preference made no difference.
4198 k
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4201 * Minimize the number of flushes by looking for 2 free registers first,
4202 * then a single flush, then two flushes.
4204 for (fmin
= 2; fmin
>= 0; fmin
--) {
4205 for (j
= k
; j
< 2; j
++) {
4206 TCGRegSet set
= reg_ct
[j
];
4208 for (i
= 0; i
< n
; i
++) {
4209 TCGReg reg
= order
[i
];
4211 if (tcg_regset_test_reg(set
, reg
)) {
4212 int f
= !s
->reg_to_temp
[reg
] + !s
->reg_to_temp
[reg
+ 1];
4214 tcg_reg_free(s
, reg
, allocated_regs
);
4215 tcg_reg_free(s
, reg
+ 1, allocated_regs
);
4222 g_assert_not_reached();
4225 /* Make sure the temporary is in a register. If needed, allocate the register
4226 from DESIRED while avoiding ALLOCATED. */
4227 static void temp_load(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet desired_regs
,
4228 TCGRegSet allocated_regs
, TCGRegSet preferred_regs
)
4232 switch (ts
->val_type
) {
4235 case TEMP_VAL_CONST
:
4236 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4237 preferred_regs
, ts
->indirect_base
);
4238 if (ts
->type
<= TCG_TYPE_I64
) {
4239 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
4241 uint64_t val
= ts
->val
;
4245 * Find the minimal vector element that matches the constant.
4246 * The targets will, in general, have to do this search anyway,
4247 * do this generically.
4249 if (val
== dup_const(MO_8
, val
)) {
4251 } else if (val
== dup_const(MO_16
, val
)) {
4253 } else if (val
== dup_const(MO_32
, val
)) {
4257 tcg_out_dupi_vec(s
, ts
->type
, vece
, reg
, ts
->val
);
4259 ts
->mem_coherent
= 0;
4262 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4263 preferred_regs
, ts
->indirect_base
);
4264 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_base
->reg
, ts
->mem_offset
);
4265 ts
->mem_coherent
= 1;
4269 g_assert_not_reached();
4271 set_temp_val_reg(s
, ts
, reg
);
4274 /* Save a temporary to memory. 'allocated_regs' is used in case a
4275 temporary registers needs to be allocated to store a constant. */
4276 static void temp_save(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
)
4278 /* The liveness analysis already ensures that globals are back
4279 in memory. Keep an tcg_debug_assert for safety. */
4280 tcg_debug_assert(ts
->val_type
== TEMP_VAL_MEM
|| temp_readonly(ts
));
4283 /* save globals to their canonical location and assume they can be
4284 modified be the following code. 'allocated_regs' is used in case a
4285 temporary registers needs to be allocated to store a constant. */
4286 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4290 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4291 temp_save(s
, &s
->temps
[i
], allocated_regs
);
4295 /* sync globals to their canonical location and assume they can be
4296 read by the following code. 'allocated_regs' is used in case a
4297 temporary registers needs to be allocated to store a constant. */
4298 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4302 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4303 TCGTemp
*ts
= &s
->temps
[i
];
4304 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
4305 || ts
->kind
== TEMP_FIXED
4306 || ts
->mem_coherent
);
4310 /* at the end of a basic block, we assume all temporaries are dead and
4311 all globals are stored at their canonical location. */
4312 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
4316 for (i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4317 TCGTemp
*ts
= &s
->temps
[i
];
4321 temp_save(s
, ts
, allocated_regs
);
4324 /* The liveness analysis already ensures that temps are dead.
4325 Keep an tcg_debug_assert for safety. */
4326 tcg_debug_assert(ts
->val_type
== TEMP_VAL_DEAD
);
4329 /* Similarly, we should have freed any allocated register. */
4330 tcg_debug_assert(ts
->val_type
== TEMP_VAL_CONST
);
4333 g_assert_not_reached();
4337 save_globals(s
, allocated_regs
);
4341 * At a conditional branch, we assume all temporaries are dead unless
4342 * explicitly live-across-conditional-branch; all globals and local
4343 * temps are synced to their location.
4345 static void tcg_reg_alloc_cbranch(TCGContext
*s
, TCGRegSet allocated_regs
)
4347 sync_globals(s
, allocated_regs
);
4349 for (int i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4350 TCGTemp
*ts
= &s
->temps
[i
];
4352 * The liveness analysis already ensures that temps are dead.
4353 * Keep tcg_debug_asserts for safety.
4357 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
|| ts
->mem_coherent
);
4363 g_assert_not_reached();
4369 * Specialized code generation for INDEX_op_mov_* with a constant.
4371 static void tcg_reg_alloc_do_movi(TCGContext
*s
, TCGTemp
*ots
,
4372 tcg_target_ulong val
, TCGLifeData arg_life
,
4373 TCGRegSet preferred_regs
)
4375 /* ENV should not be modified. */
4376 tcg_debug_assert(!temp_readonly(ots
));
4378 /* The movi is not explicitly generated here. */
4379 set_temp_val_nonreg(s
, ots
, TEMP_VAL_CONST
);
4381 ots
->mem_coherent
= 0;
4382 if (NEED_SYNC_ARG(0)) {
4383 temp_sync(s
, ots
, s
->reserved_regs
, preferred_regs
, IS_DEAD_ARG(0));
4384 } else if (IS_DEAD_ARG(0)) {
4390 * Specialized code generation for INDEX_op_mov_*.
4392 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOp
*op
)
4394 const TCGLifeData arg_life
= op
->life
;
4395 TCGRegSet allocated_regs
, preferred_regs
;
4397 TCGType otype
, itype
;
4400 allocated_regs
= s
->reserved_regs
;
4401 preferred_regs
= output_pref(op
, 0);
4402 ots
= arg_temp(op
->args
[0]);
4403 ts
= arg_temp(op
->args
[1]);
4405 /* ENV should not be modified. */
4406 tcg_debug_assert(!temp_readonly(ots
));
4408 /* Note that otype != itype for no-op truncation. */
4412 if (ts
->val_type
== TEMP_VAL_CONST
) {
4413 /* propagate constant or generate sti */
4414 tcg_target_ulong val
= ts
->val
;
4415 if (IS_DEAD_ARG(1)) {
4418 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, preferred_regs
);
4422 /* If the source value is in memory we're going to be forced
4423 to have it in a register in order to perform the copy. Copy
4424 the SOURCE value into its own register first, that way we
4425 don't have to reload SOURCE the next time it is used. */
4426 if (ts
->val_type
== TEMP_VAL_MEM
) {
4427 temp_load(s
, ts
, tcg_target_available_regs
[itype
],
4428 allocated_regs
, preferred_regs
);
4430 tcg_debug_assert(ts
->val_type
== TEMP_VAL_REG
);
4433 if (IS_DEAD_ARG(0)) {
4434 /* mov to a non-saved dead register makes no sense (even with
4435 liveness analysis disabled). */
4436 tcg_debug_assert(NEED_SYNC_ARG(0));
4437 if (!ots
->mem_allocated
) {
4438 temp_allocate_frame(s
, ots
);
4440 tcg_out_st(s
, otype
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4441 if (IS_DEAD_ARG(1)) {
4448 if (IS_DEAD_ARG(1) && ts
->kind
!= TEMP_FIXED
) {
4450 * The mov can be suppressed. Kill input first, so that it
4451 * is unlinked from reg_to_temp, then set the output to the
4452 * reg that we saved from the input.
4457 if (ots
->val_type
== TEMP_VAL_REG
) {
4460 /* Make sure to not spill the input register during allocation. */
4461 oreg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
4462 allocated_regs
| ((TCGRegSet
)1 << ireg
),
4463 preferred_regs
, ots
->indirect_base
);
4465 if (!tcg_out_mov(s
, otype
, oreg
, ireg
)) {
4467 * Cross register class move not supported.
4468 * Store the source register into the destination slot
4469 * and leave the destination temp as TEMP_VAL_MEM.
4471 assert(!temp_readonly(ots
));
4472 if (!ts
->mem_allocated
) {
4473 temp_allocate_frame(s
, ots
);
4475 tcg_out_st(s
, ts
->type
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4476 set_temp_val_nonreg(s
, ts
, TEMP_VAL_MEM
);
4477 ots
->mem_coherent
= 1;
4481 set_temp_val_reg(s
, ots
, oreg
);
4482 ots
->mem_coherent
= 0;
4484 if (NEED_SYNC_ARG(0)) {
4485 temp_sync(s
, ots
, allocated_regs
, 0, 0);
4490 * Specialized code generation for INDEX_op_dup_vec.
4492 static void tcg_reg_alloc_dup(TCGContext
*s
, const TCGOp
*op
)
4494 const TCGLifeData arg_life
= op
->life
;
4495 TCGRegSet dup_out_regs
, dup_in_regs
;
4497 TCGType itype
, vtype
;
4502 ots
= arg_temp(op
->args
[0]);
4503 its
= arg_temp(op
->args
[1]);
4505 /* ENV should not be modified. */
4506 tcg_debug_assert(!temp_readonly(ots
));
4509 vece
= TCGOP_VECE(op
);
4510 vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4512 if (its
->val_type
== TEMP_VAL_CONST
) {
4513 /* Propagate constant via movi -> dupi. */
4514 tcg_target_ulong val
= its
->val
;
4515 if (IS_DEAD_ARG(1)) {
4518 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, output_pref(op
, 0));
4522 dup_out_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4523 dup_in_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[1].regs
;
4525 /* Allocate the output register now. */
4526 if (ots
->val_type
!= TEMP_VAL_REG
) {
4527 TCGRegSet allocated_regs
= s
->reserved_regs
;
4530 if (!IS_DEAD_ARG(1) && its
->val_type
== TEMP_VAL_REG
) {
4531 /* Make sure to not spill the input register. */
4532 tcg_regset_set_reg(allocated_regs
, its
->reg
);
4534 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4535 output_pref(op
, 0), ots
->indirect_base
);
4536 set_temp_val_reg(s
, ots
, oreg
);
4539 switch (its
->val_type
) {
4542 * The dup constriaints must be broad, covering all possible VECE.
4543 * However, tcg_op_dup_vec() gets to see the VECE and we allow it
4544 * to fail, indicating that extra moves are required for that case.
4546 if (tcg_regset_test_reg(dup_in_regs
, its
->reg
)) {
4547 if (tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, its
->reg
)) {
4550 /* Try again from memory or a vector input register. */
4552 if (!its
->mem_coherent
) {
4554 * The input register is not synced, and so an extra store
4555 * would be required to use memory. Attempt an integer-vector
4556 * register move first. We do not have a TCGRegSet for this.
4558 if (tcg_out_mov(s
, itype
, ots
->reg
, its
->reg
)) {
4561 /* Sync the temp back to its slot and load from there. */
4562 temp_sync(s
, its
, s
->reserved_regs
, 0, 0);
4568 if (HOST_BIG_ENDIAN
) {
4569 lowpart_ofs
= tcg_type_size(itype
) - (1 << vece
);
4571 if (tcg_out_dupm_vec(s
, vtype
, vece
, ots
->reg
, its
->mem_base
->reg
,
4572 its
->mem_offset
+ lowpart_ofs
)) {
4575 /* Load the input into the destination vector register. */
4576 tcg_out_ld(s
, itype
, ots
->reg
, its
->mem_base
->reg
, its
->mem_offset
);
4580 g_assert_not_reached();
4583 /* We now have a vector input register, so dup must succeed. */
4584 ok
= tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, ots
->reg
);
4585 tcg_debug_assert(ok
);
4588 ots
->mem_coherent
= 0;
4589 if (IS_DEAD_ARG(1)) {
4592 if (NEED_SYNC_ARG(0)) {
4593 temp_sync(s
, ots
, s
->reserved_regs
, 0, 0);
4595 if (IS_DEAD_ARG(0)) {
4600 static void tcg_reg_alloc_op(TCGContext
*s
, const TCGOp
*op
)
4602 const TCGLifeData arg_life
= op
->life
;
4603 const TCGOpDef
* const def
= &tcg_op_defs
[op
->opc
];
4604 TCGRegSet i_allocated_regs
;
4605 TCGRegSet o_allocated_regs
;
4606 int i
, k
, nb_iargs
, nb_oargs
;
4609 const TCGArgConstraint
*arg_ct
;
4611 TCGArg new_args
[TCG_MAX_OP_ARGS
];
4612 int const_args
[TCG_MAX_OP_ARGS
];
4614 nb_oargs
= def
->nb_oargs
;
4615 nb_iargs
= def
->nb_iargs
;
4617 /* copy constants */
4618 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
4619 op
->args
+ nb_oargs
+ nb_iargs
,
4620 sizeof(TCGArg
) * def
->nb_cargs
);
4622 i_allocated_regs
= s
->reserved_regs
;
4623 o_allocated_regs
= s
->reserved_regs
;
4625 /* satisfy input constraints */
4626 for (k
= 0; k
< nb_iargs
; k
++) {
4627 TCGRegSet i_preferred_regs
, i_required_regs
;
4628 bool allocate_new_reg
, copyto_new_reg
;
4632 i
= def
->args_ct
[nb_oargs
+ k
].sort_index
;
4634 arg_ct
= &def
->args_ct
[i
];
4637 if (ts
->val_type
== TEMP_VAL_CONST
4638 && tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
->ct
)) {
4639 /* constant is OK for instruction */
4641 new_args
[i
] = ts
->val
;
4646 i_preferred_regs
= 0;
4647 i_required_regs
= arg_ct
->regs
;
4648 allocate_new_reg
= false;
4649 copyto_new_reg
= false;
4651 switch (arg_ct
->pair
) {
4652 case 0: /* not paired */
4653 if (arg_ct
->ialias
) {
4654 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4657 * If the input is readonly, then it cannot also be an
4658 * output and aliased to itself. If the input is not
4659 * dead after the instruction, we must allocate a new
4660 * register and move it.
4662 if (temp_readonly(ts
) || !IS_DEAD_ARG(i
)) {
4663 allocate_new_reg
= true;
4664 } else if (ts
->val_type
== TEMP_VAL_REG
) {
4666 * Check if the current register has already been
4667 * allocated for another input.
4670 tcg_regset_test_reg(i_allocated_regs
, reg
);
4673 if (!allocate_new_reg
) {
4674 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4677 allocate_new_reg
= !tcg_regset_test_reg(i_required_regs
, reg
);
4679 if (allocate_new_reg
) {
4681 * Allocate a new register matching the constraint
4682 * and move the temporary register into it.
4684 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4685 i_allocated_regs
, 0);
4686 reg
= tcg_reg_alloc(s
, i_required_regs
, i_allocated_regs
,
4687 i_preferred_regs
, ts
->indirect_base
);
4688 copyto_new_reg
= true;
4693 /* First of an input pair; if i1 == i2, the second is an output. */
4695 i2
= arg_ct
->pair_index
;
4696 ts2
= i1
!= i2
? arg_temp(op
->args
[i2
]) : NULL
;
4699 * It is easier to default to allocating a new pair
4700 * and to identify a few cases where it's not required.
4702 if (arg_ct
->ialias
) {
4703 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4704 if (IS_DEAD_ARG(i1
) &&
4706 !temp_readonly(ts
) &&
4707 ts
->val_type
== TEMP_VAL_REG
&&
4708 ts
->reg
< TCG_TARGET_NB_REGS
- 1 &&
4709 tcg_regset_test_reg(i_required_regs
, reg
) &&
4710 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4711 !tcg_regset_test_reg(i_allocated_regs
, reg
+ 1) &&
4713 ? ts2
->val_type
== TEMP_VAL_REG
&&
4714 ts2
->reg
== reg
+ 1 &&
4716 : s
->reg_to_temp
[reg
+ 1] == NULL
)) {
4720 /* Without aliasing, the pair must also be an input. */
4721 tcg_debug_assert(ts2
);
4722 if (ts
->val_type
== TEMP_VAL_REG
&&
4723 ts2
->val_type
== TEMP_VAL_REG
&&
4724 ts2
->reg
== reg
+ 1 &&
4725 tcg_regset_test_reg(i_required_regs
, reg
)) {
4729 reg
= tcg_reg_alloc_pair(s
, i_required_regs
, i_allocated_regs
,
4730 0, ts
->indirect_base
);
4733 case 2: /* pair second */
4734 reg
= new_args
[arg_ct
->pair_index
] + 1;
4737 case 3: /* ialias with second output, no first input */
4738 tcg_debug_assert(arg_ct
->ialias
);
4739 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4741 if (IS_DEAD_ARG(i
) &&
4742 !temp_readonly(ts
) &&
4743 ts
->val_type
== TEMP_VAL_REG
&&
4745 s
->reg_to_temp
[reg
- 1] == NULL
&&
4746 tcg_regset_test_reg(i_required_regs
, reg
) &&
4747 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4748 !tcg_regset_test_reg(i_allocated_regs
, reg
- 1)) {
4749 tcg_regset_set_reg(i_allocated_regs
, reg
- 1);
4752 reg
= tcg_reg_alloc_pair(s
, i_required_regs
>> 1,
4753 i_allocated_regs
, 0,
4755 tcg_regset_set_reg(i_allocated_regs
, reg
);
4761 * If an aliased input is not dead after the instruction,
4762 * we must allocate a new register and move it.
4764 if (arg_ct
->ialias
&& (!IS_DEAD_ARG(i
) || temp_readonly(ts
))) {
4765 TCGRegSet t_allocated_regs
= i_allocated_regs
;
4768 * Because of the alias, and the continued life, make sure
4769 * that the temp is somewhere *other* than the reg pair,
4770 * and we get a copy in reg.
4772 tcg_regset_set_reg(t_allocated_regs
, reg
);
4773 tcg_regset_set_reg(t_allocated_regs
, reg
+ 1);
4774 if (ts
->val_type
== TEMP_VAL_REG
&& ts
->reg
== reg
) {
4775 /* If ts was already in reg, copy it somewhere else. */
4779 tcg_debug_assert(ts
->kind
!= TEMP_FIXED
);
4780 nr
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
4781 t_allocated_regs
, 0, ts
->indirect_base
);
4782 ok
= tcg_out_mov(s
, ts
->type
, nr
, reg
);
4783 tcg_debug_assert(ok
);
4785 set_temp_val_reg(s
, ts
, nr
);
4787 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4788 t_allocated_regs
, 0);
4789 copyto_new_reg
= true;
4792 /* Preferably allocate to reg, otherwise copy. */
4793 i_required_regs
= (TCGRegSet
)1 << reg
;
4794 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4796 copyto_new_reg
= ts
->reg
!= reg
;
4801 g_assert_not_reached();
4804 if (copyto_new_reg
) {
4805 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4807 * Cross register class move not supported. Sync the
4808 * temp back to its slot and load from there.
4810 temp_sync(s
, ts
, i_allocated_regs
, 0, 0);
4811 tcg_out_ld(s
, ts
->type
, reg
,
4812 ts
->mem_base
->reg
, ts
->mem_offset
);
4817 tcg_regset_set_reg(i_allocated_regs
, reg
);
4820 /* mark dead temporaries and free the associated registers */
4821 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
4822 if (IS_DEAD_ARG(i
)) {
4823 temp_dead(s
, arg_temp(op
->args
[i
]));
4827 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
4828 tcg_reg_alloc_cbranch(s
, i_allocated_regs
);
4829 } else if (def
->flags
& TCG_OPF_BB_END
) {
4830 tcg_reg_alloc_bb_end(s
, i_allocated_regs
);
4832 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
4833 /* XXX: permit generic clobber register list ? */
4834 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
4835 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
4836 tcg_reg_free(s
, i
, i_allocated_regs
);
4840 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
4841 /* sync globals if the op has side effects and might trigger
4843 sync_globals(s
, i_allocated_regs
);
4846 /* satisfy the output constraints */
4847 for(k
= 0; k
< nb_oargs
; k
++) {
4848 i
= def
->args_ct
[k
].sort_index
;
4850 arg_ct
= &def
->args_ct
[i
];
4853 /* ENV should not be modified. */
4854 tcg_debug_assert(!temp_readonly(ts
));
4856 switch (arg_ct
->pair
) {
4857 case 0: /* not paired */
4858 if (arg_ct
->oalias
&& !const_args
[arg_ct
->alias_index
]) {
4859 reg
= new_args
[arg_ct
->alias_index
];
4860 } else if (arg_ct
->newreg
) {
4861 reg
= tcg_reg_alloc(s
, arg_ct
->regs
,
4862 i_allocated_regs
| o_allocated_regs
,
4863 output_pref(op
, k
), ts
->indirect_base
);
4865 reg
= tcg_reg_alloc(s
, arg_ct
->regs
, o_allocated_regs
,
4866 output_pref(op
, k
), ts
->indirect_base
);
4870 case 1: /* first of pair */
4871 tcg_debug_assert(!arg_ct
->newreg
);
4872 if (arg_ct
->oalias
) {
4873 reg
= new_args
[arg_ct
->alias_index
];
4876 reg
= tcg_reg_alloc_pair(s
, arg_ct
->regs
, o_allocated_regs
,
4877 output_pref(op
, k
), ts
->indirect_base
);
4880 case 2: /* second of pair */
4881 tcg_debug_assert(!arg_ct
->newreg
);
4882 if (arg_ct
->oalias
) {
4883 reg
= new_args
[arg_ct
->alias_index
];
4885 reg
= new_args
[arg_ct
->pair_index
] + 1;
4889 case 3: /* first of pair, aliasing with a second input */
4890 tcg_debug_assert(!arg_ct
->newreg
);
4891 reg
= new_args
[arg_ct
->pair_index
] - 1;
4895 g_assert_not_reached();
4897 tcg_regset_set_reg(o_allocated_regs
, reg
);
4898 set_temp_val_reg(s
, ts
, reg
);
4899 ts
->mem_coherent
= 0;
4904 /* emit instruction */
4906 case INDEX_op_ext8s_i32
:
4907 tcg_out_ext8s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
4909 case INDEX_op_ext8s_i64
:
4910 tcg_out_ext8s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
4912 case INDEX_op_ext8u_i32
:
4913 case INDEX_op_ext8u_i64
:
4914 tcg_out_ext8u(s
, new_args
[0], new_args
[1]);
4916 case INDEX_op_ext16s_i32
:
4917 tcg_out_ext16s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
4919 case INDEX_op_ext16s_i64
:
4920 tcg_out_ext16s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
4922 case INDEX_op_ext16u_i32
:
4923 case INDEX_op_ext16u_i64
:
4924 tcg_out_ext16u(s
, new_args
[0], new_args
[1]);
4926 case INDEX_op_ext32s_i64
:
4927 tcg_out_ext32s(s
, new_args
[0], new_args
[1]);
4929 case INDEX_op_ext32u_i64
:
4930 tcg_out_ext32u(s
, new_args
[0], new_args
[1]);
4932 case INDEX_op_ext_i32_i64
:
4933 tcg_out_exts_i32_i64(s
, new_args
[0], new_args
[1]);
4935 case INDEX_op_extu_i32_i64
:
4936 tcg_out_extu_i32_i64(s
, new_args
[0], new_args
[1]);
4938 case INDEX_op_extrl_i64_i32
:
4939 tcg_out_extrl_i64_i32(s
, new_args
[0], new_args
[1]);
4942 if (def
->flags
& TCG_OPF_VECTOR
) {
4943 tcg_out_vec_op(s
, op
->opc
, TCGOP_VECL(op
), TCGOP_VECE(op
),
4944 new_args
, const_args
);
4946 tcg_out_op(s
, op
->opc
, new_args
, const_args
);
4951 /* move the outputs in the correct register if needed */
4952 for(i
= 0; i
< nb_oargs
; i
++) {
4953 ts
= arg_temp(op
->args
[i
]);
4955 /* ENV should not be modified. */
4956 tcg_debug_assert(!temp_readonly(ts
));
4958 if (NEED_SYNC_ARG(i
)) {
4959 temp_sync(s
, ts
, o_allocated_regs
, 0, IS_DEAD_ARG(i
));
4960 } else if (IS_DEAD_ARG(i
)) {
4966 static bool tcg_reg_alloc_dup2(TCGContext
*s
, const TCGOp
*op
)
4968 const TCGLifeData arg_life
= op
->life
;
4969 TCGTemp
*ots
, *itsl
, *itsh
;
4970 TCGType vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4972 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
4973 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
4974 tcg_debug_assert(TCGOP_VECE(op
) == MO_64
);
4976 ots
= arg_temp(op
->args
[0]);
4977 itsl
= arg_temp(op
->args
[1]);
4978 itsh
= arg_temp(op
->args
[2]);
4980 /* ENV should not be modified. */
4981 tcg_debug_assert(!temp_readonly(ots
));
4983 /* Allocate the output register now. */
4984 if (ots
->val_type
!= TEMP_VAL_REG
) {
4985 TCGRegSet allocated_regs
= s
->reserved_regs
;
4986 TCGRegSet dup_out_regs
=
4987 tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4990 /* Make sure to not spill the input registers. */
4991 if (!IS_DEAD_ARG(1) && itsl
->val_type
== TEMP_VAL_REG
) {
4992 tcg_regset_set_reg(allocated_regs
, itsl
->reg
);
4994 if (!IS_DEAD_ARG(2) && itsh
->val_type
== TEMP_VAL_REG
) {
4995 tcg_regset_set_reg(allocated_regs
, itsh
->reg
);
4998 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4999 output_pref(op
, 0), ots
->indirect_base
);
5000 set_temp_val_reg(s
, ots
, oreg
);
5003 /* Promote dup2 of immediates to dupi_vec. */
5004 if (itsl
->val_type
== TEMP_VAL_CONST
&& itsh
->val_type
== TEMP_VAL_CONST
) {
5005 uint64_t val
= deposit64(itsl
->val
, 32, 32, itsh
->val
);
5008 if (val
== dup_const(MO_8
, val
)) {
5010 } else if (val
== dup_const(MO_16
, val
)) {
5012 } else if (val
== dup_const(MO_32
, val
)) {
5016 tcg_out_dupi_vec(s
, vtype
, vece
, ots
->reg
, val
);
5020 /* If the two inputs form one 64-bit value, try dupm_vec. */
5021 if (itsl
->temp_subindex
== HOST_BIG_ENDIAN
&&
5022 itsh
->temp_subindex
== !HOST_BIG_ENDIAN
&&
5023 itsl
== itsh
+ (HOST_BIG_ENDIAN
? 1 : -1)) {
5024 TCGTemp
*its
= itsl
- HOST_BIG_ENDIAN
;
5026 temp_sync(s
, its
+ 0, s
->reserved_regs
, 0, 0);
5027 temp_sync(s
, its
+ 1, s
->reserved_regs
, 0, 0);
5029 if (tcg_out_dupm_vec(s
, vtype
, MO_64
, ots
->reg
,
5030 its
->mem_base
->reg
, its
->mem_offset
)) {
5035 /* Fall back to generic expansion. */
5039 ots
->mem_coherent
= 0;
5040 if (IS_DEAD_ARG(1)) {
5043 if (IS_DEAD_ARG(2)) {
5046 if (NEED_SYNC_ARG(0)) {
5047 temp_sync(s
, ots
, s
->reserved_regs
, 0, IS_DEAD_ARG(0));
5048 } else if (IS_DEAD_ARG(0)) {
5054 static void load_arg_reg(TCGContext
*s
, TCGReg reg
, TCGTemp
*ts
,
5055 TCGRegSet allocated_regs
)
5057 if (ts
->val_type
== TEMP_VAL_REG
) {
5058 if (ts
->reg
!= reg
) {
5059 tcg_reg_free(s
, reg
, allocated_regs
);
5060 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
5062 * Cross register class move not supported. Sync the
5063 * temp back to its slot and load from there.
5065 temp_sync(s
, ts
, allocated_regs
, 0, 0);
5066 tcg_out_ld(s
, ts
->type
, reg
,
5067 ts
->mem_base
->reg
, ts
->mem_offset
);
5071 TCGRegSet arg_set
= 0;
5073 tcg_reg_free(s
, reg
, allocated_regs
);
5074 tcg_regset_set_reg(arg_set
, reg
);
5075 temp_load(s
, ts
, arg_set
, allocated_regs
, 0);
5079 static void load_arg_stk(TCGContext
*s
, unsigned arg_slot
, TCGTemp
*ts
,
5080 TCGRegSet allocated_regs
)
5083 * When the destination is on the stack, load up the temp and store.
5084 * If there are many call-saved registers, the temp might live to
5085 * see another use; otherwise it'll be discarded.
5087 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
], allocated_regs
, 0);
5088 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
,
5089 arg_slot_stk_ofs(arg_slot
));
5092 static void load_arg_normal(TCGContext
*s
, const TCGCallArgumentLoc
*l
,
5093 TCGTemp
*ts
, TCGRegSet
*allocated_regs
)
5095 if (arg_slot_reg_p(l
->arg_slot
)) {
5096 TCGReg reg
= tcg_target_call_iarg_regs
[l
->arg_slot
];
5097 load_arg_reg(s
, reg
, ts
, *allocated_regs
);
5098 tcg_regset_set_reg(*allocated_regs
, reg
);
5100 load_arg_stk(s
, l
->arg_slot
, ts
, *allocated_regs
);
5104 static void load_arg_ref(TCGContext
*s
, unsigned arg_slot
, TCGReg ref_base
,
5105 intptr_t ref_off
, TCGRegSet
*allocated_regs
)
5109 if (arg_slot_reg_p(arg_slot
)) {
5110 reg
= tcg_target_call_iarg_regs
[arg_slot
];
5111 tcg_reg_free(s
, reg
, *allocated_regs
);
5112 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
5113 tcg_regset_set_reg(*allocated_regs
, reg
);
5115 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[TCG_TYPE_PTR
],
5116 *allocated_regs
, 0, false);
5117 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
5118 tcg_out_st(s
, TCG_TYPE_PTR
, reg
, TCG_REG_CALL_STACK
,
5119 arg_slot_stk_ofs(arg_slot
));
5123 static void tcg_reg_alloc_call(TCGContext
*s
, TCGOp
*op
)
5125 const int nb_oargs
= TCGOP_CALLO(op
);
5126 const int nb_iargs
= TCGOP_CALLI(op
);
5127 const TCGLifeData arg_life
= op
->life
;
5128 const TCGHelperInfo
*info
= tcg_call_info(op
);
5129 TCGRegSet allocated_regs
= s
->reserved_regs
;
5133 * Move inputs into place in reverse order,
5134 * so that we place stacked arguments first.
5136 for (i
= nb_iargs
- 1; i
>= 0; --i
) {
5137 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
5138 TCGTemp
*ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
5140 switch (loc
->kind
) {
5141 case TCG_CALL_ARG_NORMAL
:
5142 case TCG_CALL_ARG_EXTEND_U
:
5143 case TCG_CALL_ARG_EXTEND_S
:
5144 load_arg_normal(s
, loc
, ts
, &allocated_regs
);
5146 case TCG_CALL_ARG_BY_REF
:
5147 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
5148 load_arg_ref(s
, loc
->arg_slot
, TCG_REG_CALL_STACK
,
5149 arg_slot_stk_ofs(loc
->ref_slot
),
5152 case TCG_CALL_ARG_BY_REF_N
:
5153 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
5156 g_assert_not_reached();
5160 /* Mark dead temporaries and free the associated registers. */
5161 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
5162 if (IS_DEAD_ARG(i
)) {
5163 temp_dead(s
, arg_temp(op
->args
[i
]));
5167 /* Clobber call registers. */
5168 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
5169 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
5170 tcg_reg_free(s
, i
, allocated_regs
);
5175 * Save globals if they might be written by the helper,
5176 * sync them if they might be read.
5178 if (info
->flags
& TCG_CALL_NO_READ_GLOBALS
) {
5180 } else if (info
->flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
5181 sync_globals(s
, allocated_regs
);
5183 save_globals(s
, allocated_regs
);
5187 * If the ABI passes a pointer to the returned struct as the first
5188 * argument, load that now. Pass a pointer to the output home slot.
5190 if (info
->out_kind
== TCG_CALL_RET_BY_REF
) {
5191 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5193 if (!ts
->mem_allocated
) {
5194 temp_allocate_frame(s
, ts
);
5196 load_arg_ref(s
, 0, ts
->mem_base
->reg
, ts
->mem_offset
, &allocated_regs
);
5199 tcg_out_call(s
, tcg_call_func(op
), info
);
5201 /* Assign output registers and emit moves if needed. */
5202 switch (info
->out_kind
) {
5203 case TCG_CALL_RET_NORMAL
:
5204 for (i
= 0; i
< nb_oargs
; i
++) {
5205 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5206 TCGReg reg
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, i
);
5208 /* ENV should not be modified. */
5209 tcg_debug_assert(!temp_readonly(ts
));
5211 set_temp_val_reg(s
, ts
, reg
);
5212 ts
->mem_coherent
= 0;
5216 case TCG_CALL_RET_BY_VEC
:
5218 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5220 tcg_debug_assert(ts
->base_type
== TCG_TYPE_I128
);
5221 tcg_debug_assert(ts
->temp_subindex
== 0);
5222 if (!ts
->mem_allocated
) {
5223 temp_allocate_frame(s
, ts
);
5225 tcg_out_st(s
, TCG_TYPE_V128
,
5226 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
5227 ts
->mem_base
->reg
, ts
->mem_offset
);
5229 /* fall through to mark all parts in memory */
5231 case TCG_CALL_RET_BY_REF
:
5232 /* The callee has performed a write through the reference. */
5233 for (i
= 0; i
< nb_oargs
; i
++) {
5234 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5235 ts
->val_type
= TEMP_VAL_MEM
;
5240 g_assert_not_reached();
5243 /* Flush or discard output registers as needed. */
5244 for (i
= 0; i
< nb_oargs
; i
++) {
5245 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5246 if (NEED_SYNC_ARG(i
)) {
5247 temp_sync(s
, ts
, s
->reserved_regs
, 0, IS_DEAD_ARG(i
));
5248 } else if (IS_DEAD_ARG(i
)) {
5255 * atom_and_align_for_opc:
5257 * @opc: memory operation code
5258 * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations
5259 * @allow_two_ops: true if we are prepared to issue two operations
5261 * Return the alignment and atomicity to use for the inline fast path
5262 * for the given memory operation. The alignment may be larger than
5263 * that specified in @opc, and the correct alignment will be diagnosed
5264 * by the slow path helper.
5266 * If @allow_two_ops, the host is prepared to test for 2x alignment,
5267 * and issue two loads or stores for subalignment.
5269 static TCGAtomAlign
atom_and_align_for_opc(TCGContext
*s
, MemOp opc
,
5270 MemOp host_atom
, bool allow_two_ops
)
5272 MemOp align
= get_alignment_bits(opc
);
5273 MemOp size
= opc
& MO_SIZE
;
5274 MemOp half
= size
? size
- 1 : 0;
5278 /* When serialized, no further atomicity required. */
5279 if (s
->gen_tb
->cflags
& CF_PARALLEL
) {
5280 atom
= opc
& MO_ATOM_MASK
;
5282 atom
= MO_ATOM_NONE
;
5287 /* The operation requires no specific atomicity. */
5291 case MO_ATOM_IFALIGN
:
5295 case MO_ATOM_IFALIGN_PAIR
:
5299 case MO_ATOM_WITHIN16
:
5301 if (size
== MO_128
) {
5302 /* Misalignment implies !within16, and therefore no atomicity. */
5303 } else if (host_atom
!= MO_ATOM_WITHIN16
) {
5304 /* The host does not implement within16, so require alignment. */
5305 align
= MAX(align
, size
);
5309 case MO_ATOM_WITHIN16_PAIR
:
5312 * Misalignment implies !within16, and therefore half atomicity.
5313 * Any host prepared for two operations can implement this with
5316 if (host_atom
!= MO_ATOM_WITHIN16
&& allow_two_ops
) {
5317 align
= MAX(align
, half
);
5321 case MO_ATOM_SUBALIGN
:
5323 if (host_atom
!= MO_ATOM_SUBALIGN
) {
5324 /* If unaligned but not odd, there are subobjects up to half. */
5325 if (allow_two_ops
) {
5326 align
= MAX(align
, half
);
5328 align
= MAX(align
, size
);
5334 g_assert_not_reached();
5337 return (TCGAtomAlign
){ .atom
= atmax
, .align
= align
};
5341 * Similarly for qemu_ld/st slow path helpers.
5342 * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously,
5343 * using only the provided backend tcg_out_* functions.
5346 static int tcg_out_helper_stk_ofs(TCGType type
, unsigned slot
)
5348 int ofs
= arg_slot_stk_ofs(slot
);
5351 * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not
5352 * require extension to uint64_t, adjust the address for uint32_t.
5354 if (HOST_BIG_ENDIAN
&&
5355 TCG_TARGET_REG_BITS
== 64 &&
5356 type
== TCG_TYPE_I32
) {
5362 static void tcg_out_helper_load_slots(TCGContext
*s
,
5363 unsigned nmov
, TCGMovExtend
*mov
,
5364 const TCGLdstHelperParam
*parm
)
5370 * Start from the end, storing to the stack first.
5371 * This frees those registers, so we need not consider overlap.
5373 for (i
= nmov
; i
-- > 0; ) {
5374 unsigned slot
= mov
[i
].dst
;
5376 if (arg_slot_reg_p(slot
)) {
5380 TCGReg src
= mov
[i
].src
;
5381 TCGType dst_type
= mov
[i
].dst_type
;
5382 MemOp dst_mo
= dst_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5384 /* The argument is going onto the stack; extend into scratch. */
5385 if ((mov
[i
].src_ext
& MO_SIZE
) != dst_mo
) {
5386 tcg_debug_assert(parm
->ntmp
!= 0);
5387 mov
[i
].dst
= src
= parm
->tmp
[0];
5388 tcg_out_movext1(s
, &mov
[i
]);
5391 tcg_out_st(s
, dst_type
, src
, TCG_REG_CALL_STACK
,
5392 tcg_out_helper_stk_ofs(dst_type
, slot
));
5398 * The remaining arguments are in registers.
5399 * Convert slot numbers to argument registers.
5402 for (i
= 0; i
< nmov
; ++i
) {
5403 mov
[i
].dst
= tcg_target_call_iarg_regs
[mov
[i
].dst
];
5408 /* The backend must have provided enough temps for the worst case. */
5409 tcg_debug_assert(parm
->ntmp
>= 2);
5412 for (unsigned j
= 0; j
< 3; ++j
) {
5413 if (dst3
== mov
[j
].src
) {
5415 * Conflict. Copy the source to a temporary, perform the
5416 * remaining moves, then the extension from our scratch
5419 TCGReg scratch
= parm
->tmp
[1];
5421 tcg_out_mov(s
, mov
[3].src_type
, scratch
, mov
[3].src
);
5422 tcg_out_movext3(s
, mov
, mov
+ 1, mov
+ 2, parm
->tmp
[0]);
5423 tcg_out_movext1_new_src(s
, &mov
[3], scratch
);
5428 /* No conflicts: perform this move and continue. */
5429 tcg_out_movext1(s
, &mov
[3]);
5433 tcg_out_movext3(s
, mov
, mov
+ 1, mov
+ 2,
5434 parm
->ntmp
? parm
->tmp
[0] : -1);
5437 tcg_out_movext2(s
, mov
, mov
+ 1,
5438 parm
->ntmp
? parm
->tmp
[0] : -1);
5441 tcg_out_movext1(s
, mov
);
5444 g_assert_not_reached();
5448 static void tcg_out_helper_load_imm(TCGContext
*s
, unsigned slot
,
5449 TCGType type
, tcg_target_long imm
,
5450 const TCGLdstHelperParam
*parm
)
5452 if (arg_slot_reg_p(slot
)) {
5453 tcg_out_movi(s
, type
, tcg_target_call_iarg_regs
[slot
], imm
);
5455 int ofs
= tcg_out_helper_stk_ofs(type
, slot
);
5456 if (!tcg_out_sti(s
, type
, imm
, TCG_REG_CALL_STACK
, ofs
)) {
5457 tcg_debug_assert(parm
->ntmp
!= 0);
5458 tcg_out_movi(s
, type
, parm
->tmp
[0], imm
);
5459 tcg_out_st(s
, type
, parm
->tmp
[0], TCG_REG_CALL_STACK
, ofs
);
5464 static void tcg_out_helper_load_common_args(TCGContext
*s
,
5465 const TCGLabelQemuLdst
*ldst
,
5466 const TCGLdstHelperParam
*parm
,
5467 const TCGHelperInfo
*info
,
5470 TCGMovExtend ptr_mov
= {
5471 .dst_type
= TCG_TYPE_PTR
,
5472 .src_type
= TCG_TYPE_PTR
,
5473 .src_ext
= sizeof(void *) == 4 ? MO_32
: MO_64
5475 const TCGCallArgumentLoc
*loc
= &info
->in
[0];
5478 tcg_target_ulong imm
;
5481 * Handle env, which is always first.
5483 ptr_mov
.dst
= loc
->arg_slot
;
5484 ptr_mov
.src
= TCG_AREG0
;
5485 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5491 loc
= &info
->in
[next_arg
];
5492 type
= TCG_TYPE_I32
;
5493 switch (loc
->kind
) {
5494 case TCG_CALL_ARG_NORMAL
:
5496 case TCG_CALL_ARG_EXTEND_U
:
5497 case TCG_CALL_ARG_EXTEND_S
:
5498 /* No extension required for MemOpIdx. */
5499 tcg_debug_assert(imm
<= INT32_MAX
);
5500 type
= TCG_TYPE_REG
;
5503 g_assert_not_reached();
5505 tcg_out_helper_load_imm(s
, loc
->arg_slot
, type
, imm
, parm
);
5511 loc
= &info
->in
[next_arg
];
5512 slot
= loc
->arg_slot
;
5517 if (arg_slot_reg_p(slot
)) {
5518 arg_reg
= tcg_target_call_iarg_regs
[slot
];
5520 ra_reg
= parm
->ra_gen(s
, ldst
, arg_reg
);
5523 ptr_mov
.src
= ra_reg
;
5524 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5526 imm
= (uintptr_t)ldst
->raddr
;
5527 tcg_out_helper_load_imm(s
, slot
, TCG_TYPE_PTR
, imm
, parm
);
5531 static unsigned tcg_out_helper_add_mov(TCGMovExtend
*mov
,
5532 const TCGCallArgumentLoc
*loc
,
5533 TCGType dst_type
, TCGType src_type
,
5534 TCGReg lo
, TCGReg hi
)
5538 if (dst_type
<= TCG_TYPE_REG
) {
5541 switch (loc
->kind
) {
5542 case TCG_CALL_ARG_NORMAL
:
5543 src_ext
= src_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5545 case TCG_CALL_ARG_EXTEND_U
:
5546 dst_type
= TCG_TYPE_REG
;
5549 case TCG_CALL_ARG_EXTEND_S
:
5550 dst_type
= TCG_TYPE_REG
;
5554 g_assert_not_reached();
5557 mov
[0].dst
= loc
->arg_slot
;
5558 mov
[0].dst_type
= dst_type
;
5560 mov
[0].src_type
= src_type
;
5561 mov
[0].src_ext
= src_ext
;
5565 if (TCG_TARGET_REG_BITS
== 32) {
5566 assert(dst_type
== TCG_TYPE_I64
);
5569 assert(dst_type
== TCG_TYPE_I128
);
5573 mov
[0].dst
= loc
[HOST_BIG_ENDIAN
].arg_slot
;
5575 mov
[0].dst_type
= TCG_TYPE_REG
;
5576 mov
[0].src_type
= TCG_TYPE_REG
;
5577 mov
[0].src_ext
= reg_mo
;
5579 mov
[1].dst
= loc
[!HOST_BIG_ENDIAN
].arg_slot
;
5581 mov
[1].dst_type
= TCG_TYPE_REG
;
5582 mov
[1].src_type
= TCG_TYPE_REG
;
5583 mov
[1].src_ext
= reg_mo
;
5588 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5589 const TCGLdstHelperParam
*parm
)
5591 const TCGHelperInfo
*info
;
5592 const TCGCallArgumentLoc
*loc
;
5593 TCGMovExtend mov
[2];
5594 unsigned next_arg
, nmov
;
5595 MemOp mop
= get_memop(ldst
->oi
);
5597 switch (mop
& MO_SIZE
) {
5601 info
= &info_helper_ld32_mmu
;
5604 info
= &info_helper_ld64_mmu
;
5607 info
= &info_helper_ld128_mmu
;
5610 g_assert_not_reached();
5613 /* Defer env argument. */
5616 loc
= &info
->in
[next_arg
];
5617 if (TCG_TARGET_REG_BITS
== 32 && s
->addr_type
== TCG_TYPE_I32
) {
5619 * 32-bit host with 32-bit guest: zero-extend the guest address
5620 * to 64-bits for the helper by storing the low part, then
5621 * load a zero for the high part.
5623 tcg_out_helper_add_mov(mov
, loc
+ HOST_BIG_ENDIAN
,
5624 TCG_TYPE_I32
, TCG_TYPE_I32
,
5625 ldst
->addrlo_reg
, -1);
5626 tcg_out_helper_load_slots(s
, 1, mov
, parm
);
5628 tcg_out_helper_load_imm(s
, loc
[!HOST_BIG_ENDIAN
].arg_slot
,
5629 TCG_TYPE_I32
, 0, parm
);
5632 nmov
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_I64
, s
->addr_type
,
5633 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5634 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5638 switch (info
->out_kind
) {
5639 case TCG_CALL_RET_NORMAL
:
5640 case TCG_CALL_RET_BY_VEC
:
5642 case TCG_CALL_RET_BY_REF
:
5644 * The return reference is in the first argument slot.
5645 * We need memory in which to return: re-use the top of stack.
5648 int ofs_slot0
= TCG_TARGET_CALL_STACK_OFFSET
;
5650 if (arg_slot_reg_p(0)) {
5651 tcg_out_addi_ptr(s
, tcg_target_call_iarg_regs
[0],
5652 TCG_REG_CALL_STACK
, ofs_slot0
);
5654 tcg_debug_assert(parm
->ntmp
!= 0);
5655 tcg_out_addi_ptr(s
, parm
->tmp
[0],
5656 TCG_REG_CALL_STACK
, ofs_slot0
);
5657 tcg_out_st(s
, TCG_TYPE_PTR
, parm
->tmp
[0],
5658 TCG_REG_CALL_STACK
, ofs_slot0
);
5663 g_assert_not_reached();
5666 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5669 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5671 const TCGLdstHelperParam
*parm
)
5673 MemOp mop
= get_memop(ldst
->oi
);
5674 TCGMovExtend mov
[2];
5677 switch (ldst
->type
) {
5679 if (TCG_TARGET_REG_BITS
== 32) {
5685 mov
[0].dst
= ldst
->datalo_reg
;
5686 mov
[0].src
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, 0);
5687 mov
[0].dst_type
= ldst
->type
;
5688 mov
[0].src_type
= TCG_TYPE_REG
;
5691 * If load_sign, then we allowed the helper to perform the
5692 * appropriate sign extension to tcg_target_ulong, and all
5693 * we need now is a plain move.
5695 * If they do not, then we expect the relevant extension
5696 * instruction to be no more expensive than a move, and
5697 * we thus save the icache etc by only using one of two
5700 if (load_sign
|| !(mop
& MO_SIGN
)) {
5701 if (TCG_TARGET_REG_BITS
== 32 || ldst
->type
== TCG_TYPE_I32
) {
5702 mov
[0].src_ext
= MO_32
;
5704 mov
[0].src_ext
= MO_64
;
5707 mov
[0].src_ext
= mop
& MO_SSIZE
;
5709 tcg_out_movext1(s
, mov
);
5713 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
5714 ofs_slot0
= TCG_TARGET_CALL_STACK_OFFSET
;
5715 switch (TCG_TARGET_CALL_RET_I128
) {
5716 case TCG_CALL_RET_NORMAL
:
5718 case TCG_CALL_RET_BY_VEC
:
5719 tcg_out_st(s
, TCG_TYPE_V128
,
5720 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
5721 TCG_REG_CALL_STACK
, ofs_slot0
);
5723 case TCG_CALL_RET_BY_REF
:
5724 tcg_out_ld(s
, TCG_TYPE_I64
, ldst
->datalo_reg
,
5725 TCG_REG_CALL_STACK
, ofs_slot0
+ 8 * HOST_BIG_ENDIAN
);
5726 tcg_out_ld(s
, TCG_TYPE_I64
, ldst
->datahi_reg
,
5727 TCG_REG_CALL_STACK
, ofs_slot0
+ 8 * !HOST_BIG_ENDIAN
);
5730 g_assert_not_reached();
5735 g_assert_not_reached();
5738 mov
[0].dst
= ldst
->datalo_reg
;
5740 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, HOST_BIG_ENDIAN
);
5741 mov
[0].dst_type
= TCG_TYPE_REG
;
5742 mov
[0].src_type
= TCG_TYPE_REG
;
5743 mov
[0].src_ext
= TCG_TARGET_REG_BITS
== 32 ? MO_32
: MO_64
;
5745 mov
[1].dst
= ldst
->datahi_reg
;
5747 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, !HOST_BIG_ENDIAN
);
5748 mov
[1].dst_type
= TCG_TYPE_REG
;
5749 mov
[1].src_type
= TCG_TYPE_REG
;
5750 mov
[1].src_ext
= TCG_TARGET_REG_BITS
== 32 ? MO_32
: MO_64
;
5752 tcg_out_movext2(s
, mov
, mov
+ 1, parm
->ntmp
? parm
->tmp
[0] : -1);
5755 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5756 const TCGLdstHelperParam
*parm
)
5758 const TCGHelperInfo
*info
;
5759 const TCGCallArgumentLoc
*loc
;
5760 TCGMovExtend mov
[4];
5762 unsigned next_arg
, nmov
, n
;
5763 MemOp mop
= get_memop(ldst
->oi
);
5765 switch (mop
& MO_SIZE
) {
5769 info
= &info_helper_st32_mmu
;
5770 data_type
= TCG_TYPE_I32
;
5773 info
= &info_helper_st64_mmu
;
5774 data_type
= TCG_TYPE_I64
;
5777 info
= &info_helper_st128_mmu
;
5778 data_type
= TCG_TYPE_I128
;
5781 g_assert_not_reached();
5784 /* Defer env argument. */
5788 /* Handle addr argument. */
5789 loc
= &info
->in
[next_arg
];
5790 if (TCG_TARGET_REG_BITS
== 32 && s
->addr_type
== TCG_TYPE_I32
) {
5792 * 32-bit host with 32-bit guest: zero-extend the guest address
5793 * to 64-bits for the helper by storing the low part. Later,
5794 * after we have processed the register inputs, we will load a
5795 * zero for the high part.
5797 tcg_out_helper_add_mov(mov
, loc
+ HOST_BIG_ENDIAN
,
5798 TCG_TYPE_I32
, TCG_TYPE_I32
,
5799 ldst
->addrlo_reg
, -1);
5803 n
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_I64
, s
->addr_type
,
5804 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5809 /* Handle data argument. */
5810 loc
= &info
->in
[next_arg
];
5811 switch (loc
->kind
) {
5812 case TCG_CALL_ARG_NORMAL
:
5813 case TCG_CALL_ARG_EXTEND_U
:
5814 case TCG_CALL_ARG_EXTEND_S
:
5815 n
= tcg_out_helper_add_mov(mov
+ nmov
, loc
, data_type
, ldst
->type
,
5816 ldst
->datalo_reg
, ldst
->datahi_reg
);
5819 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5822 case TCG_CALL_ARG_BY_REF
:
5823 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
5824 tcg_debug_assert(data_type
== TCG_TYPE_I128
);
5825 tcg_out_st(s
, TCG_TYPE_I64
,
5826 HOST_BIG_ENDIAN
? ldst
->datahi_reg
: ldst
->datalo_reg
,
5827 TCG_REG_CALL_STACK
, arg_slot_stk_ofs(loc
[0].ref_slot
));
5828 tcg_out_st(s
, TCG_TYPE_I64
,
5829 HOST_BIG_ENDIAN
? ldst
->datalo_reg
: ldst
->datahi_reg
,
5830 TCG_REG_CALL_STACK
, arg_slot_stk_ofs(loc
[1].ref_slot
));
5832 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5834 if (arg_slot_reg_p(loc
->arg_slot
)) {
5835 tcg_out_addi_ptr(s
, tcg_target_call_iarg_regs
[loc
->arg_slot
],
5837 arg_slot_stk_ofs(loc
->ref_slot
));
5839 tcg_debug_assert(parm
->ntmp
!= 0);
5840 tcg_out_addi_ptr(s
, parm
->tmp
[0], TCG_REG_CALL_STACK
,
5841 arg_slot_stk_ofs(loc
->ref_slot
));
5842 tcg_out_st(s
, TCG_TYPE_PTR
, parm
->tmp
[0],
5843 TCG_REG_CALL_STACK
, arg_slot_stk_ofs(loc
->arg_slot
));
5849 g_assert_not_reached();
5852 if (TCG_TARGET_REG_BITS
== 32 && s
->addr_type
== TCG_TYPE_I32
) {
5853 /* Zero extend the address by loading a zero for the high part. */
5854 loc
= &info
->in
[1 + !HOST_BIG_ENDIAN
];
5855 tcg_out_helper_load_imm(s
, loc
->arg_slot
, TCG_TYPE_I32
, 0, parm
);
5858 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5861 #ifdef CONFIG_PROFILER
5863 /* avoid copy/paste errors */
5864 #define PROF_ADD(to, from, field) \
5866 (to)->field += qatomic_read(&((from)->field)); \
5869 #define PROF_MAX(to, from, field) \
5871 typeof((from)->field) val__ = qatomic_read(&((from)->field)); \
5872 if (val__ > (to)->field) { \
5873 (to)->field = val__; \
5877 /* Pass in a zero'ed @prof */
5879 void tcg_profile_snapshot(TCGProfile
*prof
, bool counters
, bool table
)
5881 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
5884 for (i
= 0; i
< n_ctxs
; i
++) {
5885 TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
5886 const TCGProfile
*orig
= &s
->prof
;
5889 PROF_ADD(prof
, orig
, cpu_exec_time
);
5890 PROF_ADD(prof
, orig
, tb_count1
);
5891 PROF_ADD(prof
, orig
, tb_count
);
5892 PROF_ADD(prof
, orig
, op_count
);
5893 PROF_MAX(prof
, orig
, op_count_max
);
5894 PROF_ADD(prof
, orig
, temp_count
);
5895 PROF_MAX(prof
, orig
, temp_count_max
);
5896 PROF_ADD(prof
, orig
, del_op_count
);
5897 PROF_ADD(prof
, orig
, code_in_len
);
5898 PROF_ADD(prof
, orig
, code_out_len
);
5899 PROF_ADD(prof
, orig
, search_out_len
);
5900 PROF_ADD(prof
, orig
, interm_time
);
5901 PROF_ADD(prof
, orig
, code_time
);
5902 PROF_ADD(prof
, orig
, la_time
);
5903 PROF_ADD(prof
, orig
, opt_time
);
5904 PROF_ADD(prof
, orig
, restore_count
);
5905 PROF_ADD(prof
, orig
, restore_time
);
5910 for (i
= 0; i
< NB_OPS
; i
++) {
5911 PROF_ADD(prof
, orig
, table_op_count
[i
]);
5920 static void tcg_profile_snapshot_counters(TCGProfile
*prof
)
5922 tcg_profile_snapshot(prof
, true, false);
5925 static void tcg_profile_snapshot_table(TCGProfile
*prof
)
5927 tcg_profile_snapshot(prof
, false, true);
5930 void tcg_dump_op_count(GString
*buf
)
5932 TCGProfile prof
= {};
5935 tcg_profile_snapshot_table(&prof
);
5936 for (i
= 0; i
< NB_OPS
; i
++) {
5937 g_string_append_printf(buf
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
5938 prof
.table_op_count
[i
]);
5942 int64_t tcg_cpu_exec_time(void)
5944 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
5948 for (i
= 0; i
< n_ctxs
; i
++) {
5949 const TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
5950 const TCGProfile
*prof
= &s
->prof
;
5952 ret
+= qatomic_read(&prof
->cpu_exec_time
);
5957 void tcg_dump_op_count(GString
*buf
)
5959 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
5962 int64_t tcg_cpu_exec_time(void)
5964 error_report("%s: TCG profiler not compiled", __func__
);
5970 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
, uint64_t pc_start
)
5972 #ifdef CONFIG_PROFILER
5973 TCGProfile
*prof
= &s
->prof
;
5978 #ifdef CONFIG_PROFILER
5982 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
5985 qatomic_set(&prof
->op_count
, prof
->op_count
+ n
);
5986 if (n
> prof
->op_count_max
) {
5987 qatomic_set(&prof
->op_count_max
, n
);
5991 qatomic_set(&prof
->temp_count
, prof
->temp_count
+ n
);
5992 if (n
> prof
->temp_count_max
) {
5993 qatomic_set(&prof
->temp_count_max
, n
);
5998 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)
5999 && qemu_log_in_addr_range(pc_start
))) {
6000 FILE *logfile
= qemu_log_trylock();
6002 fprintf(logfile
, "OP:\n");
6003 tcg_dump_ops(s
, logfile
, false);
6004 fprintf(logfile
, "\n");
6005 qemu_log_unlock(logfile
);
6009 #ifdef CONFIG_DEBUG_TCG
6010 /* Ensure all labels referenced have been emitted. */
6015 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
6016 if (unlikely(!l
->present
) && !QSIMPLEQ_EMPTY(&l
->branches
)) {
6017 qemu_log_mask(CPU_LOG_TB_OP
,
6018 "$L%d referenced but not present.\n", l
->id
);
6026 #ifdef CONFIG_PROFILER
6027 qatomic_set(&prof
->opt_time
, prof
->opt_time
- profile_getclock());
6032 #ifdef CONFIG_PROFILER
6033 qatomic_set(&prof
->opt_time
, prof
->opt_time
+ profile_getclock());
6034 qatomic_set(&prof
->la_time
, prof
->la_time
- profile_getclock());
6037 reachable_code_pass(s
);
6041 if (s
->nb_indirects
> 0) {
6042 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND
)
6043 && qemu_log_in_addr_range(pc_start
))) {
6044 FILE *logfile
= qemu_log_trylock();
6046 fprintf(logfile
, "OP before indirect lowering:\n");
6047 tcg_dump_ops(s
, logfile
, false);
6048 fprintf(logfile
, "\n");
6049 qemu_log_unlock(logfile
);
6053 /* Replace indirect temps with direct temps. */
6054 if (liveness_pass_2(s
)) {
6055 /* If changes were made, re-run liveness. */
6060 #ifdef CONFIG_PROFILER
6061 qatomic_set(&prof
->la_time
, prof
->la_time
+ profile_getclock());
6064 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
)
6065 && qemu_log_in_addr_range(pc_start
))) {
6066 FILE *logfile
= qemu_log_trylock();
6068 fprintf(logfile
, "OP after optimization and liveness analysis:\n");
6069 tcg_dump_ops(s
, logfile
, true);
6070 fprintf(logfile
, "\n");
6071 qemu_log_unlock(logfile
);
6075 /* Initialize goto_tb jump offsets. */
6076 tb
->jmp_reset_offset
[0] = TB_JMP_OFFSET_INVALID
;
6077 tb
->jmp_reset_offset
[1] = TB_JMP_OFFSET_INVALID
;
6078 tb
->jmp_insn_offset
[0] = TB_JMP_OFFSET_INVALID
;
6079 tb
->jmp_insn_offset
[1] = TB_JMP_OFFSET_INVALID
;
6081 tcg_reg_alloc_start(s
);
6084 * Reset the buffer pointers when restarting after overflow.
6085 * TODO: Move this into translate-all.c with the rest of the
6086 * buffer management. Having only this done here is confusing.
6088 s
->code_buf
= tcg_splitwx_to_rw(tb
->tc
.ptr
);
6089 s
->code_ptr
= s
->code_buf
;
6091 #ifdef TCG_TARGET_NEED_LDST_LABELS
6092 QSIMPLEQ_INIT(&s
->ldst_labels
);
6094 #ifdef TCG_TARGET_NEED_POOL_LABELS
6095 s
->pool_labels
= NULL
;
6099 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
6100 TCGOpcode opc
= op
->opc
;
6102 #ifdef CONFIG_PROFILER
6103 qatomic_set(&prof
->table_op_count
[opc
], prof
->table_op_count
[opc
] + 1);
6107 case INDEX_op_mov_i32
:
6108 case INDEX_op_mov_i64
:
6109 case INDEX_op_mov_vec
:
6110 tcg_reg_alloc_mov(s
, op
);
6112 case INDEX_op_dup_vec
:
6113 tcg_reg_alloc_dup(s
, op
);
6115 case INDEX_op_insn_start
:
6116 if (num_insns
>= 0) {
6117 size_t off
= tcg_current_code_size(s
);
6118 s
->gen_insn_end_off
[num_insns
] = off
;
6119 /* Assert that we do not overflow our stored offset. */
6120 assert(s
->gen_insn_end_off
[num_insns
] == off
);
6123 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
6124 s
->gen_insn_data
[num_insns
][i
] =
6125 tcg_get_insn_start_param(op
, i
);
6128 case INDEX_op_discard
:
6129 temp_dead(s
, arg_temp(op
->args
[0]));
6131 case INDEX_op_set_label
:
6132 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
6133 tcg_out_label(s
, arg_label(op
->args
[0]));
6136 tcg_reg_alloc_call(s
, op
);
6138 case INDEX_op_exit_tb
:
6139 tcg_out_exit_tb(s
, op
->args
[0]);
6141 case INDEX_op_goto_tb
:
6142 tcg_out_goto_tb(s
, op
->args
[0]);
6144 case INDEX_op_dup2_vec
:
6145 if (tcg_reg_alloc_dup2(s
, op
)) {
6150 /* Sanity check that we've not introduced any unhandled opcodes. */
6151 tcg_debug_assert(tcg_op_supported(opc
));
6152 /* Note: in order to speed up the code, it would be much
6153 faster to have specialized register allocator functions for
6154 some common argument patterns */
6155 tcg_reg_alloc_op(s
, op
);
6158 /* Test for (pending) buffer overflow. The assumption is that any
6159 one operation beginning below the high water mark cannot overrun
6160 the buffer completely. Thus we can test for overflow after
6161 generating code without having to check during generation. */
6162 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
6165 /* Test for TB overflow, as seen by gen_insn_end_off. */
6166 if (unlikely(tcg_current_code_size(s
) > UINT16_MAX
)) {
6170 tcg_debug_assert(num_insns
>= 0);
6171 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
6173 /* Generate TB finalization at the end of block */
6174 #ifdef TCG_TARGET_NEED_LDST_LABELS
6175 i
= tcg_out_ldst_finalize(s
);
6180 #ifdef TCG_TARGET_NEED_POOL_LABELS
6181 i
= tcg_out_pool_finalize(s
);
6186 if (!tcg_resolve_relocs(s
)) {
6190 #ifndef CONFIG_TCG_INTERPRETER
6191 /* flush instruction cache */
6192 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
6193 (uintptr_t)s
->code_buf
,
6194 tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
));
6197 return tcg_current_code_size(s
);
6200 #ifdef CONFIG_PROFILER
6201 void tcg_dump_info(GString
*buf
)
6203 TCGProfile prof
= {};
6204 const TCGProfile
*s
;
6206 int64_t tb_div_count
;
6209 tcg_profile_snapshot_counters(&prof
);
6211 tb_count
= s
->tb_count
;
6212 tb_div_count
= tb_count
? tb_count
: 1;
6213 tot
= s
->interm_time
+ s
->code_time
;
6215 g_string_append_printf(buf
, "JIT cycles %" PRId64
6216 " (%0.3f s at 2.4 GHz)\n",
6218 g_string_append_printf(buf
, "translated TBs %" PRId64
6219 " (aborted=%" PRId64
" %0.1f%%)\n",
6220 tb_count
, s
->tb_count1
- tb_count
,
6221 (double)(s
->tb_count1
- s
->tb_count
)
6222 / (s
->tb_count1
? s
->tb_count1
: 1) * 100.0);
6223 g_string_append_printf(buf
, "avg ops/TB %0.1f max=%d\n",
6224 (double)s
->op_count
/ tb_div_count
, s
->op_count_max
);
6225 g_string_append_printf(buf
, "deleted ops/TB %0.2f\n",
6226 (double)s
->del_op_count
/ tb_div_count
);
6227 g_string_append_printf(buf
, "avg temps/TB %0.2f max=%d\n",
6228 (double)s
->temp_count
/ tb_div_count
,
6230 g_string_append_printf(buf
, "avg host code/TB %0.1f\n",
6231 (double)s
->code_out_len
/ tb_div_count
);
6232 g_string_append_printf(buf
, "avg search data/TB %0.1f\n",
6233 (double)s
->search_out_len
/ tb_div_count
);
6235 g_string_append_printf(buf
, "cycles/op %0.1f\n",
6236 s
->op_count
? (double)tot
/ s
->op_count
: 0);
6237 g_string_append_printf(buf
, "cycles/in byte %0.1f\n",
6238 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
6239 g_string_append_printf(buf
, "cycles/out byte %0.1f\n",
6240 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
6241 g_string_append_printf(buf
, "cycles/search byte %0.1f\n",
6243 (double)tot
/ s
->search_out_len
: 0);
6247 g_string_append_printf(buf
, " gen_interm time %0.1f%%\n",
6248 (double)s
->interm_time
/ tot
* 100.0);
6249 g_string_append_printf(buf
, " gen_code time %0.1f%%\n",
6250 (double)s
->code_time
/ tot
* 100.0);
6251 g_string_append_printf(buf
, "optim./code time %0.1f%%\n",
6252 (double)s
->opt_time
/ (s
->code_time
?
6255 g_string_append_printf(buf
, "liveness/code time %0.1f%%\n",
6256 (double)s
->la_time
/ (s
->code_time
?
6257 s
->code_time
: 1) * 100.0);
6258 g_string_append_printf(buf
, "cpu_restore count %" PRId64
"\n",
6260 g_string_append_printf(buf
, " avg cycles %0.1f\n",
6262 (double)s
->restore_time
/ s
->restore_count
: 0);
6265 void tcg_dump_info(GString
*buf
)
6267 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
6271 #ifdef ELF_HOST_MACHINE
6272 /* In order to use this feature, the backend needs to do three things:
6274 (1) Define ELF_HOST_MACHINE to indicate both what value to
6275 put into the ELF image and to indicate support for the feature.
6277 (2) Define tcg_register_jit. This should create a buffer containing
6278 the contents of a .debug_frame section that describes the post-
6279 prologue unwind info for the tcg machine.
6281 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
6284 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
6291 struct jit_code_entry
{
6292 struct jit_code_entry
*next_entry
;
6293 struct jit_code_entry
*prev_entry
;
6294 const void *symfile_addr
;
6295 uint64_t symfile_size
;
6298 struct jit_descriptor
{
6300 uint32_t action_flag
;
6301 struct jit_code_entry
*relevant_entry
;
6302 struct jit_code_entry
*first_entry
;
6305 void __jit_debug_register_code(void) __attribute__((noinline
));
6306 void __jit_debug_register_code(void)
6311 /* Must statically initialize the version, because GDB may check
6312 the version before we can set it. */
6313 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
6315 /* End GDB interface. */
6317 static int find_string(const char *strtab
, const char *str
)
6319 const char *p
= strtab
+ 1;
6322 if (strcmp(p
, str
) == 0) {
6329 static void tcg_register_jit_int(const void *buf_ptr
, size_t buf_size
,
6330 const void *debug_frame
,
6331 size_t debug_frame_size
)
6333 struct __attribute__((packed
)) DebugInfo
{
6340 uintptr_t cu_low_pc
;
6341 uintptr_t cu_high_pc
;
6344 uintptr_t fn_low_pc
;
6345 uintptr_t fn_high_pc
;
6354 struct DebugInfo di
;
6359 struct ElfImage
*img
;
6361 static const struct ElfImage img_template
= {
6363 .e_ident
[EI_MAG0
] = ELFMAG0
,
6364 .e_ident
[EI_MAG1
] = ELFMAG1
,
6365 .e_ident
[EI_MAG2
] = ELFMAG2
,
6366 .e_ident
[EI_MAG3
] = ELFMAG3
,
6367 .e_ident
[EI_CLASS
] = ELF_CLASS
,
6368 .e_ident
[EI_DATA
] = ELF_DATA
,
6369 .e_ident
[EI_VERSION
] = EV_CURRENT
,
6371 .e_machine
= ELF_HOST_MACHINE
,
6372 .e_version
= EV_CURRENT
,
6373 .e_phoff
= offsetof(struct ElfImage
, phdr
),
6374 .e_shoff
= offsetof(struct ElfImage
, shdr
),
6375 .e_ehsize
= sizeof(ElfW(Shdr
)),
6376 .e_phentsize
= sizeof(ElfW(Phdr
)),
6378 .e_shentsize
= sizeof(ElfW(Shdr
)),
6379 .e_shnum
= ARRAY_SIZE(img
->shdr
),
6380 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
6381 #ifdef ELF_HOST_FLAGS
6382 .e_flags
= ELF_HOST_FLAGS
,
6385 .e_ident
[EI_OSABI
] = ELF_OSABI
,
6393 [0] = { .sh_type
= SHT_NULL
},
6394 /* Trick: The contents of code_gen_buffer are not present in
6395 this fake ELF file; that got allocated elsewhere. Therefore
6396 we mark .text as SHT_NOBITS (similar to .bss) so that readers
6397 will not look for contents. We can record any address. */
6399 .sh_type
= SHT_NOBITS
,
6400 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
6402 [2] = { /* .debug_info */
6403 .sh_type
= SHT_PROGBITS
,
6404 .sh_offset
= offsetof(struct ElfImage
, di
),
6405 .sh_size
= sizeof(struct DebugInfo
),
6407 [3] = { /* .debug_abbrev */
6408 .sh_type
= SHT_PROGBITS
,
6409 .sh_offset
= offsetof(struct ElfImage
, da
),
6410 .sh_size
= sizeof(img
->da
),
6412 [4] = { /* .debug_frame */
6413 .sh_type
= SHT_PROGBITS
,
6414 .sh_offset
= sizeof(struct ElfImage
),
6416 [5] = { /* .symtab */
6417 .sh_type
= SHT_SYMTAB
,
6418 .sh_offset
= offsetof(struct ElfImage
, sym
),
6419 .sh_size
= sizeof(img
->sym
),
6421 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
6422 .sh_entsize
= sizeof(ElfW(Sym
)),
6424 [6] = { /* .strtab */
6425 .sh_type
= SHT_STRTAB
,
6426 .sh_offset
= offsetof(struct ElfImage
, str
),
6427 .sh_size
= sizeof(img
->str
),
6431 [1] = { /* code_gen_buffer */
6432 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
6437 .len
= sizeof(struct DebugInfo
) - 4,
6439 .ptr_size
= sizeof(void *),
6441 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
6443 .fn_name
= "code_gen_buffer"
6446 1, /* abbrev number (the cu) */
6447 0x11, 1, /* DW_TAG_compile_unit, has children */
6448 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
6449 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6450 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6451 0, 0, /* end of abbrev */
6452 2, /* abbrev number (the fn) */
6453 0x2e, 0, /* DW_TAG_subprogram, no children */
6454 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
6455 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6456 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6457 0, 0, /* end of abbrev */
6458 0 /* no more abbrev */
6460 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
6461 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
6464 /* We only need a single jit entry; statically allocate it. */
6465 static struct jit_code_entry one_entry
;
6467 uintptr_t buf
= (uintptr_t)buf_ptr
;
6468 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
6469 DebugFrameHeader
*dfh
;
6471 img
= g_malloc(img_size
);
6472 *img
= img_template
;
6474 img
->phdr
.p_vaddr
= buf
;
6475 img
->phdr
.p_paddr
= buf
;
6476 img
->phdr
.p_memsz
= buf_size
;
6478 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
6479 img
->shdr
[1].sh_addr
= buf
;
6480 img
->shdr
[1].sh_size
= buf_size
;
6482 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
6483 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
6485 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
6486 img
->shdr
[4].sh_size
= debug_frame_size
;
6488 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
6489 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
6491 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
6492 img
->sym
[1].st_value
= buf
;
6493 img
->sym
[1].st_size
= buf_size
;
6495 img
->di
.cu_low_pc
= buf
;
6496 img
->di
.cu_high_pc
= buf
+ buf_size
;
6497 img
->di
.fn_low_pc
= buf
;
6498 img
->di
.fn_high_pc
= buf
+ buf_size
;
6500 dfh
= (DebugFrameHeader
*)(img
+ 1);
6501 memcpy(dfh
, debug_frame
, debug_frame_size
);
6502 dfh
->fde
.func_start
= buf
;
6503 dfh
->fde
.func_len
= buf_size
;
6506 /* Enable this block to be able to debug the ELF image file creation.
6507 One can use readelf, objdump, or other inspection utilities. */
6509 g_autofree
char *jit
= g_strdup_printf("%s/qemu.jit", g_get_tmp_dir());
6510 FILE *f
= fopen(jit
, "w+b");
6512 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
6513 /* Avoid stupid unused return value warning for fwrite. */
6520 one_entry
.symfile_addr
= img
;
6521 one_entry
.symfile_size
= img_size
;
6523 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
6524 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
6525 __jit_debug_descriptor
.first_entry
= &one_entry
;
6526 __jit_debug_register_code();
6529 /* No support for the feature. Provide the entry point expected by exec.c,
6530 and implement the internal function we declared earlier. */
6532 static void tcg_register_jit_int(const void *buf
, size_t size
,
6533 const void *debug_frame
,
6534 size_t debug_frame_size
)
6538 void tcg_register_jit(const void *buf
, size_t buf_size
)
6541 #endif /* ELF_HOST_MACHINE */
6543 #if !TCG_TARGET_MAYBE_vec
6544 void tcg_expand_vec_op(TCGOpcode o
, TCGType t
, unsigned e
, TCGArg a0
, ...)
6546 g_assert_not_reached();