2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 /* Define to jump the ELF file used to communicate with GDB. */
30 #include "qemu/error-report.h"
31 #include "qemu/cutils.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/qemu-print.h"
34 #include "qemu/cacheflush.h"
35 #include "qemu/cacheinfo.h"
36 #include "qemu/timer.h"
37 #include "exec/translation-block.h"
38 #include "exec/tlb-common.h"
39 #include "tcg/startup.h"
40 #include "tcg/tcg-op-common.h"
42 #if UINTPTR_MAX == UINT32_MAX
43 # define ELF_CLASS ELFCLASS32
45 # define ELF_CLASS ELFCLASS64
48 # define ELF_DATA ELFDATA2MSB
50 # define ELF_DATA ELFDATA2LSB
55 #include "tcg/tcg-ldst.h"
56 #include "tcg/tcg-temp-internal.h"
57 #include "tcg-internal.h"
58 #include "accel/tcg/perf.h"
59 #ifdef CONFIG_USER_ONLY
60 #include "exec/user/guest-base.h"
63 /* Forward declarations for functions declared in tcg-target.c.inc and
65 static void tcg_target_init(TCGContext
*s
);
66 static void tcg_target_qemu_prologue(TCGContext
*s
);
67 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
68 intptr_t value
, intptr_t addend
);
70 /* The CIE and FDE header definitions will be common to all hosts. */
72 uint32_t len
__attribute__((aligned((sizeof(void *)))));
78 uint8_t return_column
;
81 typedef struct QEMU_PACKED
{
82 uint32_t len
__attribute__((aligned((sizeof(void *)))));
86 } DebugFrameFDEHeader
;
88 typedef struct QEMU_PACKED
{
90 DebugFrameFDEHeader fde
;
93 typedef struct TCGLabelQemuLdst
{
94 bool is_ld
; /* qemu_ld: true, qemu_st: false */
96 TCGType type
; /* result type of a load */
97 TCGReg addrlo_reg
; /* reg index for low word of guest virtual addr */
98 TCGReg addrhi_reg
; /* reg index for high word of guest virtual addr */
99 TCGReg datalo_reg
; /* reg index for low word to be loaded or stored */
100 TCGReg datahi_reg
; /* reg index for high word to be loaded or stored */
101 const tcg_insn_unit
*raddr
; /* addr of the next IR of qemu_ld/st IR */
102 tcg_insn_unit
*label_ptr
[2]; /* label pointers to be updated */
103 QSIMPLEQ_ENTRY(TCGLabelQemuLdst
) next
;
106 static void tcg_register_jit_int(const void *buf
, size_t size
,
107 const void *debug_frame
,
108 size_t debug_frame_size
)
109 __attribute__((unused
));
111 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
112 static void tcg_out_tb_start(TCGContext
*s
);
113 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
115 static bool tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
116 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
117 TCGReg ret
, tcg_target_long arg
);
118 static void tcg_out_ext8s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
119 static void tcg_out_ext16s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
120 static void tcg_out_ext8u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
121 static void tcg_out_ext16u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
122 static void tcg_out_ext32s(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
123 static void tcg_out_ext32u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
124 static void tcg_out_exts_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
125 static void tcg_out_extu_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
126 static void tcg_out_extrl_i64_i32(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
127 static void tcg_out_addi_ptr(TCGContext
*s
, TCGReg
, TCGReg
, tcg_target_long
);
128 static bool tcg_out_xchg(TCGContext
*s
, TCGType type
, TCGReg r1
, TCGReg r2
);
129 static void tcg_out_exit_tb(TCGContext
*s
, uintptr_t arg
);
130 static void tcg_out_goto_tb(TCGContext
*s
, int which
);
131 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
132 const TCGArg args
[TCG_MAX_OP_ARGS
],
133 const int const_args
[TCG_MAX_OP_ARGS
]);
134 #if TCG_TARGET_MAYBE_vec
135 static bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
136 TCGReg dst
, TCGReg src
);
137 static bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
138 TCGReg dst
, TCGReg base
, intptr_t offset
);
139 static void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
140 TCGReg dst
, int64_t arg
);
141 static void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
142 unsigned vecl
, unsigned vece
,
143 const TCGArg args
[TCG_MAX_OP_ARGS
],
144 const int const_args
[TCG_MAX_OP_ARGS
]);
146 static inline bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
147 TCGReg dst
, TCGReg src
)
149 g_assert_not_reached();
151 static inline bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
152 TCGReg dst
, TCGReg base
, intptr_t offset
)
154 g_assert_not_reached();
156 static inline void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
157 TCGReg dst
, int64_t arg
)
159 g_assert_not_reached();
161 static inline void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
162 unsigned vecl
, unsigned vece
,
163 const TCGArg args
[TCG_MAX_OP_ARGS
],
164 const int const_args
[TCG_MAX_OP_ARGS
])
166 g_assert_not_reached();
169 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
171 static bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
172 TCGReg base
, intptr_t ofs
);
173 static void tcg_out_call(TCGContext
*s
, const tcg_insn_unit
*target
,
174 const TCGHelperInfo
*info
);
175 static TCGReg
tcg_target_call_oarg_reg(TCGCallReturnKind kind
, int slot
);
176 static bool tcg_target_const_match(int64_t val
, TCGType type
, int ct
, int vece
);
177 #ifdef TCG_TARGET_NEED_LDST_LABELS
178 static int tcg_out_ldst_finalize(TCGContext
*s
);
181 #ifndef CONFIG_USER_ONLY
182 #define guest_base ({ qemu_build_not_reached(); (uintptr_t)0; })
185 typedef struct TCGLdstHelperParam
{
186 TCGReg (*ra_gen
)(TCGContext
*s
, const TCGLabelQemuLdst
*l
, int arg_reg
);
189 } TCGLdstHelperParam
;
191 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
192 const TCGLdstHelperParam
*p
)
193 __attribute__((unused
));
194 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
195 bool load_sign
, const TCGLdstHelperParam
*p
)
196 __attribute__((unused
));
197 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
198 const TCGLdstHelperParam
*p
)
199 __attribute__((unused
));
201 static void * const qemu_ld_helpers
[MO_SSIZE
+ 1] __attribute__((unused
)) = {
202 [MO_UB
] = helper_ldub_mmu
,
203 [MO_SB
] = helper_ldsb_mmu
,
204 [MO_UW
] = helper_lduw_mmu
,
205 [MO_SW
] = helper_ldsw_mmu
,
206 [MO_UL
] = helper_ldul_mmu
,
207 [MO_UQ
] = helper_ldq_mmu
,
208 #if TCG_TARGET_REG_BITS == 64
209 [MO_SL
] = helper_ldsl_mmu
,
210 [MO_128
] = helper_ld16_mmu
,
214 static void * const qemu_st_helpers
[MO_SIZE
+ 1] __attribute__((unused
)) = {
215 [MO_8
] = helper_stb_mmu
,
216 [MO_16
] = helper_stw_mmu
,
217 [MO_32
] = helper_stl_mmu
,
218 [MO_64
] = helper_stq_mmu
,
219 #if TCG_TARGET_REG_BITS == 64
220 [MO_128
] = helper_st16_mmu
,
225 MemOp atom
; /* lg2 bits of atomicity required */
226 MemOp align
; /* lg2 bits of alignment to use */
229 static TCGAtomAlign
atom_and_align_for_opc(TCGContext
*s
, MemOp opc
,
230 MemOp host_atom
, bool allow_two_ops
)
231 __attribute__((unused
));
233 #ifdef CONFIG_USER_ONLY
234 bool tcg_use_softmmu
;
237 TCGContext tcg_init_ctx
;
238 __thread TCGContext
*tcg_ctx
;
240 TCGContext
**tcg_ctxs
;
241 unsigned int tcg_cur_ctxs
;
242 unsigned int tcg_max_ctxs
;
244 const void *tcg_code_gen_epilogue
;
245 uintptr_t tcg_splitwx_diff
;
247 #ifndef CONFIG_TCG_INTERPRETER
248 tcg_prologue_fn
*tcg_qemu_tb_exec
;
251 static TCGRegSet tcg_target_available_regs
[TCG_TYPE_COUNT
];
252 static TCGRegSet tcg_target_call_clobber_regs
;
254 #if TCG_TARGET_INSN_UNIT_SIZE == 1
255 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
260 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
267 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
268 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
270 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
273 tcg_insn_unit
*p
= s
->code_ptr
;
274 memcpy(p
, &v
, sizeof(v
));
275 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
279 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
282 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
285 memcpy(p
, &v
, sizeof(v
));
290 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
291 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
293 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
296 tcg_insn_unit
*p
= s
->code_ptr
;
297 memcpy(p
, &v
, sizeof(v
));
298 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
302 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
305 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
308 memcpy(p
, &v
, sizeof(v
));
313 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
314 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
316 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
319 tcg_insn_unit
*p
= s
->code_ptr
;
320 memcpy(p
, &v
, sizeof(v
));
321 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
325 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
328 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
331 memcpy(p
, &v
, sizeof(v
));
336 /* label relocation processing */
338 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
339 TCGLabel
*l
, intptr_t addend
)
341 TCGRelocation
*r
= tcg_malloc(sizeof(TCGRelocation
));
346 QSIMPLEQ_INSERT_TAIL(&l
->relocs
, r
, next
);
349 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
)
351 tcg_debug_assert(!l
->has_value
);
353 l
->u
.value_ptr
= tcg_splitwx_to_rx(s
->code_ptr
);
356 TCGLabel
*gen_new_label(void)
358 TCGContext
*s
= tcg_ctx
;
359 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
361 memset(l
, 0, sizeof(TCGLabel
));
362 l
->id
= s
->nb_labels
++;
363 QSIMPLEQ_INIT(&l
->branches
);
364 QSIMPLEQ_INIT(&l
->relocs
);
366 QSIMPLEQ_INSERT_TAIL(&s
->labels
, l
, next
);
371 static bool tcg_resolve_relocs(TCGContext
*s
)
375 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
377 uintptr_t value
= l
->u
.value
;
379 QSIMPLEQ_FOREACH(r
, &l
->relocs
, next
) {
380 if (!patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
)) {
388 static void set_jmp_reset_offset(TCGContext
*s
, int which
)
391 * We will check for overflow at the end of the opcode loop in
392 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
394 s
->gen_tb
->jmp_reset_offset
[which
] = tcg_current_code_size(s
);
397 static void G_GNUC_UNUSED
set_jmp_insn_offset(TCGContext
*s
, int which
)
400 * We will check for overflow at the end of the opcode loop in
401 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
403 s
->gen_tb
->jmp_insn_offset
[which
] = tcg_current_code_size(s
);
406 static uintptr_t G_GNUC_UNUSED
get_jmp_target_addr(TCGContext
*s
, int which
)
409 * Return the read-execute version of the pointer, for the benefit
410 * of any pc-relative addressing mode.
412 return (uintptr_t)tcg_splitwx_to_rx(&s
->gen_tb
->jmp_target_addr
[which
]);
415 static int __attribute__((unused
))
416 tlb_mask_table_ofs(TCGContext
*s
, int which
)
418 return (offsetof(CPUNegativeOffsetState
, tlb
.f
[which
]) -
419 sizeof(CPUNegativeOffsetState
));
422 /* Signal overflow, starting over with fewer guest insns. */
424 void tcg_raise_tb_overflow(TCGContext
*s
)
426 siglongjmp(s
->jmp_trans
, -2);
430 * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext.
431 * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg.
433 * However, tcg_out_helper_load_slots reuses this field to hold an
434 * argument slot number (which may designate a argument register or an
435 * argument stack slot), converting to TCGReg once all arguments that
436 * are destined for the stack are processed.
438 typedef struct TCGMovExtend
{
447 * tcg_out_movext -- move and extend
449 * @dst_type: integral type for destination
450 * @dst: destination register
451 * @src_type: integral type for source
452 * @src_ext: extension to apply to source
453 * @src: source register
455 * Move or extend @src into @dst, depending on @src_ext and the types.
457 static void tcg_out_movext(TCGContext
*s
, TCGType dst_type
, TCGReg dst
,
458 TCGType src_type
, MemOp src_ext
, TCGReg src
)
462 tcg_out_ext8u(s
, dst
, src
);
465 tcg_out_ext8s(s
, dst_type
, dst
, src
);
468 tcg_out_ext16u(s
, dst
, src
);
471 tcg_out_ext16s(s
, dst_type
, dst
, src
);
475 if (dst_type
== TCG_TYPE_I32
) {
476 if (src_type
== TCG_TYPE_I32
) {
477 tcg_out_mov(s
, TCG_TYPE_I32
, dst
, src
);
479 tcg_out_extrl_i64_i32(s
, dst
, src
);
481 } else if (src_type
== TCG_TYPE_I32
) {
482 if (src_ext
& MO_SIGN
) {
483 tcg_out_exts_i32_i64(s
, dst
, src
);
485 tcg_out_extu_i32_i64(s
, dst
, src
);
488 if (src_ext
& MO_SIGN
) {
489 tcg_out_ext32s(s
, dst
, src
);
491 tcg_out_ext32u(s
, dst
, src
);
496 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
497 if (dst_type
== TCG_TYPE_I32
) {
498 tcg_out_extrl_i64_i32(s
, dst
, src
);
500 tcg_out_mov(s
, TCG_TYPE_I64
, dst
, src
);
504 g_assert_not_reached();
508 /* Minor variations on a theme, using a structure. */
509 static void tcg_out_movext1_new_src(TCGContext
*s
, const TCGMovExtend
*i
,
512 tcg_out_movext(s
, i
->dst_type
, i
->dst
, i
->src_type
, i
->src_ext
, src
);
515 static void tcg_out_movext1(TCGContext
*s
, const TCGMovExtend
*i
)
517 tcg_out_movext1_new_src(s
, i
, i
->src
);
521 * tcg_out_movext2 -- move and extend two pair
523 * @i1: first move description
524 * @i2: second move description
525 * @scratch: temporary register, or -1 for none
527 * As tcg_out_movext, for both @i1 and @i2, caring for overlap
528 * between the sources and destinations.
531 static void tcg_out_movext2(TCGContext
*s
, const TCGMovExtend
*i1
,
532 const TCGMovExtend
*i2
, int scratch
)
534 TCGReg src1
= i1
->src
;
535 TCGReg src2
= i2
->src
;
537 if (i1
->dst
!= src2
) {
538 tcg_out_movext1(s
, i1
);
539 tcg_out_movext1(s
, i2
);
542 if (i2
->dst
== src1
) {
543 TCGType src1_type
= i1
->src_type
;
544 TCGType src2_type
= i2
->src_type
;
546 if (tcg_out_xchg(s
, MAX(src1_type
, src2_type
), src1
, src2
)) {
547 /* The data is now in the correct registers, now extend. */
551 tcg_debug_assert(scratch
>= 0);
552 tcg_out_mov(s
, src1_type
, scratch
, src1
);
556 tcg_out_movext1_new_src(s
, i2
, src2
);
557 tcg_out_movext1_new_src(s
, i1
, src1
);
561 * tcg_out_movext3 -- move and extend three pair
563 * @i1: first move description
564 * @i2: second move description
565 * @i3: third move description
566 * @scratch: temporary register, or -1 for none
568 * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap
569 * between the sources and destinations.
572 static void tcg_out_movext3(TCGContext
*s
, const TCGMovExtend
*i1
,
573 const TCGMovExtend
*i2
, const TCGMovExtend
*i3
,
576 TCGReg src1
= i1
->src
;
577 TCGReg src2
= i2
->src
;
578 TCGReg src3
= i3
->src
;
580 if (i1
->dst
!= src2
&& i1
->dst
!= src3
) {
581 tcg_out_movext1(s
, i1
);
582 tcg_out_movext2(s
, i2
, i3
, scratch
);
585 if (i2
->dst
!= src1
&& i2
->dst
!= src3
) {
586 tcg_out_movext1(s
, i2
);
587 tcg_out_movext2(s
, i1
, i3
, scratch
);
590 if (i3
->dst
!= src1
&& i3
->dst
!= src2
) {
591 tcg_out_movext1(s
, i3
);
592 tcg_out_movext2(s
, i1
, i2
, scratch
);
597 * There is a cycle. Since there are only 3 nodes, the cycle is
598 * either "clockwise" or "anti-clockwise", and can be solved with
599 * a single scratch or two xchg.
601 if (i1
->dst
== src2
&& i2
->dst
== src3
&& i3
->dst
== src1
) {
603 if (tcg_out_xchg(s
, MAX(i1
->src_type
, i2
->src_type
), src1
, src2
)) {
604 tcg_out_xchg(s
, MAX(i2
->src_type
, i3
->src_type
), src2
, src3
);
605 /* The data is now in the correct registers, now extend. */
606 tcg_out_movext1_new_src(s
, i1
, i1
->dst
);
607 tcg_out_movext1_new_src(s
, i2
, i2
->dst
);
608 tcg_out_movext1_new_src(s
, i3
, i3
->dst
);
610 tcg_debug_assert(scratch
>= 0);
611 tcg_out_mov(s
, i1
->src_type
, scratch
, src1
);
612 tcg_out_movext1(s
, i3
);
613 tcg_out_movext1(s
, i2
);
614 tcg_out_movext1_new_src(s
, i1
, scratch
);
616 } else if (i1
->dst
== src3
&& i2
->dst
== src1
&& i3
->dst
== src2
) {
617 /* "Anti-clockwise" */
618 if (tcg_out_xchg(s
, MAX(i2
->src_type
, i3
->src_type
), src2
, src3
)) {
619 tcg_out_xchg(s
, MAX(i1
->src_type
, i2
->src_type
), src1
, src2
);
620 /* The data is now in the correct registers, now extend. */
621 tcg_out_movext1_new_src(s
, i1
, i1
->dst
);
622 tcg_out_movext1_new_src(s
, i2
, i2
->dst
);
623 tcg_out_movext1_new_src(s
, i3
, i3
->dst
);
625 tcg_debug_assert(scratch
>= 0);
626 tcg_out_mov(s
, i1
->src_type
, scratch
, src1
);
627 tcg_out_movext1(s
, i2
);
628 tcg_out_movext1(s
, i3
);
629 tcg_out_movext1_new_src(s
, i1
, scratch
);
632 g_assert_not_reached();
636 #define C_PFX1(P, A) P##A
637 #define C_PFX2(P, A, B) P##A##_##B
638 #define C_PFX3(P, A, B, C) P##A##_##B##_##C
639 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
640 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
641 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
643 /* Define an enumeration for the various combinations. */
645 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
646 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
647 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
648 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
650 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
651 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
652 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
653 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
655 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
656 #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1),
658 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
659 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
660 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
661 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
662 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4),
665 #include "tcg-target-con-set.h"
666 } TCGConstraintSetIndex
;
668 static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode
);
686 /* Put all of the constraint sets into an array, indexed by the enum. */
688 #define C_O0_I1(I1) { .args_ct_str = { #I1 } },
689 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
690 #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
691 #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
693 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
694 #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
695 #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
696 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
698 #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
699 #define C_N2_I1(O1, O2, I1) { .args_ct_str = { "&" #O1, "&" #O2, #I1 } },
701 #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
702 #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
703 #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
704 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
705 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { "&" #O1, #O2, #I1, #I2, #I3, #I4 } },
707 static const TCGTargetOpDef constraint_sets
[] = {
708 #include "tcg-target-con-set.h"
728 /* Expand the enumerator to be returned from tcg_target_op_def(). */
730 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
731 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
732 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
733 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
735 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
736 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
737 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
738 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
740 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
741 #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1)
743 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
744 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
745 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
746 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
747 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4)
749 #include "tcg-target.c.inc"
751 #ifndef CONFIG_TCG_INTERPRETER
752 /* Validate CPUTLBDescFast placement. */
753 QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState
, tlb
.f
[0]) -
754 sizeof(CPUNegativeOffsetState
))
755 < MIN_TLB_MASK_TABLE_OFS
);
758 static void alloc_tcg_plugin_context(TCGContext
*s
)
761 s
->plugin_tb
= g_new0(struct qemu_plugin_tb
, 1);
762 s
->plugin_tb
->insns
=
763 g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn
);
768 * All TCG threads except the parent (i.e. the one that called tcg_context_init
769 * and registered the target's TCG globals) must register with this function
770 * before initiating translation.
772 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation
773 * of tcg_region_init() for the reasoning behind this.
775 * In system-mode each caller registers its context in tcg_ctxs[]. Note that in
776 * system-mode tcg_ctxs[] does not track tcg_ctx_init, since the initial context
777 * is not used anymore for translation once this function is called.
779 * Not tracking tcg_init_ctx in tcg_ctxs[] in system-mode keeps code that
780 * iterates over the array (e.g. tcg_code_size() the same for both system/user
783 #ifdef CONFIG_USER_ONLY
784 void tcg_register_thread(void)
786 tcg_ctx
= &tcg_init_ctx
;
789 void tcg_register_thread(void)
791 TCGContext
*s
= g_malloc(sizeof(*s
));
796 /* Relink mem_base. */
797 for (i
= 0, n
= tcg_init_ctx
.nb_globals
; i
< n
; ++i
) {
798 if (tcg_init_ctx
.temps
[i
].mem_base
) {
799 ptrdiff_t b
= tcg_init_ctx
.temps
[i
].mem_base
- tcg_init_ctx
.temps
;
800 tcg_debug_assert(b
>= 0 && b
< n
);
801 s
->temps
[i
].mem_base
= &s
->temps
[b
];
805 /* Claim an entry in tcg_ctxs */
806 n
= qatomic_fetch_inc(&tcg_cur_ctxs
);
807 g_assert(n
< tcg_max_ctxs
);
808 qatomic_set(&tcg_ctxs
[n
], s
);
811 alloc_tcg_plugin_context(s
);
812 tcg_region_initial_alloc(s
);
817 #endif /* !CONFIG_USER_ONLY */
819 /* pool based memory allocation */
820 void *tcg_malloc_internal(TCGContext
*s
, int size
)
825 if (size
> TCG_POOL_CHUNK_SIZE
) {
826 /* big malloc: insert a new pool (XXX: could optimize) */
827 p
= g_malloc(sizeof(TCGPool
) + size
);
829 p
->next
= s
->pool_first_large
;
830 s
->pool_first_large
= p
;
841 pool_size
= TCG_POOL_CHUNK_SIZE
;
842 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
845 if (s
->pool_current
) {
846 s
->pool_current
->next
= p
;
856 s
->pool_cur
= p
->data
+ size
;
857 s
->pool_end
= p
->data
+ p
->size
;
861 void tcg_pool_reset(TCGContext
*s
)
864 for (p
= s
->pool_first_large
; p
; p
= t
) {
868 s
->pool_first_large
= NULL
;
869 s
->pool_cur
= s
->pool_end
= NULL
;
870 s
->pool_current
= NULL
;
874 * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions,
875 * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N.
876 * We only use these for layout in tcg_out_ld_helper_ret and
877 * tcg_out_st_helper_args, and share them between several of
878 * the helpers, with the end result that it's easier to build manually.
881 #if TCG_TARGET_REG_BITS == 32
882 # define dh_typecode_ttl dh_typecode_i32
884 # define dh_typecode_ttl dh_typecode_i64
887 static TCGHelperInfo info_helper_ld32_mmu
= {
888 .flags
= TCG_CALL_NO_WG
,
889 .typemask
= dh_typemask(ttl
, 0) /* return tcg_target_ulong */
890 | dh_typemask(env
, 1)
891 | dh_typemask(i64
, 2) /* uint64_t addr */
892 | dh_typemask(i32
, 3) /* unsigned oi */
893 | dh_typemask(ptr
, 4) /* uintptr_t ra */
896 static TCGHelperInfo info_helper_ld64_mmu
= {
897 .flags
= TCG_CALL_NO_WG
,
898 .typemask
= dh_typemask(i64
, 0) /* return uint64_t */
899 | dh_typemask(env
, 1)
900 | dh_typemask(i64
, 2) /* uint64_t addr */
901 | dh_typemask(i32
, 3) /* unsigned oi */
902 | dh_typemask(ptr
, 4) /* uintptr_t ra */
905 static TCGHelperInfo info_helper_ld128_mmu
= {
906 .flags
= TCG_CALL_NO_WG
,
907 .typemask
= dh_typemask(i128
, 0) /* return Int128 */
908 | dh_typemask(env
, 1)
909 | dh_typemask(i64
, 2) /* uint64_t addr */
910 | dh_typemask(i32
, 3) /* unsigned oi */
911 | dh_typemask(ptr
, 4) /* uintptr_t ra */
914 static TCGHelperInfo info_helper_st32_mmu
= {
915 .flags
= TCG_CALL_NO_WG
,
916 .typemask
= dh_typemask(void, 0)
917 | dh_typemask(env
, 1)
918 | dh_typemask(i64
, 2) /* uint64_t addr */
919 | dh_typemask(i32
, 3) /* uint32_t data */
920 | dh_typemask(i32
, 4) /* unsigned oi */
921 | dh_typemask(ptr
, 5) /* uintptr_t ra */
924 static TCGHelperInfo info_helper_st64_mmu
= {
925 .flags
= TCG_CALL_NO_WG
,
926 .typemask
= dh_typemask(void, 0)
927 | dh_typemask(env
, 1)
928 | dh_typemask(i64
, 2) /* uint64_t addr */
929 | dh_typemask(i64
, 3) /* uint64_t data */
930 | dh_typemask(i32
, 4) /* unsigned oi */
931 | dh_typemask(ptr
, 5) /* uintptr_t ra */
934 static TCGHelperInfo info_helper_st128_mmu
= {
935 .flags
= TCG_CALL_NO_WG
,
936 .typemask
= dh_typemask(void, 0)
937 | dh_typemask(env
, 1)
938 | dh_typemask(i64
, 2) /* uint64_t addr */
939 | dh_typemask(i128
, 3) /* Int128 data */
940 | dh_typemask(i32
, 4) /* unsigned oi */
941 | dh_typemask(ptr
, 5) /* uintptr_t ra */
944 #ifdef CONFIG_TCG_INTERPRETER
945 static ffi_type
*typecode_to_ffi(int argmask
)
948 * libffi does not support __int128_t, so we have forced Int128
949 * to use the structure definition instead of the builtin type.
951 static ffi_type
*ffi_type_i128_elements
[3] = {
956 static ffi_type ffi_type_i128
= {
958 .alignment
= __alignof__(Int128
),
959 .type
= FFI_TYPE_STRUCT
,
960 .elements
= ffi_type_i128_elements
,
964 case dh_typecode_void
:
965 return &ffi_type_void
;
966 case dh_typecode_i32
:
967 return &ffi_type_uint32
;
968 case dh_typecode_s32
:
969 return &ffi_type_sint32
;
970 case dh_typecode_i64
:
971 return &ffi_type_uint64
;
972 case dh_typecode_s64
:
973 return &ffi_type_sint64
;
974 case dh_typecode_ptr
:
975 return &ffi_type_pointer
;
976 case dh_typecode_i128
:
977 return &ffi_type_i128
;
979 g_assert_not_reached();
982 static ffi_cif
*init_ffi_layout(TCGHelperInfo
*info
)
984 unsigned typemask
= info
->typemask
;
992 /* Ignoring the return type, find the last non-zero field. */
993 nargs
= 32 - clz32(typemask
>> 3);
994 nargs
= DIV_ROUND_UP(nargs
, 3);
995 assert(nargs
<= MAX_CALL_IARGS
);
997 ca
= g_malloc0(sizeof(*ca
) + nargs
* sizeof(ffi_type
*));
998 ca
->cif
.rtype
= typecode_to_ffi(typemask
& 7);
999 ca
->cif
.nargs
= nargs
;
1002 ca
->cif
.arg_types
= ca
->args
;
1003 for (int j
= 0; j
< nargs
; ++j
) {
1004 int typecode
= extract32(typemask
, (j
+ 1) * 3, 3);
1005 ca
->args
[j
] = typecode_to_ffi(typecode
);
1009 status
= ffi_prep_cif(&ca
->cif
, FFI_DEFAULT_ABI
, nargs
,
1010 ca
->cif
.rtype
, ca
->cif
.arg_types
);
1011 assert(status
== FFI_OK
);
1016 #define HELPER_INFO_INIT(I) (&(I)->cif)
1017 #define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I)
1019 #define HELPER_INFO_INIT(I) (&(I)->init)
1020 #define HELPER_INFO_INIT_VAL(I) 1
1021 #endif /* CONFIG_TCG_INTERPRETER */
1023 static inline bool arg_slot_reg_p(unsigned arg_slot
)
1026 * Split the sizeof away from the comparison to avoid Werror from
1027 * "unsigned < 0 is always false", when iarg_regs is empty.
1029 unsigned nreg
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
1030 return arg_slot
< nreg
;
1033 static inline int arg_slot_stk_ofs(unsigned arg_slot
)
1035 unsigned max
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
1036 unsigned stk_slot
= arg_slot
- ARRAY_SIZE(tcg_target_call_iarg_regs
);
1038 tcg_debug_assert(stk_slot
< max
);
1039 return TCG_TARGET_CALL_STACK_OFFSET
+ stk_slot
* sizeof(tcg_target_long
);
1042 typedef struct TCGCumulativeArgs
{
1043 int arg_idx
; /* tcg_gen_callN args[] */
1044 int info_in_idx
; /* TCGHelperInfo in[] */
1045 int arg_slot
; /* regs+stack slot */
1046 int ref_slot
; /* stack slots for references */
1047 } TCGCumulativeArgs
;
1049 static void layout_arg_even(TCGCumulativeArgs
*cum
)
1051 cum
->arg_slot
+= cum
->arg_slot
& 1;
1054 static void layout_arg_1(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
,
1055 TCGCallArgumentKind kind
)
1057 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1059 *loc
= (TCGCallArgumentLoc
){
1061 .arg_idx
= cum
->arg_idx
,
1062 .arg_slot
= cum
->arg_slot
,
1068 static void layout_arg_normal_n(TCGCumulativeArgs
*cum
,
1069 TCGHelperInfo
*info
, int n
)
1071 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1073 for (int i
= 0; i
< n
; ++i
) {
1074 /* Layout all using the same arg_idx, adjusting the subindex. */
1075 loc
[i
] = (TCGCallArgumentLoc
){
1076 .kind
= TCG_CALL_ARG_NORMAL
,
1077 .arg_idx
= cum
->arg_idx
,
1079 .arg_slot
= cum
->arg_slot
+ i
,
1082 cum
->info_in_idx
+= n
;
1086 static void layout_arg_by_ref(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
)
1088 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1089 int n
= 128 / TCG_TARGET_REG_BITS
;
1091 /* The first subindex carries the pointer. */
1092 layout_arg_1(cum
, info
, TCG_CALL_ARG_BY_REF
);
1095 * The callee is allowed to clobber memory associated with
1096 * structure pass by-reference. Therefore we must make copies.
1097 * Allocate space from "ref_slot", which will be adjusted to
1098 * follow the parameters on the stack.
1100 loc
[0].ref_slot
= cum
->ref_slot
;
1103 * Subsequent words also go into the reference slot, but
1104 * do not accumulate into the regular arguments.
1106 for (int i
= 1; i
< n
; ++i
) {
1107 loc
[i
] = (TCGCallArgumentLoc
){
1108 .kind
= TCG_CALL_ARG_BY_REF_N
,
1109 .arg_idx
= cum
->arg_idx
,
1111 .ref_slot
= cum
->ref_slot
+ i
,
1114 cum
->info_in_idx
+= n
- 1; /* i=0 accounted for in layout_arg_1 */
1118 static void init_call_layout(TCGHelperInfo
*info
)
1120 int max_reg_slots
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
1121 int max_stk_slots
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
1122 unsigned typemask
= info
->typemask
;
1124 TCGCumulativeArgs cum
= { };
1127 * Parse and place any function return value.
1129 typecode
= typemask
& 7;
1131 case dh_typecode_void
:
1134 case dh_typecode_i32
:
1135 case dh_typecode_s32
:
1136 case dh_typecode_ptr
:
1138 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1140 case dh_typecode_i64
:
1141 case dh_typecode_s64
:
1142 info
->nr_out
= 64 / TCG_TARGET_REG_BITS
;
1143 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1144 /* Query the last register now to trigger any assert early. */
1145 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1147 case dh_typecode_i128
:
1148 info
->nr_out
= 128 / TCG_TARGET_REG_BITS
;
1149 info
->out_kind
= TCG_TARGET_CALL_RET_I128
;
1150 switch (TCG_TARGET_CALL_RET_I128
) {
1151 case TCG_CALL_RET_NORMAL
:
1152 /* Query the last register now to trigger any assert early. */
1153 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1155 case TCG_CALL_RET_BY_VEC
:
1156 /* Query the single register now to trigger any assert early. */
1157 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0);
1159 case TCG_CALL_RET_BY_REF
:
1161 * Allocate the first argument to the output.
1162 * We don't need to store this anywhere, just make it
1163 * unavailable for use in the input loop below.
1168 qemu_build_not_reached();
1172 g_assert_not_reached();
1176 * Parse and place function arguments.
1178 for (typemask
>>= 3; typemask
; typemask
>>= 3, cum
.arg_idx
++) {
1179 TCGCallArgumentKind kind
;
1182 typecode
= typemask
& 7;
1184 case dh_typecode_i32
:
1185 case dh_typecode_s32
:
1186 type
= TCG_TYPE_I32
;
1188 case dh_typecode_i64
:
1189 case dh_typecode_s64
:
1190 type
= TCG_TYPE_I64
;
1192 case dh_typecode_ptr
:
1193 type
= TCG_TYPE_PTR
;
1195 case dh_typecode_i128
:
1196 type
= TCG_TYPE_I128
;
1199 g_assert_not_reached();
1204 switch (TCG_TARGET_CALL_ARG_I32
) {
1205 case TCG_CALL_ARG_EVEN
:
1206 layout_arg_even(&cum
);
1208 case TCG_CALL_ARG_NORMAL
:
1209 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1211 case TCG_CALL_ARG_EXTEND
:
1212 kind
= TCG_CALL_ARG_EXTEND_U
+ (typecode
& 1);
1213 layout_arg_1(&cum
, info
, kind
);
1216 qemu_build_not_reached();
1221 switch (TCG_TARGET_CALL_ARG_I64
) {
1222 case TCG_CALL_ARG_EVEN
:
1223 layout_arg_even(&cum
);
1225 case TCG_CALL_ARG_NORMAL
:
1226 if (TCG_TARGET_REG_BITS
== 32) {
1227 layout_arg_normal_n(&cum
, info
, 2);
1229 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1233 qemu_build_not_reached();
1238 switch (TCG_TARGET_CALL_ARG_I128
) {
1239 case TCG_CALL_ARG_EVEN
:
1240 layout_arg_even(&cum
);
1242 case TCG_CALL_ARG_NORMAL
:
1243 layout_arg_normal_n(&cum
, info
, 128 / TCG_TARGET_REG_BITS
);
1245 case TCG_CALL_ARG_BY_REF
:
1246 layout_arg_by_ref(&cum
, info
);
1249 qemu_build_not_reached();
1254 g_assert_not_reached();
1257 info
->nr_in
= cum
.info_in_idx
;
1259 /* Validate that we didn't overrun the input array. */
1260 assert(cum
.info_in_idx
<= ARRAY_SIZE(info
->in
));
1261 /* Validate the backend has enough argument space. */
1262 assert(cum
.arg_slot
<= max_reg_slots
+ max_stk_slots
);
1265 * Relocate the "ref_slot" area to the end of the parameters.
1266 * Minimizing this stack offset helps code size for x86,
1267 * which has a signed 8-bit offset encoding.
1269 if (cum
.ref_slot
!= 0) {
1272 if (cum
.arg_slot
> max_reg_slots
) {
1273 int align
= __alignof(Int128
) / sizeof(tcg_target_long
);
1275 ref_base
= cum
.arg_slot
- max_reg_slots
;
1277 ref_base
= ROUND_UP(ref_base
, align
);
1280 assert(ref_base
+ cum
.ref_slot
<= max_stk_slots
);
1281 ref_base
+= max_reg_slots
;
1283 if (ref_base
!= 0) {
1284 for (int i
= cum
.info_in_idx
- 1; i
>= 0; --i
) {
1285 TCGCallArgumentLoc
*loc
= &info
->in
[i
];
1286 switch (loc
->kind
) {
1287 case TCG_CALL_ARG_BY_REF
:
1288 case TCG_CALL_ARG_BY_REF_N
:
1289 loc
->ref_slot
+= ref_base
;
1299 static int indirect_reg_alloc_order
[ARRAY_SIZE(tcg_target_reg_alloc_order
)];
1300 static void process_op_defs(TCGContext
*s
);
1301 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1302 TCGReg reg
, const char *name
);
1304 static void tcg_context_init(unsigned max_cpus
)
1306 TCGContext
*s
= &tcg_init_ctx
;
1307 int op
, total_args
, n
, i
;
1309 TCGArgConstraint
*args_ct
;
1312 memset(s
, 0, sizeof(*s
));
1315 /* Count total number of arguments and allocate the corresponding
1318 for(op
= 0; op
< NB_OPS
; op
++) {
1319 def
= &tcg_op_defs
[op
];
1320 n
= def
->nb_iargs
+ def
->nb_oargs
;
1324 args_ct
= g_new0(TCGArgConstraint
, total_args
);
1326 for(op
= 0; op
< NB_OPS
; op
++) {
1327 def
= &tcg_op_defs
[op
];
1328 def
->args_ct
= args_ct
;
1329 n
= def
->nb_iargs
+ def
->nb_oargs
;
1333 init_call_layout(&info_helper_ld32_mmu
);
1334 init_call_layout(&info_helper_ld64_mmu
);
1335 init_call_layout(&info_helper_ld128_mmu
);
1336 init_call_layout(&info_helper_st32_mmu
);
1337 init_call_layout(&info_helper_st64_mmu
);
1338 init_call_layout(&info_helper_st128_mmu
);
1343 /* Reverse the order of the saved registers, assuming they're all at
1344 the start of tcg_target_reg_alloc_order. */
1345 for (n
= 0; n
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++n
) {
1346 int r
= tcg_target_reg_alloc_order
[n
];
1347 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, r
)) {
1351 for (i
= 0; i
< n
; ++i
) {
1352 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[n
- 1 - i
];
1354 for (; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++i
) {
1355 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[i
];
1358 alloc_tcg_plugin_context(s
);
1362 * In user-mode we simply share the init context among threads, since we
1363 * use a single region. See the documentation tcg_region_init() for the
1364 * reasoning behind this.
1365 * In system-mode we will have at most max_cpus TCG threads.
1367 #ifdef CONFIG_USER_ONLY
1368 tcg_ctxs
= &tcg_ctx
;
1372 tcg_max_ctxs
= max_cpus
;
1373 tcg_ctxs
= g_new0(TCGContext
*, max_cpus
);
1376 tcg_debug_assert(!tcg_regset_test_reg(s
->reserved_regs
, TCG_AREG0
));
1377 ts
= tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, TCG_AREG0
, "env");
1378 tcg_env
= temp_tcgv_ptr(ts
);
1381 void tcg_init(size_t tb_size
, int splitwx
, unsigned max_cpus
)
1383 tcg_context_init(max_cpus
);
1384 tcg_region_init(tb_size
, splitwx
, max_cpus
);
1388 * Allocate TBs right before their corresponding translated code, making
1389 * sure that TBs and code are on different cache lines.
1391 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
)
1393 uintptr_t align
= qemu_icache_linesize
;
1394 TranslationBlock
*tb
;
1398 tb
= (void *)ROUND_UP((uintptr_t)s
->code_gen_ptr
, align
);
1399 next
= (void *)ROUND_UP((uintptr_t)(tb
+ 1), align
);
1401 if (unlikely(next
> s
->code_gen_highwater
)) {
1402 if (tcg_region_alloc(s
)) {
1407 qatomic_set(&s
->code_gen_ptr
, next
);
1408 s
->data_gen_ptr
= NULL
;
1412 void tcg_prologue_init(void)
1414 TCGContext
*s
= tcg_ctx
;
1415 size_t prologue_size
;
1417 s
->code_ptr
= s
->code_gen_ptr
;
1418 s
->code_buf
= s
->code_gen_ptr
;
1419 s
->data_gen_ptr
= NULL
;
1421 #ifndef CONFIG_TCG_INTERPRETER
1422 tcg_qemu_tb_exec
= (tcg_prologue_fn
*)tcg_splitwx_to_rx(s
->code_ptr
);
1425 #ifdef TCG_TARGET_NEED_POOL_LABELS
1426 s
->pool_labels
= NULL
;
1429 qemu_thread_jit_write();
1430 /* Generate the prologue. */
1431 tcg_target_qemu_prologue(s
);
1433 #ifdef TCG_TARGET_NEED_POOL_LABELS
1434 /* Allow the prologue to put e.g. guest_base into a pool entry. */
1436 int result
= tcg_out_pool_finalize(s
);
1437 tcg_debug_assert(result
== 0);
1441 prologue_size
= tcg_current_code_size(s
);
1442 perf_report_prologue(s
->code_gen_ptr
, prologue_size
);
1444 #ifndef CONFIG_TCG_INTERPRETER
1445 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
1446 (uintptr_t)s
->code_buf
, prologue_size
);
1449 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
1450 FILE *logfile
= qemu_log_trylock();
1452 fprintf(logfile
, "PROLOGUE: [size=%zu]\n", prologue_size
);
1453 if (s
->data_gen_ptr
) {
1454 size_t code_size
= s
->data_gen_ptr
- s
->code_gen_ptr
;
1455 size_t data_size
= prologue_size
- code_size
;
1458 disas(logfile
, s
->code_gen_ptr
, code_size
);
1460 for (i
= 0; i
< data_size
; i
+= sizeof(tcg_target_ulong
)) {
1461 if (sizeof(tcg_target_ulong
) == 8) {
1463 "0x%08" PRIxPTR
": .quad 0x%016" PRIx64
"\n",
1464 (uintptr_t)s
->data_gen_ptr
+ i
,
1465 *(uint64_t *)(s
->data_gen_ptr
+ i
));
1468 "0x%08" PRIxPTR
": .long 0x%08x\n",
1469 (uintptr_t)s
->data_gen_ptr
+ i
,
1470 *(uint32_t *)(s
->data_gen_ptr
+ i
));
1474 disas(logfile
, s
->code_gen_ptr
, prologue_size
);
1476 fprintf(logfile
, "\n");
1477 qemu_log_unlock(logfile
);
1481 #ifndef CONFIG_TCG_INTERPRETER
1483 * Assert that goto_ptr is implemented completely, setting an epilogue.
1484 * For tci, we use NULL as the signal to return from the interpreter,
1485 * so skip this check.
1487 tcg_debug_assert(tcg_code_gen_epilogue
!= NULL
);
1490 tcg_region_prologue_set(s
);
1493 void tcg_func_start(TCGContext
*s
)
1496 s
->nb_temps
= s
->nb_globals
;
1498 /* No temps have been previously allocated for size or locality. */
1499 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
1501 /* No constant temps have been previously allocated. */
1502 for (int i
= 0; i
< TCG_TYPE_COUNT
; ++i
) {
1503 if (s
->const_table
[i
]) {
1504 g_hash_table_remove_all(s
->const_table
[i
]);
1510 s
->current_frame_offset
= s
->frame_start
;
1512 #ifdef CONFIG_DEBUG_TCG
1513 s
->goto_tb_issue_mask
= 0;
1516 QTAILQ_INIT(&s
->ops
);
1517 QTAILQ_INIT(&s
->free_ops
);
1518 QSIMPLEQ_INIT(&s
->labels
);
1520 tcg_debug_assert(s
->addr_type
== TCG_TYPE_I32
||
1521 s
->addr_type
== TCG_TYPE_I64
);
1523 tcg_debug_assert(s
->insn_start_words
> 0);
1526 static TCGTemp
*tcg_temp_alloc(TCGContext
*s
)
1528 int n
= s
->nb_temps
++;
1530 if (n
>= TCG_MAX_TEMPS
) {
1531 tcg_raise_tb_overflow(s
);
1533 return memset(&s
->temps
[n
], 0, sizeof(TCGTemp
));
1536 static TCGTemp
*tcg_global_alloc(TCGContext
*s
)
1540 tcg_debug_assert(s
->nb_globals
== s
->nb_temps
);
1541 tcg_debug_assert(s
->nb_globals
< TCG_MAX_TEMPS
);
1543 ts
= tcg_temp_alloc(s
);
1544 ts
->kind
= TEMP_GLOBAL
;
1549 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1550 TCGReg reg
, const char *name
)
1554 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
1556 ts
= tcg_global_alloc(s
);
1557 ts
->base_type
= type
;
1559 ts
->kind
= TEMP_FIXED
;
1562 tcg_regset_set_reg(s
->reserved_regs
, reg
);
1567 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
)
1569 s
->frame_start
= start
;
1570 s
->frame_end
= start
+ size
;
1572 = tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, reg
, "_frame");
1575 static TCGTemp
*tcg_global_mem_new_internal(TCGv_ptr base
, intptr_t offset
,
1576 const char *name
, TCGType type
)
1578 TCGContext
*s
= tcg_ctx
;
1579 TCGTemp
*base_ts
= tcgv_ptr_temp(base
);
1580 TCGTemp
*ts
= tcg_global_alloc(s
);
1581 int indirect_reg
= 0;
1583 switch (base_ts
->kind
) {
1587 /* We do not support double-indirect registers. */
1588 tcg_debug_assert(!base_ts
->indirect_reg
);
1589 base_ts
->indirect_base
= 1;
1590 s
->nb_indirects
+= (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
1595 g_assert_not_reached();
1598 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1599 TCGTemp
*ts2
= tcg_global_alloc(s
);
1602 ts
->base_type
= TCG_TYPE_I64
;
1603 ts
->type
= TCG_TYPE_I32
;
1604 ts
->indirect_reg
= indirect_reg
;
1605 ts
->mem_allocated
= 1;
1606 ts
->mem_base
= base_ts
;
1607 ts
->mem_offset
= offset
;
1608 pstrcpy(buf
, sizeof(buf
), name
);
1609 pstrcat(buf
, sizeof(buf
), "_0");
1610 ts
->name
= strdup(buf
);
1612 tcg_debug_assert(ts2
== ts
+ 1);
1613 ts2
->base_type
= TCG_TYPE_I64
;
1614 ts2
->type
= TCG_TYPE_I32
;
1615 ts2
->indirect_reg
= indirect_reg
;
1616 ts2
->mem_allocated
= 1;
1617 ts2
->mem_base
= base_ts
;
1618 ts2
->mem_offset
= offset
+ 4;
1619 ts2
->temp_subindex
= 1;
1620 pstrcpy(buf
, sizeof(buf
), name
);
1621 pstrcat(buf
, sizeof(buf
), "_1");
1622 ts2
->name
= strdup(buf
);
1624 ts
->base_type
= type
;
1626 ts
->indirect_reg
= indirect_reg
;
1627 ts
->mem_allocated
= 1;
1628 ts
->mem_base
= base_ts
;
1629 ts
->mem_offset
= offset
;
1635 TCGv_i32
tcg_global_mem_new_i32(TCGv_ptr reg
, intptr_t off
, const char *name
)
1637 TCGTemp
*ts
= tcg_global_mem_new_internal(reg
, off
, name
, TCG_TYPE_I32
);
1638 return temp_tcgv_i32(ts
);
1641 TCGv_i64
tcg_global_mem_new_i64(TCGv_ptr reg
, intptr_t off
, const char *name
)
1643 TCGTemp
*ts
= tcg_global_mem_new_internal(reg
, off
, name
, TCG_TYPE_I64
);
1644 return temp_tcgv_i64(ts
);
1647 TCGv_ptr
tcg_global_mem_new_ptr(TCGv_ptr reg
, intptr_t off
, const char *name
)
1649 TCGTemp
*ts
= tcg_global_mem_new_internal(reg
, off
, name
, TCG_TYPE_PTR
);
1650 return temp_tcgv_ptr(ts
);
1653 static TCGTemp
*tcg_temp_new_internal(TCGType type
, TCGTempKind kind
)
1655 TCGContext
*s
= tcg_ctx
;
1659 if (kind
== TEMP_EBB
) {
1660 int idx
= find_first_bit(s
->free_temps
[type
].l
, TCG_MAX_TEMPS
);
1662 if (idx
< TCG_MAX_TEMPS
) {
1663 /* There is already an available temp with the right type. */
1664 clear_bit(idx
, s
->free_temps
[type
].l
);
1666 ts
= &s
->temps
[idx
];
1667 ts
->temp_allocated
= 1;
1668 tcg_debug_assert(ts
->base_type
== type
);
1669 tcg_debug_assert(ts
->kind
== kind
);
1673 tcg_debug_assert(kind
== TEMP_TB
);
1684 n
= 64 / TCG_TARGET_REG_BITS
;
1687 n
= 128 / TCG_TARGET_REG_BITS
;
1690 g_assert_not_reached();
1693 ts
= tcg_temp_alloc(s
);
1694 ts
->base_type
= type
;
1695 ts
->temp_allocated
= 1;
1701 ts
->type
= TCG_TYPE_REG
;
1703 for (int i
= 1; i
< n
; ++i
) {
1704 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1706 tcg_debug_assert(ts2
== ts
+ i
);
1707 ts2
->base_type
= type
;
1708 ts2
->type
= TCG_TYPE_REG
;
1709 ts2
->temp_allocated
= 1;
1710 ts2
->temp_subindex
= i
;
1717 TCGv_i32
tcg_temp_new_i32(void)
1719 return temp_tcgv_i32(tcg_temp_new_internal(TCG_TYPE_I32
, TEMP_TB
));
1722 TCGv_i32
tcg_temp_ebb_new_i32(void)
1724 return temp_tcgv_i32(tcg_temp_new_internal(TCG_TYPE_I32
, TEMP_EBB
));
1727 TCGv_i64
tcg_temp_new_i64(void)
1729 return temp_tcgv_i64(tcg_temp_new_internal(TCG_TYPE_I64
, TEMP_TB
));
1732 TCGv_i64
tcg_temp_ebb_new_i64(void)
1734 return temp_tcgv_i64(tcg_temp_new_internal(TCG_TYPE_I64
, TEMP_EBB
));
1737 TCGv_ptr
tcg_temp_new_ptr(void)
1739 return temp_tcgv_ptr(tcg_temp_new_internal(TCG_TYPE_PTR
, TEMP_TB
));
1742 TCGv_ptr
tcg_temp_ebb_new_ptr(void)
1744 return temp_tcgv_ptr(tcg_temp_new_internal(TCG_TYPE_PTR
, TEMP_EBB
));
1747 TCGv_i128
tcg_temp_new_i128(void)
1749 return temp_tcgv_i128(tcg_temp_new_internal(TCG_TYPE_I128
, TEMP_TB
));
1752 TCGv_i128
tcg_temp_ebb_new_i128(void)
1754 return temp_tcgv_i128(tcg_temp_new_internal(TCG_TYPE_I128
, TEMP_EBB
));
1757 TCGv_vec
tcg_temp_new_vec(TCGType type
)
1761 #ifdef CONFIG_DEBUG_TCG
1764 assert(TCG_TARGET_HAS_v64
);
1767 assert(TCG_TARGET_HAS_v128
);
1770 assert(TCG_TARGET_HAS_v256
);
1773 g_assert_not_reached();
1777 t
= tcg_temp_new_internal(type
, TEMP_EBB
);
1778 return temp_tcgv_vec(t
);
1781 /* Create a new temp of the same type as an existing temp. */
1782 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
)
1784 TCGTemp
*t
= tcgv_vec_temp(match
);
1786 tcg_debug_assert(t
->temp_allocated
!= 0);
1788 t
= tcg_temp_new_internal(t
->base_type
, TEMP_EBB
);
1789 return temp_tcgv_vec(t
);
1792 void tcg_temp_free_internal(TCGTemp
*ts
)
1794 TCGContext
*s
= tcg_ctx
;
1799 /* Silently ignore free. */
1802 tcg_debug_assert(ts
->temp_allocated
!= 0);
1803 ts
->temp_allocated
= 0;
1804 set_bit(temp_idx(ts
), s
->free_temps
[ts
->base_type
].l
);
1807 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */
1808 g_assert_not_reached();
1812 TCGTemp
*tcg_constant_internal(TCGType type
, int64_t val
)
1814 TCGContext
*s
= tcg_ctx
;
1815 GHashTable
*h
= s
->const_table
[type
];
1819 h
= g_hash_table_new(g_int64_hash
, g_int64_equal
);
1820 s
->const_table
[type
] = h
;
1823 ts
= g_hash_table_lookup(h
, &val
);
1827 ts
= tcg_temp_alloc(s
);
1829 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1830 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1832 tcg_debug_assert(ts2
== ts
+ 1);
1834 ts
->base_type
= TCG_TYPE_I64
;
1835 ts
->type
= TCG_TYPE_I32
;
1836 ts
->kind
= TEMP_CONST
;
1837 ts
->temp_allocated
= 1;
1839 ts2
->base_type
= TCG_TYPE_I64
;
1840 ts2
->type
= TCG_TYPE_I32
;
1841 ts2
->kind
= TEMP_CONST
;
1842 ts2
->temp_allocated
= 1;
1843 ts2
->temp_subindex
= 1;
1846 * Retain the full value of the 64-bit constant in the low
1847 * part, so that the hash table works. Actual uses will
1848 * truncate the value to the low part.
1850 ts
[HOST_BIG_ENDIAN
].val
= val
;
1851 ts
[!HOST_BIG_ENDIAN
].val
= val
>> 32;
1852 val_ptr
= &ts
[HOST_BIG_ENDIAN
].val
;
1854 ts
->base_type
= type
;
1856 ts
->kind
= TEMP_CONST
;
1857 ts
->temp_allocated
= 1;
1861 g_hash_table_insert(h
, val_ptr
, ts
);
1867 TCGv_i32
tcg_constant_i32(int32_t val
)
1869 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32
, val
));
1872 TCGv_i64
tcg_constant_i64(int64_t val
)
1874 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64
, val
));
1877 TCGv_ptr
tcg_constant_ptr_int(intptr_t val
)
1879 return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR
, val
));
1882 TCGv_vec
tcg_constant_vec(TCGType type
, unsigned vece
, int64_t val
)
1884 val
= dup_const(vece
, val
);
1885 return temp_tcgv_vec(tcg_constant_internal(type
, val
));
1888 TCGv_vec
tcg_constant_vec_matching(TCGv_vec match
, unsigned vece
, int64_t val
)
1890 TCGTemp
*t
= tcgv_vec_temp(match
);
1892 tcg_debug_assert(t
->temp_allocated
!= 0);
1893 return tcg_constant_vec(t
->base_type
, vece
, val
);
1896 #ifdef CONFIG_DEBUG_TCG
1897 size_t temp_idx(TCGTemp
*ts
)
1899 ptrdiff_t n
= ts
- tcg_ctx
->temps
;
1900 assert(n
>= 0 && n
< tcg_ctx
->nb_temps
);
1904 TCGTemp
*tcgv_i32_temp(TCGv_i32 v
)
1906 uintptr_t o
= (uintptr_t)v
- offsetof(TCGContext
, temps
);
1908 assert(o
< sizeof(TCGTemp
) * tcg_ctx
->nb_temps
);
1909 assert(o
% sizeof(TCGTemp
) == 0);
1911 return (void *)tcg_ctx
+ (uintptr_t)v
;
1913 #endif /* CONFIG_DEBUG_TCG */
1915 /* Return true if OP may appear in the opcode stream.
1916 Test the runtime variable that controls each opcode. */
1917 bool tcg_op_supported(TCGOpcode op
)
1920 = TCG_TARGET_HAS_v64
| TCG_TARGET_HAS_v128
| TCG_TARGET_HAS_v256
;
1923 case INDEX_op_discard
:
1924 case INDEX_op_set_label
:
1928 case INDEX_op_insn_start
:
1929 case INDEX_op_exit_tb
:
1930 case INDEX_op_goto_tb
:
1931 case INDEX_op_goto_ptr
:
1932 case INDEX_op_qemu_ld_a32_i32
:
1933 case INDEX_op_qemu_ld_a64_i32
:
1934 case INDEX_op_qemu_st_a32_i32
:
1935 case INDEX_op_qemu_st_a64_i32
:
1936 case INDEX_op_qemu_ld_a32_i64
:
1937 case INDEX_op_qemu_ld_a64_i64
:
1938 case INDEX_op_qemu_st_a32_i64
:
1939 case INDEX_op_qemu_st_a64_i64
:
1942 case INDEX_op_qemu_st8_a32_i32
:
1943 case INDEX_op_qemu_st8_a64_i32
:
1944 return TCG_TARGET_HAS_qemu_st8_i32
;
1946 case INDEX_op_qemu_ld_a32_i128
:
1947 case INDEX_op_qemu_ld_a64_i128
:
1948 case INDEX_op_qemu_st_a32_i128
:
1949 case INDEX_op_qemu_st_a64_i128
:
1950 return TCG_TARGET_HAS_qemu_ldst_i128
;
1952 case INDEX_op_mov_i32
:
1953 case INDEX_op_setcond_i32
:
1954 case INDEX_op_brcond_i32
:
1955 case INDEX_op_ld8u_i32
:
1956 case INDEX_op_ld8s_i32
:
1957 case INDEX_op_ld16u_i32
:
1958 case INDEX_op_ld16s_i32
:
1959 case INDEX_op_ld_i32
:
1960 case INDEX_op_st8_i32
:
1961 case INDEX_op_st16_i32
:
1962 case INDEX_op_st_i32
:
1963 case INDEX_op_add_i32
:
1964 case INDEX_op_sub_i32
:
1965 case INDEX_op_mul_i32
:
1966 case INDEX_op_and_i32
:
1967 case INDEX_op_or_i32
:
1968 case INDEX_op_xor_i32
:
1969 case INDEX_op_shl_i32
:
1970 case INDEX_op_shr_i32
:
1971 case INDEX_op_sar_i32
:
1974 case INDEX_op_negsetcond_i32
:
1975 return TCG_TARGET_HAS_negsetcond_i32
;
1976 case INDEX_op_movcond_i32
:
1977 return TCG_TARGET_HAS_movcond_i32
;
1978 case INDEX_op_div_i32
:
1979 case INDEX_op_divu_i32
:
1980 return TCG_TARGET_HAS_div_i32
;
1981 case INDEX_op_rem_i32
:
1982 case INDEX_op_remu_i32
:
1983 return TCG_TARGET_HAS_rem_i32
;
1984 case INDEX_op_div2_i32
:
1985 case INDEX_op_divu2_i32
:
1986 return TCG_TARGET_HAS_div2_i32
;
1987 case INDEX_op_rotl_i32
:
1988 case INDEX_op_rotr_i32
:
1989 return TCG_TARGET_HAS_rot_i32
;
1990 case INDEX_op_deposit_i32
:
1991 return TCG_TARGET_HAS_deposit_i32
;
1992 case INDEX_op_extract_i32
:
1993 return TCG_TARGET_HAS_extract_i32
;
1994 case INDEX_op_sextract_i32
:
1995 return TCG_TARGET_HAS_sextract_i32
;
1996 case INDEX_op_extract2_i32
:
1997 return TCG_TARGET_HAS_extract2_i32
;
1998 case INDEX_op_add2_i32
:
1999 return TCG_TARGET_HAS_add2_i32
;
2000 case INDEX_op_sub2_i32
:
2001 return TCG_TARGET_HAS_sub2_i32
;
2002 case INDEX_op_mulu2_i32
:
2003 return TCG_TARGET_HAS_mulu2_i32
;
2004 case INDEX_op_muls2_i32
:
2005 return TCG_TARGET_HAS_muls2_i32
;
2006 case INDEX_op_muluh_i32
:
2007 return TCG_TARGET_HAS_muluh_i32
;
2008 case INDEX_op_mulsh_i32
:
2009 return TCG_TARGET_HAS_mulsh_i32
;
2010 case INDEX_op_ext8s_i32
:
2011 return TCG_TARGET_HAS_ext8s_i32
;
2012 case INDEX_op_ext16s_i32
:
2013 return TCG_TARGET_HAS_ext16s_i32
;
2014 case INDEX_op_ext8u_i32
:
2015 return TCG_TARGET_HAS_ext8u_i32
;
2016 case INDEX_op_ext16u_i32
:
2017 return TCG_TARGET_HAS_ext16u_i32
;
2018 case INDEX_op_bswap16_i32
:
2019 return TCG_TARGET_HAS_bswap16_i32
;
2020 case INDEX_op_bswap32_i32
:
2021 return TCG_TARGET_HAS_bswap32_i32
;
2022 case INDEX_op_not_i32
:
2023 return TCG_TARGET_HAS_not_i32
;
2024 case INDEX_op_neg_i32
:
2025 return TCG_TARGET_HAS_neg_i32
;
2026 case INDEX_op_andc_i32
:
2027 return TCG_TARGET_HAS_andc_i32
;
2028 case INDEX_op_orc_i32
:
2029 return TCG_TARGET_HAS_orc_i32
;
2030 case INDEX_op_eqv_i32
:
2031 return TCG_TARGET_HAS_eqv_i32
;
2032 case INDEX_op_nand_i32
:
2033 return TCG_TARGET_HAS_nand_i32
;
2034 case INDEX_op_nor_i32
:
2035 return TCG_TARGET_HAS_nor_i32
;
2036 case INDEX_op_clz_i32
:
2037 return TCG_TARGET_HAS_clz_i32
;
2038 case INDEX_op_ctz_i32
:
2039 return TCG_TARGET_HAS_ctz_i32
;
2040 case INDEX_op_ctpop_i32
:
2041 return TCG_TARGET_HAS_ctpop_i32
;
2043 case INDEX_op_brcond2_i32
:
2044 case INDEX_op_setcond2_i32
:
2045 return TCG_TARGET_REG_BITS
== 32;
2047 case INDEX_op_mov_i64
:
2048 case INDEX_op_setcond_i64
:
2049 case INDEX_op_brcond_i64
:
2050 case INDEX_op_ld8u_i64
:
2051 case INDEX_op_ld8s_i64
:
2052 case INDEX_op_ld16u_i64
:
2053 case INDEX_op_ld16s_i64
:
2054 case INDEX_op_ld32u_i64
:
2055 case INDEX_op_ld32s_i64
:
2056 case INDEX_op_ld_i64
:
2057 case INDEX_op_st8_i64
:
2058 case INDEX_op_st16_i64
:
2059 case INDEX_op_st32_i64
:
2060 case INDEX_op_st_i64
:
2061 case INDEX_op_add_i64
:
2062 case INDEX_op_sub_i64
:
2063 case INDEX_op_mul_i64
:
2064 case INDEX_op_and_i64
:
2065 case INDEX_op_or_i64
:
2066 case INDEX_op_xor_i64
:
2067 case INDEX_op_shl_i64
:
2068 case INDEX_op_shr_i64
:
2069 case INDEX_op_sar_i64
:
2070 case INDEX_op_ext_i32_i64
:
2071 case INDEX_op_extu_i32_i64
:
2072 return TCG_TARGET_REG_BITS
== 64;
2074 case INDEX_op_negsetcond_i64
:
2075 return TCG_TARGET_HAS_negsetcond_i64
;
2076 case INDEX_op_movcond_i64
:
2077 return TCG_TARGET_HAS_movcond_i64
;
2078 case INDEX_op_div_i64
:
2079 case INDEX_op_divu_i64
:
2080 return TCG_TARGET_HAS_div_i64
;
2081 case INDEX_op_rem_i64
:
2082 case INDEX_op_remu_i64
:
2083 return TCG_TARGET_HAS_rem_i64
;
2084 case INDEX_op_div2_i64
:
2085 case INDEX_op_divu2_i64
:
2086 return TCG_TARGET_HAS_div2_i64
;
2087 case INDEX_op_rotl_i64
:
2088 case INDEX_op_rotr_i64
:
2089 return TCG_TARGET_HAS_rot_i64
;
2090 case INDEX_op_deposit_i64
:
2091 return TCG_TARGET_HAS_deposit_i64
;
2092 case INDEX_op_extract_i64
:
2093 return TCG_TARGET_HAS_extract_i64
;
2094 case INDEX_op_sextract_i64
:
2095 return TCG_TARGET_HAS_sextract_i64
;
2096 case INDEX_op_extract2_i64
:
2097 return TCG_TARGET_HAS_extract2_i64
;
2098 case INDEX_op_extrl_i64_i32
:
2099 case INDEX_op_extrh_i64_i32
:
2100 return TCG_TARGET_HAS_extr_i64_i32
;
2101 case INDEX_op_ext8s_i64
:
2102 return TCG_TARGET_HAS_ext8s_i64
;
2103 case INDEX_op_ext16s_i64
:
2104 return TCG_TARGET_HAS_ext16s_i64
;
2105 case INDEX_op_ext32s_i64
:
2106 return TCG_TARGET_HAS_ext32s_i64
;
2107 case INDEX_op_ext8u_i64
:
2108 return TCG_TARGET_HAS_ext8u_i64
;
2109 case INDEX_op_ext16u_i64
:
2110 return TCG_TARGET_HAS_ext16u_i64
;
2111 case INDEX_op_ext32u_i64
:
2112 return TCG_TARGET_HAS_ext32u_i64
;
2113 case INDEX_op_bswap16_i64
:
2114 return TCG_TARGET_HAS_bswap16_i64
;
2115 case INDEX_op_bswap32_i64
:
2116 return TCG_TARGET_HAS_bswap32_i64
;
2117 case INDEX_op_bswap64_i64
:
2118 return TCG_TARGET_HAS_bswap64_i64
;
2119 case INDEX_op_not_i64
:
2120 return TCG_TARGET_HAS_not_i64
;
2121 case INDEX_op_neg_i64
:
2122 return TCG_TARGET_HAS_neg_i64
;
2123 case INDEX_op_andc_i64
:
2124 return TCG_TARGET_HAS_andc_i64
;
2125 case INDEX_op_orc_i64
:
2126 return TCG_TARGET_HAS_orc_i64
;
2127 case INDEX_op_eqv_i64
:
2128 return TCG_TARGET_HAS_eqv_i64
;
2129 case INDEX_op_nand_i64
:
2130 return TCG_TARGET_HAS_nand_i64
;
2131 case INDEX_op_nor_i64
:
2132 return TCG_TARGET_HAS_nor_i64
;
2133 case INDEX_op_clz_i64
:
2134 return TCG_TARGET_HAS_clz_i64
;
2135 case INDEX_op_ctz_i64
:
2136 return TCG_TARGET_HAS_ctz_i64
;
2137 case INDEX_op_ctpop_i64
:
2138 return TCG_TARGET_HAS_ctpop_i64
;
2139 case INDEX_op_add2_i64
:
2140 return TCG_TARGET_HAS_add2_i64
;
2141 case INDEX_op_sub2_i64
:
2142 return TCG_TARGET_HAS_sub2_i64
;
2143 case INDEX_op_mulu2_i64
:
2144 return TCG_TARGET_HAS_mulu2_i64
;
2145 case INDEX_op_muls2_i64
:
2146 return TCG_TARGET_HAS_muls2_i64
;
2147 case INDEX_op_muluh_i64
:
2148 return TCG_TARGET_HAS_muluh_i64
;
2149 case INDEX_op_mulsh_i64
:
2150 return TCG_TARGET_HAS_mulsh_i64
;
2152 case INDEX_op_mov_vec
:
2153 case INDEX_op_dup_vec
:
2154 case INDEX_op_dupm_vec
:
2155 case INDEX_op_ld_vec
:
2156 case INDEX_op_st_vec
:
2157 case INDEX_op_add_vec
:
2158 case INDEX_op_sub_vec
:
2159 case INDEX_op_and_vec
:
2160 case INDEX_op_or_vec
:
2161 case INDEX_op_xor_vec
:
2162 case INDEX_op_cmp_vec
:
2164 case INDEX_op_dup2_vec
:
2165 return have_vec
&& TCG_TARGET_REG_BITS
== 32;
2166 case INDEX_op_not_vec
:
2167 return have_vec
&& TCG_TARGET_HAS_not_vec
;
2168 case INDEX_op_neg_vec
:
2169 return have_vec
&& TCG_TARGET_HAS_neg_vec
;
2170 case INDEX_op_abs_vec
:
2171 return have_vec
&& TCG_TARGET_HAS_abs_vec
;
2172 case INDEX_op_andc_vec
:
2173 return have_vec
&& TCG_TARGET_HAS_andc_vec
;
2174 case INDEX_op_orc_vec
:
2175 return have_vec
&& TCG_TARGET_HAS_orc_vec
;
2176 case INDEX_op_nand_vec
:
2177 return have_vec
&& TCG_TARGET_HAS_nand_vec
;
2178 case INDEX_op_nor_vec
:
2179 return have_vec
&& TCG_TARGET_HAS_nor_vec
;
2180 case INDEX_op_eqv_vec
:
2181 return have_vec
&& TCG_TARGET_HAS_eqv_vec
;
2182 case INDEX_op_mul_vec
:
2183 return have_vec
&& TCG_TARGET_HAS_mul_vec
;
2184 case INDEX_op_shli_vec
:
2185 case INDEX_op_shri_vec
:
2186 case INDEX_op_sari_vec
:
2187 return have_vec
&& TCG_TARGET_HAS_shi_vec
;
2188 case INDEX_op_shls_vec
:
2189 case INDEX_op_shrs_vec
:
2190 case INDEX_op_sars_vec
:
2191 return have_vec
&& TCG_TARGET_HAS_shs_vec
;
2192 case INDEX_op_shlv_vec
:
2193 case INDEX_op_shrv_vec
:
2194 case INDEX_op_sarv_vec
:
2195 return have_vec
&& TCG_TARGET_HAS_shv_vec
;
2196 case INDEX_op_rotli_vec
:
2197 return have_vec
&& TCG_TARGET_HAS_roti_vec
;
2198 case INDEX_op_rotls_vec
:
2199 return have_vec
&& TCG_TARGET_HAS_rots_vec
;
2200 case INDEX_op_rotlv_vec
:
2201 case INDEX_op_rotrv_vec
:
2202 return have_vec
&& TCG_TARGET_HAS_rotv_vec
;
2203 case INDEX_op_ssadd_vec
:
2204 case INDEX_op_usadd_vec
:
2205 case INDEX_op_sssub_vec
:
2206 case INDEX_op_ussub_vec
:
2207 return have_vec
&& TCG_TARGET_HAS_sat_vec
;
2208 case INDEX_op_smin_vec
:
2209 case INDEX_op_umin_vec
:
2210 case INDEX_op_smax_vec
:
2211 case INDEX_op_umax_vec
:
2212 return have_vec
&& TCG_TARGET_HAS_minmax_vec
;
2213 case INDEX_op_bitsel_vec
:
2214 return have_vec
&& TCG_TARGET_HAS_bitsel_vec
;
2215 case INDEX_op_cmpsel_vec
:
2216 return have_vec
&& TCG_TARGET_HAS_cmpsel_vec
;
2219 tcg_debug_assert(op
> INDEX_op_last_generic
&& op
< NB_OPS
);
2224 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
);
2226 static void tcg_gen_callN(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
**args
)
2228 TCGv_i64 extend_free
[MAX_CALL_IARGS
];
2231 int i
, n
, pi
= 0, total_args
;
2233 if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info
)))) {
2234 init_call_layout(info
);
2235 g_once_init_leave(HELPER_INFO_INIT(info
), HELPER_INFO_INIT_VAL(info
));
2238 total_args
= info
->nr_out
+ info
->nr_in
+ 2;
2239 op
= tcg_op_alloc(INDEX_op_call
, total_args
);
2241 #ifdef CONFIG_PLUGIN
2242 /* Flag helpers that may affect guest state */
2243 if (tcg_ctx
->plugin_insn
&&
2244 !(info
->flags
& TCG_CALL_PLUGIN
) &&
2245 !(info
->flags
& TCG_CALL_NO_SIDE_EFFECTS
)) {
2246 tcg_ctx
->plugin_insn
->calls_helpers
= true;
2250 TCGOP_CALLO(op
) = n
= info
->nr_out
;
2253 tcg_debug_assert(ret
== NULL
);
2256 tcg_debug_assert(ret
!= NULL
);
2257 op
->args
[pi
++] = temp_arg(ret
);
2261 tcg_debug_assert(ret
!= NULL
);
2262 tcg_debug_assert(ret
->base_type
== ret
->type
+ ctz32(n
));
2263 tcg_debug_assert(ret
->temp_subindex
== 0);
2264 for (i
= 0; i
< n
; ++i
) {
2265 op
->args
[pi
++] = temp_arg(ret
+ i
);
2269 g_assert_not_reached();
2272 TCGOP_CALLI(op
) = n
= info
->nr_in
;
2273 for (i
= 0; i
< n
; i
++) {
2274 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
2275 TCGTemp
*ts
= args
[loc
->arg_idx
] + loc
->tmp_subindex
;
2277 switch (loc
->kind
) {
2278 case TCG_CALL_ARG_NORMAL
:
2279 case TCG_CALL_ARG_BY_REF
:
2280 case TCG_CALL_ARG_BY_REF_N
:
2281 op
->args
[pi
++] = temp_arg(ts
);
2284 case TCG_CALL_ARG_EXTEND_U
:
2285 case TCG_CALL_ARG_EXTEND_S
:
2287 TCGv_i64 temp
= tcg_temp_ebb_new_i64();
2288 TCGv_i32 orig
= temp_tcgv_i32(ts
);
2290 if (loc
->kind
== TCG_CALL_ARG_EXTEND_S
) {
2291 tcg_gen_ext_i32_i64(temp
, orig
);
2293 tcg_gen_extu_i32_i64(temp
, orig
);
2295 op
->args
[pi
++] = tcgv_i64_arg(temp
);
2296 extend_free
[n_extend
++] = temp
;
2301 g_assert_not_reached();
2304 op
->args
[pi
++] = (uintptr_t)info
->func
;
2305 op
->args
[pi
++] = (uintptr_t)info
;
2306 tcg_debug_assert(pi
== total_args
);
2308 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2310 tcg_debug_assert(n_extend
< ARRAY_SIZE(extend_free
));
2311 for (i
= 0; i
< n_extend
; ++i
) {
2312 tcg_temp_free_i64(extend_free
[i
]);
2316 void tcg_gen_call0(TCGHelperInfo
*info
, TCGTemp
*ret
)
2318 tcg_gen_callN(info
, ret
, NULL
);
2321 void tcg_gen_call1(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
)
2323 tcg_gen_callN(info
, ret
, &t1
);
2326 void tcg_gen_call2(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
, TCGTemp
*t2
)
2328 TCGTemp
*args
[2] = { t1
, t2
};
2329 tcg_gen_callN(info
, ret
, args
);
2332 void tcg_gen_call3(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
,
2333 TCGTemp
*t2
, TCGTemp
*t3
)
2335 TCGTemp
*args
[3] = { t1
, t2
, t3
};
2336 tcg_gen_callN(info
, ret
, args
);
2339 void tcg_gen_call4(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
,
2340 TCGTemp
*t2
, TCGTemp
*t3
, TCGTemp
*t4
)
2342 TCGTemp
*args
[4] = { t1
, t2
, t3
, t4
};
2343 tcg_gen_callN(info
, ret
, args
);
2346 void tcg_gen_call5(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
,
2347 TCGTemp
*t2
, TCGTemp
*t3
, TCGTemp
*t4
, TCGTemp
*t5
)
2349 TCGTemp
*args
[5] = { t1
, t2
, t3
, t4
, t5
};
2350 tcg_gen_callN(info
, ret
, args
);
2353 void tcg_gen_call6(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
, TCGTemp
*t2
,
2354 TCGTemp
*t3
, TCGTemp
*t4
, TCGTemp
*t5
, TCGTemp
*t6
)
2356 TCGTemp
*args
[6] = { t1
, t2
, t3
, t4
, t5
, t6
};
2357 tcg_gen_callN(info
, ret
, args
);
2360 void tcg_gen_call7(TCGHelperInfo
*info
, TCGTemp
*ret
, TCGTemp
*t1
,
2361 TCGTemp
*t2
, TCGTemp
*t3
, TCGTemp
*t4
,
2362 TCGTemp
*t5
, TCGTemp
*t6
, TCGTemp
*t7
)
2364 TCGTemp
*args
[7] = { t1
, t2
, t3
, t4
, t5
, t6
, t7
};
2365 tcg_gen_callN(info
, ret
, args
);
2368 static void tcg_reg_alloc_start(TCGContext
*s
)
2372 for (i
= 0, n
= s
->nb_temps
; i
< n
; i
++) {
2373 TCGTemp
*ts
= &s
->temps
[i
];
2374 TCGTempVal val
= TEMP_VAL_MEM
;
2378 val
= TEMP_VAL_CONST
;
2386 val
= TEMP_VAL_DEAD
;
2389 ts
->mem_allocated
= 0;
2392 g_assert_not_reached();
2397 memset(s
->reg_to_temp
, 0, sizeof(s
->reg_to_temp
));
2400 static char *tcg_get_arg_str_ptr(TCGContext
*s
, char *buf
, int buf_size
,
2403 int idx
= temp_idx(ts
);
2408 pstrcpy(buf
, buf_size
, ts
->name
);
2411 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
2414 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
2419 snprintf(buf
, buf_size
, "$0x%x", (int32_t)ts
->val
);
2421 #if TCG_TARGET_REG_BITS > 32
2423 snprintf(buf
, buf_size
, "$0x%" PRIx64
, ts
->val
);
2429 snprintf(buf
, buf_size
, "v%d$0x%" PRIx64
,
2430 64 << (ts
->type
- TCG_TYPE_V64
), ts
->val
);
2433 g_assert_not_reached();
2440 static char *tcg_get_arg_str(TCGContext
*s
, char *buf
,
2441 int buf_size
, TCGArg arg
)
2443 return tcg_get_arg_str_ptr(s
, buf
, buf_size
, arg_temp(arg
));
2446 static const char * const cond_name
[] =
2448 [TCG_COND_NEVER
] = "never",
2449 [TCG_COND_ALWAYS
] = "always",
2450 [TCG_COND_EQ
] = "eq",
2451 [TCG_COND_NE
] = "ne",
2452 [TCG_COND_LT
] = "lt",
2453 [TCG_COND_GE
] = "ge",
2454 [TCG_COND_LE
] = "le",
2455 [TCG_COND_GT
] = "gt",
2456 [TCG_COND_LTU
] = "ltu",
2457 [TCG_COND_GEU
] = "geu",
2458 [TCG_COND_LEU
] = "leu",
2459 [TCG_COND_GTU
] = "gtu"
2462 static const char * const ldst_name
[(MO_BSWAP
| MO_SSIZE
) + 1] =
2476 [MO_128
+ MO_BE
] = "beo",
2477 [MO_128
+ MO_LE
] = "leo",
2480 static const char * const alignment_name
[(MO_AMASK
>> MO_ASHIFT
) + 1] = {
2481 [MO_UNALN
>> MO_ASHIFT
] = "un+",
2482 [MO_ALIGN
>> MO_ASHIFT
] = "al+",
2483 [MO_ALIGN_2
>> MO_ASHIFT
] = "al2+",
2484 [MO_ALIGN_4
>> MO_ASHIFT
] = "al4+",
2485 [MO_ALIGN_8
>> MO_ASHIFT
] = "al8+",
2486 [MO_ALIGN_16
>> MO_ASHIFT
] = "al16+",
2487 [MO_ALIGN_32
>> MO_ASHIFT
] = "al32+",
2488 [MO_ALIGN_64
>> MO_ASHIFT
] = "al64+",
2491 static const char * const atom_name
[(MO_ATOM_MASK
>> MO_ATOM_SHIFT
) + 1] = {
2492 [MO_ATOM_IFALIGN
>> MO_ATOM_SHIFT
] = "",
2493 [MO_ATOM_IFALIGN_PAIR
>> MO_ATOM_SHIFT
] = "pair+",
2494 [MO_ATOM_WITHIN16
>> MO_ATOM_SHIFT
] = "w16+",
2495 [MO_ATOM_WITHIN16_PAIR
>> MO_ATOM_SHIFT
] = "w16p+",
2496 [MO_ATOM_SUBALIGN
>> MO_ATOM_SHIFT
] = "sub+",
2497 [MO_ATOM_NONE
>> MO_ATOM_SHIFT
] = "noat+",
2500 static const char bswap_flag_name
[][6] = {
2501 [TCG_BSWAP_IZ
] = "iz",
2502 [TCG_BSWAP_OZ
] = "oz",
2503 [TCG_BSWAP_OS
] = "os",
2504 [TCG_BSWAP_IZ
| TCG_BSWAP_OZ
] = "iz,oz",
2505 [TCG_BSWAP_IZ
| TCG_BSWAP_OS
] = "iz,os",
2508 static inline bool tcg_regset_single(TCGRegSet d
)
2510 return (d
& (d
- 1)) == 0;
2513 static inline TCGReg
tcg_regset_first(TCGRegSet d
)
2515 if (TCG_TARGET_NB_REGS
<= 32) {
2522 /* Return only the number of characters output -- no error return. */
2523 #define ne_fprintf(...) \
2524 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; })
2526 static void tcg_dump_ops(TCGContext
*s
, FILE *f
, bool have_prefs
)
2531 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
2532 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
2533 const TCGOpDef
*def
;
2538 def
= &tcg_op_defs
[c
];
2540 if (c
== INDEX_op_insn_start
) {
2542 col
+= ne_fprintf(f
, "\n ----");
2544 for (i
= 0, k
= s
->insn_start_words
; i
< k
; ++i
) {
2545 col
+= ne_fprintf(f
, " %016" PRIx64
,
2546 tcg_get_insn_start_param(op
, i
));
2548 } else if (c
== INDEX_op_call
) {
2549 const TCGHelperInfo
*info
= tcg_call_info(op
);
2550 void *func
= tcg_call_func(op
);
2552 /* variable number of arguments */
2553 nb_oargs
= TCGOP_CALLO(op
);
2554 nb_iargs
= TCGOP_CALLI(op
);
2555 nb_cargs
= def
->nb_cargs
;
2557 col
+= ne_fprintf(f
, " %s ", def
->name
);
2560 * Print the function name from TCGHelperInfo, if available.
2561 * Note that plugins have a template function for the info,
2562 * but the actual function pointer comes from the plugin.
2564 if (func
== info
->func
) {
2565 col
+= ne_fprintf(f
, "%s", info
->name
);
2567 col
+= ne_fprintf(f
, "plugin(%p)", func
);
2570 col
+= ne_fprintf(f
, ",$0x%x,$%d", info
->flags
, nb_oargs
);
2571 for (i
= 0; i
< nb_oargs
; i
++) {
2572 col
+= ne_fprintf(f
, ",%s", tcg_get_arg_str(s
, buf
, sizeof(buf
),
2575 for (i
= 0; i
< nb_iargs
; i
++) {
2576 TCGArg arg
= op
->args
[nb_oargs
+ i
];
2577 const char *t
= tcg_get_arg_str(s
, buf
, sizeof(buf
), arg
);
2578 col
+= ne_fprintf(f
, ",%s", t
);
2581 col
+= ne_fprintf(f
, " %s ", def
->name
);
2583 nb_oargs
= def
->nb_oargs
;
2584 nb_iargs
= def
->nb_iargs
;
2585 nb_cargs
= def
->nb_cargs
;
2587 if (def
->flags
& TCG_OPF_VECTOR
) {
2588 col
+= ne_fprintf(f
, "v%d,e%d,", 64 << TCGOP_VECL(op
),
2589 8 << TCGOP_VECE(op
));
2593 for (i
= 0; i
< nb_oargs
; i
++) {
2594 const char *sep
= k
? "," : "";
2595 col
+= ne_fprintf(f
, "%s%s", sep
,
2596 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2599 for (i
= 0; i
< nb_iargs
; i
++) {
2600 const char *sep
= k
? "," : "";
2601 col
+= ne_fprintf(f
, "%s%s", sep
,
2602 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2606 case INDEX_op_brcond_i32
:
2607 case INDEX_op_setcond_i32
:
2608 case INDEX_op_negsetcond_i32
:
2609 case INDEX_op_movcond_i32
:
2610 case INDEX_op_brcond2_i32
:
2611 case INDEX_op_setcond2_i32
:
2612 case INDEX_op_brcond_i64
:
2613 case INDEX_op_setcond_i64
:
2614 case INDEX_op_negsetcond_i64
:
2615 case INDEX_op_movcond_i64
:
2616 case INDEX_op_cmp_vec
:
2617 case INDEX_op_cmpsel_vec
:
2618 if (op
->args
[k
] < ARRAY_SIZE(cond_name
)
2619 && cond_name
[op
->args
[k
]]) {
2620 col
+= ne_fprintf(f
, ",%s", cond_name
[op
->args
[k
++]]);
2622 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, op
->args
[k
++]);
2626 case INDEX_op_qemu_ld_a32_i32
:
2627 case INDEX_op_qemu_ld_a64_i32
:
2628 case INDEX_op_qemu_st_a32_i32
:
2629 case INDEX_op_qemu_st_a64_i32
:
2630 case INDEX_op_qemu_st8_a32_i32
:
2631 case INDEX_op_qemu_st8_a64_i32
:
2632 case INDEX_op_qemu_ld_a32_i64
:
2633 case INDEX_op_qemu_ld_a64_i64
:
2634 case INDEX_op_qemu_st_a32_i64
:
2635 case INDEX_op_qemu_st_a64_i64
:
2636 case INDEX_op_qemu_ld_a32_i128
:
2637 case INDEX_op_qemu_ld_a64_i128
:
2638 case INDEX_op_qemu_st_a32_i128
:
2639 case INDEX_op_qemu_st_a64_i128
:
2641 const char *s_al
, *s_op
, *s_at
;
2642 MemOpIdx oi
= op
->args
[k
++];
2643 MemOp mop
= get_memop(oi
);
2644 unsigned ix
= get_mmuidx(oi
);
2646 s_al
= alignment_name
[(mop
& MO_AMASK
) >> MO_ASHIFT
];
2647 s_op
= ldst_name
[mop
& (MO_BSWAP
| MO_SSIZE
)];
2648 s_at
= atom_name
[(mop
& MO_ATOM_MASK
) >> MO_ATOM_SHIFT
];
2649 mop
&= ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
| MO_ATOM_MASK
);
2651 /* If all fields are accounted for, print symbolically. */
2652 if (!mop
&& s_al
&& s_op
&& s_at
) {
2653 col
+= ne_fprintf(f
, ",%s%s%s,%u",
2654 s_at
, s_al
, s_op
, ix
);
2656 mop
= get_memop(oi
);
2657 col
+= ne_fprintf(f
, ",$0x%x,%u", mop
, ix
);
2662 case INDEX_op_bswap16_i32
:
2663 case INDEX_op_bswap16_i64
:
2664 case INDEX_op_bswap32_i32
:
2665 case INDEX_op_bswap32_i64
:
2666 case INDEX_op_bswap64_i64
:
2668 TCGArg flags
= op
->args
[k
];
2669 const char *name
= NULL
;
2671 if (flags
< ARRAY_SIZE(bswap_flag_name
)) {
2672 name
= bswap_flag_name
[flags
];
2675 col
+= ne_fprintf(f
, ",%s", name
);
2677 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, flags
);
2687 case INDEX_op_set_label
:
2689 case INDEX_op_brcond_i32
:
2690 case INDEX_op_brcond_i64
:
2691 case INDEX_op_brcond2_i32
:
2692 col
+= ne_fprintf(f
, "%s$L%d", k
? "," : "",
2693 arg_label(op
->args
[k
])->id
);
2698 TCGBar membar
= op
->args
[k
];
2699 const char *b_op
, *m_op
;
2701 switch (membar
& TCG_BAR_SC
) {
2715 g_assert_not_reached();
2718 switch (membar
& TCG_MO_ALL
) {
2734 case TCG_MO_LD_LD
| TCG_MO_LD_ST
:
2737 case TCG_MO_LD_LD
| TCG_MO_ST_LD
:
2740 case TCG_MO_LD_LD
| TCG_MO_ST_ST
:
2743 case TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2746 case TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2749 case TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2752 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2755 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2758 case TCG_MO_LD_LD
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2761 case TCG_MO_LD_ST
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2768 g_assert_not_reached();
2771 col
+= ne_fprintf(f
, "%s%s:%s", (k
? "," : ""), b_op
, m_op
);
2778 for (; i
< nb_cargs
; i
++, k
++) {
2779 col
+= ne_fprintf(f
, "%s$0x%" TCG_PRIlx
, k
? "," : "",
2784 if (have_prefs
|| op
->life
) {
2785 for (; col
< 40; ++col
) {
2791 unsigned life
= op
->life
;
2793 if (life
& (SYNC_ARG
* 3)) {
2794 ne_fprintf(f
, " sync:");
2795 for (i
= 0; i
< 2; ++i
) {
2796 if (life
& (SYNC_ARG
<< i
)) {
2797 ne_fprintf(f
, " %d", i
);
2803 ne_fprintf(f
, " dead:");
2804 for (i
= 0; life
; ++i
, life
>>= 1) {
2806 ne_fprintf(f
, " %d", i
);
2813 for (i
= 0; i
< nb_oargs
; ++i
) {
2814 TCGRegSet set
= output_pref(op
, i
);
2817 ne_fprintf(f
, " pref=");
2822 ne_fprintf(f
, "none");
2823 } else if (set
== MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS
)) {
2824 ne_fprintf(f
, "all");
2825 #ifdef CONFIG_DEBUG_TCG
2826 } else if (tcg_regset_single(set
)) {
2827 TCGReg reg
= tcg_regset_first(set
);
2828 ne_fprintf(f
, "%s", tcg_target_reg_names
[reg
]);
2830 } else if (TCG_TARGET_NB_REGS
<= 32) {
2831 ne_fprintf(f
, "0x%x", (uint32_t)set
);
2833 ne_fprintf(f
, "0x%" PRIx64
, (uint64_t)set
);
2842 /* we give more priority to constraints with less registers */
2843 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
2845 const TCGArgConstraint
*arg_ct
= &def
->args_ct
[k
];
2846 int n
= ctpop64(arg_ct
->regs
);
2849 * Sort constraints of a single register first, which includes output
2850 * aliases (which must exactly match the input already allocated).
2852 if (n
== 1 || arg_ct
->oalias
) {
2857 * Sort register pairs next, first then second immediately after.
2858 * Arbitrarily sort multiple pairs by the index of the first reg;
2859 * there shouldn't be many pairs.
2861 switch (arg_ct
->pair
) {
2866 return (arg_ct
->pair_index
+ 1) * 2 - 1;
2869 /* Finally, sort by decreasing register count. */
2874 /* sort from highest priority to lowest */
2875 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
2878 TCGArgConstraint
*a
= def
->args_ct
;
2880 for (i
= 0; i
< n
; i
++) {
2881 a
[start
+ i
].sort_index
= start
+ i
;
2886 for (i
= 0; i
< n
- 1; i
++) {
2887 for (j
= i
+ 1; j
< n
; j
++) {
2888 int p1
= get_constraint_priority(def
, a
[start
+ i
].sort_index
);
2889 int p2
= get_constraint_priority(def
, a
[start
+ j
].sort_index
);
2891 int tmp
= a
[start
+ i
].sort_index
;
2892 a
[start
+ i
].sort_index
= a
[start
+ j
].sort_index
;
2893 a
[start
+ j
].sort_index
= tmp
;
2899 static void process_op_defs(TCGContext
*s
)
2903 for (op
= 0; op
< NB_OPS
; op
++) {
2904 TCGOpDef
*def
= &tcg_op_defs
[op
];
2905 const TCGTargetOpDef
*tdefs
;
2906 bool saw_alias_pair
= false;
2907 int i
, o
, i2
, o2
, nb_args
;
2909 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2913 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
2919 * Macro magic should make it impossible, but double-check that
2920 * the array index is in range. Since the signness of an enum
2921 * is implementation defined, force the result to unsigned.
2923 unsigned con_set
= tcg_target_op_def(op
);
2924 tcg_debug_assert(con_set
< ARRAY_SIZE(constraint_sets
));
2925 tdefs
= &constraint_sets
[con_set
];
2927 for (i
= 0; i
< nb_args
; i
++) {
2928 const char *ct_str
= tdefs
->args_ct_str
[i
];
2929 bool input_p
= i
>= def
->nb_oargs
;
2931 /* Incomplete TCGTargetOpDef entry. */
2932 tcg_debug_assert(ct_str
!= NULL
);
2937 tcg_debug_assert(input_p
);
2938 tcg_debug_assert(o
< def
->nb_oargs
);
2939 tcg_debug_assert(def
->args_ct
[o
].regs
!= 0);
2940 tcg_debug_assert(!def
->args_ct
[o
].oalias
);
2941 def
->args_ct
[i
] = def
->args_ct
[o
];
2942 /* The output sets oalias. */
2943 def
->args_ct
[o
].oalias
= 1;
2944 def
->args_ct
[o
].alias_index
= i
;
2945 /* The input sets ialias. */
2946 def
->args_ct
[i
].ialias
= 1;
2947 def
->args_ct
[i
].alias_index
= o
;
2948 if (def
->args_ct
[i
].pair
) {
2949 saw_alias_pair
= true;
2951 tcg_debug_assert(ct_str
[1] == '\0');
2955 tcg_debug_assert(!input_p
);
2956 def
->args_ct
[i
].newreg
= true;
2960 case 'p': /* plus */
2961 /* Allocate to the register after the previous. */
2962 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2964 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2965 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2966 def
->args_ct
[i
] = (TCGArgConstraint
){
2969 .regs
= def
->args_ct
[o
].regs
<< 1,
2971 def
->args_ct
[o
].pair
= 1;
2972 def
->args_ct
[o
].pair_index
= i
;
2973 tcg_debug_assert(ct_str
[1] == '\0');
2976 case 'm': /* minus */
2977 /* Allocate to the register before the previous. */
2978 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2980 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2981 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2982 def
->args_ct
[i
] = (TCGArgConstraint
){
2985 .regs
= def
->args_ct
[o
].regs
>> 1,
2987 def
->args_ct
[o
].pair
= 2;
2988 def
->args_ct
[o
].pair_index
= i
;
2989 tcg_debug_assert(ct_str
[1] == '\0');
2996 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
2999 /* Include all of the target-specific constraints. */
3002 #define CONST(CASE, MASK) \
3003 case CASE: def->args_ct[i].ct |= MASK; break;
3004 #define REGS(CASE, MASK) \
3005 case CASE: def->args_ct[i].regs |= MASK; break;
3007 #include "tcg-target-con-str.h"
3016 /* Typo in TCGTargetOpDef constraint. */
3017 g_assert_not_reached();
3019 } while (*++ct_str
!= '\0');
3022 /* TCGTargetOpDef entry with too much information? */
3023 tcg_debug_assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
3026 * Fix up output pairs that are aliased with inputs.
3027 * When we created the alias, we copied pair from the output.
3028 * There are three cases:
3029 * (1a) Pairs of inputs alias pairs of outputs.
3030 * (1b) One input aliases the first of a pair of outputs.
3031 * (2) One input aliases the second of a pair of outputs.
3033 * Case 1a is handled by making sure that the pair_index'es are
3034 * properly updated so that they appear the same as a pair of inputs.
3036 * Case 1b is handled by setting the pair_index of the input to
3037 * itself, simply so it doesn't point to an unrelated argument.
3038 * Since we don't encounter the "second" during the input allocation
3039 * phase, nothing happens with the second half of the input pair.
3041 * Case 2 is handled by setting the second input to pair=3, the
3042 * first output to pair=3, and the pair_index'es to match.
3044 if (saw_alias_pair
) {
3045 for (i
= def
->nb_oargs
; i
< nb_args
; i
++) {
3047 * Since [0-9pm] must be alone in the constraint string,
3048 * the only way they can both be set is if the pair comes
3049 * from the output alias.
3051 if (!def
->args_ct
[i
].ialias
) {
3054 switch (def
->args_ct
[i
].pair
) {
3058 o
= def
->args_ct
[i
].alias_index
;
3059 o2
= def
->args_ct
[o
].pair_index
;
3060 tcg_debug_assert(def
->args_ct
[o
].pair
== 1);
3061 tcg_debug_assert(def
->args_ct
[o2
].pair
== 2);
3062 if (def
->args_ct
[o2
].oalias
) {
3064 i2
= def
->args_ct
[o2
].alias_index
;
3065 tcg_debug_assert(def
->args_ct
[i2
].pair
== 2);
3066 def
->args_ct
[i2
].pair_index
= i
;
3067 def
->args_ct
[i
].pair_index
= i2
;
3070 def
->args_ct
[i
].pair_index
= i
;
3074 o
= def
->args_ct
[i
].alias_index
;
3075 o2
= def
->args_ct
[o
].pair_index
;
3076 tcg_debug_assert(def
->args_ct
[o
].pair
== 2);
3077 tcg_debug_assert(def
->args_ct
[o2
].pair
== 1);
3078 if (def
->args_ct
[o2
].oalias
) {
3080 i2
= def
->args_ct
[o2
].alias_index
;
3081 tcg_debug_assert(def
->args_ct
[i2
].pair
== 1);
3082 def
->args_ct
[i2
].pair_index
= i
;
3083 def
->args_ct
[i
].pair_index
= i2
;
3086 def
->args_ct
[i
].pair
= 3;
3087 def
->args_ct
[o2
].pair
= 3;
3088 def
->args_ct
[i
].pair_index
= o2
;
3089 def
->args_ct
[o2
].pair_index
= i
;
3093 g_assert_not_reached();
3098 /* sort the constraints (XXX: this is just an heuristic) */
3099 sort_constraints(def
, 0, def
->nb_oargs
);
3100 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
3104 static void remove_label_use(TCGOp
*op
, int idx
)
3106 TCGLabel
*label
= arg_label(op
->args
[idx
]);
3109 QSIMPLEQ_FOREACH(use
, &label
->branches
, next
) {
3110 if (use
->op
== op
) {
3111 QSIMPLEQ_REMOVE(&label
->branches
, use
, TCGLabelUse
, next
);
3115 g_assert_not_reached();
3118 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
3122 remove_label_use(op
, 0);
3124 case INDEX_op_brcond_i32
:
3125 case INDEX_op_brcond_i64
:
3126 remove_label_use(op
, 3);
3128 case INDEX_op_brcond2_i32
:
3129 remove_label_use(op
, 5);
3135 QTAILQ_REMOVE(&s
->ops
, op
, link
);
3136 QTAILQ_INSERT_TAIL(&s
->free_ops
, op
, link
);
3140 void tcg_remove_ops_after(TCGOp
*op
)
3142 TCGContext
*s
= tcg_ctx
;
3145 TCGOp
*last
= tcg_last_op();
3149 tcg_op_remove(s
, last
);
3153 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
)
3155 TCGContext
*s
= tcg_ctx
;
3158 if (unlikely(!QTAILQ_EMPTY(&s
->free_ops
))) {
3159 QTAILQ_FOREACH(op
, &s
->free_ops
, link
) {
3160 if (nargs
<= op
->nargs
) {
3161 QTAILQ_REMOVE(&s
->free_ops
, op
, link
);
3168 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */
3169 nargs
= MAX(4, nargs
);
3170 op
= tcg_malloc(sizeof(TCGOp
) + sizeof(TCGArg
) * nargs
);
3173 memset(op
, 0, offsetof(TCGOp
, link
));
3177 /* Check for bitfield overflow. */
3178 tcg_debug_assert(op
->nargs
== nargs
);
3184 TCGOp
*tcg_emit_op(TCGOpcode opc
, unsigned nargs
)
3186 TCGOp
*op
= tcg_op_alloc(opc
, nargs
);
3187 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
3191 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*old_op
,
3192 TCGOpcode opc
, unsigned nargs
)
3194 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
3195 QTAILQ_INSERT_BEFORE(old_op
, new_op
, link
);
3199 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*old_op
,
3200 TCGOpcode opc
, unsigned nargs
)
3202 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
3203 QTAILQ_INSERT_AFTER(&s
->ops
, old_op
, new_op
, link
);
3207 static void move_label_uses(TCGLabel
*to
, TCGLabel
*from
)
3211 QSIMPLEQ_FOREACH(u
, &from
->branches
, next
) {
3215 op
->args
[0] = label_arg(to
);
3217 case INDEX_op_brcond_i32
:
3218 case INDEX_op_brcond_i64
:
3219 op
->args
[3] = label_arg(to
);
3221 case INDEX_op_brcond2_i32
:
3222 op
->args
[5] = label_arg(to
);
3225 g_assert_not_reached();
3229 QSIMPLEQ_CONCAT(&to
->branches
, &from
->branches
);
3232 /* Reachable analysis : remove unreachable code. */
3233 static void __attribute__((noinline
))
3234 reachable_code_pass(TCGContext
*s
)
3236 TCGOp
*op
, *op_next
, *op_prev
;
3239 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3244 case INDEX_op_set_label
:
3245 label
= arg_label(op
->args
[0]);
3248 * Note that the first op in the TB is always a load,
3249 * so there is always something before a label.
3251 op_prev
= QTAILQ_PREV(op
, link
);
3254 * If we find two sequential labels, move all branches to
3255 * reference the second label and remove the first label.
3256 * Do this before branch to next optimization, so that the
3257 * middle label is out of the way.
3259 if (op_prev
->opc
== INDEX_op_set_label
) {
3260 move_label_uses(label
, arg_label(op_prev
->args
[0]));
3261 tcg_op_remove(s
, op_prev
);
3262 op_prev
= QTAILQ_PREV(op
, link
);
3266 * Optimization can fold conditional branches to unconditional.
3267 * If we find a label which is preceded by an unconditional
3268 * branch to next, remove the branch. We couldn't do this when
3269 * processing the branch because any dead code between the branch
3270 * and label had not yet been removed.
3272 if (op_prev
->opc
== INDEX_op_br
&&
3273 label
== arg_label(op_prev
->args
[0])) {
3274 tcg_op_remove(s
, op_prev
);
3275 /* Fall through means insns become live again. */
3279 if (QSIMPLEQ_EMPTY(&label
->branches
)) {
3281 * While there is an occasional backward branch, virtually
3282 * all branches generated by the translators are forward.
3283 * Which means that generally we will have already removed
3284 * all references to the label that will be, and there is
3285 * little to be gained by iterating.
3289 /* Once we see a label, insns become live again. */
3296 case INDEX_op_exit_tb
:
3297 case INDEX_op_goto_ptr
:
3298 /* Unconditional branches; everything following is dead. */
3303 /* Notice noreturn helper calls, raising exceptions. */
3304 if (tcg_call_flags(op
) & TCG_CALL_NO_RETURN
) {
3309 case INDEX_op_insn_start
:
3310 /* Never remove -- we need to keep these for unwind. */
3319 tcg_op_remove(s
, op
);
3327 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
3328 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
3330 /* For liveness_pass_1, the register preferences for a given temp. */
3331 static inline TCGRegSet
*la_temp_pref(TCGTemp
*ts
)
3333 return ts
->state_ptr
;
3336 /* For liveness_pass_1, reset the preferences for a given temp to the
3337 * maximal regset for its type.
3339 static inline void la_reset_pref(TCGTemp
*ts
)
3342 = (ts
->state
== TS_DEAD
? 0 : tcg_target_available_regs
[ts
->type
]);
3345 /* liveness analysis: end of function: all temps are dead, and globals
3346 should be in memory. */
3347 static void la_func_end(TCGContext
*s
, int ng
, int nt
)
3351 for (i
= 0; i
< ng
; ++i
) {
3352 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3353 la_reset_pref(&s
->temps
[i
]);
3355 for (i
= ng
; i
< nt
; ++i
) {
3356 s
->temps
[i
].state
= TS_DEAD
;
3357 la_reset_pref(&s
->temps
[i
]);
3361 /* liveness analysis: end of basic block: all temps are dead, globals
3362 and local temps should be in memory. */
3363 static void la_bb_end(TCGContext
*s
, int ng
, int nt
)
3367 for (i
= 0; i
< nt
; ++i
) {
3368 TCGTemp
*ts
= &s
->temps
[i
];
3375 state
= TS_DEAD
| TS_MEM
;
3382 g_assert_not_reached();
3389 /* liveness analysis: sync globals back to memory. */
3390 static void la_global_sync(TCGContext
*s
, int ng
)
3394 for (i
= 0; i
< ng
; ++i
) {
3395 int state
= s
->temps
[i
].state
;
3396 s
->temps
[i
].state
= state
| TS_MEM
;
3397 if (state
== TS_DEAD
) {
3398 /* If the global was previously dead, reset prefs. */
3399 la_reset_pref(&s
->temps
[i
]);
3405 * liveness analysis: conditional branch: all temps are dead unless
3406 * explicitly live-across-conditional-branch, globals and local temps
3409 static void la_bb_sync(TCGContext
*s
, int ng
, int nt
)
3411 la_global_sync(s
, ng
);
3413 for (int i
= ng
; i
< nt
; ++i
) {
3414 TCGTemp
*ts
= &s
->temps
[i
];
3420 ts
->state
= state
| TS_MEM
;
3421 if (state
!= TS_DEAD
) {
3429 g_assert_not_reached();
3431 la_reset_pref(&s
->temps
[i
]);
3435 /* liveness analysis: sync globals back to memory and kill. */
3436 static void la_global_kill(TCGContext
*s
, int ng
)
3440 for (i
= 0; i
< ng
; i
++) {
3441 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3442 la_reset_pref(&s
->temps
[i
]);
3446 /* liveness analysis: note live globals crossing calls. */
3447 static void la_cross_call(TCGContext
*s
, int nt
)
3449 TCGRegSet mask
= ~tcg_target_call_clobber_regs
;
3452 for (i
= 0; i
< nt
; i
++) {
3453 TCGTemp
*ts
= &s
->temps
[i
];
3454 if (!(ts
->state
& TS_DEAD
)) {
3455 TCGRegSet
*pset
= la_temp_pref(ts
);
3456 TCGRegSet set
= *pset
;
3459 /* If the combination is not possible, restart. */
3461 set
= tcg_target_available_regs
[ts
->type
] & mask
;
3469 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce
3470 * to TEMP_EBB, if possible.
3472 static void __attribute__((noinline
))
3473 liveness_pass_0(TCGContext
*s
)
3475 void * const multiple_ebb
= (void *)(uintptr_t)-1;
3476 int nb_temps
= s
->nb_temps
;
3479 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3480 s
->temps
[i
].state_ptr
= NULL
;
3484 * Represent each EBB by the op at which it begins. In the case of
3485 * the first EBB, this is the first op, otherwise it is a label.
3486 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use
3487 * within a single EBB, else MULTIPLE_EBB.
3489 ebb
= QTAILQ_FIRST(&s
->ops
);
3490 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
3491 const TCGOpDef
*def
;
3492 int nb_oargs
, nb_iargs
;
3495 case INDEX_op_set_label
:
3498 case INDEX_op_discard
:
3501 nb_oargs
= TCGOP_CALLO(op
);
3502 nb_iargs
= TCGOP_CALLI(op
);
3505 def
= &tcg_op_defs
[op
->opc
];
3506 nb_oargs
= def
->nb_oargs
;
3507 nb_iargs
= def
->nb_iargs
;
3511 for (int i
= 0; i
< nb_oargs
+ nb_iargs
; ++i
) {
3512 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
3514 if (ts
->kind
!= TEMP_TB
) {
3517 if (ts
->state_ptr
== NULL
) {
3518 ts
->state_ptr
= ebb
;
3519 } else if (ts
->state_ptr
!= ebb
) {
3520 ts
->state_ptr
= multiple_ebb
;
3526 * For TEMP_TB that turned out not to be used beyond one EBB,
3527 * reduce the liveness to TEMP_EBB.
3529 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3530 TCGTemp
*ts
= &s
->temps
[i
];
3531 if (ts
->kind
== TEMP_TB
&& ts
->state_ptr
!= multiple_ebb
) {
3532 ts
->kind
= TEMP_EBB
;
3537 /* Liveness analysis : update the opc_arg_life array to tell if a
3538 given input arguments is dead. Instructions updating dead
3539 temporaries are removed. */
3540 static void __attribute__((noinline
))
3541 liveness_pass_1(TCGContext
*s
)
3543 int nb_globals
= s
->nb_globals
;
3544 int nb_temps
= s
->nb_temps
;
3545 TCGOp
*op
, *op_prev
;
3549 prefs
= tcg_malloc(sizeof(TCGRegSet
) * nb_temps
);
3550 for (i
= 0; i
< nb_temps
; ++i
) {
3551 s
->temps
[i
].state_ptr
= prefs
+ i
;
3554 /* ??? Should be redundant with the exit_tb that ends the TB. */
3555 la_func_end(s
, nb_globals
, nb_temps
);
3557 QTAILQ_FOREACH_REVERSE_SAFE(op
, &s
->ops
, link
, op_prev
) {
3558 int nb_iargs
, nb_oargs
;
3559 TCGOpcode opc_new
, opc_new2
;
3561 TCGLifeData arg_life
= 0;
3563 TCGOpcode opc
= op
->opc
;
3564 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3569 const TCGHelperInfo
*info
= tcg_call_info(op
);
3570 int call_flags
= tcg_call_flags(op
);
3572 nb_oargs
= TCGOP_CALLO(op
);
3573 nb_iargs
= TCGOP_CALLI(op
);
3575 /* pure functions can be removed if their result is unused */
3576 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
3577 for (i
= 0; i
< nb_oargs
; i
++) {
3578 ts
= arg_temp(op
->args
[i
]);
3579 if (ts
->state
!= TS_DEAD
) {
3580 goto do_not_remove_call
;
3587 /* Output args are dead. */
3588 for (i
= 0; i
< nb_oargs
; i
++) {
3589 ts
= arg_temp(op
->args
[i
]);
3590 if (ts
->state
& TS_DEAD
) {
3591 arg_life
|= DEAD_ARG
<< i
;
3593 if (ts
->state
& TS_MEM
) {
3594 arg_life
|= SYNC_ARG
<< i
;
3596 ts
->state
= TS_DEAD
;
3600 /* Not used -- it will be tcg_target_call_oarg_reg(). */
3601 memset(op
->output_pref
, 0, sizeof(op
->output_pref
));
3603 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
3604 TCG_CALL_NO_READ_GLOBALS
))) {
3605 la_global_kill(s
, nb_globals
);
3606 } else if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
3607 la_global_sync(s
, nb_globals
);
3610 /* Record arguments that die in this helper. */
3611 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3612 ts
= arg_temp(op
->args
[i
]);
3613 if (ts
->state
& TS_DEAD
) {
3614 arg_life
|= DEAD_ARG
<< i
;
3618 /* For all live registers, remove call-clobbered prefs. */
3619 la_cross_call(s
, nb_temps
);
3622 * Input arguments are live for preceding opcodes.
3624 * For those arguments that die, and will be allocated in
3625 * registers, clear the register set for that arg, to be
3626 * filled in below. For args that will be on the stack,
3627 * reset to any available reg. Process arguments in reverse
3628 * order so that if a temp is used more than once, the stack
3629 * reset to max happens before the register reset to 0.
3631 for (i
= nb_iargs
- 1; i
>= 0; i
--) {
3632 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3633 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3635 if (ts
->state
& TS_DEAD
) {
3636 switch (loc
->kind
) {
3637 case TCG_CALL_ARG_NORMAL
:
3638 case TCG_CALL_ARG_EXTEND_U
:
3639 case TCG_CALL_ARG_EXTEND_S
:
3640 if (arg_slot_reg_p(loc
->arg_slot
)) {
3641 *la_temp_pref(ts
) = 0;
3647 tcg_target_available_regs
[ts
->type
];
3650 ts
->state
&= ~TS_DEAD
;
3655 * For each input argument, add its input register to prefs.
3656 * If a temp is used once, this produces a single set bit;
3657 * if a temp is used multiple times, this produces a set.
3659 for (i
= 0; i
< nb_iargs
; i
++) {
3660 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3661 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3663 switch (loc
->kind
) {
3664 case TCG_CALL_ARG_NORMAL
:
3665 case TCG_CALL_ARG_EXTEND_U
:
3666 case TCG_CALL_ARG_EXTEND_S
:
3667 if (arg_slot_reg_p(loc
->arg_slot
)) {
3668 tcg_regset_set_reg(*la_temp_pref(ts
),
3669 tcg_target_call_iarg_regs
[loc
->arg_slot
]);
3678 case INDEX_op_insn_start
:
3680 case INDEX_op_discard
:
3681 /* mark the temporary as dead */
3682 ts
= arg_temp(op
->args
[0]);
3683 ts
->state
= TS_DEAD
;
3687 case INDEX_op_add2_i32
:
3688 opc_new
= INDEX_op_add_i32
;
3690 case INDEX_op_sub2_i32
:
3691 opc_new
= INDEX_op_sub_i32
;
3693 case INDEX_op_add2_i64
:
3694 opc_new
= INDEX_op_add_i64
;
3696 case INDEX_op_sub2_i64
:
3697 opc_new
= INDEX_op_sub_i64
;
3701 /* Test if the high part of the operation is dead, but not
3702 the low part. The result can be optimized to a simple
3703 add or sub. This happens often for x86_64 guest when the
3704 cpu mode is set to 32 bit. */
3705 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3706 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3709 /* Replace the opcode and adjust the args in place,
3710 leaving 3 unused args at the end. */
3711 op
->opc
= opc
= opc_new
;
3712 op
->args
[1] = op
->args
[2];
3713 op
->args
[2] = op
->args
[4];
3714 /* Fall through and mark the single-word operation live. */
3720 case INDEX_op_mulu2_i32
:
3721 opc_new
= INDEX_op_mul_i32
;
3722 opc_new2
= INDEX_op_muluh_i32
;
3723 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
3725 case INDEX_op_muls2_i32
:
3726 opc_new
= INDEX_op_mul_i32
;
3727 opc_new2
= INDEX_op_mulsh_i32
;
3728 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
3730 case INDEX_op_mulu2_i64
:
3731 opc_new
= INDEX_op_mul_i64
;
3732 opc_new2
= INDEX_op_muluh_i64
;
3733 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
3735 case INDEX_op_muls2_i64
:
3736 opc_new
= INDEX_op_mul_i64
;
3737 opc_new2
= INDEX_op_mulsh_i64
;
3738 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
3743 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3744 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3745 /* Both parts of the operation are dead. */
3748 /* The high part of the operation is dead; generate the low. */
3749 op
->opc
= opc
= opc_new
;
3750 op
->args
[1] = op
->args
[2];
3751 op
->args
[2] = op
->args
[3];
3752 } else if (arg_temp(op
->args
[0])->state
== TS_DEAD
&& have_opc_new2
) {
3753 /* The low part of the operation is dead; generate the high. */
3754 op
->opc
= opc
= opc_new2
;
3755 op
->args
[0] = op
->args
[1];
3756 op
->args
[1] = op
->args
[2];
3757 op
->args
[2] = op
->args
[3];
3761 /* Mark the single-word operation live. */
3766 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
3767 nb_iargs
= def
->nb_iargs
;
3768 nb_oargs
= def
->nb_oargs
;
3770 /* Test if the operation can be removed because all
3771 its outputs are dead. We assume that nb_oargs == 0
3772 implies side effects */
3773 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
3774 for (i
= 0; i
< nb_oargs
; i
++) {
3775 if (arg_temp(op
->args
[i
])->state
!= TS_DEAD
) {
3784 tcg_op_remove(s
, op
);
3788 for (i
= 0; i
< nb_oargs
; i
++) {
3789 ts
= arg_temp(op
->args
[i
]);
3791 /* Remember the preference of the uses that followed. */
3792 if (i
< ARRAY_SIZE(op
->output_pref
)) {
3793 op
->output_pref
[i
] = *la_temp_pref(ts
);
3796 /* Output args are dead. */
3797 if (ts
->state
& TS_DEAD
) {
3798 arg_life
|= DEAD_ARG
<< i
;
3800 if (ts
->state
& TS_MEM
) {
3801 arg_life
|= SYNC_ARG
<< i
;
3803 ts
->state
= TS_DEAD
;
3807 /* If end of basic block, update. */
3808 if (def
->flags
& TCG_OPF_BB_EXIT
) {
3809 la_func_end(s
, nb_globals
, nb_temps
);
3810 } else if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3811 la_bb_sync(s
, nb_globals
, nb_temps
);
3812 } else if (def
->flags
& TCG_OPF_BB_END
) {
3813 la_bb_end(s
, nb_globals
, nb_temps
);
3814 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3815 la_global_sync(s
, nb_globals
);
3816 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
3817 la_cross_call(s
, nb_temps
);
3821 /* Record arguments that die in this opcode. */
3822 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3823 ts
= arg_temp(op
->args
[i
]);
3824 if (ts
->state
& TS_DEAD
) {
3825 arg_life
|= DEAD_ARG
<< i
;
3829 /* Input arguments are live for preceding opcodes. */
3830 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3831 ts
= arg_temp(op
->args
[i
]);
3832 if (ts
->state
& TS_DEAD
) {
3833 /* For operands that were dead, initially allow
3834 all regs for the type. */
3835 *la_temp_pref(ts
) = tcg_target_available_regs
[ts
->type
];
3836 ts
->state
&= ~TS_DEAD
;
3840 /* Incorporate constraints for this operand. */
3842 case INDEX_op_mov_i32
:
3843 case INDEX_op_mov_i64
:
3844 /* Note that these are TCG_OPF_NOT_PRESENT and do not
3845 have proper constraints. That said, special case
3846 moves to propagate preferences backward. */
3847 if (IS_DEAD_ARG(1)) {
3848 *la_temp_pref(arg_temp(op
->args
[0]))
3849 = *la_temp_pref(arg_temp(op
->args
[1]));
3854 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3855 const TCGArgConstraint
*ct
= &def
->args_ct
[i
];
3856 TCGRegSet set
, *pset
;
3858 ts
= arg_temp(op
->args
[i
]);
3859 pset
= la_temp_pref(ts
);
3864 set
&= output_pref(op
, ct
->alias_index
);
3866 /* If the combination is not possible, restart. */
3876 op
->life
= arg_life
;
3880 /* Liveness analysis: Convert indirect regs to direct temporaries. */
3881 static bool __attribute__((noinline
))
3882 liveness_pass_2(TCGContext
*s
)
3884 int nb_globals
= s
->nb_globals
;
3886 bool changes
= false;
3887 TCGOp
*op
, *op_next
;
3889 /* Create a temporary for each indirect global. */
3890 for (i
= 0; i
< nb_globals
; ++i
) {
3891 TCGTemp
*its
= &s
->temps
[i
];
3892 if (its
->indirect_reg
) {
3893 TCGTemp
*dts
= tcg_temp_alloc(s
);
3894 dts
->type
= its
->type
;
3895 dts
->base_type
= its
->base_type
;
3896 dts
->temp_subindex
= its
->temp_subindex
;
3897 dts
->kind
= TEMP_EBB
;
3898 its
->state_ptr
= dts
;
3900 its
->state_ptr
= NULL
;
3902 /* All globals begin dead. */
3903 its
->state
= TS_DEAD
;
3905 for (nb_temps
= s
->nb_temps
; i
< nb_temps
; ++i
) {
3906 TCGTemp
*its
= &s
->temps
[i
];
3907 its
->state_ptr
= NULL
;
3908 its
->state
= TS_DEAD
;
3911 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3912 TCGOpcode opc
= op
->opc
;
3913 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3914 TCGLifeData arg_life
= op
->life
;
3915 int nb_iargs
, nb_oargs
, call_flags
;
3916 TCGTemp
*arg_ts
, *dir_ts
;
3918 if (opc
== INDEX_op_call
) {
3919 nb_oargs
= TCGOP_CALLO(op
);
3920 nb_iargs
= TCGOP_CALLI(op
);
3921 call_flags
= tcg_call_flags(op
);
3923 nb_iargs
= def
->nb_iargs
;
3924 nb_oargs
= def
->nb_oargs
;
3926 /* Set flags similar to how calls require. */
3927 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3928 /* Like reading globals: sync_globals */
3929 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3930 } else if (def
->flags
& TCG_OPF_BB_END
) {
3931 /* Like writing globals: save_globals */
3933 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3934 /* Like reading globals: sync_globals */
3935 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3937 /* No effect on globals. */
3938 call_flags
= (TCG_CALL_NO_READ_GLOBALS
|
3939 TCG_CALL_NO_WRITE_GLOBALS
);
3943 /* Make sure that input arguments are available. */
3944 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3945 arg_ts
= arg_temp(op
->args
[i
]);
3946 dir_ts
= arg_ts
->state_ptr
;
3947 if (dir_ts
&& arg_ts
->state
== TS_DEAD
) {
3948 TCGOpcode lopc
= (arg_ts
->type
== TCG_TYPE_I32
3951 TCGOp
*lop
= tcg_op_insert_before(s
, op
, lopc
, 3);
3953 lop
->args
[0] = temp_arg(dir_ts
);
3954 lop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3955 lop
->args
[2] = arg_ts
->mem_offset
;
3957 /* Loaded, but synced with memory. */
3958 arg_ts
->state
= TS_MEM
;
3962 /* Perform input replacement, and mark inputs that became dead.
3963 No action is required except keeping temp_state up to date
3964 so that we reload when needed. */
3965 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3966 arg_ts
= arg_temp(op
->args
[i
]);
3967 dir_ts
= arg_ts
->state_ptr
;
3969 op
->args
[i
] = temp_arg(dir_ts
);
3971 if (IS_DEAD_ARG(i
)) {
3972 arg_ts
->state
= TS_DEAD
;
3977 /* Liveness analysis should ensure that the following are
3978 all correct, for call sites and basic block end points. */
3979 if (call_flags
& TCG_CALL_NO_READ_GLOBALS
) {
3981 } else if (call_flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
3982 for (i
= 0; i
< nb_globals
; ++i
) {
3983 /* Liveness should see that globals are synced back,
3984 that is, either TS_DEAD or TS_MEM. */
3985 arg_ts
= &s
->temps
[i
];
3986 tcg_debug_assert(arg_ts
->state_ptr
== 0
3987 || arg_ts
->state
!= 0);
3990 for (i
= 0; i
< nb_globals
; ++i
) {
3991 /* Liveness should see that globals are saved back,
3992 that is, TS_DEAD, waiting to be reloaded. */
3993 arg_ts
= &s
->temps
[i
];
3994 tcg_debug_assert(arg_ts
->state_ptr
== 0
3995 || arg_ts
->state
== TS_DEAD
);
3999 /* Outputs become available. */
4000 if (opc
== INDEX_op_mov_i32
|| opc
== INDEX_op_mov_i64
) {
4001 arg_ts
= arg_temp(op
->args
[0]);
4002 dir_ts
= arg_ts
->state_ptr
;
4004 op
->args
[0] = temp_arg(dir_ts
);
4007 /* The output is now live and modified. */
4010 if (NEED_SYNC_ARG(0)) {
4011 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
4014 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
4015 TCGTemp
*out_ts
= dir_ts
;
4017 if (IS_DEAD_ARG(0)) {
4018 out_ts
= arg_temp(op
->args
[1]);
4019 arg_ts
->state
= TS_DEAD
;
4020 tcg_op_remove(s
, op
);
4022 arg_ts
->state
= TS_MEM
;
4025 sop
->args
[0] = temp_arg(out_ts
);
4026 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
4027 sop
->args
[2] = arg_ts
->mem_offset
;
4029 tcg_debug_assert(!IS_DEAD_ARG(0));
4033 for (i
= 0; i
< nb_oargs
; i
++) {
4034 arg_ts
= arg_temp(op
->args
[i
]);
4035 dir_ts
= arg_ts
->state_ptr
;
4039 op
->args
[i
] = temp_arg(dir_ts
);
4042 /* The output is now live and modified. */
4045 /* Sync outputs upon their last write. */
4046 if (NEED_SYNC_ARG(i
)) {
4047 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
4050 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
4052 sop
->args
[0] = temp_arg(dir_ts
);
4053 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
4054 sop
->args
[2] = arg_ts
->mem_offset
;
4056 arg_ts
->state
= TS_MEM
;
4058 /* Drop outputs that are dead. */
4059 if (IS_DEAD_ARG(i
)) {
4060 arg_ts
->state
= TS_DEAD
;
4069 static void temp_allocate_frame(TCGContext
*s
, TCGTemp
*ts
)
4074 /* When allocating an object, look at the full type. */
4075 size
= tcg_type_size(ts
->base_type
);
4076 switch (ts
->base_type
) {
4088 * Note that we do not require aligned storage for V256,
4089 * and that we provide alignment for I128 to match V128,
4090 * even if that's above what the host ABI requires.
4095 g_assert_not_reached();
4099 * Assume the stack is sufficiently aligned.
4100 * This affects e.g. ARM NEON, where we have 8 byte stack alignment
4101 * and do not require 16 byte vector alignment. This seems slightly
4102 * easier than fully parameterizing the above switch statement.
4104 align
= MIN(TCG_TARGET_STACK_ALIGN
, align
);
4105 off
= ROUND_UP(s
->current_frame_offset
, align
);
4107 /* If we've exhausted the stack frame, restart with a smaller TB. */
4108 if (off
+ size
> s
->frame_end
) {
4109 tcg_raise_tb_overflow(s
);
4111 s
->current_frame_offset
= off
+ size
;
4112 #if defined(__sparc__)
4113 off
+= TCG_TARGET_STACK_BIAS
;
4116 /* If the object was subdivided, assign memory to all the parts. */
4117 if (ts
->base_type
!= ts
->type
) {
4118 int part_size
= tcg_type_size(ts
->type
);
4119 int part_count
= size
/ part_size
;
4122 * Each part is allocated sequentially in tcg_temp_new_internal.
4123 * Jump back to the first part by subtracting the current index.
4125 ts
-= ts
->temp_subindex
;
4126 for (int i
= 0; i
< part_count
; ++i
) {
4127 ts
[i
].mem_offset
= off
+ i
* part_size
;
4128 ts
[i
].mem_base
= s
->frame_temp
;
4129 ts
[i
].mem_allocated
= 1;
4132 ts
->mem_offset
= off
;
4133 ts
->mem_base
= s
->frame_temp
;
4134 ts
->mem_allocated
= 1;
4138 /* Assign @reg to @ts, and update reg_to_temp[]. */
4139 static void set_temp_val_reg(TCGContext
*s
, TCGTemp
*ts
, TCGReg reg
)
4141 if (ts
->val_type
== TEMP_VAL_REG
) {
4142 TCGReg old
= ts
->reg
;
4143 tcg_debug_assert(s
->reg_to_temp
[old
] == ts
);
4147 s
->reg_to_temp
[old
] = NULL
;
4149 tcg_debug_assert(s
->reg_to_temp
[reg
] == NULL
);
4150 s
->reg_to_temp
[reg
] = ts
;
4151 ts
->val_type
= TEMP_VAL_REG
;
4155 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */
4156 static void set_temp_val_nonreg(TCGContext
*s
, TCGTemp
*ts
, TCGTempVal type
)
4158 tcg_debug_assert(type
!= TEMP_VAL_REG
);
4159 if (ts
->val_type
== TEMP_VAL_REG
) {
4160 TCGReg reg
= ts
->reg
;
4161 tcg_debug_assert(s
->reg_to_temp
[reg
] == ts
);
4162 s
->reg_to_temp
[reg
] = NULL
;
4164 ts
->val_type
= type
;
4167 static void temp_load(TCGContext
*, TCGTemp
*, TCGRegSet
, TCGRegSet
, TCGRegSet
);
4169 /* Mark a temporary as free or dead. If 'free_or_dead' is negative,
4170 mark it free; otherwise mark it dead. */
4171 static void temp_free_or_dead(TCGContext
*s
, TCGTemp
*ts
, int free_or_dead
)
4173 TCGTempVal new_type
;
4180 new_type
= TEMP_VAL_MEM
;
4183 new_type
= free_or_dead
< 0 ? TEMP_VAL_MEM
: TEMP_VAL_DEAD
;
4186 new_type
= TEMP_VAL_CONST
;
4189 g_assert_not_reached();
4191 set_temp_val_nonreg(s
, ts
, new_type
);
4194 /* Mark a temporary as dead. */
4195 static inline void temp_dead(TCGContext
*s
, TCGTemp
*ts
)
4197 temp_free_or_dead(s
, ts
, 1);
4200 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
4201 registers needs to be allocated to store a constant. If 'free_or_dead'
4202 is non-zero, subsequently release the temporary; if it is positive, the
4203 temp is dead; if it is negative, the temp is free. */
4204 static void temp_sync(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
,
4205 TCGRegSet preferred_regs
, int free_or_dead
)
4207 if (!temp_readonly(ts
) && !ts
->mem_coherent
) {
4208 if (!ts
->mem_allocated
) {
4209 temp_allocate_frame(s
, ts
);
4211 switch (ts
->val_type
) {
4212 case TEMP_VAL_CONST
:
4213 /* If we're going to free the temp immediately, then we won't
4214 require it later in a register, so attempt to store the
4215 constant to memory directly. */
4217 && tcg_out_sti(s
, ts
->type
, ts
->val
,
4218 ts
->mem_base
->reg
, ts
->mem_offset
)) {
4221 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4222 allocated_regs
, preferred_regs
);
4226 tcg_out_st(s
, ts
->type
, ts
->reg
,
4227 ts
->mem_base
->reg
, ts
->mem_offset
);
4235 g_assert_not_reached();
4237 ts
->mem_coherent
= 1;
4240 temp_free_or_dead(s
, ts
, free_or_dead
);
4244 /* free register 'reg' by spilling the corresponding temporary if necessary */
4245 static void tcg_reg_free(TCGContext
*s
, TCGReg reg
, TCGRegSet allocated_regs
)
4247 TCGTemp
*ts
= s
->reg_to_temp
[reg
];
4249 temp_sync(s
, ts
, allocated_regs
, 0, -1);
4255 * @required_regs: Set of registers in which we must allocate.
4256 * @allocated_regs: Set of registers which must be avoided.
4257 * @preferred_regs: Set of registers we should prefer.
4258 * @rev: True if we search the registers in "indirect" order.
4260 * The allocated register must be in @required_regs & ~@allocated_regs,
4261 * but if we can put it in @preferred_regs we may save a move later.
4263 static TCGReg
tcg_reg_alloc(TCGContext
*s
, TCGRegSet required_regs
,
4264 TCGRegSet allocated_regs
,
4265 TCGRegSet preferred_regs
, bool rev
)
4267 int i
, j
, f
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4268 TCGRegSet reg_ct
[2];
4271 reg_ct
[1] = required_regs
& ~allocated_regs
;
4272 tcg_debug_assert(reg_ct
[1] != 0);
4273 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4275 /* Skip the preferred_regs option if it cannot be satisfied,
4276 or if the preference made no difference. */
4277 f
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4279 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4281 /* Try free registers, preferences first. */
4282 for (j
= f
; j
< 2; j
++) {
4283 TCGRegSet set
= reg_ct
[j
];
4285 if (tcg_regset_single(set
)) {
4286 /* One register in the set. */
4287 TCGReg reg
= tcg_regset_first(set
);
4288 if (s
->reg_to_temp
[reg
] == NULL
) {
4292 for (i
= 0; i
< n
; i
++) {
4293 TCGReg reg
= order
[i
];
4294 if (s
->reg_to_temp
[reg
] == NULL
&&
4295 tcg_regset_test_reg(set
, reg
)) {
4302 /* We must spill something. */
4303 for (j
= f
; j
< 2; j
++) {
4304 TCGRegSet set
= reg_ct
[j
];
4306 if (tcg_regset_single(set
)) {
4307 /* One register in the set. */
4308 TCGReg reg
= tcg_regset_first(set
);
4309 tcg_reg_free(s
, reg
, allocated_regs
);
4312 for (i
= 0; i
< n
; i
++) {
4313 TCGReg reg
= order
[i
];
4314 if (tcg_regset_test_reg(set
, reg
)) {
4315 tcg_reg_free(s
, reg
, allocated_regs
);
4322 g_assert_not_reached();
4325 static TCGReg
tcg_reg_alloc_pair(TCGContext
*s
, TCGRegSet required_regs
,
4326 TCGRegSet allocated_regs
,
4327 TCGRegSet preferred_regs
, bool rev
)
4329 int i
, j
, k
, fmin
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4330 TCGRegSet reg_ct
[2];
4333 /* Ensure that if I is not in allocated_regs, I+1 is not either. */
4334 reg_ct
[1] = required_regs
& ~(allocated_regs
| (allocated_regs
>> 1));
4335 tcg_debug_assert(reg_ct
[1] != 0);
4336 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4338 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4341 * Skip the preferred_regs option if it cannot be satisfied,
4342 * or if the preference made no difference.
4344 k
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4347 * Minimize the number of flushes by looking for 2 free registers first,
4348 * then a single flush, then two flushes.
4350 for (fmin
= 2; fmin
>= 0; fmin
--) {
4351 for (j
= k
; j
< 2; j
++) {
4352 TCGRegSet set
= reg_ct
[j
];
4354 for (i
= 0; i
< n
; i
++) {
4355 TCGReg reg
= order
[i
];
4357 if (tcg_regset_test_reg(set
, reg
)) {
4358 int f
= !s
->reg_to_temp
[reg
] + !s
->reg_to_temp
[reg
+ 1];
4360 tcg_reg_free(s
, reg
, allocated_regs
);
4361 tcg_reg_free(s
, reg
+ 1, allocated_regs
);
4368 g_assert_not_reached();
4371 /* Make sure the temporary is in a register. If needed, allocate the register
4372 from DESIRED while avoiding ALLOCATED. */
4373 static void temp_load(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet desired_regs
,
4374 TCGRegSet allocated_regs
, TCGRegSet preferred_regs
)
4378 switch (ts
->val_type
) {
4381 case TEMP_VAL_CONST
:
4382 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4383 preferred_regs
, ts
->indirect_base
);
4384 if (ts
->type
<= TCG_TYPE_I64
) {
4385 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
4387 uint64_t val
= ts
->val
;
4391 * Find the minimal vector element that matches the constant.
4392 * The targets will, in general, have to do this search anyway,
4393 * do this generically.
4395 if (val
== dup_const(MO_8
, val
)) {
4397 } else if (val
== dup_const(MO_16
, val
)) {
4399 } else if (val
== dup_const(MO_32
, val
)) {
4403 tcg_out_dupi_vec(s
, ts
->type
, vece
, reg
, ts
->val
);
4405 ts
->mem_coherent
= 0;
4408 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4409 preferred_regs
, ts
->indirect_base
);
4410 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_base
->reg
, ts
->mem_offset
);
4411 ts
->mem_coherent
= 1;
4415 g_assert_not_reached();
4417 set_temp_val_reg(s
, ts
, reg
);
4420 /* Save a temporary to memory. 'allocated_regs' is used in case a
4421 temporary registers needs to be allocated to store a constant. */
4422 static void temp_save(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
)
4424 /* The liveness analysis already ensures that globals are back
4425 in memory. Keep an tcg_debug_assert for safety. */
4426 tcg_debug_assert(ts
->val_type
== TEMP_VAL_MEM
|| temp_readonly(ts
));
4429 /* save globals to their canonical location and assume they can be
4430 modified be the following code. 'allocated_regs' is used in case a
4431 temporary registers needs to be allocated to store a constant. */
4432 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4436 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4437 temp_save(s
, &s
->temps
[i
], allocated_regs
);
4441 /* sync globals to their canonical location and assume they can be
4442 read by the following code. 'allocated_regs' is used in case a
4443 temporary registers needs to be allocated to store a constant. */
4444 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4448 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4449 TCGTemp
*ts
= &s
->temps
[i
];
4450 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
4451 || ts
->kind
== TEMP_FIXED
4452 || ts
->mem_coherent
);
4456 /* at the end of a basic block, we assume all temporaries are dead and
4457 all globals are stored at their canonical location. */
4458 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
4462 for (i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4463 TCGTemp
*ts
= &s
->temps
[i
];
4467 temp_save(s
, ts
, allocated_regs
);
4470 /* The liveness analysis already ensures that temps are dead.
4471 Keep an tcg_debug_assert for safety. */
4472 tcg_debug_assert(ts
->val_type
== TEMP_VAL_DEAD
);
4475 /* Similarly, we should have freed any allocated register. */
4476 tcg_debug_assert(ts
->val_type
== TEMP_VAL_CONST
);
4479 g_assert_not_reached();
4483 save_globals(s
, allocated_regs
);
4487 * At a conditional branch, we assume all temporaries are dead unless
4488 * explicitly live-across-conditional-branch; all globals and local
4489 * temps are synced to their location.
4491 static void tcg_reg_alloc_cbranch(TCGContext
*s
, TCGRegSet allocated_regs
)
4493 sync_globals(s
, allocated_regs
);
4495 for (int i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4496 TCGTemp
*ts
= &s
->temps
[i
];
4498 * The liveness analysis already ensures that temps are dead.
4499 * Keep tcg_debug_asserts for safety.
4503 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
|| ts
->mem_coherent
);
4509 g_assert_not_reached();
4515 * Specialized code generation for INDEX_op_mov_* with a constant.
4517 static void tcg_reg_alloc_do_movi(TCGContext
*s
, TCGTemp
*ots
,
4518 tcg_target_ulong val
, TCGLifeData arg_life
,
4519 TCGRegSet preferred_regs
)
4521 /* ENV should not be modified. */
4522 tcg_debug_assert(!temp_readonly(ots
));
4524 /* The movi is not explicitly generated here. */
4525 set_temp_val_nonreg(s
, ots
, TEMP_VAL_CONST
);
4527 ots
->mem_coherent
= 0;
4528 if (NEED_SYNC_ARG(0)) {
4529 temp_sync(s
, ots
, s
->reserved_regs
, preferred_regs
, IS_DEAD_ARG(0));
4530 } else if (IS_DEAD_ARG(0)) {
4536 * Specialized code generation for INDEX_op_mov_*.
4538 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOp
*op
)
4540 const TCGLifeData arg_life
= op
->life
;
4541 TCGRegSet allocated_regs
, preferred_regs
;
4543 TCGType otype
, itype
;
4546 allocated_regs
= s
->reserved_regs
;
4547 preferred_regs
= output_pref(op
, 0);
4548 ots
= arg_temp(op
->args
[0]);
4549 ts
= arg_temp(op
->args
[1]);
4551 /* ENV should not be modified. */
4552 tcg_debug_assert(!temp_readonly(ots
));
4554 /* Note that otype != itype for no-op truncation. */
4558 if (ts
->val_type
== TEMP_VAL_CONST
) {
4559 /* propagate constant or generate sti */
4560 tcg_target_ulong val
= ts
->val
;
4561 if (IS_DEAD_ARG(1)) {
4564 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, preferred_regs
);
4568 /* If the source value is in memory we're going to be forced
4569 to have it in a register in order to perform the copy. Copy
4570 the SOURCE value into its own register first, that way we
4571 don't have to reload SOURCE the next time it is used. */
4572 if (ts
->val_type
== TEMP_VAL_MEM
) {
4573 temp_load(s
, ts
, tcg_target_available_regs
[itype
],
4574 allocated_regs
, preferred_regs
);
4576 tcg_debug_assert(ts
->val_type
== TEMP_VAL_REG
);
4579 if (IS_DEAD_ARG(0)) {
4580 /* mov to a non-saved dead register makes no sense (even with
4581 liveness analysis disabled). */
4582 tcg_debug_assert(NEED_SYNC_ARG(0));
4583 if (!ots
->mem_allocated
) {
4584 temp_allocate_frame(s
, ots
);
4586 tcg_out_st(s
, otype
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4587 if (IS_DEAD_ARG(1)) {
4594 if (IS_DEAD_ARG(1) && ts
->kind
!= TEMP_FIXED
) {
4596 * The mov can be suppressed. Kill input first, so that it
4597 * is unlinked from reg_to_temp, then set the output to the
4598 * reg that we saved from the input.
4603 if (ots
->val_type
== TEMP_VAL_REG
) {
4606 /* Make sure to not spill the input register during allocation. */
4607 oreg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
4608 allocated_regs
| ((TCGRegSet
)1 << ireg
),
4609 preferred_regs
, ots
->indirect_base
);
4611 if (!tcg_out_mov(s
, otype
, oreg
, ireg
)) {
4613 * Cross register class move not supported.
4614 * Store the source register into the destination slot
4615 * and leave the destination temp as TEMP_VAL_MEM.
4617 assert(!temp_readonly(ots
));
4618 if (!ts
->mem_allocated
) {
4619 temp_allocate_frame(s
, ots
);
4621 tcg_out_st(s
, ts
->type
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4622 set_temp_val_nonreg(s
, ts
, TEMP_VAL_MEM
);
4623 ots
->mem_coherent
= 1;
4627 set_temp_val_reg(s
, ots
, oreg
);
4628 ots
->mem_coherent
= 0;
4630 if (NEED_SYNC_ARG(0)) {
4631 temp_sync(s
, ots
, allocated_regs
, 0, 0);
4636 * Specialized code generation for INDEX_op_dup_vec.
4638 static void tcg_reg_alloc_dup(TCGContext
*s
, const TCGOp
*op
)
4640 const TCGLifeData arg_life
= op
->life
;
4641 TCGRegSet dup_out_regs
, dup_in_regs
;
4643 TCGType itype
, vtype
;
4648 ots
= arg_temp(op
->args
[0]);
4649 its
= arg_temp(op
->args
[1]);
4651 /* ENV should not be modified. */
4652 tcg_debug_assert(!temp_readonly(ots
));
4655 vece
= TCGOP_VECE(op
);
4656 vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4658 if (its
->val_type
== TEMP_VAL_CONST
) {
4659 /* Propagate constant via movi -> dupi. */
4660 tcg_target_ulong val
= its
->val
;
4661 if (IS_DEAD_ARG(1)) {
4664 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, output_pref(op
, 0));
4668 dup_out_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4669 dup_in_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[1].regs
;
4671 /* Allocate the output register now. */
4672 if (ots
->val_type
!= TEMP_VAL_REG
) {
4673 TCGRegSet allocated_regs
= s
->reserved_regs
;
4676 if (!IS_DEAD_ARG(1) && its
->val_type
== TEMP_VAL_REG
) {
4677 /* Make sure to not spill the input register. */
4678 tcg_regset_set_reg(allocated_regs
, its
->reg
);
4680 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4681 output_pref(op
, 0), ots
->indirect_base
);
4682 set_temp_val_reg(s
, ots
, oreg
);
4685 switch (its
->val_type
) {
4688 * The dup constriaints must be broad, covering all possible VECE.
4689 * However, tcg_op_dup_vec() gets to see the VECE and we allow it
4690 * to fail, indicating that extra moves are required for that case.
4692 if (tcg_regset_test_reg(dup_in_regs
, its
->reg
)) {
4693 if (tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, its
->reg
)) {
4696 /* Try again from memory or a vector input register. */
4698 if (!its
->mem_coherent
) {
4700 * The input register is not synced, and so an extra store
4701 * would be required to use memory. Attempt an integer-vector
4702 * register move first. We do not have a TCGRegSet for this.
4704 if (tcg_out_mov(s
, itype
, ots
->reg
, its
->reg
)) {
4707 /* Sync the temp back to its slot and load from there. */
4708 temp_sync(s
, its
, s
->reserved_regs
, 0, 0);
4714 if (HOST_BIG_ENDIAN
) {
4715 lowpart_ofs
= tcg_type_size(itype
) - (1 << vece
);
4717 if (tcg_out_dupm_vec(s
, vtype
, vece
, ots
->reg
, its
->mem_base
->reg
,
4718 its
->mem_offset
+ lowpart_ofs
)) {
4721 /* Load the input into the destination vector register. */
4722 tcg_out_ld(s
, itype
, ots
->reg
, its
->mem_base
->reg
, its
->mem_offset
);
4726 g_assert_not_reached();
4729 /* We now have a vector input register, so dup must succeed. */
4730 ok
= tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, ots
->reg
);
4731 tcg_debug_assert(ok
);
4734 ots
->mem_coherent
= 0;
4735 if (IS_DEAD_ARG(1)) {
4738 if (NEED_SYNC_ARG(0)) {
4739 temp_sync(s
, ots
, s
->reserved_regs
, 0, 0);
4741 if (IS_DEAD_ARG(0)) {
4746 static void tcg_reg_alloc_op(TCGContext
*s
, const TCGOp
*op
)
4748 const TCGLifeData arg_life
= op
->life
;
4749 const TCGOpDef
* const def
= &tcg_op_defs
[op
->opc
];
4750 TCGRegSet i_allocated_regs
;
4751 TCGRegSet o_allocated_regs
;
4752 int i
, k
, nb_iargs
, nb_oargs
;
4755 const TCGArgConstraint
*arg_ct
;
4757 TCGArg new_args
[TCG_MAX_OP_ARGS
];
4758 int const_args
[TCG_MAX_OP_ARGS
];
4760 nb_oargs
= def
->nb_oargs
;
4761 nb_iargs
= def
->nb_iargs
;
4763 /* copy constants */
4764 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
4765 op
->args
+ nb_oargs
+ nb_iargs
,
4766 sizeof(TCGArg
) * def
->nb_cargs
);
4768 i_allocated_regs
= s
->reserved_regs
;
4769 o_allocated_regs
= s
->reserved_regs
;
4771 /* satisfy input constraints */
4772 for (k
= 0; k
< nb_iargs
; k
++) {
4773 TCGRegSet i_preferred_regs
, i_required_regs
;
4774 bool allocate_new_reg
, copyto_new_reg
;
4778 i
= def
->args_ct
[nb_oargs
+ k
].sort_index
;
4780 arg_ct
= &def
->args_ct
[i
];
4783 if (ts
->val_type
== TEMP_VAL_CONST
4784 && tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
->ct
, TCGOP_VECE(op
))) {
4785 /* constant is OK for instruction */
4787 new_args
[i
] = ts
->val
;
4792 i_preferred_regs
= 0;
4793 i_required_regs
= arg_ct
->regs
;
4794 allocate_new_reg
= false;
4795 copyto_new_reg
= false;
4797 switch (arg_ct
->pair
) {
4798 case 0: /* not paired */
4799 if (arg_ct
->ialias
) {
4800 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4803 * If the input is readonly, then it cannot also be an
4804 * output and aliased to itself. If the input is not
4805 * dead after the instruction, we must allocate a new
4806 * register and move it.
4808 if (temp_readonly(ts
) || !IS_DEAD_ARG(i
)
4809 || def
->args_ct
[arg_ct
->alias_index
].newreg
) {
4810 allocate_new_reg
= true;
4811 } else if (ts
->val_type
== TEMP_VAL_REG
) {
4813 * Check if the current register has already been
4814 * allocated for another input.
4817 tcg_regset_test_reg(i_allocated_regs
, reg
);
4820 if (!allocate_new_reg
) {
4821 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4824 allocate_new_reg
= !tcg_regset_test_reg(i_required_regs
, reg
);
4826 if (allocate_new_reg
) {
4828 * Allocate a new register matching the constraint
4829 * and move the temporary register into it.
4831 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4832 i_allocated_regs
, 0);
4833 reg
= tcg_reg_alloc(s
, i_required_regs
, i_allocated_regs
,
4834 i_preferred_regs
, ts
->indirect_base
);
4835 copyto_new_reg
= true;
4840 /* First of an input pair; if i1 == i2, the second is an output. */
4842 i2
= arg_ct
->pair_index
;
4843 ts2
= i1
!= i2
? arg_temp(op
->args
[i2
]) : NULL
;
4846 * It is easier to default to allocating a new pair
4847 * and to identify a few cases where it's not required.
4849 if (arg_ct
->ialias
) {
4850 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4851 if (IS_DEAD_ARG(i1
) &&
4853 !temp_readonly(ts
) &&
4854 ts
->val_type
== TEMP_VAL_REG
&&
4855 ts
->reg
< TCG_TARGET_NB_REGS
- 1 &&
4856 tcg_regset_test_reg(i_required_regs
, reg
) &&
4857 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4858 !tcg_regset_test_reg(i_allocated_regs
, reg
+ 1) &&
4860 ? ts2
->val_type
== TEMP_VAL_REG
&&
4861 ts2
->reg
== reg
+ 1 &&
4863 : s
->reg_to_temp
[reg
+ 1] == NULL
)) {
4867 /* Without aliasing, the pair must also be an input. */
4868 tcg_debug_assert(ts2
);
4869 if (ts
->val_type
== TEMP_VAL_REG
&&
4870 ts2
->val_type
== TEMP_VAL_REG
&&
4871 ts2
->reg
== reg
+ 1 &&
4872 tcg_regset_test_reg(i_required_regs
, reg
)) {
4876 reg
= tcg_reg_alloc_pair(s
, i_required_regs
, i_allocated_regs
,
4877 0, ts
->indirect_base
);
4880 case 2: /* pair second */
4881 reg
= new_args
[arg_ct
->pair_index
] + 1;
4884 case 3: /* ialias with second output, no first input */
4885 tcg_debug_assert(arg_ct
->ialias
);
4886 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4888 if (IS_DEAD_ARG(i
) &&
4889 !temp_readonly(ts
) &&
4890 ts
->val_type
== TEMP_VAL_REG
&&
4892 s
->reg_to_temp
[reg
- 1] == NULL
&&
4893 tcg_regset_test_reg(i_required_regs
, reg
) &&
4894 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4895 !tcg_regset_test_reg(i_allocated_regs
, reg
- 1)) {
4896 tcg_regset_set_reg(i_allocated_regs
, reg
- 1);
4899 reg
= tcg_reg_alloc_pair(s
, i_required_regs
>> 1,
4900 i_allocated_regs
, 0,
4902 tcg_regset_set_reg(i_allocated_regs
, reg
);
4908 * If an aliased input is not dead after the instruction,
4909 * we must allocate a new register and move it.
4911 if (arg_ct
->ialias
&& (!IS_DEAD_ARG(i
) || temp_readonly(ts
))) {
4912 TCGRegSet t_allocated_regs
= i_allocated_regs
;
4915 * Because of the alias, and the continued life, make sure
4916 * that the temp is somewhere *other* than the reg pair,
4917 * and we get a copy in reg.
4919 tcg_regset_set_reg(t_allocated_regs
, reg
);
4920 tcg_regset_set_reg(t_allocated_regs
, reg
+ 1);
4921 if (ts
->val_type
== TEMP_VAL_REG
&& ts
->reg
== reg
) {
4922 /* If ts was already in reg, copy it somewhere else. */
4926 tcg_debug_assert(ts
->kind
!= TEMP_FIXED
);
4927 nr
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
4928 t_allocated_regs
, 0, ts
->indirect_base
);
4929 ok
= tcg_out_mov(s
, ts
->type
, nr
, reg
);
4930 tcg_debug_assert(ok
);
4932 set_temp_val_reg(s
, ts
, nr
);
4934 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4935 t_allocated_regs
, 0);
4936 copyto_new_reg
= true;
4939 /* Preferably allocate to reg, otherwise copy. */
4940 i_required_regs
= (TCGRegSet
)1 << reg
;
4941 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4943 copyto_new_reg
= ts
->reg
!= reg
;
4948 g_assert_not_reached();
4951 if (copyto_new_reg
) {
4952 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4954 * Cross register class move not supported. Sync the
4955 * temp back to its slot and load from there.
4957 temp_sync(s
, ts
, i_allocated_regs
, 0, 0);
4958 tcg_out_ld(s
, ts
->type
, reg
,
4959 ts
->mem_base
->reg
, ts
->mem_offset
);
4964 tcg_regset_set_reg(i_allocated_regs
, reg
);
4967 /* mark dead temporaries and free the associated registers */
4968 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
4969 if (IS_DEAD_ARG(i
)) {
4970 temp_dead(s
, arg_temp(op
->args
[i
]));
4974 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
4975 tcg_reg_alloc_cbranch(s
, i_allocated_regs
);
4976 } else if (def
->flags
& TCG_OPF_BB_END
) {
4977 tcg_reg_alloc_bb_end(s
, i_allocated_regs
);
4979 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
4980 /* XXX: permit generic clobber register list ? */
4981 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
4982 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
4983 tcg_reg_free(s
, i
, i_allocated_regs
);
4987 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
4988 /* sync globals if the op has side effects and might trigger
4990 sync_globals(s
, i_allocated_regs
);
4993 /* satisfy the output constraints */
4994 for(k
= 0; k
< nb_oargs
; k
++) {
4995 i
= def
->args_ct
[k
].sort_index
;
4997 arg_ct
= &def
->args_ct
[i
];
5000 /* ENV should not be modified. */
5001 tcg_debug_assert(!temp_readonly(ts
));
5003 switch (arg_ct
->pair
) {
5004 case 0: /* not paired */
5005 if (arg_ct
->oalias
&& !const_args
[arg_ct
->alias_index
]) {
5006 reg
= new_args
[arg_ct
->alias_index
];
5007 } else if (arg_ct
->newreg
) {
5008 reg
= tcg_reg_alloc(s
, arg_ct
->regs
,
5009 i_allocated_regs
| o_allocated_regs
,
5010 output_pref(op
, k
), ts
->indirect_base
);
5012 reg
= tcg_reg_alloc(s
, arg_ct
->regs
, o_allocated_regs
,
5013 output_pref(op
, k
), ts
->indirect_base
);
5017 case 1: /* first of pair */
5018 tcg_debug_assert(!arg_ct
->newreg
);
5019 if (arg_ct
->oalias
) {
5020 reg
= new_args
[arg_ct
->alias_index
];
5023 reg
= tcg_reg_alloc_pair(s
, arg_ct
->regs
, o_allocated_regs
,
5024 output_pref(op
, k
), ts
->indirect_base
);
5027 case 2: /* second of pair */
5028 tcg_debug_assert(!arg_ct
->newreg
);
5029 if (arg_ct
->oalias
) {
5030 reg
= new_args
[arg_ct
->alias_index
];
5032 reg
= new_args
[arg_ct
->pair_index
] + 1;
5036 case 3: /* first of pair, aliasing with a second input */
5037 tcg_debug_assert(!arg_ct
->newreg
);
5038 reg
= new_args
[arg_ct
->pair_index
] - 1;
5042 g_assert_not_reached();
5044 tcg_regset_set_reg(o_allocated_regs
, reg
);
5045 set_temp_val_reg(s
, ts
, reg
);
5046 ts
->mem_coherent
= 0;
5051 /* emit instruction */
5053 case INDEX_op_ext8s_i32
:
5054 tcg_out_ext8s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
5056 case INDEX_op_ext8s_i64
:
5057 tcg_out_ext8s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
5059 case INDEX_op_ext8u_i32
:
5060 case INDEX_op_ext8u_i64
:
5061 tcg_out_ext8u(s
, new_args
[0], new_args
[1]);
5063 case INDEX_op_ext16s_i32
:
5064 tcg_out_ext16s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
5066 case INDEX_op_ext16s_i64
:
5067 tcg_out_ext16s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
5069 case INDEX_op_ext16u_i32
:
5070 case INDEX_op_ext16u_i64
:
5071 tcg_out_ext16u(s
, new_args
[0], new_args
[1]);
5073 case INDEX_op_ext32s_i64
:
5074 tcg_out_ext32s(s
, new_args
[0], new_args
[1]);
5076 case INDEX_op_ext32u_i64
:
5077 tcg_out_ext32u(s
, new_args
[0], new_args
[1]);
5079 case INDEX_op_ext_i32_i64
:
5080 tcg_out_exts_i32_i64(s
, new_args
[0], new_args
[1]);
5082 case INDEX_op_extu_i32_i64
:
5083 tcg_out_extu_i32_i64(s
, new_args
[0], new_args
[1]);
5085 case INDEX_op_extrl_i64_i32
:
5086 tcg_out_extrl_i64_i32(s
, new_args
[0], new_args
[1]);
5089 if (def
->flags
& TCG_OPF_VECTOR
) {
5090 tcg_out_vec_op(s
, op
->opc
, TCGOP_VECL(op
), TCGOP_VECE(op
),
5091 new_args
, const_args
);
5093 tcg_out_op(s
, op
->opc
, new_args
, const_args
);
5098 /* move the outputs in the correct register if needed */
5099 for(i
= 0; i
< nb_oargs
; i
++) {
5100 ts
= arg_temp(op
->args
[i
]);
5102 /* ENV should not be modified. */
5103 tcg_debug_assert(!temp_readonly(ts
));
5105 if (NEED_SYNC_ARG(i
)) {
5106 temp_sync(s
, ts
, o_allocated_regs
, 0, IS_DEAD_ARG(i
));
5107 } else if (IS_DEAD_ARG(i
)) {
5113 static bool tcg_reg_alloc_dup2(TCGContext
*s
, const TCGOp
*op
)
5115 const TCGLifeData arg_life
= op
->life
;
5116 TCGTemp
*ots
, *itsl
, *itsh
;
5117 TCGType vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
5119 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
5120 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
5121 tcg_debug_assert(TCGOP_VECE(op
) == MO_64
);
5123 ots
= arg_temp(op
->args
[0]);
5124 itsl
= arg_temp(op
->args
[1]);
5125 itsh
= arg_temp(op
->args
[2]);
5127 /* ENV should not be modified. */
5128 tcg_debug_assert(!temp_readonly(ots
));
5130 /* Allocate the output register now. */
5131 if (ots
->val_type
!= TEMP_VAL_REG
) {
5132 TCGRegSet allocated_regs
= s
->reserved_regs
;
5133 TCGRegSet dup_out_regs
=
5134 tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
5137 /* Make sure to not spill the input registers. */
5138 if (!IS_DEAD_ARG(1) && itsl
->val_type
== TEMP_VAL_REG
) {
5139 tcg_regset_set_reg(allocated_regs
, itsl
->reg
);
5141 if (!IS_DEAD_ARG(2) && itsh
->val_type
== TEMP_VAL_REG
) {
5142 tcg_regset_set_reg(allocated_regs
, itsh
->reg
);
5145 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
5146 output_pref(op
, 0), ots
->indirect_base
);
5147 set_temp_val_reg(s
, ots
, oreg
);
5150 /* Promote dup2 of immediates to dupi_vec. */
5151 if (itsl
->val_type
== TEMP_VAL_CONST
&& itsh
->val_type
== TEMP_VAL_CONST
) {
5152 uint64_t val
= deposit64(itsl
->val
, 32, 32, itsh
->val
);
5155 if (val
== dup_const(MO_8
, val
)) {
5157 } else if (val
== dup_const(MO_16
, val
)) {
5159 } else if (val
== dup_const(MO_32
, val
)) {
5163 tcg_out_dupi_vec(s
, vtype
, vece
, ots
->reg
, val
);
5167 /* If the two inputs form one 64-bit value, try dupm_vec. */
5168 if (itsl
->temp_subindex
== HOST_BIG_ENDIAN
&&
5169 itsh
->temp_subindex
== !HOST_BIG_ENDIAN
&&
5170 itsl
== itsh
+ (HOST_BIG_ENDIAN
? 1 : -1)) {
5171 TCGTemp
*its
= itsl
- HOST_BIG_ENDIAN
;
5173 temp_sync(s
, its
+ 0, s
->reserved_regs
, 0, 0);
5174 temp_sync(s
, its
+ 1, s
->reserved_regs
, 0, 0);
5176 if (tcg_out_dupm_vec(s
, vtype
, MO_64
, ots
->reg
,
5177 its
->mem_base
->reg
, its
->mem_offset
)) {
5182 /* Fall back to generic expansion. */
5186 ots
->mem_coherent
= 0;
5187 if (IS_DEAD_ARG(1)) {
5190 if (IS_DEAD_ARG(2)) {
5193 if (NEED_SYNC_ARG(0)) {
5194 temp_sync(s
, ots
, s
->reserved_regs
, 0, IS_DEAD_ARG(0));
5195 } else if (IS_DEAD_ARG(0)) {
5201 static void load_arg_reg(TCGContext
*s
, TCGReg reg
, TCGTemp
*ts
,
5202 TCGRegSet allocated_regs
)
5204 if (ts
->val_type
== TEMP_VAL_REG
) {
5205 if (ts
->reg
!= reg
) {
5206 tcg_reg_free(s
, reg
, allocated_regs
);
5207 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
5209 * Cross register class move not supported. Sync the
5210 * temp back to its slot and load from there.
5212 temp_sync(s
, ts
, allocated_regs
, 0, 0);
5213 tcg_out_ld(s
, ts
->type
, reg
,
5214 ts
->mem_base
->reg
, ts
->mem_offset
);
5218 TCGRegSet arg_set
= 0;
5220 tcg_reg_free(s
, reg
, allocated_regs
);
5221 tcg_regset_set_reg(arg_set
, reg
);
5222 temp_load(s
, ts
, arg_set
, allocated_regs
, 0);
5226 static void load_arg_stk(TCGContext
*s
, unsigned arg_slot
, TCGTemp
*ts
,
5227 TCGRegSet allocated_regs
)
5230 * When the destination is on the stack, load up the temp and store.
5231 * If there are many call-saved registers, the temp might live to
5232 * see another use; otherwise it'll be discarded.
5234 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
], allocated_regs
, 0);
5235 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
,
5236 arg_slot_stk_ofs(arg_slot
));
5239 static void load_arg_normal(TCGContext
*s
, const TCGCallArgumentLoc
*l
,
5240 TCGTemp
*ts
, TCGRegSet
*allocated_regs
)
5242 if (arg_slot_reg_p(l
->arg_slot
)) {
5243 TCGReg reg
= tcg_target_call_iarg_regs
[l
->arg_slot
];
5244 load_arg_reg(s
, reg
, ts
, *allocated_regs
);
5245 tcg_regset_set_reg(*allocated_regs
, reg
);
5247 load_arg_stk(s
, l
->arg_slot
, ts
, *allocated_regs
);
5251 static void load_arg_ref(TCGContext
*s
, unsigned arg_slot
, TCGReg ref_base
,
5252 intptr_t ref_off
, TCGRegSet
*allocated_regs
)
5256 if (arg_slot_reg_p(arg_slot
)) {
5257 reg
= tcg_target_call_iarg_regs
[arg_slot
];
5258 tcg_reg_free(s
, reg
, *allocated_regs
);
5259 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
5260 tcg_regset_set_reg(*allocated_regs
, reg
);
5262 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[TCG_TYPE_PTR
],
5263 *allocated_regs
, 0, false);
5264 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
5265 tcg_out_st(s
, TCG_TYPE_PTR
, reg
, TCG_REG_CALL_STACK
,
5266 arg_slot_stk_ofs(arg_slot
));
5270 static void tcg_reg_alloc_call(TCGContext
*s
, TCGOp
*op
)
5272 const int nb_oargs
= TCGOP_CALLO(op
);
5273 const int nb_iargs
= TCGOP_CALLI(op
);
5274 const TCGLifeData arg_life
= op
->life
;
5275 const TCGHelperInfo
*info
= tcg_call_info(op
);
5276 TCGRegSet allocated_regs
= s
->reserved_regs
;
5280 * Move inputs into place in reverse order,
5281 * so that we place stacked arguments first.
5283 for (i
= nb_iargs
- 1; i
>= 0; --i
) {
5284 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
5285 TCGTemp
*ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
5287 switch (loc
->kind
) {
5288 case TCG_CALL_ARG_NORMAL
:
5289 case TCG_CALL_ARG_EXTEND_U
:
5290 case TCG_CALL_ARG_EXTEND_S
:
5291 load_arg_normal(s
, loc
, ts
, &allocated_regs
);
5293 case TCG_CALL_ARG_BY_REF
:
5294 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
5295 load_arg_ref(s
, loc
->arg_slot
, TCG_REG_CALL_STACK
,
5296 arg_slot_stk_ofs(loc
->ref_slot
),
5299 case TCG_CALL_ARG_BY_REF_N
:
5300 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
5303 g_assert_not_reached();
5307 /* Mark dead temporaries and free the associated registers. */
5308 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
5309 if (IS_DEAD_ARG(i
)) {
5310 temp_dead(s
, arg_temp(op
->args
[i
]));
5314 /* Clobber call registers. */
5315 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
5316 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
5317 tcg_reg_free(s
, i
, allocated_regs
);
5322 * Save globals if they might be written by the helper,
5323 * sync them if they might be read.
5325 if (info
->flags
& TCG_CALL_NO_READ_GLOBALS
) {
5327 } else if (info
->flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
5328 sync_globals(s
, allocated_regs
);
5330 save_globals(s
, allocated_regs
);
5334 * If the ABI passes a pointer to the returned struct as the first
5335 * argument, load that now. Pass a pointer to the output home slot.
5337 if (info
->out_kind
== TCG_CALL_RET_BY_REF
) {
5338 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5340 if (!ts
->mem_allocated
) {
5341 temp_allocate_frame(s
, ts
);
5343 load_arg_ref(s
, 0, ts
->mem_base
->reg
, ts
->mem_offset
, &allocated_regs
);
5346 tcg_out_call(s
, tcg_call_func(op
), info
);
5348 /* Assign output registers and emit moves if needed. */
5349 switch (info
->out_kind
) {
5350 case TCG_CALL_RET_NORMAL
:
5351 for (i
= 0; i
< nb_oargs
; i
++) {
5352 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5353 TCGReg reg
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, i
);
5355 /* ENV should not be modified. */
5356 tcg_debug_assert(!temp_readonly(ts
));
5358 set_temp_val_reg(s
, ts
, reg
);
5359 ts
->mem_coherent
= 0;
5363 case TCG_CALL_RET_BY_VEC
:
5365 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5367 tcg_debug_assert(ts
->base_type
== TCG_TYPE_I128
);
5368 tcg_debug_assert(ts
->temp_subindex
== 0);
5369 if (!ts
->mem_allocated
) {
5370 temp_allocate_frame(s
, ts
);
5372 tcg_out_st(s
, TCG_TYPE_V128
,
5373 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
5374 ts
->mem_base
->reg
, ts
->mem_offset
);
5376 /* fall through to mark all parts in memory */
5378 case TCG_CALL_RET_BY_REF
:
5379 /* The callee has performed a write through the reference. */
5380 for (i
= 0; i
< nb_oargs
; i
++) {
5381 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5382 ts
->val_type
= TEMP_VAL_MEM
;
5387 g_assert_not_reached();
5390 /* Flush or discard output registers as needed. */
5391 for (i
= 0; i
< nb_oargs
; i
++) {
5392 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5393 if (NEED_SYNC_ARG(i
)) {
5394 temp_sync(s
, ts
, s
->reserved_regs
, 0, IS_DEAD_ARG(i
));
5395 } else if (IS_DEAD_ARG(i
)) {
5402 * atom_and_align_for_opc:
5404 * @opc: memory operation code
5405 * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations
5406 * @allow_two_ops: true if we are prepared to issue two operations
5408 * Return the alignment and atomicity to use for the inline fast path
5409 * for the given memory operation. The alignment may be larger than
5410 * that specified in @opc, and the correct alignment will be diagnosed
5411 * by the slow path helper.
5413 * If @allow_two_ops, the host is prepared to test for 2x alignment,
5414 * and issue two loads or stores for subalignment.
5416 static TCGAtomAlign
atom_and_align_for_opc(TCGContext
*s
, MemOp opc
,
5417 MemOp host_atom
, bool allow_two_ops
)
5419 MemOp align
= get_alignment_bits(opc
);
5420 MemOp size
= opc
& MO_SIZE
;
5421 MemOp half
= size
? size
- 1 : 0;
5425 /* When serialized, no further atomicity required. */
5426 if (s
->gen_tb
->cflags
& CF_PARALLEL
) {
5427 atom
= opc
& MO_ATOM_MASK
;
5429 atom
= MO_ATOM_NONE
;
5434 /* The operation requires no specific atomicity. */
5438 case MO_ATOM_IFALIGN
:
5442 case MO_ATOM_IFALIGN_PAIR
:
5446 case MO_ATOM_WITHIN16
:
5448 if (size
== MO_128
) {
5449 /* Misalignment implies !within16, and therefore no atomicity. */
5450 } else if (host_atom
!= MO_ATOM_WITHIN16
) {
5451 /* The host does not implement within16, so require alignment. */
5452 align
= MAX(align
, size
);
5456 case MO_ATOM_WITHIN16_PAIR
:
5459 * Misalignment implies !within16, and therefore half atomicity.
5460 * Any host prepared for two operations can implement this with
5463 if (host_atom
!= MO_ATOM_WITHIN16
&& allow_two_ops
) {
5464 align
= MAX(align
, half
);
5468 case MO_ATOM_SUBALIGN
:
5470 if (host_atom
!= MO_ATOM_SUBALIGN
) {
5471 /* If unaligned but not odd, there are subobjects up to half. */
5472 if (allow_two_ops
) {
5473 align
= MAX(align
, half
);
5475 align
= MAX(align
, size
);
5481 g_assert_not_reached();
5484 return (TCGAtomAlign
){ .atom
= atmax
, .align
= align
};
5488 * Similarly for qemu_ld/st slow path helpers.
5489 * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously,
5490 * using only the provided backend tcg_out_* functions.
5493 static int tcg_out_helper_stk_ofs(TCGType type
, unsigned slot
)
5495 int ofs
= arg_slot_stk_ofs(slot
);
5498 * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not
5499 * require extension to uint64_t, adjust the address for uint32_t.
5501 if (HOST_BIG_ENDIAN
&&
5502 TCG_TARGET_REG_BITS
== 64 &&
5503 type
== TCG_TYPE_I32
) {
5509 static void tcg_out_helper_load_slots(TCGContext
*s
,
5510 unsigned nmov
, TCGMovExtend
*mov
,
5511 const TCGLdstHelperParam
*parm
)
5517 * Start from the end, storing to the stack first.
5518 * This frees those registers, so we need not consider overlap.
5520 for (i
= nmov
; i
-- > 0; ) {
5521 unsigned slot
= mov
[i
].dst
;
5523 if (arg_slot_reg_p(slot
)) {
5527 TCGReg src
= mov
[i
].src
;
5528 TCGType dst_type
= mov
[i
].dst_type
;
5529 MemOp dst_mo
= dst_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5531 /* The argument is going onto the stack; extend into scratch. */
5532 if ((mov
[i
].src_ext
& MO_SIZE
) != dst_mo
) {
5533 tcg_debug_assert(parm
->ntmp
!= 0);
5534 mov
[i
].dst
= src
= parm
->tmp
[0];
5535 tcg_out_movext1(s
, &mov
[i
]);
5538 tcg_out_st(s
, dst_type
, src
, TCG_REG_CALL_STACK
,
5539 tcg_out_helper_stk_ofs(dst_type
, slot
));
5545 * The remaining arguments are in registers.
5546 * Convert slot numbers to argument registers.
5549 for (i
= 0; i
< nmov
; ++i
) {
5550 mov
[i
].dst
= tcg_target_call_iarg_regs
[mov
[i
].dst
];
5555 /* The backend must have provided enough temps for the worst case. */
5556 tcg_debug_assert(parm
->ntmp
>= 2);
5559 for (unsigned j
= 0; j
< 3; ++j
) {
5560 if (dst3
== mov
[j
].src
) {
5562 * Conflict. Copy the source to a temporary, perform the
5563 * remaining moves, then the extension from our scratch
5566 TCGReg scratch
= parm
->tmp
[1];
5568 tcg_out_mov(s
, mov
[3].src_type
, scratch
, mov
[3].src
);
5569 tcg_out_movext3(s
, mov
, mov
+ 1, mov
+ 2, parm
->tmp
[0]);
5570 tcg_out_movext1_new_src(s
, &mov
[3], scratch
);
5575 /* No conflicts: perform this move and continue. */
5576 tcg_out_movext1(s
, &mov
[3]);
5580 tcg_out_movext3(s
, mov
, mov
+ 1, mov
+ 2,
5581 parm
->ntmp
? parm
->tmp
[0] : -1);
5584 tcg_out_movext2(s
, mov
, mov
+ 1,
5585 parm
->ntmp
? parm
->tmp
[0] : -1);
5588 tcg_out_movext1(s
, mov
);
5591 g_assert_not_reached();
5595 static void tcg_out_helper_load_imm(TCGContext
*s
, unsigned slot
,
5596 TCGType type
, tcg_target_long imm
,
5597 const TCGLdstHelperParam
*parm
)
5599 if (arg_slot_reg_p(slot
)) {
5600 tcg_out_movi(s
, type
, tcg_target_call_iarg_regs
[slot
], imm
);
5602 int ofs
= tcg_out_helper_stk_ofs(type
, slot
);
5603 if (!tcg_out_sti(s
, type
, imm
, TCG_REG_CALL_STACK
, ofs
)) {
5604 tcg_debug_assert(parm
->ntmp
!= 0);
5605 tcg_out_movi(s
, type
, parm
->tmp
[0], imm
);
5606 tcg_out_st(s
, type
, parm
->tmp
[0], TCG_REG_CALL_STACK
, ofs
);
5611 static void tcg_out_helper_load_common_args(TCGContext
*s
,
5612 const TCGLabelQemuLdst
*ldst
,
5613 const TCGLdstHelperParam
*parm
,
5614 const TCGHelperInfo
*info
,
5617 TCGMovExtend ptr_mov
= {
5618 .dst_type
= TCG_TYPE_PTR
,
5619 .src_type
= TCG_TYPE_PTR
,
5620 .src_ext
= sizeof(void *) == 4 ? MO_32
: MO_64
5622 const TCGCallArgumentLoc
*loc
= &info
->in
[0];
5625 tcg_target_ulong imm
;
5628 * Handle env, which is always first.
5630 ptr_mov
.dst
= loc
->arg_slot
;
5631 ptr_mov
.src
= TCG_AREG0
;
5632 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5638 loc
= &info
->in
[next_arg
];
5639 type
= TCG_TYPE_I32
;
5640 switch (loc
->kind
) {
5641 case TCG_CALL_ARG_NORMAL
:
5643 case TCG_CALL_ARG_EXTEND_U
:
5644 case TCG_CALL_ARG_EXTEND_S
:
5645 /* No extension required for MemOpIdx. */
5646 tcg_debug_assert(imm
<= INT32_MAX
);
5647 type
= TCG_TYPE_REG
;
5650 g_assert_not_reached();
5652 tcg_out_helper_load_imm(s
, loc
->arg_slot
, type
, imm
, parm
);
5658 loc
= &info
->in
[next_arg
];
5659 slot
= loc
->arg_slot
;
5664 if (arg_slot_reg_p(slot
)) {
5665 arg_reg
= tcg_target_call_iarg_regs
[slot
];
5667 ra_reg
= parm
->ra_gen(s
, ldst
, arg_reg
);
5670 ptr_mov
.src
= ra_reg
;
5671 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5673 imm
= (uintptr_t)ldst
->raddr
;
5674 tcg_out_helper_load_imm(s
, slot
, TCG_TYPE_PTR
, imm
, parm
);
5678 static unsigned tcg_out_helper_add_mov(TCGMovExtend
*mov
,
5679 const TCGCallArgumentLoc
*loc
,
5680 TCGType dst_type
, TCGType src_type
,
5681 TCGReg lo
, TCGReg hi
)
5685 if (dst_type
<= TCG_TYPE_REG
) {
5688 switch (loc
->kind
) {
5689 case TCG_CALL_ARG_NORMAL
:
5690 src_ext
= src_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5692 case TCG_CALL_ARG_EXTEND_U
:
5693 dst_type
= TCG_TYPE_REG
;
5696 case TCG_CALL_ARG_EXTEND_S
:
5697 dst_type
= TCG_TYPE_REG
;
5701 g_assert_not_reached();
5704 mov
[0].dst
= loc
->arg_slot
;
5705 mov
[0].dst_type
= dst_type
;
5707 mov
[0].src_type
= src_type
;
5708 mov
[0].src_ext
= src_ext
;
5712 if (TCG_TARGET_REG_BITS
== 32) {
5713 assert(dst_type
== TCG_TYPE_I64
);
5716 assert(dst_type
== TCG_TYPE_I128
);
5720 mov
[0].dst
= loc
[HOST_BIG_ENDIAN
].arg_slot
;
5722 mov
[0].dst_type
= TCG_TYPE_REG
;
5723 mov
[0].src_type
= TCG_TYPE_REG
;
5724 mov
[0].src_ext
= reg_mo
;
5726 mov
[1].dst
= loc
[!HOST_BIG_ENDIAN
].arg_slot
;
5728 mov
[1].dst_type
= TCG_TYPE_REG
;
5729 mov
[1].src_type
= TCG_TYPE_REG
;
5730 mov
[1].src_ext
= reg_mo
;
5735 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5736 const TCGLdstHelperParam
*parm
)
5738 const TCGHelperInfo
*info
;
5739 const TCGCallArgumentLoc
*loc
;
5740 TCGMovExtend mov
[2];
5741 unsigned next_arg
, nmov
;
5742 MemOp mop
= get_memop(ldst
->oi
);
5744 switch (mop
& MO_SIZE
) {
5748 info
= &info_helper_ld32_mmu
;
5751 info
= &info_helper_ld64_mmu
;
5754 info
= &info_helper_ld128_mmu
;
5757 g_assert_not_reached();
5760 /* Defer env argument. */
5763 loc
= &info
->in
[next_arg
];
5764 if (TCG_TARGET_REG_BITS
== 32 && s
->addr_type
== TCG_TYPE_I32
) {
5766 * 32-bit host with 32-bit guest: zero-extend the guest address
5767 * to 64-bits for the helper by storing the low part, then
5768 * load a zero for the high part.
5770 tcg_out_helper_add_mov(mov
, loc
+ HOST_BIG_ENDIAN
,
5771 TCG_TYPE_I32
, TCG_TYPE_I32
,
5772 ldst
->addrlo_reg
, -1);
5773 tcg_out_helper_load_slots(s
, 1, mov
, parm
);
5775 tcg_out_helper_load_imm(s
, loc
[!HOST_BIG_ENDIAN
].arg_slot
,
5776 TCG_TYPE_I32
, 0, parm
);
5779 nmov
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_I64
, s
->addr_type
,
5780 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5781 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5785 switch (info
->out_kind
) {
5786 case TCG_CALL_RET_NORMAL
:
5787 case TCG_CALL_RET_BY_VEC
:
5789 case TCG_CALL_RET_BY_REF
:
5791 * The return reference is in the first argument slot.
5792 * We need memory in which to return: re-use the top of stack.
5795 int ofs_slot0
= TCG_TARGET_CALL_STACK_OFFSET
;
5797 if (arg_slot_reg_p(0)) {
5798 tcg_out_addi_ptr(s
, tcg_target_call_iarg_regs
[0],
5799 TCG_REG_CALL_STACK
, ofs_slot0
);
5801 tcg_debug_assert(parm
->ntmp
!= 0);
5802 tcg_out_addi_ptr(s
, parm
->tmp
[0],
5803 TCG_REG_CALL_STACK
, ofs_slot0
);
5804 tcg_out_st(s
, TCG_TYPE_PTR
, parm
->tmp
[0],
5805 TCG_REG_CALL_STACK
, ofs_slot0
);
5810 g_assert_not_reached();
5813 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5816 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5818 const TCGLdstHelperParam
*parm
)
5820 MemOp mop
= get_memop(ldst
->oi
);
5821 TCGMovExtend mov
[2];
5824 switch (ldst
->type
) {
5826 if (TCG_TARGET_REG_BITS
== 32) {
5832 mov
[0].dst
= ldst
->datalo_reg
;
5833 mov
[0].src
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, 0);
5834 mov
[0].dst_type
= ldst
->type
;
5835 mov
[0].src_type
= TCG_TYPE_REG
;
5838 * If load_sign, then we allowed the helper to perform the
5839 * appropriate sign extension to tcg_target_ulong, and all
5840 * we need now is a plain move.
5842 * If they do not, then we expect the relevant extension
5843 * instruction to be no more expensive than a move, and
5844 * we thus save the icache etc by only using one of two
5847 if (load_sign
|| !(mop
& MO_SIGN
)) {
5848 if (TCG_TARGET_REG_BITS
== 32 || ldst
->type
== TCG_TYPE_I32
) {
5849 mov
[0].src_ext
= MO_32
;
5851 mov
[0].src_ext
= MO_64
;
5854 mov
[0].src_ext
= mop
& MO_SSIZE
;
5856 tcg_out_movext1(s
, mov
);
5860 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
5861 ofs_slot0
= TCG_TARGET_CALL_STACK_OFFSET
;
5862 switch (TCG_TARGET_CALL_RET_I128
) {
5863 case TCG_CALL_RET_NORMAL
:
5865 case TCG_CALL_RET_BY_VEC
:
5866 tcg_out_st(s
, TCG_TYPE_V128
,
5867 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
5868 TCG_REG_CALL_STACK
, ofs_slot0
);
5870 case TCG_CALL_RET_BY_REF
:
5871 tcg_out_ld(s
, TCG_TYPE_I64
, ldst
->datalo_reg
,
5872 TCG_REG_CALL_STACK
, ofs_slot0
+ 8 * HOST_BIG_ENDIAN
);
5873 tcg_out_ld(s
, TCG_TYPE_I64
, ldst
->datahi_reg
,
5874 TCG_REG_CALL_STACK
, ofs_slot0
+ 8 * !HOST_BIG_ENDIAN
);
5877 g_assert_not_reached();
5882 g_assert_not_reached();
5885 mov
[0].dst
= ldst
->datalo_reg
;
5887 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, HOST_BIG_ENDIAN
);
5888 mov
[0].dst_type
= TCG_TYPE_REG
;
5889 mov
[0].src_type
= TCG_TYPE_REG
;
5890 mov
[0].src_ext
= TCG_TARGET_REG_BITS
== 32 ? MO_32
: MO_64
;
5892 mov
[1].dst
= ldst
->datahi_reg
;
5894 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, !HOST_BIG_ENDIAN
);
5895 mov
[1].dst_type
= TCG_TYPE_REG
;
5896 mov
[1].src_type
= TCG_TYPE_REG
;
5897 mov
[1].src_ext
= TCG_TARGET_REG_BITS
== 32 ? MO_32
: MO_64
;
5899 tcg_out_movext2(s
, mov
, mov
+ 1, parm
->ntmp
? parm
->tmp
[0] : -1);
5902 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5903 const TCGLdstHelperParam
*parm
)
5905 const TCGHelperInfo
*info
;
5906 const TCGCallArgumentLoc
*loc
;
5907 TCGMovExtend mov
[4];
5909 unsigned next_arg
, nmov
, n
;
5910 MemOp mop
= get_memop(ldst
->oi
);
5912 switch (mop
& MO_SIZE
) {
5916 info
= &info_helper_st32_mmu
;
5917 data_type
= TCG_TYPE_I32
;
5920 info
= &info_helper_st64_mmu
;
5921 data_type
= TCG_TYPE_I64
;
5924 info
= &info_helper_st128_mmu
;
5925 data_type
= TCG_TYPE_I128
;
5928 g_assert_not_reached();
5931 /* Defer env argument. */
5935 /* Handle addr argument. */
5936 loc
= &info
->in
[next_arg
];
5937 if (TCG_TARGET_REG_BITS
== 32 && s
->addr_type
== TCG_TYPE_I32
) {
5939 * 32-bit host with 32-bit guest: zero-extend the guest address
5940 * to 64-bits for the helper by storing the low part. Later,
5941 * after we have processed the register inputs, we will load a
5942 * zero for the high part.
5944 tcg_out_helper_add_mov(mov
, loc
+ HOST_BIG_ENDIAN
,
5945 TCG_TYPE_I32
, TCG_TYPE_I32
,
5946 ldst
->addrlo_reg
, -1);
5950 n
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_I64
, s
->addr_type
,
5951 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5956 /* Handle data argument. */
5957 loc
= &info
->in
[next_arg
];
5958 switch (loc
->kind
) {
5959 case TCG_CALL_ARG_NORMAL
:
5960 case TCG_CALL_ARG_EXTEND_U
:
5961 case TCG_CALL_ARG_EXTEND_S
:
5962 n
= tcg_out_helper_add_mov(mov
+ nmov
, loc
, data_type
, ldst
->type
,
5963 ldst
->datalo_reg
, ldst
->datahi_reg
);
5966 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5969 case TCG_CALL_ARG_BY_REF
:
5970 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
5971 tcg_debug_assert(data_type
== TCG_TYPE_I128
);
5972 tcg_out_st(s
, TCG_TYPE_I64
,
5973 HOST_BIG_ENDIAN
? ldst
->datahi_reg
: ldst
->datalo_reg
,
5974 TCG_REG_CALL_STACK
, arg_slot_stk_ofs(loc
[0].ref_slot
));
5975 tcg_out_st(s
, TCG_TYPE_I64
,
5976 HOST_BIG_ENDIAN
? ldst
->datalo_reg
: ldst
->datahi_reg
,
5977 TCG_REG_CALL_STACK
, arg_slot_stk_ofs(loc
[1].ref_slot
));
5979 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5981 if (arg_slot_reg_p(loc
->arg_slot
)) {
5982 tcg_out_addi_ptr(s
, tcg_target_call_iarg_regs
[loc
->arg_slot
],
5984 arg_slot_stk_ofs(loc
->ref_slot
));
5986 tcg_debug_assert(parm
->ntmp
!= 0);
5987 tcg_out_addi_ptr(s
, parm
->tmp
[0], TCG_REG_CALL_STACK
,
5988 arg_slot_stk_ofs(loc
->ref_slot
));
5989 tcg_out_st(s
, TCG_TYPE_PTR
, parm
->tmp
[0],
5990 TCG_REG_CALL_STACK
, arg_slot_stk_ofs(loc
->arg_slot
));
5996 g_assert_not_reached();
5999 if (TCG_TARGET_REG_BITS
== 32 && s
->addr_type
== TCG_TYPE_I32
) {
6000 /* Zero extend the address by loading a zero for the high part. */
6001 loc
= &info
->in
[1 + !HOST_BIG_ENDIAN
];
6002 tcg_out_helper_load_imm(s
, loc
->arg_slot
, TCG_TYPE_I32
, 0, parm
);
6005 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
6008 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
, uint64_t pc_start
)
6010 int i
, start_words
, num_insns
;
6013 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)
6014 && qemu_log_in_addr_range(pc_start
))) {
6015 FILE *logfile
= qemu_log_trylock();
6017 fprintf(logfile
, "OP:\n");
6018 tcg_dump_ops(s
, logfile
, false);
6019 fprintf(logfile
, "\n");
6020 qemu_log_unlock(logfile
);
6024 #ifdef CONFIG_DEBUG_TCG
6025 /* Ensure all labels referenced have been emitted. */
6030 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
6031 if (unlikely(!l
->present
) && !QSIMPLEQ_EMPTY(&l
->branches
)) {
6032 qemu_log_mask(CPU_LOG_TB_OP
,
6033 "$L%d referenced but not present.\n", l
->id
);
6043 reachable_code_pass(s
);
6047 if (s
->nb_indirects
> 0) {
6048 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND
)
6049 && qemu_log_in_addr_range(pc_start
))) {
6050 FILE *logfile
= qemu_log_trylock();
6052 fprintf(logfile
, "OP before indirect lowering:\n");
6053 tcg_dump_ops(s
, logfile
, false);
6054 fprintf(logfile
, "\n");
6055 qemu_log_unlock(logfile
);
6059 /* Replace indirect temps with direct temps. */
6060 if (liveness_pass_2(s
)) {
6061 /* If changes were made, re-run liveness. */
6066 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
)
6067 && qemu_log_in_addr_range(pc_start
))) {
6068 FILE *logfile
= qemu_log_trylock();
6070 fprintf(logfile
, "OP after optimization and liveness analysis:\n");
6071 tcg_dump_ops(s
, logfile
, true);
6072 fprintf(logfile
, "\n");
6073 qemu_log_unlock(logfile
);
6077 /* Initialize goto_tb jump offsets. */
6078 tb
->jmp_reset_offset
[0] = TB_JMP_OFFSET_INVALID
;
6079 tb
->jmp_reset_offset
[1] = TB_JMP_OFFSET_INVALID
;
6080 tb
->jmp_insn_offset
[0] = TB_JMP_OFFSET_INVALID
;
6081 tb
->jmp_insn_offset
[1] = TB_JMP_OFFSET_INVALID
;
6083 tcg_reg_alloc_start(s
);
6086 * Reset the buffer pointers when restarting after overflow.
6087 * TODO: Move this into translate-all.c with the rest of the
6088 * buffer management. Having only this done here is confusing.
6090 s
->code_buf
= tcg_splitwx_to_rw(tb
->tc
.ptr
);
6091 s
->code_ptr
= s
->code_buf
;
6093 #ifdef TCG_TARGET_NEED_LDST_LABELS
6094 QSIMPLEQ_INIT(&s
->ldst_labels
);
6096 #ifdef TCG_TARGET_NEED_POOL_LABELS
6097 s
->pool_labels
= NULL
;
6100 start_words
= s
->insn_start_words
;
6102 tcg_malloc(sizeof(uint64_t) * s
->gen_tb
->icount
* start_words
);
6104 tcg_out_tb_start(s
);
6107 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
6108 TCGOpcode opc
= op
->opc
;
6111 case INDEX_op_mov_i32
:
6112 case INDEX_op_mov_i64
:
6113 case INDEX_op_mov_vec
:
6114 tcg_reg_alloc_mov(s
, op
);
6116 case INDEX_op_dup_vec
:
6117 tcg_reg_alloc_dup(s
, op
);
6119 case INDEX_op_insn_start
:
6120 if (num_insns
>= 0) {
6121 size_t off
= tcg_current_code_size(s
);
6122 s
->gen_insn_end_off
[num_insns
] = off
;
6123 /* Assert that we do not overflow our stored offset. */
6124 assert(s
->gen_insn_end_off
[num_insns
] == off
);
6127 for (i
= 0; i
< start_words
; ++i
) {
6128 s
->gen_insn_data
[num_insns
* start_words
+ i
] =
6129 tcg_get_insn_start_param(op
, i
);
6132 case INDEX_op_discard
:
6133 temp_dead(s
, arg_temp(op
->args
[0]));
6135 case INDEX_op_set_label
:
6136 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
6137 tcg_out_label(s
, arg_label(op
->args
[0]));
6140 tcg_reg_alloc_call(s
, op
);
6142 case INDEX_op_exit_tb
:
6143 tcg_out_exit_tb(s
, op
->args
[0]);
6145 case INDEX_op_goto_tb
:
6146 tcg_out_goto_tb(s
, op
->args
[0]);
6148 case INDEX_op_dup2_vec
:
6149 if (tcg_reg_alloc_dup2(s
, op
)) {
6154 /* Sanity check that we've not introduced any unhandled opcodes. */
6155 tcg_debug_assert(tcg_op_supported(opc
));
6156 /* Note: in order to speed up the code, it would be much
6157 faster to have specialized register allocator functions for
6158 some common argument patterns */
6159 tcg_reg_alloc_op(s
, op
);
6162 /* Test for (pending) buffer overflow. The assumption is that any
6163 one operation beginning below the high water mark cannot overrun
6164 the buffer completely. Thus we can test for overflow after
6165 generating code without having to check during generation. */
6166 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
6169 /* Test for TB overflow, as seen by gen_insn_end_off. */
6170 if (unlikely(tcg_current_code_size(s
) > UINT16_MAX
)) {
6174 tcg_debug_assert(num_insns
+ 1 == s
->gen_tb
->icount
);
6175 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
6177 /* Generate TB finalization at the end of block */
6178 #ifdef TCG_TARGET_NEED_LDST_LABELS
6179 i
= tcg_out_ldst_finalize(s
);
6184 #ifdef TCG_TARGET_NEED_POOL_LABELS
6185 i
= tcg_out_pool_finalize(s
);
6190 if (!tcg_resolve_relocs(s
)) {
6194 #ifndef CONFIG_TCG_INTERPRETER
6195 /* flush instruction cache */
6196 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
6197 (uintptr_t)s
->code_buf
,
6198 tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
));
6201 return tcg_current_code_size(s
);
6204 #ifdef ELF_HOST_MACHINE
6205 /* In order to use this feature, the backend needs to do three things:
6207 (1) Define ELF_HOST_MACHINE to indicate both what value to
6208 put into the ELF image and to indicate support for the feature.
6210 (2) Define tcg_register_jit. This should create a buffer containing
6211 the contents of a .debug_frame section that describes the post-
6212 prologue unwind info for the tcg machine.
6214 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
6217 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
6224 struct jit_code_entry
{
6225 struct jit_code_entry
*next_entry
;
6226 struct jit_code_entry
*prev_entry
;
6227 const void *symfile_addr
;
6228 uint64_t symfile_size
;
6231 struct jit_descriptor
{
6233 uint32_t action_flag
;
6234 struct jit_code_entry
*relevant_entry
;
6235 struct jit_code_entry
*first_entry
;
6238 void __jit_debug_register_code(void) __attribute__((noinline
));
6239 void __jit_debug_register_code(void)
6244 /* Must statically initialize the version, because GDB may check
6245 the version before we can set it. */
6246 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
6248 /* End GDB interface. */
6250 static int find_string(const char *strtab
, const char *str
)
6252 const char *p
= strtab
+ 1;
6255 if (strcmp(p
, str
) == 0) {
6262 static void tcg_register_jit_int(const void *buf_ptr
, size_t buf_size
,
6263 const void *debug_frame
,
6264 size_t debug_frame_size
)
6266 struct __attribute__((packed
)) DebugInfo
{
6273 uintptr_t cu_low_pc
;
6274 uintptr_t cu_high_pc
;
6277 uintptr_t fn_low_pc
;
6278 uintptr_t fn_high_pc
;
6287 struct DebugInfo di
;
6292 struct ElfImage
*img
;
6294 static const struct ElfImage img_template
= {
6296 .e_ident
[EI_MAG0
] = ELFMAG0
,
6297 .e_ident
[EI_MAG1
] = ELFMAG1
,
6298 .e_ident
[EI_MAG2
] = ELFMAG2
,
6299 .e_ident
[EI_MAG3
] = ELFMAG3
,
6300 .e_ident
[EI_CLASS
] = ELF_CLASS
,
6301 .e_ident
[EI_DATA
] = ELF_DATA
,
6302 .e_ident
[EI_VERSION
] = EV_CURRENT
,
6304 .e_machine
= ELF_HOST_MACHINE
,
6305 .e_version
= EV_CURRENT
,
6306 .e_phoff
= offsetof(struct ElfImage
, phdr
),
6307 .e_shoff
= offsetof(struct ElfImage
, shdr
),
6308 .e_ehsize
= sizeof(ElfW(Shdr
)),
6309 .e_phentsize
= sizeof(ElfW(Phdr
)),
6311 .e_shentsize
= sizeof(ElfW(Shdr
)),
6312 .e_shnum
= ARRAY_SIZE(img
->shdr
),
6313 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
6314 #ifdef ELF_HOST_FLAGS
6315 .e_flags
= ELF_HOST_FLAGS
,
6318 .e_ident
[EI_OSABI
] = ELF_OSABI
,
6326 [0] = { .sh_type
= SHT_NULL
},
6327 /* Trick: The contents of code_gen_buffer are not present in
6328 this fake ELF file; that got allocated elsewhere. Therefore
6329 we mark .text as SHT_NOBITS (similar to .bss) so that readers
6330 will not look for contents. We can record any address. */
6332 .sh_type
= SHT_NOBITS
,
6333 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
6335 [2] = { /* .debug_info */
6336 .sh_type
= SHT_PROGBITS
,
6337 .sh_offset
= offsetof(struct ElfImage
, di
),
6338 .sh_size
= sizeof(struct DebugInfo
),
6340 [3] = { /* .debug_abbrev */
6341 .sh_type
= SHT_PROGBITS
,
6342 .sh_offset
= offsetof(struct ElfImage
, da
),
6343 .sh_size
= sizeof(img
->da
),
6345 [4] = { /* .debug_frame */
6346 .sh_type
= SHT_PROGBITS
,
6347 .sh_offset
= sizeof(struct ElfImage
),
6349 [5] = { /* .symtab */
6350 .sh_type
= SHT_SYMTAB
,
6351 .sh_offset
= offsetof(struct ElfImage
, sym
),
6352 .sh_size
= sizeof(img
->sym
),
6354 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
6355 .sh_entsize
= sizeof(ElfW(Sym
)),
6357 [6] = { /* .strtab */
6358 .sh_type
= SHT_STRTAB
,
6359 .sh_offset
= offsetof(struct ElfImage
, str
),
6360 .sh_size
= sizeof(img
->str
),
6364 [1] = { /* code_gen_buffer */
6365 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
6370 .len
= sizeof(struct DebugInfo
) - 4,
6372 .ptr_size
= sizeof(void *),
6374 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
6376 .fn_name
= "code_gen_buffer"
6379 1, /* abbrev number (the cu) */
6380 0x11, 1, /* DW_TAG_compile_unit, has children */
6381 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
6382 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6383 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6384 0, 0, /* end of abbrev */
6385 2, /* abbrev number (the fn) */
6386 0x2e, 0, /* DW_TAG_subprogram, no children */
6387 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
6388 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6389 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6390 0, 0, /* end of abbrev */
6391 0 /* no more abbrev */
6393 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
6394 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
6397 /* We only need a single jit entry; statically allocate it. */
6398 static struct jit_code_entry one_entry
;
6400 uintptr_t buf
= (uintptr_t)buf_ptr
;
6401 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
6402 DebugFrameHeader
*dfh
;
6404 img
= g_malloc(img_size
);
6405 *img
= img_template
;
6407 img
->phdr
.p_vaddr
= buf
;
6408 img
->phdr
.p_paddr
= buf
;
6409 img
->phdr
.p_memsz
= buf_size
;
6411 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
6412 img
->shdr
[1].sh_addr
= buf
;
6413 img
->shdr
[1].sh_size
= buf_size
;
6415 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
6416 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
6418 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
6419 img
->shdr
[4].sh_size
= debug_frame_size
;
6421 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
6422 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
6424 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
6425 img
->sym
[1].st_value
= buf
;
6426 img
->sym
[1].st_size
= buf_size
;
6428 img
->di
.cu_low_pc
= buf
;
6429 img
->di
.cu_high_pc
= buf
+ buf_size
;
6430 img
->di
.fn_low_pc
= buf
;
6431 img
->di
.fn_high_pc
= buf
+ buf_size
;
6433 dfh
= (DebugFrameHeader
*)(img
+ 1);
6434 memcpy(dfh
, debug_frame
, debug_frame_size
);
6435 dfh
->fde
.func_start
= buf
;
6436 dfh
->fde
.func_len
= buf_size
;
6439 /* Enable this block to be able to debug the ELF image file creation.
6440 One can use readelf, objdump, or other inspection utilities. */
6442 g_autofree
char *jit
= g_strdup_printf("%s/qemu.jit", g_get_tmp_dir());
6443 FILE *f
= fopen(jit
, "w+b");
6445 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
6446 /* Avoid stupid unused return value warning for fwrite. */
6453 one_entry
.symfile_addr
= img
;
6454 one_entry
.symfile_size
= img_size
;
6456 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
6457 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
6458 __jit_debug_descriptor
.first_entry
= &one_entry
;
6459 __jit_debug_register_code();
6462 /* No support for the feature. Provide the entry point expected by exec.c,
6463 and implement the internal function we declared earlier. */
6465 static void tcg_register_jit_int(const void *buf
, size_t size
,
6466 const void *debug_frame
,
6467 size_t debug_frame_size
)
6471 void tcg_register_jit(const void *buf
, size_t buf_size
)
6474 #endif /* ELF_HOST_MACHINE */
6476 #if !TCG_TARGET_MAYBE_vec
6477 void tcg_expand_vec_op(TCGOpcode o
, TCGType t
, unsigned e
, TCGArg a0
, ...)
6479 g_assert_not_reached();