2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_TCG_OPTIMIZATIONS
28 #include "qemu/osdep.h"
30 /* Define to jump the ELF file used to communicate with GDB. */
33 #include "qemu/error-report.h"
34 #include "qemu/cutils.h"
35 #include "qemu/host-utils.h"
36 #include "qemu/qemu-print.h"
37 #include "qemu/cacheflush.h"
38 #include "qemu/cacheinfo.h"
39 #include "qemu/timer.h"
41 /* Note: the long term plan is to reduce the dependencies on the QEMU
42 CPU definitions. Currently they are used for qemu_ld/st
44 #define NO_CPU_IO_DEFS
46 #include "exec/exec-all.h"
47 #include "tcg/tcg-op.h"
49 #if UINTPTR_MAX == UINT32_MAX
50 # define ELF_CLASS ELFCLASS32
52 # define ELF_CLASS ELFCLASS64
55 # define ELF_DATA ELFDATA2MSB
57 # define ELF_DATA ELFDATA2LSB
62 #include "tcg/tcg-ldst.h"
63 #include "tcg/tcg-temp-internal.h"
64 #include "tcg-internal.h"
65 #include "accel/tcg/perf.h"
67 /* Forward declarations for functions declared in tcg-target.c.inc and
69 static void tcg_target_init(TCGContext
*s
);
70 static void tcg_target_qemu_prologue(TCGContext
*s
);
71 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
72 intptr_t value
, intptr_t addend
);
74 /* The CIE and FDE header definitions will be common to all hosts. */
76 uint32_t len
__attribute__((aligned((sizeof(void *)))));
82 uint8_t return_column
;
85 typedef struct QEMU_PACKED
{
86 uint32_t len
__attribute__((aligned((sizeof(void *)))));
90 } DebugFrameFDEHeader
;
92 typedef struct QEMU_PACKED
{
94 DebugFrameFDEHeader fde
;
97 static void tcg_register_jit_int(const void *buf
, size_t size
,
98 const void *debug_frame
,
99 size_t debug_frame_size
)
100 __attribute__((unused
));
102 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
103 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
105 static bool tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
106 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
107 TCGReg ret
, tcg_target_long arg
);
108 static void tcg_out_addi_ptr(TCGContext
*s
, TCGReg
, TCGReg
, tcg_target_long
);
109 static void tcg_out_exit_tb(TCGContext
*s
, uintptr_t arg
);
110 static void tcg_out_goto_tb(TCGContext
*s
, int which
);
111 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
112 const TCGArg args
[TCG_MAX_OP_ARGS
],
113 const int const_args
[TCG_MAX_OP_ARGS
]);
114 #if TCG_TARGET_MAYBE_vec
115 static bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
116 TCGReg dst
, TCGReg src
);
117 static bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
118 TCGReg dst
, TCGReg base
, intptr_t offset
);
119 static void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
120 TCGReg dst
, int64_t arg
);
121 static void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
122 unsigned vecl
, unsigned vece
,
123 const TCGArg args
[TCG_MAX_OP_ARGS
],
124 const int const_args
[TCG_MAX_OP_ARGS
]);
126 static inline bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
127 TCGReg dst
, TCGReg src
)
129 g_assert_not_reached();
131 static inline bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
132 TCGReg dst
, TCGReg base
, intptr_t offset
)
134 g_assert_not_reached();
136 static inline void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
137 TCGReg dst
, int64_t arg
)
139 g_assert_not_reached();
141 static inline void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
142 unsigned vecl
, unsigned vece
,
143 const TCGArg args
[TCG_MAX_OP_ARGS
],
144 const int const_args
[TCG_MAX_OP_ARGS
])
146 g_assert_not_reached();
149 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
151 static bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
152 TCGReg base
, intptr_t ofs
);
153 static void tcg_out_call(TCGContext
*s
, const tcg_insn_unit
*target
,
154 const TCGHelperInfo
*info
);
155 static TCGReg
tcg_target_call_oarg_reg(TCGCallReturnKind kind
, int slot
);
156 static bool tcg_target_const_match(int64_t val
, TCGType type
, int ct
);
157 #ifdef TCG_TARGET_NEED_LDST_LABELS
158 static int tcg_out_ldst_finalize(TCGContext
*s
);
161 TCGContext tcg_init_ctx
;
162 __thread TCGContext
*tcg_ctx
;
164 TCGContext
**tcg_ctxs
;
165 unsigned int tcg_cur_ctxs
;
166 unsigned int tcg_max_ctxs
;
167 TCGv_env cpu_env
= 0;
168 const void *tcg_code_gen_epilogue
;
169 uintptr_t tcg_splitwx_diff
;
171 #ifndef CONFIG_TCG_INTERPRETER
172 tcg_prologue_fn
*tcg_qemu_tb_exec
;
175 static TCGRegSet tcg_target_available_regs
[TCG_TYPE_COUNT
];
176 static TCGRegSet tcg_target_call_clobber_regs
;
178 #if TCG_TARGET_INSN_UNIT_SIZE == 1
179 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
184 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
191 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
192 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
194 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
197 tcg_insn_unit
*p
= s
->code_ptr
;
198 memcpy(p
, &v
, sizeof(v
));
199 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
203 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
206 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
209 memcpy(p
, &v
, sizeof(v
));
214 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
215 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
217 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
220 tcg_insn_unit
*p
= s
->code_ptr
;
221 memcpy(p
, &v
, sizeof(v
));
222 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
226 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
229 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
232 memcpy(p
, &v
, sizeof(v
));
237 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
238 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
240 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
243 tcg_insn_unit
*p
= s
->code_ptr
;
244 memcpy(p
, &v
, sizeof(v
));
245 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
249 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
252 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
255 memcpy(p
, &v
, sizeof(v
));
260 /* label relocation processing */
262 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
263 TCGLabel
*l
, intptr_t addend
)
265 TCGRelocation
*r
= tcg_malloc(sizeof(TCGRelocation
));
270 QSIMPLEQ_INSERT_TAIL(&l
->relocs
, r
, next
);
273 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
)
275 tcg_debug_assert(!l
->has_value
);
277 l
->u
.value_ptr
= tcg_splitwx_to_rx(s
->code_ptr
);
280 TCGLabel
*gen_new_label(void)
282 TCGContext
*s
= tcg_ctx
;
283 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
285 memset(l
, 0, sizeof(TCGLabel
));
286 l
->id
= s
->nb_labels
++;
287 QSIMPLEQ_INIT(&l
->branches
);
288 QSIMPLEQ_INIT(&l
->relocs
);
290 QSIMPLEQ_INSERT_TAIL(&s
->labels
, l
, next
);
295 static bool tcg_resolve_relocs(TCGContext
*s
)
299 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
301 uintptr_t value
= l
->u
.value
;
303 QSIMPLEQ_FOREACH(r
, &l
->relocs
, next
) {
304 if (!patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
)) {
312 static void set_jmp_reset_offset(TCGContext
*s
, int which
)
315 * We will check for overflow at the end of the opcode loop in
316 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
318 s
->gen_tb
->jmp_reset_offset
[which
] = tcg_current_code_size(s
);
321 static void G_GNUC_UNUSED
set_jmp_insn_offset(TCGContext
*s
, int which
)
324 * We will check for overflow at the end of the opcode loop in
325 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
327 s
->gen_tb
->jmp_insn_offset
[which
] = tcg_current_code_size(s
);
330 static uintptr_t G_GNUC_UNUSED
get_jmp_target_addr(TCGContext
*s
, int which
)
333 * Return the read-execute version of the pointer, for the benefit
334 * of any pc-relative addressing mode.
336 return (uintptr_t)tcg_splitwx_to_rx(&s
->gen_tb
->jmp_target_addr
[which
]);
339 /* Signal overflow, starting over with fewer guest insns. */
341 void tcg_raise_tb_overflow(TCGContext
*s
)
343 siglongjmp(s
->jmp_trans
, -2);
346 #define C_PFX1(P, A) P##A
347 #define C_PFX2(P, A, B) P##A##_##B
348 #define C_PFX3(P, A, B, C) P##A##_##B##_##C
349 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
350 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
351 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
353 /* Define an enumeration for the various combinations. */
355 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
356 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
357 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
358 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
360 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
361 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
362 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
363 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
365 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
367 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
368 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
369 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
370 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
373 #include "tcg-target-con-set.h"
374 } TCGConstraintSetIndex
;
376 static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode
);
392 /* Put all of the constraint sets into an array, indexed by the enum. */
394 #define C_O0_I1(I1) { .args_ct_str = { #I1 } },
395 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
396 #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
397 #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
399 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
400 #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
401 #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
402 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
404 #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
406 #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
407 #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
408 #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
409 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
411 static const TCGTargetOpDef constraint_sets
[] = {
412 #include "tcg-target-con-set.h"
430 /* Expand the enumerator to be returned from tcg_target_op_def(). */
432 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
433 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
434 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
435 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
437 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
438 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
439 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
440 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
442 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
444 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
445 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
446 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
447 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
449 #include "tcg-target.c.inc"
451 static void alloc_tcg_plugin_context(TCGContext
*s
)
454 s
->plugin_tb
= g_new0(struct qemu_plugin_tb
, 1);
455 s
->plugin_tb
->insns
=
456 g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn
);
461 * All TCG threads except the parent (i.e. the one that called tcg_context_init
462 * and registered the target's TCG globals) must register with this function
463 * before initiating translation.
465 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation
466 * of tcg_region_init() for the reasoning behind this.
468 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in
469 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context
470 * is not used anymore for translation once this function is called.
472 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates
473 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode.
475 #ifdef CONFIG_USER_ONLY
476 void tcg_register_thread(void)
478 tcg_ctx
= &tcg_init_ctx
;
481 void tcg_register_thread(void)
483 TCGContext
*s
= g_malloc(sizeof(*s
));
488 /* Relink mem_base. */
489 for (i
= 0, n
= tcg_init_ctx
.nb_globals
; i
< n
; ++i
) {
490 if (tcg_init_ctx
.temps
[i
].mem_base
) {
491 ptrdiff_t b
= tcg_init_ctx
.temps
[i
].mem_base
- tcg_init_ctx
.temps
;
492 tcg_debug_assert(b
>= 0 && b
< n
);
493 s
->temps
[i
].mem_base
= &s
->temps
[b
];
497 /* Claim an entry in tcg_ctxs */
498 n
= qatomic_fetch_inc(&tcg_cur_ctxs
);
499 g_assert(n
< tcg_max_ctxs
);
500 qatomic_set(&tcg_ctxs
[n
], s
);
503 alloc_tcg_plugin_context(s
);
504 tcg_region_initial_alloc(s
);
509 #endif /* !CONFIG_USER_ONLY */
511 /* pool based memory allocation */
512 void *tcg_malloc_internal(TCGContext
*s
, int size
)
517 if (size
> TCG_POOL_CHUNK_SIZE
) {
518 /* big malloc: insert a new pool (XXX: could optimize) */
519 p
= g_malloc(sizeof(TCGPool
) + size
);
521 p
->next
= s
->pool_first_large
;
522 s
->pool_first_large
= p
;
533 pool_size
= TCG_POOL_CHUNK_SIZE
;
534 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
537 if (s
->pool_current
) {
538 s
->pool_current
->next
= p
;
548 s
->pool_cur
= p
->data
+ size
;
549 s
->pool_end
= p
->data
+ p
->size
;
553 void tcg_pool_reset(TCGContext
*s
)
556 for (p
= s
->pool_first_large
; p
; p
= t
) {
560 s
->pool_first_large
= NULL
;
561 s
->pool_cur
= s
->pool_end
= NULL
;
562 s
->pool_current
= NULL
;
565 #include "exec/helper-proto.h"
567 static TCGHelperInfo all_helpers
[] = {
568 #include "exec/helper-tcg.h"
570 static GHashTable
*helper_table
;
572 #ifdef CONFIG_TCG_INTERPRETER
573 static ffi_type
*typecode_to_ffi(int argmask
)
576 * libffi does not support __int128_t, so we have forced Int128
577 * to use the structure definition instead of the builtin type.
579 static ffi_type
*ffi_type_i128_elements
[3] = {
584 static ffi_type ffi_type_i128
= {
586 .alignment
= __alignof__(Int128
),
587 .type
= FFI_TYPE_STRUCT
,
588 .elements
= ffi_type_i128_elements
,
592 case dh_typecode_void
:
593 return &ffi_type_void
;
594 case dh_typecode_i32
:
595 return &ffi_type_uint32
;
596 case dh_typecode_s32
:
597 return &ffi_type_sint32
;
598 case dh_typecode_i64
:
599 return &ffi_type_uint64
;
600 case dh_typecode_s64
:
601 return &ffi_type_sint64
;
602 case dh_typecode_ptr
:
603 return &ffi_type_pointer
;
604 case dh_typecode_i128
:
605 return &ffi_type_i128
;
607 g_assert_not_reached();
610 static void init_ffi_layouts(void)
612 /* g_direct_hash/equal for direct comparisons on uint32_t. */
613 GHashTable
*ffi_table
= g_hash_table_new(NULL
, NULL
);
615 for (int i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
616 TCGHelperInfo
*info
= &all_helpers
[i
];
617 unsigned typemask
= info
->typemask
;
618 gpointer hash
= (gpointer
)(uintptr_t)typemask
;
627 cif
= g_hash_table_lookup(ffi_table
, hash
);
633 /* Ignoring the return type, find the last non-zero field. */
634 nargs
= 32 - clz32(typemask
>> 3);
635 nargs
= DIV_ROUND_UP(nargs
, 3);
636 assert(nargs
<= MAX_CALL_IARGS
);
638 ca
= g_malloc0(sizeof(*ca
) + nargs
* sizeof(ffi_type
*));
639 ca
->cif
.rtype
= typecode_to_ffi(typemask
& 7);
640 ca
->cif
.nargs
= nargs
;
643 ca
->cif
.arg_types
= ca
->args
;
644 for (int j
= 0; j
< nargs
; ++j
) {
645 int typecode
= extract32(typemask
, (j
+ 1) * 3, 3);
646 ca
->args
[j
] = typecode_to_ffi(typecode
);
650 status
= ffi_prep_cif(&ca
->cif
, FFI_DEFAULT_ABI
, nargs
,
651 ca
->cif
.rtype
, ca
->cif
.arg_types
);
652 assert(status
== FFI_OK
);
656 g_hash_table_insert(ffi_table
, hash
, (gpointer
)cif
);
659 g_hash_table_destroy(ffi_table
);
661 #endif /* CONFIG_TCG_INTERPRETER */
663 typedef struct TCGCumulativeArgs
{
664 int arg_idx
; /* tcg_gen_callN args[] */
665 int info_in_idx
; /* TCGHelperInfo in[] */
666 int arg_slot
; /* regs+stack slot */
667 int ref_slot
; /* stack slots for references */
670 static void layout_arg_even(TCGCumulativeArgs
*cum
)
672 cum
->arg_slot
+= cum
->arg_slot
& 1;
675 static void layout_arg_1(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
,
676 TCGCallArgumentKind kind
)
678 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
680 *loc
= (TCGCallArgumentLoc
){
682 .arg_idx
= cum
->arg_idx
,
683 .arg_slot
= cum
->arg_slot
,
689 static void layout_arg_normal_n(TCGCumulativeArgs
*cum
,
690 TCGHelperInfo
*info
, int n
)
692 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
694 for (int i
= 0; i
< n
; ++i
) {
695 /* Layout all using the same arg_idx, adjusting the subindex. */
696 loc
[i
] = (TCGCallArgumentLoc
){
697 .kind
= TCG_CALL_ARG_NORMAL
,
698 .arg_idx
= cum
->arg_idx
,
700 .arg_slot
= cum
->arg_slot
+ i
,
703 cum
->info_in_idx
+= n
;
707 static void layout_arg_by_ref(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
)
709 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
710 int n
= 128 / TCG_TARGET_REG_BITS
;
712 /* The first subindex carries the pointer. */
713 layout_arg_1(cum
, info
, TCG_CALL_ARG_BY_REF
);
716 * The callee is allowed to clobber memory associated with
717 * structure pass by-reference. Therefore we must make copies.
718 * Allocate space from "ref_slot", which will be adjusted to
719 * follow the parameters on the stack.
721 loc
[0].ref_slot
= cum
->ref_slot
;
724 * Subsequent words also go into the reference slot, but
725 * do not accumulate into the regular arguments.
727 for (int i
= 1; i
< n
; ++i
) {
728 loc
[i
] = (TCGCallArgumentLoc
){
729 .kind
= TCG_CALL_ARG_BY_REF_N
,
730 .arg_idx
= cum
->arg_idx
,
732 .ref_slot
= cum
->ref_slot
+ i
,
735 cum
->info_in_idx
+= n
;
739 static void init_call_layout(TCGHelperInfo
*info
)
741 int max_reg_slots
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
742 int max_stk_slots
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
743 unsigned typemask
= info
->typemask
;
745 TCGCumulativeArgs cum
= { };
748 * Parse and place any function return value.
750 typecode
= typemask
& 7;
752 case dh_typecode_void
:
755 case dh_typecode_i32
:
756 case dh_typecode_s32
:
757 case dh_typecode_ptr
:
759 info
->out_kind
= TCG_CALL_RET_NORMAL
;
761 case dh_typecode_i64
:
762 case dh_typecode_s64
:
763 info
->nr_out
= 64 / TCG_TARGET_REG_BITS
;
764 info
->out_kind
= TCG_CALL_RET_NORMAL
;
765 /* Query the last register now to trigger any assert early. */
766 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
768 case dh_typecode_i128
:
769 info
->nr_out
= 128 / TCG_TARGET_REG_BITS
;
770 info
->out_kind
= TCG_TARGET_CALL_RET_I128
;
771 switch (TCG_TARGET_CALL_RET_I128
) {
772 case TCG_CALL_RET_NORMAL
:
773 /* Query the last register now to trigger any assert early. */
774 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
776 case TCG_CALL_RET_BY_VEC
:
777 /* Query the single register now to trigger any assert early. */
778 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0);
780 case TCG_CALL_RET_BY_REF
:
782 * Allocate the first argument to the output.
783 * We don't need to store this anywhere, just make it
784 * unavailable for use in the input loop below.
789 qemu_build_not_reached();
793 g_assert_not_reached();
797 * Parse and place function arguments.
799 for (typemask
>>= 3; typemask
; typemask
>>= 3, cum
.arg_idx
++) {
800 TCGCallArgumentKind kind
;
803 typecode
= typemask
& 7;
805 case dh_typecode_i32
:
806 case dh_typecode_s32
:
809 case dh_typecode_i64
:
810 case dh_typecode_s64
:
813 case dh_typecode_ptr
:
816 case dh_typecode_i128
:
817 type
= TCG_TYPE_I128
;
820 g_assert_not_reached();
825 switch (TCG_TARGET_CALL_ARG_I32
) {
826 case TCG_CALL_ARG_EVEN
:
827 layout_arg_even(&cum
);
829 case TCG_CALL_ARG_NORMAL
:
830 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
832 case TCG_CALL_ARG_EXTEND
:
833 kind
= TCG_CALL_ARG_EXTEND_U
+ (typecode
& 1);
834 layout_arg_1(&cum
, info
, kind
);
837 qemu_build_not_reached();
842 switch (TCG_TARGET_CALL_ARG_I64
) {
843 case TCG_CALL_ARG_EVEN
:
844 layout_arg_even(&cum
);
846 case TCG_CALL_ARG_NORMAL
:
847 if (TCG_TARGET_REG_BITS
== 32) {
848 layout_arg_normal_n(&cum
, info
, 2);
850 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
854 qemu_build_not_reached();
859 switch (TCG_TARGET_CALL_ARG_I128
) {
860 case TCG_CALL_ARG_EVEN
:
861 layout_arg_even(&cum
);
863 case TCG_CALL_ARG_NORMAL
:
864 layout_arg_normal_n(&cum
, info
, 128 / TCG_TARGET_REG_BITS
);
866 case TCG_CALL_ARG_BY_REF
:
867 layout_arg_by_ref(&cum
, info
);
870 qemu_build_not_reached();
875 g_assert_not_reached();
878 info
->nr_in
= cum
.info_in_idx
;
880 /* Validate that we didn't overrun the input array. */
881 assert(cum
.info_in_idx
<= ARRAY_SIZE(info
->in
));
882 /* Validate the backend has enough argument space. */
883 assert(cum
.arg_slot
<= max_reg_slots
+ max_stk_slots
);
886 * Relocate the "ref_slot" area to the end of the parameters.
887 * Minimizing this stack offset helps code size for x86,
888 * which has a signed 8-bit offset encoding.
890 if (cum
.ref_slot
!= 0) {
893 if (cum
.arg_slot
> max_reg_slots
) {
894 int align
= __alignof(Int128
) / sizeof(tcg_target_long
);
896 ref_base
= cum
.arg_slot
- max_reg_slots
;
898 ref_base
= ROUND_UP(ref_base
, align
);
901 assert(ref_base
+ cum
.ref_slot
<= max_stk_slots
);
904 for (int i
= cum
.info_in_idx
- 1; i
>= 0; --i
) {
905 TCGCallArgumentLoc
*loc
= &info
->in
[i
];
907 case TCG_CALL_ARG_BY_REF
:
908 case TCG_CALL_ARG_BY_REF_N
:
909 loc
->ref_slot
+= ref_base
;
919 static int indirect_reg_alloc_order
[ARRAY_SIZE(tcg_target_reg_alloc_order
)];
920 static void process_op_defs(TCGContext
*s
);
921 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
922 TCGReg reg
, const char *name
);
924 static void tcg_context_init(unsigned max_cpus
)
926 TCGContext
*s
= &tcg_init_ctx
;
927 int op
, total_args
, n
, i
;
929 TCGArgConstraint
*args_ct
;
932 memset(s
, 0, sizeof(*s
));
935 /* Count total number of arguments and allocate the corresponding
938 for(op
= 0; op
< NB_OPS
; op
++) {
939 def
= &tcg_op_defs
[op
];
940 n
= def
->nb_iargs
+ def
->nb_oargs
;
944 args_ct
= g_new0(TCGArgConstraint
, total_args
);
946 for(op
= 0; op
< NB_OPS
; op
++) {
947 def
= &tcg_op_defs
[op
];
948 def
->args_ct
= args_ct
;
949 n
= def
->nb_iargs
+ def
->nb_oargs
;
953 /* Register helpers. */
954 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
955 helper_table
= g_hash_table_new(NULL
, NULL
);
957 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
958 init_call_layout(&all_helpers
[i
]);
959 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
960 (gpointer
)&all_helpers
[i
]);
963 #ifdef CONFIG_TCG_INTERPRETER
970 /* Reverse the order of the saved registers, assuming they're all at
971 the start of tcg_target_reg_alloc_order. */
972 for (n
= 0; n
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++n
) {
973 int r
= tcg_target_reg_alloc_order
[n
];
974 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, r
)) {
978 for (i
= 0; i
< n
; ++i
) {
979 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[n
- 1 - i
];
981 for (; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++i
) {
982 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[i
];
985 alloc_tcg_plugin_context(s
);
989 * In user-mode we simply share the init context among threads, since we
990 * use a single region. See the documentation tcg_region_init() for the
991 * reasoning behind this.
992 * In softmmu we will have at most max_cpus TCG threads.
994 #ifdef CONFIG_USER_ONLY
999 tcg_max_ctxs
= max_cpus
;
1000 tcg_ctxs
= g_new0(TCGContext
*, max_cpus
);
1003 tcg_debug_assert(!tcg_regset_test_reg(s
->reserved_regs
, TCG_AREG0
));
1004 ts
= tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, TCG_AREG0
, "env");
1005 cpu_env
= temp_tcgv_ptr(ts
);
1008 void tcg_init(size_t tb_size
, int splitwx
, unsigned max_cpus
)
1010 tcg_context_init(max_cpus
);
1011 tcg_region_init(tb_size
, splitwx
, max_cpus
);
1015 * Allocate TBs right before their corresponding translated code, making
1016 * sure that TBs and code are on different cache lines.
1018 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
)
1020 uintptr_t align
= qemu_icache_linesize
;
1021 TranslationBlock
*tb
;
1025 tb
= (void *)ROUND_UP((uintptr_t)s
->code_gen_ptr
, align
);
1026 next
= (void *)ROUND_UP((uintptr_t)(tb
+ 1), align
);
1028 if (unlikely(next
> s
->code_gen_highwater
)) {
1029 if (tcg_region_alloc(s
)) {
1034 qatomic_set(&s
->code_gen_ptr
, next
);
1035 s
->data_gen_ptr
= NULL
;
1039 void tcg_prologue_init(TCGContext
*s
)
1041 size_t prologue_size
;
1043 s
->code_ptr
= s
->code_gen_ptr
;
1044 s
->code_buf
= s
->code_gen_ptr
;
1045 s
->data_gen_ptr
= NULL
;
1047 #ifndef CONFIG_TCG_INTERPRETER
1048 tcg_qemu_tb_exec
= (tcg_prologue_fn
*)tcg_splitwx_to_rx(s
->code_ptr
);
1051 #ifdef TCG_TARGET_NEED_POOL_LABELS
1052 s
->pool_labels
= NULL
;
1055 qemu_thread_jit_write();
1056 /* Generate the prologue. */
1057 tcg_target_qemu_prologue(s
);
1059 #ifdef TCG_TARGET_NEED_POOL_LABELS
1060 /* Allow the prologue to put e.g. guest_base into a pool entry. */
1062 int result
= tcg_out_pool_finalize(s
);
1063 tcg_debug_assert(result
== 0);
1067 prologue_size
= tcg_current_code_size(s
);
1068 perf_report_prologue(s
->code_gen_ptr
, prologue_size
);
1070 #ifndef CONFIG_TCG_INTERPRETER
1071 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
1072 (uintptr_t)s
->code_buf
, prologue_size
);
1076 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
1077 FILE *logfile
= qemu_log_trylock();
1079 fprintf(logfile
, "PROLOGUE: [size=%zu]\n", prologue_size
);
1080 if (s
->data_gen_ptr
) {
1081 size_t code_size
= s
->data_gen_ptr
- s
->code_gen_ptr
;
1082 size_t data_size
= prologue_size
- code_size
;
1085 disas(logfile
, s
->code_gen_ptr
, code_size
);
1087 for (i
= 0; i
< data_size
; i
+= sizeof(tcg_target_ulong
)) {
1088 if (sizeof(tcg_target_ulong
) == 8) {
1090 "0x%08" PRIxPTR
": .quad 0x%016" PRIx64
"\n",
1091 (uintptr_t)s
->data_gen_ptr
+ i
,
1092 *(uint64_t *)(s
->data_gen_ptr
+ i
));
1095 "0x%08" PRIxPTR
": .long 0x%08x\n",
1096 (uintptr_t)s
->data_gen_ptr
+ i
,
1097 *(uint32_t *)(s
->data_gen_ptr
+ i
));
1101 disas(logfile
, s
->code_gen_ptr
, prologue_size
);
1103 fprintf(logfile
, "\n");
1104 qemu_log_unlock(logfile
);
1109 #ifndef CONFIG_TCG_INTERPRETER
1111 * Assert that goto_ptr is implemented completely, setting an epilogue.
1112 * For tci, we use NULL as the signal to return from the interpreter,
1113 * so skip this check.
1115 tcg_debug_assert(tcg_code_gen_epilogue
!= NULL
);
1118 tcg_region_prologue_set(s
);
1121 void tcg_func_start(TCGContext
*s
)
1124 s
->nb_temps
= s
->nb_globals
;
1126 /* No temps have been previously allocated for size or locality. */
1127 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
1129 /* No constant temps have been previously allocated. */
1130 for (int i
= 0; i
< TCG_TYPE_COUNT
; ++i
) {
1131 if (s
->const_table
[i
]) {
1132 g_hash_table_remove_all(s
->const_table
[i
]);
1138 s
->current_frame_offset
= s
->frame_start
;
1140 #ifdef CONFIG_DEBUG_TCG
1141 s
->goto_tb_issue_mask
= 0;
1144 QTAILQ_INIT(&s
->ops
);
1145 QTAILQ_INIT(&s
->free_ops
);
1146 QSIMPLEQ_INIT(&s
->labels
);
1149 static TCGTemp
*tcg_temp_alloc(TCGContext
*s
)
1151 int n
= s
->nb_temps
++;
1153 if (n
>= TCG_MAX_TEMPS
) {
1154 tcg_raise_tb_overflow(s
);
1156 return memset(&s
->temps
[n
], 0, sizeof(TCGTemp
));
1159 static TCGTemp
*tcg_global_alloc(TCGContext
*s
)
1163 tcg_debug_assert(s
->nb_globals
== s
->nb_temps
);
1164 tcg_debug_assert(s
->nb_globals
< TCG_MAX_TEMPS
);
1166 ts
= tcg_temp_alloc(s
);
1167 ts
->kind
= TEMP_GLOBAL
;
1172 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1173 TCGReg reg
, const char *name
)
1177 if (TCG_TARGET_REG_BITS
== 32 && type
!= TCG_TYPE_I32
) {
1181 ts
= tcg_global_alloc(s
);
1182 ts
->base_type
= type
;
1184 ts
->kind
= TEMP_FIXED
;
1187 tcg_regset_set_reg(s
->reserved_regs
, reg
);
1192 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
)
1194 s
->frame_start
= start
;
1195 s
->frame_end
= start
+ size
;
1197 = tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, reg
, "_frame");
1200 TCGTemp
*tcg_global_mem_new_internal(TCGType type
, TCGv_ptr base
,
1201 intptr_t offset
, const char *name
)
1203 TCGContext
*s
= tcg_ctx
;
1204 TCGTemp
*base_ts
= tcgv_ptr_temp(base
);
1205 TCGTemp
*ts
= tcg_global_alloc(s
);
1206 int indirect_reg
= 0;
1208 switch (base_ts
->kind
) {
1212 /* We do not support double-indirect registers. */
1213 tcg_debug_assert(!base_ts
->indirect_reg
);
1214 base_ts
->indirect_base
= 1;
1215 s
->nb_indirects
+= (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
1220 g_assert_not_reached();
1223 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1224 TCGTemp
*ts2
= tcg_global_alloc(s
);
1227 ts
->base_type
= TCG_TYPE_I64
;
1228 ts
->type
= TCG_TYPE_I32
;
1229 ts
->indirect_reg
= indirect_reg
;
1230 ts
->mem_allocated
= 1;
1231 ts
->mem_base
= base_ts
;
1232 ts
->mem_offset
= offset
;
1233 pstrcpy(buf
, sizeof(buf
), name
);
1234 pstrcat(buf
, sizeof(buf
), "_0");
1235 ts
->name
= strdup(buf
);
1237 tcg_debug_assert(ts2
== ts
+ 1);
1238 ts2
->base_type
= TCG_TYPE_I64
;
1239 ts2
->type
= TCG_TYPE_I32
;
1240 ts2
->indirect_reg
= indirect_reg
;
1241 ts2
->mem_allocated
= 1;
1242 ts2
->mem_base
= base_ts
;
1243 ts2
->mem_offset
= offset
+ 4;
1244 ts2
->temp_subindex
= 1;
1245 pstrcpy(buf
, sizeof(buf
), name
);
1246 pstrcat(buf
, sizeof(buf
), "_1");
1247 ts2
->name
= strdup(buf
);
1249 ts
->base_type
= type
;
1251 ts
->indirect_reg
= indirect_reg
;
1252 ts
->mem_allocated
= 1;
1253 ts
->mem_base
= base_ts
;
1254 ts
->mem_offset
= offset
;
1260 TCGTemp
*tcg_temp_new_internal(TCGType type
, TCGTempKind kind
)
1262 TCGContext
*s
= tcg_ctx
;
1266 if (kind
== TEMP_EBB
) {
1267 int idx
= find_first_bit(s
->free_temps
[type
].l
, TCG_MAX_TEMPS
);
1269 if (idx
< TCG_MAX_TEMPS
) {
1270 /* There is already an available temp with the right type. */
1271 clear_bit(idx
, s
->free_temps
[type
].l
);
1273 ts
= &s
->temps
[idx
];
1274 ts
->temp_allocated
= 1;
1275 tcg_debug_assert(ts
->base_type
== type
);
1276 tcg_debug_assert(ts
->kind
== kind
);
1280 tcg_debug_assert(kind
== TEMP_TB
);
1291 n
= 64 / TCG_TARGET_REG_BITS
;
1294 n
= 128 / TCG_TARGET_REG_BITS
;
1297 g_assert_not_reached();
1300 ts
= tcg_temp_alloc(s
);
1301 ts
->base_type
= type
;
1302 ts
->temp_allocated
= 1;
1308 ts
->type
= TCG_TYPE_REG
;
1310 for (int i
= 1; i
< n
; ++i
) {
1311 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1313 tcg_debug_assert(ts2
== ts
+ i
);
1314 ts2
->base_type
= type
;
1315 ts2
->type
= TCG_TYPE_REG
;
1316 ts2
->temp_allocated
= 1;
1317 ts2
->temp_subindex
= i
;
1324 TCGv_vec
tcg_temp_new_vec(TCGType type
)
1328 #ifdef CONFIG_DEBUG_TCG
1331 assert(TCG_TARGET_HAS_v64
);
1334 assert(TCG_TARGET_HAS_v128
);
1337 assert(TCG_TARGET_HAS_v256
);
1340 g_assert_not_reached();
1344 t
= tcg_temp_new_internal(type
, TEMP_EBB
);
1345 return temp_tcgv_vec(t
);
1348 /* Create a new temp of the same type as an existing temp. */
1349 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
)
1351 TCGTemp
*t
= tcgv_vec_temp(match
);
1353 tcg_debug_assert(t
->temp_allocated
!= 0);
1355 t
= tcg_temp_new_internal(t
->base_type
, TEMP_EBB
);
1356 return temp_tcgv_vec(t
);
1359 void tcg_temp_free_internal(TCGTemp
*ts
)
1361 TCGContext
*s
= tcg_ctx
;
1366 /* Silently ignore free. */
1369 tcg_debug_assert(ts
->temp_allocated
!= 0);
1370 ts
->temp_allocated
= 0;
1371 set_bit(temp_idx(ts
), s
->free_temps
[ts
->base_type
].l
);
1374 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */
1375 g_assert_not_reached();
1379 TCGTemp
*tcg_constant_internal(TCGType type
, int64_t val
)
1381 TCGContext
*s
= tcg_ctx
;
1382 GHashTable
*h
= s
->const_table
[type
];
1386 h
= g_hash_table_new(g_int64_hash
, g_int64_equal
);
1387 s
->const_table
[type
] = h
;
1390 ts
= g_hash_table_lookup(h
, &val
);
1394 ts
= tcg_temp_alloc(s
);
1396 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1397 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1399 tcg_debug_assert(ts2
== ts
+ 1);
1401 ts
->base_type
= TCG_TYPE_I64
;
1402 ts
->type
= TCG_TYPE_I32
;
1403 ts
->kind
= TEMP_CONST
;
1404 ts
->temp_allocated
= 1;
1406 ts2
->base_type
= TCG_TYPE_I64
;
1407 ts2
->type
= TCG_TYPE_I32
;
1408 ts2
->kind
= TEMP_CONST
;
1409 ts2
->temp_allocated
= 1;
1410 ts2
->temp_subindex
= 1;
1413 * Retain the full value of the 64-bit constant in the low
1414 * part, so that the hash table works. Actual uses will
1415 * truncate the value to the low part.
1417 ts
[HOST_BIG_ENDIAN
].val
= val
;
1418 ts
[!HOST_BIG_ENDIAN
].val
= val
>> 32;
1419 val_ptr
= &ts
[HOST_BIG_ENDIAN
].val
;
1421 ts
->base_type
= type
;
1423 ts
->kind
= TEMP_CONST
;
1424 ts
->temp_allocated
= 1;
1428 g_hash_table_insert(h
, val_ptr
, ts
);
1434 TCGv_vec
tcg_constant_vec(TCGType type
, unsigned vece
, int64_t val
)
1436 val
= dup_const(vece
, val
);
1437 return temp_tcgv_vec(tcg_constant_internal(type
, val
));
1440 TCGv_vec
tcg_constant_vec_matching(TCGv_vec match
, unsigned vece
, int64_t val
)
1442 TCGTemp
*t
= tcgv_vec_temp(match
);
1444 tcg_debug_assert(t
->temp_allocated
!= 0);
1445 return tcg_constant_vec(t
->base_type
, vece
, val
);
1448 TCGv_i32
tcg_const_i32(int32_t val
)
1451 t0
= tcg_temp_new_i32();
1452 tcg_gen_movi_i32(t0
, val
);
1456 TCGv_i64
tcg_const_i64(int64_t val
)
1459 t0
= tcg_temp_new_i64();
1460 tcg_gen_movi_i64(t0
, val
);
1464 /* Return true if OP may appear in the opcode stream.
1465 Test the runtime variable that controls each opcode. */
1466 bool tcg_op_supported(TCGOpcode op
)
1469 = TCG_TARGET_HAS_v64
| TCG_TARGET_HAS_v128
| TCG_TARGET_HAS_v256
;
1472 case INDEX_op_discard
:
1473 case INDEX_op_set_label
:
1477 case INDEX_op_insn_start
:
1478 case INDEX_op_exit_tb
:
1479 case INDEX_op_goto_tb
:
1480 case INDEX_op_goto_ptr
:
1481 case INDEX_op_qemu_ld_i32
:
1482 case INDEX_op_qemu_st_i32
:
1483 case INDEX_op_qemu_ld_i64
:
1484 case INDEX_op_qemu_st_i64
:
1487 case INDEX_op_qemu_st8_i32
:
1488 return TCG_TARGET_HAS_qemu_st8_i32
;
1490 case INDEX_op_mov_i32
:
1491 case INDEX_op_setcond_i32
:
1492 case INDEX_op_brcond_i32
:
1493 case INDEX_op_ld8u_i32
:
1494 case INDEX_op_ld8s_i32
:
1495 case INDEX_op_ld16u_i32
:
1496 case INDEX_op_ld16s_i32
:
1497 case INDEX_op_ld_i32
:
1498 case INDEX_op_st8_i32
:
1499 case INDEX_op_st16_i32
:
1500 case INDEX_op_st_i32
:
1501 case INDEX_op_add_i32
:
1502 case INDEX_op_sub_i32
:
1503 case INDEX_op_mul_i32
:
1504 case INDEX_op_and_i32
:
1505 case INDEX_op_or_i32
:
1506 case INDEX_op_xor_i32
:
1507 case INDEX_op_shl_i32
:
1508 case INDEX_op_shr_i32
:
1509 case INDEX_op_sar_i32
:
1512 case INDEX_op_movcond_i32
:
1513 return TCG_TARGET_HAS_movcond_i32
;
1514 case INDEX_op_div_i32
:
1515 case INDEX_op_divu_i32
:
1516 return TCG_TARGET_HAS_div_i32
;
1517 case INDEX_op_rem_i32
:
1518 case INDEX_op_remu_i32
:
1519 return TCG_TARGET_HAS_rem_i32
;
1520 case INDEX_op_div2_i32
:
1521 case INDEX_op_divu2_i32
:
1522 return TCG_TARGET_HAS_div2_i32
;
1523 case INDEX_op_rotl_i32
:
1524 case INDEX_op_rotr_i32
:
1525 return TCG_TARGET_HAS_rot_i32
;
1526 case INDEX_op_deposit_i32
:
1527 return TCG_TARGET_HAS_deposit_i32
;
1528 case INDEX_op_extract_i32
:
1529 return TCG_TARGET_HAS_extract_i32
;
1530 case INDEX_op_sextract_i32
:
1531 return TCG_TARGET_HAS_sextract_i32
;
1532 case INDEX_op_extract2_i32
:
1533 return TCG_TARGET_HAS_extract2_i32
;
1534 case INDEX_op_add2_i32
:
1535 return TCG_TARGET_HAS_add2_i32
;
1536 case INDEX_op_sub2_i32
:
1537 return TCG_TARGET_HAS_sub2_i32
;
1538 case INDEX_op_mulu2_i32
:
1539 return TCG_TARGET_HAS_mulu2_i32
;
1540 case INDEX_op_muls2_i32
:
1541 return TCG_TARGET_HAS_muls2_i32
;
1542 case INDEX_op_muluh_i32
:
1543 return TCG_TARGET_HAS_muluh_i32
;
1544 case INDEX_op_mulsh_i32
:
1545 return TCG_TARGET_HAS_mulsh_i32
;
1546 case INDEX_op_ext8s_i32
:
1547 return TCG_TARGET_HAS_ext8s_i32
;
1548 case INDEX_op_ext16s_i32
:
1549 return TCG_TARGET_HAS_ext16s_i32
;
1550 case INDEX_op_ext8u_i32
:
1551 return TCG_TARGET_HAS_ext8u_i32
;
1552 case INDEX_op_ext16u_i32
:
1553 return TCG_TARGET_HAS_ext16u_i32
;
1554 case INDEX_op_bswap16_i32
:
1555 return TCG_TARGET_HAS_bswap16_i32
;
1556 case INDEX_op_bswap32_i32
:
1557 return TCG_TARGET_HAS_bswap32_i32
;
1558 case INDEX_op_not_i32
:
1559 return TCG_TARGET_HAS_not_i32
;
1560 case INDEX_op_neg_i32
:
1561 return TCG_TARGET_HAS_neg_i32
;
1562 case INDEX_op_andc_i32
:
1563 return TCG_TARGET_HAS_andc_i32
;
1564 case INDEX_op_orc_i32
:
1565 return TCG_TARGET_HAS_orc_i32
;
1566 case INDEX_op_eqv_i32
:
1567 return TCG_TARGET_HAS_eqv_i32
;
1568 case INDEX_op_nand_i32
:
1569 return TCG_TARGET_HAS_nand_i32
;
1570 case INDEX_op_nor_i32
:
1571 return TCG_TARGET_HAS_nor_i32
;
1572 case INDEX_op_clz_i32
:
1573 return TCG_TARGET_HAS_clz_i32
;
1574 case INDEX_op_ctz_i32
:
1575 return TCG_TARGET_HAS_ctz_i32
;
1576 case INDEX_op_ctpop_i32
:
1577 return TCG_TARGET_HAS_ctpop_i32
;
1579 case INDEX_op_brcond2_i32
:
1580 case INDEX_op_setcond2_i32
:
1581 return TCG_TARGET_REG_BITS
== 32;
1583 case INDEX_op_mov_i64
:
1584 case INDEX_op_setcond_i64
:
1585 case INDEX_op_brcond_i64
:
1586 case INDEX_op_ld8u_i64
:
1587 case INDEX_op_ld8s_i64
:
1588 case INDEX_op_ld16u_i64
:
1589 case INDEX_op_ld16s_i64
:
1590 case INDEX_op_ld32u_i64
:
1591 case INDEX_op_ld32s_i64
:
1592 case INDEX_op_ld_i64
:
1593 case INDEX_op_st8_i64
:
1594 case INDEX_op_st16_i64
:
1595 case INDEX_op_st32_i64
:
1596 case INDEX_op_st_i64
:
1597 case INDEX_op_add_i64
:
1598 case INDEX_op_sub_i64
:
1599 case INDEX_op_mul_i64
:
1600 case INDEX_op_and_i64
:
1601 case INDEX_op_or_i64
:
1602 case INDEX_op_xor_i64
:
1603 case INDEX_op_shl_i64
:
1604 case INDEX_op_shr_i64
:
1605 case INDEX_op_sar_i64
:
1606 case INDEX_op_ext_i32_i64
:
1607 case INDEX_op_extu_i32_i64
:
1608 return TCG_TARGET_REG_BITS
== 64;
1610 case INDEX_op_movcond_i64
:
1611 return TCG_TARGET_HAS_movcond_i64
;
1612 case INDEX_op_div_i64
:
1613 case INDEX_op_divu_i64
:
1614 return TCG_TARGET_HAS_div_i64
;
1615 case INDEX_op_rem_i64
:
1616 case INDEX_op_remu_i64
:
1617 return TCG_TARGET_HAS_rem_i64
;
1618 case INDEX_op_div2_i64
:
1619 case INDEX_op_divu2_i64
:
1620 return TCG_TARGET_HAS_div2_i64
;
1621 case INDEX_op_rotl_i64
:
1622 case INDEX_op_rotr_i64
:
1623 return TCG_TARGET_HAS_rot_i64
;
1624 case INDEX_op_deposit_i64
:
1625 return TCG_TARGET_HAS_deposit_i64
;
1626 case INDEX_op_extract_i64
:
1627 return TCG_TARGET_HAS_extract_i64
;
1628 case INDEX_op_sextract_i64
:
1629 return TCG_TARGET_HAS_sextract_i64
;
1630 case INDEX_op_extract2_i64
:
1631 return TCG_TARGET_HAS_extract2_i64
;
1632 case INDEX_op_extrl_i64_i32
:
1633 return TCG_TARGET_HAS_extrl_i64_i32
;
1634 case INDEX_op_extrh_i64_i32
:
1635 return TCG_TARGET_HAS_extrh_i64_i32
;
1636 case INDEX_op_ext8s_i64
:
1637 return TCG_TARGET_HAS_ext8s_i64
;
1638 case INDEX_op_ext16s_i64
:
1639 return TCG_TARGET_HAS_ext16s_i64
;
1640 case INDEX_op_ext32s_i64
:
1641 return TCG_TARGET_HAS_ext32s_i64
;
1642 case INDEX_op_ext8u_i64
:
1643 return TCG_TARGET_HAS_ext8u_i64
;
1644 case INDEX_op_ext16u_i64
:
1645 return TCG_TARGET_HAS_ext16u_i64
;
1646 case INDEX_op_ext32u_i64
:
1647 return TCG_TARGET_HAS_ext32u_i64
;
1648 case INDEX_op_bswap16_i64
:
1649 return TCG_TARGET_HAS_bswap16_i64
;
1650 case INDEX_op_bswap32_i64
:
1651 return TCG_TARGET_HAS_bswap32_i64
;
1652 case INDEX_op_bswap64_i64
:
1653 return TCG_TARGET_HAS_bswap64_i64
;
1654 case INDEX_op_not_i64
:
1655 return TCG_TARGET_HAS_not_i64
;
1656 case INDEX_op_neg_i64
:
1657 return TCG_TARGET_HAS_neg_i64
;
1658 case INDEX_op_andc_i64
:
1659 return TCG_TARGET_HAS_andc_i64
;
1660 case INDEX_op_orc_i64
:
1661 return TCG_TARGET_HAS_orc_i64
;
1662 case INDEX_op_eqv_i64
:
1663 return TCG_TARGET_HAS_eqv_i64
;
1664 case INDEX_op_nand_i64
:
1665 return TCG_TARGET_HAS_nand_i64
;
1666 case INDEX_op_nor_i64
:
1667 return TCG_TARGET_HAS_nor_i64
;
1668 case INDEX_op_clz_i64
:
1669 return TCG_TARGET_HAS_clz_i64
;
1670 case INDEX_op_ctz_i64
:
1671 return TCG_TARGET_HAS_ctz_i64
;
1672 case INDEX_op_ctpop_i64
:
1673 return TCG_TARGET_HAS_ctpop_i64
;
1674 case INDEX_op_add2_i64
:
1675 return TCG_TARGET_HAS_add2_i64
;
1676 case INDEX_op_sub2_i64
:
1677 return TCG_TARGET_HAS_sub2_i64
;
1678 case INDEX_op_mulu2_i64
:
1679 return TCG_TARGET_HAS_mulu2_i64
;
1680 case INDEX_op_muls2_i64
:
1681 return TCG_TARGET_HAS_muls2_i64
;
1682 case INDEX_op_muluh_i64
:
1683 return TCG_TARGET_HAS_muluh_i64
;
1684 case INDEX_op_mulsh_i64
:
1685 return TCG_TARGET_HAS_mulsh_i64
;
1687 case INDEX_op_mov_vec
:
1688 case INDEX_op_dup_vec
:
1689 case INDEX_op_dupm_vec
:
1690 case INDEX_op_ld_vec
:
1691 case INDEX_op_st_vec
:
1692 case INDEX_op_add_vec
:
1693 case INDEX_op_sub_vec
:
1694 case INDEX_op_and_vec
:
1695 case INDEX_op_or_vec
:
1696 case INDEX_op_xor_vec
:
1697 case INDEX_op_cmp_vec
:
1699 case INDEX_op_dup2_vec
:
1700 return have_vec
&& TCG_TARGET_REG_BITS
== 32;
1701 case INDEX_op_not_vec
:
1702 return have_vec
&& TCG_TARGET_HAS_not_vec
;
1703 case INDEX_op_neg_vec
:
1704 return have_vec
&& TCG_TARGET_HAS_neg_vec
;
1705 case INDEX_op_abs_vec
:
1706 return have_vec
&& TCG_TARGET_HAS_abs_vec
;
1707 case INDEX_op_andc_vec
:
1708 return have_vec
&& TCG_TARGET_HAS_andc_vec
;
1709 case INDEX_op_orc_vec
:
1710 return have_vec
&& TCG_TARGET_HAS_orc_vec
;
1711 case INDEX_op_nand_vec
:
1712 return have_vec
&& TCG_TARGET_HAS_nand_vec
;
1713 case INDEX_op_nor_vec
:
1714 return have_vec
&& TCG_TARGET_HAS_nor_vec
;
1715 case INDEX_op_eqv_vec
:
1716 return have_vec
&& TCG_TARGET_HAS_eqv_vec
;
1717 case INDEX_op_mul_vec
:
1718 return have_vec
&& TCG_TARGET_HAS_mul_vec
;
1719 case INDEX_op_shli_vec
:
1720 case INDEX_op_shri_vec
:
1721 case INDEX_op_sari_vec
:
1722 return have_vec
&& TCG_TARGET_HAS_shi_vec
;
1723 case INDEX_op_shls_vec
:
1724 case INDEX_op_shrs_vec
:
1725 case INDEX_op_sars_vec
:
1726 return have_vec
&& TCG_TARGET_HAS_shs_vec
;
1727 case INDEX_op_shlv_vec
:
1728 case INDEX_op_shrv_vec
:
1729 case INDEX_op_sarv_vec
:
1730 return have_vec
&& TCG_TARGET_HAS_shv_vec
;
1731 case INDEX_op_rotli_vec
:
1732 return have_vec
&& TCG_TARGET_HAS_roti_vec
;
1733 case INDEX_op_rotls_vec
:
1734 return have_vec
&& TCG_TARGET_HAS_rots_vec
;
1735 case INDEX_op_rotlv_vec
:
1736 case INDEX_op_rotrv_vec
:
1737 return have_vec
&& TCG_TARGET_HAS_rotv_vec
;
1738 case INDEX_op_ssadd_vec
:
1739 case INDEX_op_usadd_vec
:
1740 case INDEX_op_sssub_vec
:
1741 case INDEX_op_ussub_vec
:
1742 return have_vec
&& TCG_TARGET_HAS_sat_vec
;
1743 case INDEX_op_smin_vec
:
1744 case INDEX_op_umin_vec
:
1745 case INDEX_op_smax_vec
:
1746 case INDEX_op_umax_vec
:
1747 return have_vec
&& TCG_TARGET_HAS_minmax_vec
;
1748 case INDEX_op_bitsel_vec
:
1749 return have_vec
&& TCG_TARGET_HAS_bitsel_vec
;
1750 case INDEX_op_cmpsel_vec
:
1751 return have_vec
&& TCG_TARGET_HAS_cmpsel_vec
;
1754 tcg_debug_assert(op
> INDEX_op_last_generic
&& op
< NB_OPS
);
1759 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
);
1761 void tcg_gen_callN(void *func
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
)
1763 const TCGHelperInfo
*info
;
1764 TCGv_i64 extend_free
[MAX_CALL_IARGS
];
1767 int i
, n
, pi
= 0, total_args
;
1769 info
= g_hash_table_lookup(helper_table
, (gpointer
)func
);
1770 total_args
= info
->nr_out
+ info
->nr_in
+ 2;
1771 op
= tcg_op_alloc(INDEX_op_call
, total_args
);
1773 #ifdef CONFIG_PLUGIN
1774 /* Flag helpers that may affect guest state */
1775 if (tcg_ctx
->plugin_insn
&&
1776 !(info
->flags
& TCG_CALL_PLUGIN
) &&
1777 !(info
->flags
& TCG_CALL_NO_SIDE_EFFECTS
)) {
1778 tcg_ctx
->plugin_insn
->calls_helpers
= true;
1782 TCGOP_CALLO(op
) = n
= info
->nr_out
;
1785 tcg_debug_assert(ret
== NULL
);
1788 tcg_debug_assert(ret
!= NULL
);
1789 op
->args
[pi
++] = temp_arg(ret
);
1793 tcg_debug_assert(ret
!= NULL
);
1794 tcg_debug_assert(ret
->base_type
== ret
->type
+ ctz32(n
));
1795 tcg_debug_assert(ret
->temp_subindex
== 0);
1796 for (i
= 0; i
< n
; ++i
) {
1797 op
->args
[pi
++] = temp_arg(ret
+ i
);
1801 g_assert_not_reached();
1804 TCGOP_CALLI(op
) = n
= info
->nr_in
;
1805 for (i
= 0; i
< n
; i
++) {
1806 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
1807 TCGTemp
*ts
= args
[loc
->arg_idx
] + loc
->tmp_subindex
;
1809 switch (loc
->kind
) {
1810 case TCG_CALL_ARG_NORMAL
:
1811 case TCG_CALL_ARG_BY_REF
:
1812 case TCG_CALL_ARG_BY_REF_N
:
1813 op
->args
[pi
++] = temp_arg(ts
);
1816 case TCG_CALL_ARG_EXTEND_U
:
1817 case TCG_CALL_ARG_EXTEND_S
:
1819 TCGv_i64 temp
= tcg_temp_ebb_new_i64();
1820 TCGv_i32 orig
= temp_tcgv_i32(ts
);
1822 if (loc
->kind
== TCG_CALL_ARG_EXTEND_S
) {
1823 tcg_gen_ext_i32_i64(temp
, orig
);
1825 tcg_gen_extu_i32_i64(temp
, orig
);
1827 op
->args
[pi
++] = tcgv_i64_arg(temp
);
1828 extend_free
[n_extend
++] = temp
;
1833 g_assert_not_reached();
1836 op
->args
[pi
++] = (uintptr_t)func
;
1837 op
->args
[pi
++] = (uintptr_t)info
;
1838 tcg_debug_assert(pi
== total_args
);
1840 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
1842 tcg_debug_assert(n_extend
< ARRAY_SIZE(extend_free
));
1843 for (i
= 0; i
< n_extend
; ++i
) {
1844 tcg_temp_free_i64(extend_free
[i
]);
1848 static void tcg_reg_alloc_start(TCGContext
*s
)
1852 for (i
= 0, n
= s
->nb_temps
; i
< n
; i
++) {
1853 TCGTemp
*ts
= &s
->temps
[i
];
1854 TCGTempVal val
= TEMP_VAL_MEM
;
1858 val
= TEMP_VAL_CONST
;
1866 val
= TEMP_VAL_DEAD
;
1869 ts
->mem_allocated
= 0;
1872 g_assert_not_reached();
1877 memset(s
->reg_to_temp
, 0, sizeof(s
->reg_to_temp
));
1880 static char *tcg_get_arg_str_ptr(TCGContext
*s
, char *buf
, int buf_size
,
1883 int idx
= temp_idx(ts
);
1888 pstrcpy(buf
, buf_size
, ts
->name
);
1891 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
1894 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
1899 snprintf(buf
, buf_size
, "$0x%x", (int32_t)ts
->val
);
1901 #if TCG_TARGET_REG_BITS > 32
1903 snprintf(buf
, buf_size
, "$0x%" PRIx64
, ts
->val
);
1909 snprintf(buf
, buf_size
, "v%d$0x%" PRIx64
,
1910 64 << (ts
->type
- TCG_TYPE_V64
), ts
->val
);
1913 g_assert_not_reached();
1920 static char *tcg_get_arg_str(TCGContext
*s
, char *buf
,
1921 int buf_size
, TCGArg arg
)
1923 return tcg_get_arg_str_ptr(s
, buf
, buf_size
, arg_temp(arg
));
1926 static const char * const cond_name
[] =
1928 [TCG_COND_NEVER
] = "never",
1929 [TCG_COND_ALWAYS
] = "always",
1930 [TCG_COND_EQ
] = "eq",
1931 [TCG_COND_NE
] = "ne",
1932 [TCG_COND_LT
] = "lt",
1933 [TCG_COND_GE
] = "ge",
1934 [TCG_COND_LE
] = "le",
1935 [TCG_COND_GT
] = "gt",
1936 [TCG_COND_LTU
] = "ltu",
1937 [TCG_COND_GEU
] = "geu",
1938 [TCG_COND_LEU
] = "leu",
1939 [TCG_COND_GTU
] = "gtu"
1942 static const char * const ldst_name
[] =
1958 static const char * const alignment_name
[(MO_AMASK
>> MO_ASHIFT
) + 1] = {
1959 #ifdef TARGET_ALIGNED_ONLY
1960 [MO_UNALN
>> MO_ASHIFT
] = "un+",
1961 [MO_ALIGN
>> MO_ASHIFT
] = "",
1963 [MO_UNALN
>> MO_ASHIFT
] = "",
1964 [MO_ALIGN
>> MO_ASHIFT
] = "al+",
1966 [MO_ALIGN_2
>> MO_ASHIFT
] = "al2+",
1967 [MO_ALIGN_4
>> MO_ASHIFT
] = "al4+",
1968 [MO_ALIGN_8
>> MO_ASHIFT
] = "al8+",
1969 [MO_ALIGN_16
>> MO_ASHIFT
] = "al16+",
1970 [MO_ALIGN_32
>> MO_ASHIFT
] = "al32+",
1971 [MO_ALIGN_64
>> MO_ASHIFT
] = "al64+",
1974 static const char bswap_flag_name
[][6] = {
1975 [TCG_BSWAP_IZ
] = "iz",
1976 [TCG_BSWAP_OZ
] = "oz",
1977 [TCG_BSWAP_OS
] = "os",
1978 [TCG_BSWAP_IZ
| TCG_BSWAP_OZ
] = "iz,oz",
1979 [TCG_BSWAP_IZ
| TCG_BSWAP_OS
] = "iz,os",
1982 static inline bool tcg_regset_single(TCGRegSet d
)
1984 return (d
& (d
- 1)) == 0;
1987 static inline TCGReg
tcg_regset_first(TCGRegSet d
)
1989 if (TCG_TARGET_NB_REGS
<= 32) {
1996 /* Return only the number of characters output -- no error return. */
1997 #define ne_fprintf(...) \
1998 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; })
2000 static void tcg_dump_ops(TCGContext
*s
, FILE *f
, bool have_prefs
)
2005 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
2006 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
2007 const TCGOpDef
*def
;
2012 def
= &tcg_op_defs
[c
];
2014 if (c
== INDEX_op_insn_start
) {
2016 col
+= ne_fprintf(f
, "\n ----");
2018 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
2020 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2021 a
= deposit64(op
->args
[i
* 2], 32, 32, op
->args
[i
* 2 + 1]);
2025 col
+= ne_fprintf(f
, " " TARGET_FMT_lx
, a
);
2027 } else if (c
== INDEX_op_call
) {
2028 const TCGHelperInfo
*info
= tcg_call_info(op
);
2029 void *func
= tcg_call_func(op
);
2031 /* variable number of arguments */
2032 nb_oargs
= TCGOP_CALLO(op
);
2033 nb_iargs
= TCGOP_CALLI(op
);
2034 nb_cargs
= def
->nb_cargs
;
2036 col
+= ne_fprintf(f
, " %s ", def
->name
);
2039 * Print the function name from TCGHelperInfo, if available.
2040 * Note that plugins have a template function for the info,
2041 * but the actual function pointer comes from the plugin.
2043 if (func
== info
->func
) {
2044 col
+= ne_fprintf(f
, "%s", info
->name
);
2046 col
+= ne_fprintf(f
, "plugin(%p)", func
);
2049 col
+= ne_fprintf(f
, ",$0x%x,$%d", info
->flags
, nb_oargs
);
2050 for (i
= 0; i
< nb_oargs
; i
++) {
2051 col
+= ne_fprintf(f
, ",%s", tcg_get_arg_str(s
, buf
, sizeof(buf
),
2054 for (i
= 0; i
< nb_iargs
; i
++) {
2055 TCGArg arg
= op
->args
[nb_oargs
+ i
];
2056 const char *t
= tcg_get_arg_str(s
, buf
, sizeof(buf
), arg
);
2057 col
+= ne_fprintf(f
, ",%s", t
);
2060 col
+= ne_fprintf(f
, " %s ", def
->name
);
2062 nb_oargs
= def
->nb_oargs
;
2063 nb_iargs
= def
->nb_iargs
;
2064 nb_cargs
= def
->nb_cargs
;
2066 if (def
->flags
& TCG_OPF_VECTOR
) {
2067 col
+= ne_fprintf(f
, "v%d,e%d,", 64 << TCGOP_VECL(op
),
2068 8 << TCGOP_VECE(op
));
2072 for (i
= 0; i
< nb_oargs
; i
++) {
2073 const char *sep
= k
? "," : "";
2074 col
+= ne_fprintf(f
, "%s%s", sep
,
2075 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2078 for (i
= 0; i
< nb_iargs
; i
++) {
2079 const char *sep
= k
? "," : "";
2080 col
+= ne_fprintf(f
, "%s%s", sep
,
2081 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2085 case INDEX_op_brcond_i32
:
2086 case INDEX_op_setcond_i32
:
2087 case INDEX_op_movcond_i32
:
2088 case INDEX_op_brcond2_i32
:
2089 case INDEX_op_setcond2_i32
:
2090 case INDEX_op_brcond_i64
:
2091 case INDEX_op_setcond_i64
:
2092 case INDEX_op_movcond_i64
:
2093 case INDEX_op_cmp_vec
:
2094 case INDEX_op_cmpsel_vec
:
2095 if (op
->args
[k
] < ARRAY_SIZE(cond_name
)
2096 && cond_name
[op
->args
[k
]]) {
2097 col
+= ne_fprintf(f
, ",%s", cond_name
[op
->args
[k
++]]);
2099 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, op
->args
[k
++]);
2103 case INDEX_op_qemu_ld_i32
:
2104 case INDEX_op_qemu_st_i32
:
2105 case INDEX_op_qemu_st8_i32
:
2106 case INDEX_op_qemu_ld_i64
:
2107 case INDEX_op_qemu_st_i64
:
2109 MemOpIdx oi
= op
->args
[k
++];
2110 MemOp op
= get_memop(oi
);
2111 unsigned ix
= get_mmuidx(oi
);
2113 if (op
& ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
)) {
2114 col
+= ne_fprintf(f
, ",$0x%x,%u", op
, ix
);
2116 const char *s_al
, *s_op
;
2117 s_al
= alignment_name
[(op
& MO_AMASK
) >> MO_ASHIFT
];
2118 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
2119 col
+= ne_fprintf(f
, ",%s%s,%u", s_al
, s_op
, ix
);
2124 case INDEX_op_bswap16_i32
:
2125 case INDEX_op_bswap16_i64
:
2126 case INDEX_op_bswap32_i32
:
2127 case INDEX_op_bswap32_i64
:
2128 case INDEX_op_bswap64_i64
:
2130 TCGArg flags
= op
->args
[k
];
2131 const char *name
= NULL
;
2133 if (flags
< ARRAY_SIZE(bswap_flag_name
)) {
2134 name
= bswap_flag_name
[flags
];
2137 col
+= ne_fprintf(f
, ",%s", name
);
2139 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, flags
);
2149 case INDEX_op_set_label
:
2151 case INDEX_op_brcond_i32
:
2152 case INDEX_op_brcond_i64
:
2153 case INDEX_op_brcond2_i32
:
2154 col
+= ne_fprintf(f
, "%s$L%d", k
? "," : "",
2155 arg_label(op
->args
[k
])->id
);
2160 TCGBar membar
= op
->args
[k
];
2161 const char *b_op
, *m_op
;
2163 switch (membar
& TCG_BAR_SC
) {
2177 g_assert_not_reached();
2180 switch (membar
& TCG_MO_ALL
) {
2196 case TCG_MO_LD_LD
| TCG_MO_LD_ST
:
2199 case TCG_MO_LD_LD
| TCG_MO_ST_LD
:
2202 case TCG_MO_LD_LD
| TCG_MO_ST_ST
:
2205 case TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2208 case TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2211 case TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2214 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2217 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2220 case TCG_MO_LD_LD
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2223 case TCG_MO_LD_ST
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2230 g_assert_not_reached();
2233 col
+= ne_fprintf(f
, "%s%s:%s", (k
? "," : ""), b_op
, m_op
);
2240 for (; i
< nb_cargs
; i
++, k
++) {
2241 col
+= ne_fprintf(f
, "%s$0x%" TCG_PRIlx
, k
? "," : "",
2246 if (have_prefs
|| op
->life
) {
2247 for (; col
< 40; ++col
) {
2253 unsigned life
= op
->life
;
2255 if (life
& (SYNC_ARG
* 3)) {
2256 ne_fprintf(f
, " sync:");
2257 for (i
= 0; i
< 2; ++i
) {
2258 if (life
& (SYNC_ARG
<< i
)) {
2259 ne_fprintf(f
, " %d", i
);
2265 ne_fprintf(f
, " dead:");
2266 for (i
= 0; life
; ++i
, life
>>= 1) {
2268 ne_fprintf(f
, " %d", i
);
2275 for (i
= 0; i
< nb_oargs
; ++i
) {
2276 TCGRegSet set
= output_pref(op
, i
);
2279 ne_fprintf(f
, " pref=");
2284 ne_fprintf(f
, "none");
2285 } else if (set
== MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS
)) {
2286 ne_fprintf(f
, "all");
2287 #ifdef CONFIG_DEBUG_TCG
2288 } else if (tcg_regset_single(set
)) {
2289 TCGReg reg
= tcg_regset_first(set
);
2290 ne_fprintf(f
, "%s", tcg_target_reg_names
[reg
]);
2292 } else if (TCG_TARGET_NB_REGS
<= 32) {
2293 ne_fprintf(f
, "0x%x", (uint32_t)set
);
2295 ne_fprintf(f
, "0x%" PRIx64
, (uint64_t)set
);
2304 /* we give more priority to constraints with less registers */
2305 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
2307 const TCGArgConstraint
*arg_ct
= &def
->args_ct
[k
];
2308 int n
= ctpop64(arg_ct
->regs
);
2311 * Sort constraints of a single register first, which includes output
2312 * aliases (which must exactly match the input already allocated).
2314 if (n
== 1 || arg_ct
->oalias
) {
2319 * Sort register pairs next, first then second immediately after.
2320 * Arbitrarily sort multiple pairs by the index of the first reg;
2321 * there shouldn't be many pairs.
2323 switch (arg_ct
->pair
) {
2328 return (arg_ct
->pair_index
+ 1) * 2 - 1;
2331 /* Finally, sort by decreasing register count. */
2336 /* sort from highest priority to lowest */
2337 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
2340 TCGArgConstraint
*a
= def
->args_ct
;
2342 for (i
= 0; i
< n
; i
++) {
2343 a
[start
+ i
].sort_index
= start
+ i
;
2348 for (i
= 0; i
< n
- 1; i
++) {
2349 for (j
= i
+ 1; j
< n
; j
++) {
2350 int p1
= get_constraint_priority(def
, a
[start
+ i
].sort_index
);
2351 int p2
= get_constraint_priority(def
, a
[start
+ j
].sort_index
);
2353 int tmp
= a
[start
+ i
].sort_index
;
2354 a
[start
+ i
].sort_index
= a
[start
+ j
].sort_index
;
2355 a
[start
+ j
].sort_index
= tmp
;
2361 static void process_op_defs(TCGContext
*s
)
2365 for (op
= 0; op
< NB_OPS
; op
++) {
2366 TCGOpDef
*def
= &tcg_op_defs
[op
];
2367 const TCGTargetOpDef
*tdefs
;
2368 bool saw_alias_pair
= false;
2369 int i
, o
, i2
, o2
, nb_args
;
2371 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2375 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
2381 * Macro magic should make it impossible, but double-check that
2382 * the array index is in range. Since the signness of an enum
2383 * is implementation defined, force the result to unsigned.
2385 unsigned con_set
= tcg_target_op_def(op
);
2386 tcg_debug_assert(con_set
< ARRAY_SIZE(constraint_sets
));
2387 tdefs
= &constraint_sets
[con_set
];
2389 for (i
= 0; i
< nb_args
; i
++) {
2390 const char *ct_str
= tdefs
->args_ct_str
[i
];
2391 bool input_p
= i
>= def
->nb_oargs
;
2393 /* Incomplete TCGTargetOpDef entry. */
2394 tcg_debug_assert(ct_str
!= NULL
);
2399 tcg_debug_assert(input_p
);
2400 tcg_debug_assert(o
< def
->nb_oargs
);
2401 tcg_debug_assert(def
->args_ct
[o
].regs
!= 0);
2402 tcg_debug_assert(!def
->args_ct
[o
].oalias
);
2403 def
->args_ct
[i
] = def
->args_ct
[o
];
2404 /* The output sets oalias. */
2405 def
->args_ct
[o
].oalias
= 1;
2406 def
->args_ct
[o
].alias_index
= i
;
2407 /* The input sets ialias. */
2408 def
->args_ct
[i
].ialias
= 1;
2409 def
->args_ct
[i
].alias_index
= o
;
2410 if (def
->args_ct
[i
].pair
) {
2411 saw_alias_pair
= true;
2413 tcg_debug_assert(ct_str
[1] == '\0');
2417 tcg_debug_assert(!input_p
);
2418 def
->args_ct
[i
].newreg
= true;
2422 case 'p': /* plus */
2423 /* Allocate to the register after the previous. */
2424 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2426 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2427 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2428 def
->args_ct
[i
] = (TCGArgConstraint
){
2431 .regs
= def
->args_ct
[o
].regs
<< 1,
2433 def
->args_ct
[o
].pair
= 1;
2434 def
->args_ct
[o
].pair_index
= i
;
2435 tcg_debug_assert(ct_str
[1] == '\0');
2438 case 'm': /* minus */
2439 /* Allocate to the register before the previous. */
2440 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2442 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2443 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2444 def
->args_ct
[i
] = (TCGArgConstraint
){
2447 .regs
= def
->args_ct
[o
].regs
>> 1,
2449 def
->args_ct
[o
].pair
= 2;
2450 def
->args_ct
[o
].pair_index
= i
;
2451 tcg_debug_assert(ct_str
[1] == '\0');
2458 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
2461 /* Include all of the target-specific constraints. */
2464 #define CONST(CASE, MASK) \
2465 case CASE: def->args_ct[i].ct |= MASK; break;
2466 #define REGS(CASE, MASK) \
2467 case CASE: def->args_ct[i].regs |= MASK; break;
2469 #include "tcg-target-con-str.h"
2478 /* Typo in TCGTargetOpDef constraint. */
2479 g_assert_not_reached();
2481 } while (*++ct_str
!= '\0');
2484 /* TCGTargetOpDef entry with too much information? */
2485 tcg_debug_assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
2488 * Fix up output pairs that are aliased with inputs.
2489 * When we created the alias, we copied pair from the output.
2490 * There are three cases:
2491 * (1a) Pairs of inputs alias pairs of outputs.
2492 * (1b) One input aliases the first of a pair of outputs.
2493 * (2) One input aliases the second of a pair of outputs.
2495 * Case 1a is handled by making sure that the pair_index'es are
2496 * properly updated so that they appear the same as a pair of inputs.
2498 * Case 1b is handled by setting the pair_index of the input to
2499 * itself, simply so it doesn't point to an unrelated argument.
2500 * Since we don't encounter the "second" during the input allocation
2501 * phase, nothing happens with the second half of the input pair.
2503 * Case 2 is handled by setting the second input to pair=3, the
2504 * first output to pair=3, and the pair_index'es to match.
2506 if (saw_alias_pair
) {
2507 for (i
= def
->nb_oargs
; i
< nb_args
; i
++) {
2509 * Since [0-9pm] must be alone in the constraint string,
2510 * the only way they can both be set is if the pair comes
2511 * from the output alias.
2513 if (!def
->args_ct
[i
].ialias
) {
2516 switch (def
->args_ct
[i
].pair
) {
2520 o
= def
->args_ct
[i
].alias_index
;
2521 o2
= def
->args_ct
[o
].pair_index
;
2522 tcg_debug_assert(def
->args_ct
[o
].pair
== 1);
2523 tcg_debug_assert(def
->args_ct
[o2
].pair
== 2);
2524 if (def
->args_ct
[o2
].oalias
) {
2526 i2
= def
->args_ct
[o2
].alias_index
;
2527 tcg_debug_assert(def
->args_ct
[i2
].pair
== 2);
2528 def
->args_ct
[i2
].pair_index
= i
;
2529 def
->args_ct
[i
].pair_index
= i2
;
2532 def
->args_ct
[i
].pair_index
= i
;
2536 o
= def
->args_ct
[i
].alias_index
;
2537 o2
= def
->args_ct
[o
].pair_index
;
2538 tcg_debug_assert(def
->args_ct
[o
].pair
== 2);
2539 tcg_debug_assert(def
->args_ct
[o2
].pair
== 1);
2540 if (def
->args_ct
[o2
].oalias
) {
2542 i2
= def
->args_ct
[o2
].alias_index
;
2543 tcg_debug_assert(def
->args_ct
[i2
].pair
== 1);
2544 def
->args_ct
[i2
].pair_index
= i
;
2545 def
->args_ct
[i
].pair_index
= i2
;
2548 def
->args_ct
[i
].pair
= 3;
2549 def
->args_ct
[o2
].pair
= 3;
2550 def
->args_ct
[i
].pair_index
= o2
;
2551 def
->args_ct
[o2
].pair_index
= i
;
2555 g_assert_not_reached();
2560 /* sort the constraints (XXX: this is just an heuristic) */
2561 sort_constraints(def
, 0, def
->nb_oargs
);
2562 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
2566 static void remove_label_use(TCGOp
*op
, int idx
)
2568 TCGLabel
*label
= arg_label(op
->args
[idx
]);
2571 QSIMPLEQ_FOREACH(use
, &label
->branches
, next
) {
2572 if (use
->op
== op
) {
2573 QSIMPLEQ_REMOVE(&label
->branches
, use
, TCGLabelUse
, next
);
2577 g_assert_not_reached();
2580 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
2584 remove_label_use(op
, 0);
2586 case INDEX_op_brcond_i32
:
2587 case INDEX_op_brcond_i64
:
2588 remove_label_use(op
, 3);
2590 case INDEX_op_brcond2_i32
:
2591 remove_label_use(op
, 5);
2597 QTAILQ_REMOVE(&s
->ops
, op
, link
);
2598 QTAILQ_INSERT_TAIL(&s
->free_ops
, op
, link
);
2601 #ifdef CONFIG_PROFILER
2602 qatomic_set(&s
->prof
.del_op_count
, s
->prof
.del_op_count
+ 1);
2606 void tcg_remove_ops_after(TCGOp
*op
)
2608 TCGContext
*s
= tcg_ctx
;
2611 TCGOp
*last
= tcg_last_op();
2615 tcg_op_remove(s
, last
);
2619 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
)
2621 TCGContext
*s
= tcg_ctx
;
2624 if (unlikely(!QTAILQ_EMPTY(&s
->free_ops
))) {
2625 QTAILQ_FOREACH(op
, &s
->free_ops
, link
) {
2626 if (nargs
<= op
->nargs
) {
2627 QTAILQ_REMOVE(&s
->free_ops
, op
, link
);
2634 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */
2635 nargs
= MAX(4, nargs
);
2636 op
= tcg_malloc(sizeof(TCGOp
) + sizeof(TCGArg
) * nargs
);
2639 memset(op
, 0, offsetof(TCGOp
, link
));
2643 /* Check for bitfield overflow. */
2644 tcg_debug_assert(op
->nargs
== nargs
);
2650 TCGOp
*tcg_emit_op(TCGOpcode opc
, unsigned nargs
)
2652 TCGOp
*op
= tcg_op_alloc(opc
, nargs
);
2653 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2657 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*old_op
,
2658 TCGOpcode opc
, unsigned nargs
)
2660 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
2661 QTAILQ_INSERT_BEFORE(old_op
, new_op
, link
);
2665 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*old_op
,
2666 TCGOpcode opc
, unsigned nargs
)
2668 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
2669 QTAILQ_INSERT_AFTER(&s
->ops
, old_op
, new_op
, link
);
2673 static void move_label_uses(TCGLabel
*to
, TCGLabel
*from
)
2677 QSIMPLEQ_FOREACH(u
, &from
->branches
, next
) {
2681 op
->args
[0] = label_arg(to
);
2683 case INDEX_op_brcond_i32
:
2684 case INDEX_op_brcond_i64
:
2685 op
->args
[3] = label_arg(to
);
2687 case INDEX_op_brcond2_i32
:
2688 op
->args
[5] = label_arg(to
);
2691 g_assert_not_reached();
2695 QSIMPLEQ_CONCAT(&to
->branches
, &from
->branches
);
2698 /* Reachable analysis : remove unreachable code. */
2699 static void __attribute__((noinline
))
2700 reachable_code_pass(TCGContext
*s
)
2702 TCGOp
*op
, *op_next
, *op_prev
;
2705 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
2710 case INDEX_op_set_label
:
2711 label
= arg_label(op
->args
[0]);
2714 * Note that the first op in the TB is always a load,
2715 * so there is always something before a label.
2717 op_prev
= QTAILQ_PREV(op
, link
);
2720 * If we find two sequential labels, move all branches to
2721 * reference the second label and remove the first label.
2722 * Do this before branch to next optimization, so that the
2723 * middle label is out of the way.
2725 if (op_prev
->opc
== INDEX_op_set_label
) {
2726 move_label_uses(label
, arg_label(op_prev
->args
[0]));
2727 tcg_op_remove(s
, op_prev
);
2728 op_prev
= QTAILQ_PREV(op
, link
);
2732 * Optimization can fold conditional branches to unconditional.
2733 * If we find a label which is preceded by an unconditional
2734 * branch to next, remove the branch. We couldn't do this when
2735 * processing the branch because any dead code between the branch
2736 * and label had not yet been removed.
2738 if (op_prev
->opc
== INDEX_op_br
&&
2739 label
== arg_label(op_prev
->args
[0])) {
2740 tcg_op_remove(s
, op_prev
);
2741 /* Fall through means insns become live again. */
2745 if (QSIMPLEQ_EMPTY(&label
->branches
)) {
2747 * While there is an occasional backward branch, virtually
2748 * all branches generated by the translators are forward.
2749 * Which means that generally we will have already removed
2750 * all references to the label that will be, and there is
2751 * little to be gained by iterating.
2755 /* Once we see a label, insns become live again. */
2762 case INDEX_op_exit_tb
:
2763 case INDEX_op_goto_ptr
:
2764 /* Unconditional branches; everything following is dead. */
2769 /* Notice noreturn helper calls, raising exceptions. */
2770 if (tcg_call_flags(op
) & TCG_CALL_NO_RETURN
) {
2775 case INDEX_op_insn_start
:
2776 /* Never remove -- we need to keep these for unwind. */
2785 tcg_op_remove(s
, op
);
2793 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
2794 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
2796 /* For liveness_pass_1, the register preferences for a given temp. */
2797 static inline TCGRegSet
*la_temp_pref(TCGTemp
*ts
)
2799 return ts
->state_ptr
;
2802 /* For liveness_pass_1, reset the preferences for a given temp to the
2803 * maximal regset for its type.
2805 static inline void la_reset_pref(TCGTemp
*ts
)
2808 = (ts
->state
== TS_DEAD
? 0 : tcg_target_available_regs
[ts
->type
]);
2811 /* liveness analysis: end of function: all temps are dead, and globals
2812 should be in memory. */
2813 static void la_func_end(TCGContext
*s
, int ng
, int nt
)
2817 for (i
= 0; i
< ng
; ++i
) {
2818 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
2819 la_reset_pref(&s
->temps
[i
]);
2821 for (i
= ng
; i
< nt
; ++i
) {
2822 s
->temps
[i
].state
= TS_DEAD
;
2823 la_reset_pref(&s
->temps
[i
]);
2827 /* liveness analysis: end of basic block: all temps are dead, globals
2828 and local temps should be in memory. */
2829 static void la_bb_end(TCGContext
*s
, int ng
, int nt
)
2833 for (i
= 0; i
< nt
; ++i
) {
2834 TCGTemp
*ts
= &s
->temps
[i
];
2841 state
= TS_DEAD
| TS_MEM
;
2848 g_assert_not_reached();
2855 /* liveness analysis: sync globals back to memory. */
2856 static void la_global_sync(TCGContext
*s
, int ng
)
2860 for (i
= 0; i
< ng
; ++i
) {
2861 int state
= s
->temps
[i
].state
;
2862 s
->temps
[i
].state
= state
| TS_MEM
;
2863 if (state
== TS_DEAD
) {
2864 /* If the global was previously dead, reset prefs. */
2865 la_reset_pref(&s
->temps
[i
]);
2871 * liveness analysis: conditional branch: all temps are dead unless
2872 * explicitly live-across-conditional-branch, globals and local temps
2875 static void la_bb_sync(TCGContext
*s
, int ng
, int nt
)
2877 la_global_sync(s
, ng
);
2879 for (int i
= ng
; i
< nt
; ++i
) {
2880 TCGTemp
*ts
= &s
->temps
[i
];
2886 ts
->state
= state
| TS_MEM
;
2887 if (state
!= TS_DEAD
) {
2895 g_assert_not_reached();
2897 la_reset_pref(&s
->temps
[i
]);
2901 /* liveness analysis: sync globals back to memory and kill. */
2902 static void la_global_kill(TCGContext
*s
, int ng
)
2906 for (i
= 0; i
< ng
; i
++) {
2907 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
2908 la_reset_pref(&s
->temps
[i
]);
2912 /* liveness analysis: note live globals crossing calls. */
2913 static void la_cross_call(TCGContext
*s
, int nt
)
2915 TCGRegSet mask
= ~tcg_target_call_clobber_regs
;
2918 for (i
= 0; i
< nt
; i
++) {
2919 TCGTemp
*ts
= &s
->temps
[i
];
2920 if (!(ts
->state
& TS_DEAD
)) {
2921 TCGRegSet
*pset
= la_temp_pref(ts
);
2922 TCGRegSet set
= *pset
;
2925 /* If the combination is not possible, restart. */
2927 set
= tcg_target_available_regs
[ts
->type
] & mask
;
2935 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce
2936 * to TEMP_EBB, if possible.
2938 static void __attribute__((noinline
))
2939 liveness_pass_0(TCGContext
*s
)
2941 void * const multiple_ebb
= (void *)(uintptr_t)-1;
2942 int nb_temps
= s
->nb_temps
;
2945 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
2946 s
->temps
[i
].state_ptr
= NULL
;
2950 * Represent each EBB by the op at which it begins. In the case of
2951 * the first EBB, this is the first op, otherwise it is a label.
2952 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use
2953 * within a single EBB, else MULTIPLE_EBB.
2955 ebb
= QTAILQ_FIRST(&s
->ops
);
2956 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
2957 const TCGOpDef
*def
;
2958 int nb_oargs
, nb_iargs
;
2961 case INDEX_op_set_label
:
2964 case INDEX_op_discard
:
2967 nb_oargs
= TCGOP_CALLO(op
);
2968 nb_iargs
= TCGOP_CALLI(op
);
2971 def
= &tcg_op_defs
[op
->opc
];
2972 nb_oargs
= def
->nb_oargs
;
2973 nb_iargs
= def
->nb_iargs
;
2977 for (int i
= 0; i
< nb_oargs
+ nb_iargs
; ++i
) {
2978 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
2980 if (ts
->kind
!= TEMP_TB
) {
2983 if (ts
->state_ptr
== NULL
) {
2984 ts
->state_ptr
= ebb
;
2985 } else if (ts
->state_ptr
!= ebb
) {
2986 ts
->state_ptr
= multiple_ebb
;
2992 * For TEMP_TB that turned out not to be used beyond one EBB,
2993 * reduce the liveness to TEMP_EBB.
2995 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
2996 TCGTemp
*ts
= &s
->temps
[i
];
2997 if (ts
->kind
== TEMP_TB
&& ts
->state_ptr
!= multiple_ebb
) {
2998 ts
->kind
= TEMP_EBB
;
3003 /* Liveness analysis : update the opc_arg_life array to tell if a
3004 given input arguments is dead. Instructions updating dead
3005 temporaries are removed. */
3006 static void __attribute__((noinline
))
3007 liveness_pass_1(TCGContext
*s
)
3009 int nb_globals
= s
->nb_globals
;
3010 int nb_temps
= s
->nb_temps
;
3011 TCGOp
*op
, *op_prev
;
3015 prefs
= tcg_malloc(sizeof(TCGRegSet
) * nb_temps
);
3016 for (i
= 0; i
< nb_temps
; ++i
) {
3017 s
->temps
[i
].state_ptr
= prefs
+ i
;
3020 /* ??? Should be redundant with the exit_tb that ends the TB. */
3021 la_func_end(s
, nb_globals
, nb_temps
);
3023 QTAILQ_FOREACH_REVERSE_SAFE(op
, &s
->ops
, link
, op_prev
) {
3024 int nb_iargs
, nb_oargs
;
3025 TCGOpcode opc_new
, opc_new2
;
3027 TCGLifeData arg_life
= 0;
3029 TCGOpcode opc
= op
->opc
;
3030 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3035 const TCGHelperInfo
*info
= tcg_call_info(op
);
3036 int call_flags
= tcg_call_flags(op
);
3038 nb_oargs
= TCGOP_CALLO(op
);
3039 nb_iargs
= TCGOP_CALLI(op
);
3041 /* pure functions can be removed if their result is unused */
3042 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
3043 for (i
= 0; i
< nb_oargs
; i
++) {
3044 ts
= arg_temp(op
->args
[i
]);
3045 if (ts
->state
!= TS_DEAD
) {
3046 goto do_not_remove_call
;
3053 /* Output args are dead. */
3054 for (i
= 0; i
< nb_oargs
; i
++) {
3055 ts
= arg_temp(op
->args
[i
]);
3056 if (ts
->state
& TS_DEAD
) {
3057 arg_life
|= DEAD_ARG
<< i
;
3059 if (ts
->state
& TS_MEM
) {
3060 arg_life
|= SYNC_ARG
<< i
;
3062 ts
->state
= TS_DEAD
;
3066 /* Not used -- it will be tcg_target_call_oarg_reg(). */
3067 memset(op
->output_pref
, 0, sizeof(op
->output_pref
));
3069 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
3070 TCG_CALL_NO_READ_GLOBALS
))) {
3071 la_global_kill(s
, nb_globals
);
3072 } else if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
3073 la_global_sync(s
, nb_globals
);
3076 /* Record arguments that die in this helper. */
3077 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3078 ts
= arg_temp(op
->args
[i
]);
3079 if (ts
->state
& TS_DEAD
) {
3080 arg_life
|= DEAD_ARG
<< i
;
3084 /* For all live registers, remove call-clobbered prefs. */
3085 la_cross_call(s
, nb_temps
);
3088 * Input arguments are live for preceding opcodes.
3090 * For those arguments that die, and will be allocated in
3091 * registers, clear the register set for that arg, to be
3092 * filled in below. For args that will be on the stack,
3093 * reset to any available reg. Process arguments in reverse
3094 * order so that if a temp is used more than once, the stack
3095 * reset to max happens before the register reset to 0.
3097 for (i
= nb_iargs
- 1; i
>= 0; i
--) {
3098 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3099 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3101 if (ts
->state
& TS_DEAD
) {
3102 switch (loc
->kind
) {
3103 case TCG_CALL_ARG_NORMAL
:
3104 case TCG_CALL_ARG_EXTEND_U
:
3105 case TCG_CALL_ARG_EXTEND_S
:
3107 *la_temp_pref(ts
) = 0;
3113 tcg_target_available_regs
[ts
->type
];
3116 ts
->state
&= ~TS_DEAD
;
3121 * For each input argument, add its input register to prefs.
3122 * If a temp is used once, this produces a single set bit;
3123 * if a temp is used multiple times, this produces a set.
3125 for (i
= 0; i
< nb_iargs
; i
++) {
3126 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3127 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3129 switch (loc
->kind
) {
3130 case TCG_CALL_ARG_NORMAL
:
3131 case TCG_CALL_ARG_EXTEND_U
:
3132 case TCG_CALL_ARG_EXTEND_S
:
3134 tcg_regset_set_reg(*la_temp_pref(ts
),
3135 tcg_target_call_iarg_regs
[loc
->arg_slot
]);
3144 case INDEX_op_insn_start
:
3146 case INDEX_op_discard
:
3147 /* mark the temporary as dead */
3148 ts
= arg_temp(op
->args
[0]);
3149 ts
->state
= TS_DEAD
;
3153 case INDEX_op_add2_i32
:
3154 opc_new
= INDEX_op_add_i32
;
3156 case INDEX_op_sub2_i32
:
3157 opc_new
= INDEX_op_sub_i32
;
3159 case INDEX_op_add2_i64
:
3160 opc_new
= INDEX_op_add_i64
;
3162 case INDEX_op_sub2_i64
:
3163 opc_new
= INDEX_op_sub_i64
;
3167 /* Test if the high part of the operation is dead, but not
3168 the low part. The result can be optimized to a simple
3169 add or sub. This happens often for x86_64 guest when the
3170 cpu mode is set to 32 bit. */
3171 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3172 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3175 /* Replace the opcode and adjust the args in place,
3176 leaving 3 unused args at the end. */
3177 op
->opc
= opc
= opc_new
;
3178 op
->args
[1] = op
->args
[2];
3179 op
->args
[2] = op
->args
[4];
3180 /* Fall through and mark the single-word operation live. */
3186 case INDEX_op_mulu2_i32
:
3187 opc_new
= INDEX_op_mul_i32
;
3188 opc_new2
= INDEX_op_muluh_i32
;
3189 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
3191 case INDEX_op_muls2_i32
:
3192 opc_new
= INDEX_op_mul_i32
;
3193 opc_new2
= INDEX_op_mulsh_i32
;
3194 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
3196 case INDEX_op_mulu2_i64
:
3197 opc_new
= INDEX_op_mul_i64
;
3198 opc_new2
= INDEX_op_muluh_i64
;
3199 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
3201 case INDEX_op_muls2_i64
:
3202 opc_new
= INDEX_op_mul_i64
;
3203 opc_new2
= INDEX_op_mulsh_i64
;
3204 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
3209 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3210 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3211 /* Both parts of the operation are dead. */
3214 /* The high part of the operation is dead; generate the low. */
3215 op
->opc
= opc
= opc_new
;
3216 op
->args
[1] = op
->args
[2];
3217 op
->args
[2] = op
->args
[3];
3218 } else if (arg_temp(op
->args
[0])->state
== TS_DEAD
&& have_opc_new2
) {
3219 /* The low part of the operation is dead; generate the high. */
3220 op
->opc
= opc
= opc_new2
;
3221 op
->args
[0] = op
->args
[1];
3222 op
->args
[1] = op
->args
[2];
3223 op
->args
[2] = op
->args
[3];
3227 /* Mark the single-word operation live. */
3232 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
3233 nb_iargs
= def
->nb_iargs
;
3234 nb_oargs
= def
->nb_oargs
;
3236 /* Test if the operation can be removed because all
3237 its outputs are dead. We assume that nb_oargs == 0
3238 implies side effects */
3239 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
3240 for (i
= 0; i
< nb_oargs
; i
++) {
3241 if (arg_temp(op
->args
[i
])->state
!= TS_DEAD
) {
3250 tcg_op_remove(s
, op
);
3254 for (i
= 0; i
< nb_oargs
; i
++) {
3255 ts
= arg_temp(op
->args
[i
]);
3257 /* Remember the preference of the uses that followed. */
3258 if (i
< ARRAY_SIZE(op
->output_pref
)) {
3259 op
->output_pref
[i
] = *la_temp_pref(ts
);
3262 /* Output args are dead. */
3263 if (ts
->state
& TS_DEAD
) {
3264 arg_life
|= DEAD_ARG
<< i
;
3266 if (ts
->state
& TS_MEM
) {
3267 arg_life
|= SYNC_ARG
<< i
;
3269 ts
->state
= TS_DEAD
;
3273 /* If end of basic block, update. */
3274 if (def
->flags
& TCG_OPF_BB_EXIT
) {
3275 la_func_end(s
, nb_globals
, nb_temps
);
3276 } else if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3277 la_bb_sync(s
, nb_globals
, nb_temps
);
3278 } else if (def
->flags
& TCG_OPF_BB_END
) {
3279 la_bb_end(s
, nb_globals
, nb_temps
);
3280 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3281 la_global_sync(s
, nb_globals
);
3282 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
3283 la_cross_call(s
, nb_temps
);
3287 /* Record arguments that die in this opcode. */
3288 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3289 ts
= arg_temp(op
->args
[i
]);
3290 if (ts
->state
& TS_DEAD
) {
3291 arg_life
|= DEAD_ARG
<< i
;
3295 /* Input arguments are live for preceding opcodes. */
3296 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3297 ts
= arg_temp(op
->args
[i
]);
3298 if (ts
->state
& TS_DEAD
) {
3299 /* For operands that were dead, initially allow
3300 all regs for the type. */
3301 *la_temp_pref(ts
) = tcg_target_available_regs
[ts
->type
];
3302 ts
->state
&= ~TS_DEAD
;
3306 /* Incorporate constraints for this operand. */
3308 case INDEX_op_mov_i32
:
3309 case INDEX_op_mov_i64
:
3310 /* Note that these are TCG_OPF_NOT_PRESENT and do not
3311 have proper constraints. That said, special case
3312 moves to propagate preferences backward. */
3313 if (IS_DEAD_ARG(1)) {
3314 *la_temp_pref(arg_temp(op
->args
[0]))
3315 = *la_temp_pref(arg_temp(op
->args
[1]));
3320 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3321 const TCGArgConstraint
*ct
= &def
->args_ct
[i
];
3322 TCGRegSet set
, *pset
;
3324 ts
= arg_temp(op
->args
[i
]);
3325 pset
= la_temp_pref(ts
);
3330 set
&= output_pref(op
, ct
->alias_index
);
3332 /* If the combination is not possible, restart. */
3342 op
->life
= arg_life
;
3346 /* Liveness analysis: Convert indirect regs to direct temporaries. */
3347 static bool __attribute__((noinline
))
3348 liveness_pass_2(TCGContext
*s
)
3350 int nb_globals
= s
->nb_globals
;
3352 bool changes
= false;
3353 TCGOp
*op
, *op_next
;
3355 /* Create a temporary for each indirect global. */
3356 for (i
= 0; i
< nb_globals
; ++i
) {
3357 TCGTemp
*its
= &s
->temps
[i
];
3358 if (its
->indirect_reg
) {
3359 TCGTemp
*dts
= tcg_temp_alloc(s
);
3360 dts
->type
= its
->type
;
3361 dts
->base_type
= its
->base_type
;
3362 dts
->temp_subindex
= its
->temp_subindex
;
3363 dts
->kind
= TEMP_EBB
;
3364 its
->state_ptr
= dts
;
3366 its
->state_ptr
= NULL
;
3368 /* All globals begin dead. */
3369 its
->state
= TS_DEAD
;
3371 for (nb_temps
= s
->nb_temps
; i
< nb_temps
; ++i
) {
3372 TCGTemp
*its
= &s
->temps
[i
];
3373 its
->state_ptr
= NULL
;
3374 its
->state
= TS_DEAD
;
3377 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3378 TCGOpcode opc
= op
->opc
;
3379 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3380 TCGLifeData arg_life
= op
->life
;
3381 int nb_iargs
, nb_oargs
, call_flags
;
3382 TCGTemp
*arg_ts
, *dir_ts
;
3384 if (opc
== INDEX_op_call
) {
3385 nb_oargs
= TCGOP_CALLO(op
);
3386 nb_iargs
= TCGOP_CALLI(op
);
3387 call_flags
= tcg_call_flags(op
);
3389 nb_iargs
= def
->nb_iargs
;
3390 nb_oargs
= def
->nb_oargs
;
3392 /* Set flags similar to how calls require. */
3393 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3394 /* Like reading globals: sync_globals */
3395 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3396 } else if (def
->flags
& TCG_OPF_BB_END
) {
3397 /* Like writing globals: save_globals */
3399 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3400 /* Like reading globals: sync_globals */
3401 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3403 /* No effect on globals. */
3404 call_flags
= (TCG_CALL_NO_READ_GLOBALS
|
3405 TCG_CALL_NO_WRITE_GLOBALS
);
3409 /* Make sure that input arguments are available. */
3410 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3411 arg_ts
= arg_temp(op
->args
[i
]);
3412 dir_ts
= arg_ts
->state_ptr
;
3413 if (dir_ts
&& arg_ts
->state
== TS_DEAD
) {
3414 TCGOpcode lopc
= (arg_ts
->type
== TCG_TYPE_I32
3417 TCGOp
*lop
= tcg_op_insert_before(s
, op
, lopc
, 3);
3419 lop
->args
[0] = temp_arg(dir_ts
);
3420 lop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3421 lop
->args
[2] = arg_ts
->mem_offset
;
3423 /* Loaded, but synced with memory. */
3424 arg_ts
->state
= TS_MEM
;
3428 /* Perform input replacement, and mark inputs that became dead.
3429 No action is required except keeping temp_state up to date
3430 so that we reload when needed. */
3431 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3432 arg_ts
= arg_temp(op
->args
[i
]);
3433 dir_ts
= arg_ts
->state_ptr
;
3435 op
->args
[i
] = temp_arg(dir_ts
);
3437 if (IS_DEAD_ARG(i
)) {
3438 arg_ts
->state
= TS_DEAD
;
3443 /* Liveness analysis should ensure that the following are
3444 all correct, for call sites and basic block end points. */
3445 if (call_flags
& TCG_CALL_NO_READ_GLOBALS
) {
3447 } else if (call_flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
3448 for (i
= 0; i
< nb_globals
; ++i
) {
3449 /* Liveness should see that globals are synced back,
3450 that is, either TS_DEAD or TS_MEM. */
3451 arg_ts
= &s
->temps
[i
];
3452 tcg_debug_assert(arg_ts
->state_ptr
== 0
3453 || arg_ts
->state
!= 0);
3456 for (i
= 0; i
< nb_globals
; ++i
) {
3457 /* Liveness should see that globals are saved back,
3458 that is, TS_DEAD, waiting to be reloaded. */
3459 arg_ts
= &s
->temps
[i
];
3460 tcg_debug_assert(arg_ts
->state_ptr
== 0
3461 || arg_ts
->state
== TS_DEAD
);
3465 /* Outputs become available. */
3466 if (opc
== INDEX_op_mov_i32
|| opc
== INDEX_op_mov_i64
) {
3467 arg_ts
= arg_temp(op
->args
[0]);
3468 dir_ts
= arg_ts
->state_ptr
;
3470 op
->args
[0] = temp_arg(dir_ts
);
3473 /* The output is now live and modified. */
3476 if (NEED_SYNC_ARG(0)) {
3477 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3480 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3481 TCGTemp
*out_ts
= dir_ts
;
3483 if (IS_DEAD_ARG(0)) {
3484 out_ts
= arg_temp(op
->args
[1]);
3485 arg_ts
->state
= TS_DEAD
;
3486 tcg_op_remove(s
, op
);
3488 arg_ts
->state
= TS_MEM
;
3491 sop
->args
[0] = temp_arg(out_ts
);
3492 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3493 sop
->args
[2] = arg_ts
->mem_offset
;
3495 tcg_debug_assert(!IS_DEAD_ARG(0));
3499 for (i
= 0; i
< nb_oargs
; i
++) {
3500 arg_ts
= arg_temp(op
->args
[i
]);
3501 dir_ts
= arg_ts
->state_ptr
;
3505 op
->args
[i
] = temp_arg(dir_ts
);
3508 /* The output is now live and modified. */
3511 /* Sync outputs upon their last write. */
3512 if (NEED_SYNC_ARG(i
)) {
3513 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3516 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3518 sop
->args
[0] = temp_arg(dir_ts
);
3519 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3520 sop
->args
[2] = arg_ts
->mem_offset
;
3522 arg_ts
->state
= TS_MEM
;
3524 /* Drop outputs that are dead. */
3525 if (IS_DEAD_ARG(i
)) {
3526 arg_ts
->state
= TS_DEAD
;
3535 static void temp_allocate_frame(TCGContext
*s
, TCGTemp
*ts
)
3540 /* When allocating an object, look at the full type. */
3541 size
= tcg_type_size(ts
->base_type
);
3542 switch (ts
->base_type
) {
3554 * Note that we do not require aligned storage for V256,
3555 * and that we provide alignment for I128 to match V128,
3556 * even if that's above what the host ABI requires.
3561 g_assert_not_reached();
3565 * Assume the stack is sufficiently aligned.
3566 * This affects e.g. ARM NEON, where we have 8 byte stack alignment
3567 * and do not require 16 byte vector alignment. This seems slightly
3568 * easier than fully parameterizing the above switch statement.
3570 align
= MIN(TCG_TARGET_STACK_ALIGN
, align
);
3571 off
= ROUND_UP(s
->current_frame_offset
, align
);
3573 /* If we've exhausted the stack frame, restart with a smaller TB. */
3574 if (off
+ size
> s
->frame_end
) {
3575 tcg_raise_tb_overflow(s
);
3577 s
->current_frame_offset
= off
+ size
;
3578 #if defined(__sparc__)
3579 off
+= TCG_TARGET_STACK_BIAS
;
3582 /* If the object was subdivided, assign memory to all the parts. */
3583 if (ts
->base_type
!= ts
->type
) {
3584 int part_size
= tcg_type_size(ts
->type
);
3585 int part_count
= size
/ part_size
;
3588 * Each part is allocated sequentially in tcg_temp_new_internal.
3589 * Jump back to the first part by subtracting the current index.
3591 ts
-= ts
->temp_subindex
;
3592 for (int i
= 0; i
< part_count
; ++i
) {
3593 ts
[i
].mem_offset
= off
+ i
* part_size
;
3594 ts
[i
].mem_base
= s
->frame_temp
;
3595 ts
[i
].mem_allocated
= 1;
3598 ts
->mem_offset
= off
;
3599 ts
->mem_base
= s
->frame_temp
;
3600 ts
->mem_allocated
= 1;
3604 /* Assign @reg to @ts, and update reg_to_temp[]. */
3605 static void set_temp_val_reg(TCGContext
*s
, TCGTemp
*ts
, TCGReg reg
)
3607 if (ts
->val_type
== TEMP_VAL_REG
) {
3608 TCGReg old
= ts
->reg
;
3609 tcg_debug_assert(s
->reg_to_temp
[old
] == ts
);
3613 s
->reg_to_temp
[old
] = NULL
;
3615 tcg_debug_assert(s
->reg_to_temp
[reg
] == NULL
);
3616 s
->reg_to_temp
[reg
] = ts
;
3617 ts
->val_type
= TEMP_VAL_REG
;
3621 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */
3622 static void set_temp_val_nonreg(TCGContext
*s
, TCGTemp
*ts
, TCGTempVal type
)
3624 tcg_debug_assert(type
!= TEMP_VAL_REG
);
3625 if (ts
->val_type
== TEMP_VAL_REG
) {
3626 TCGReg reg
= ts
->reg
;
3627 tcg_debug_assert(s
->reg_to_temp
[reg
] == ts
);
3628 s
->reg_to_temp
[reg
] = NULL
;
3630 ts
->val_type
= type
;
3633 static void temp_load(TCGContext
*, TCGTemp
*, TCGRegSet
, TCGRegSet
, TCGRegSet
);
3635 /* Mark a temporary as free or dead. If 'free_or_dead' is negative,
3636 mark it free; otherwise mark it dead. */
3637 static void temp_free_or_dead(TCGContext
*s
, TCGTemp
*ts
, int free_or_dead
)
3639 TCGTempVal new_type
;
3646 new_type
= TEMP_VAL_MEM
;
3649 new_type
= free_or_dead
< 0 ? TEMP_VAL_MEM
: TEMP_VAL_DEAD
;
3652 new_type
= TEMP_VAL_CONST
;
3655 g_assert_not_reached();
3657 set_temp_val_nonreg(s
, ts
, new_type
);
3660 /* Mark a temporary as dead. */
3661 static inline void temp_dead(TCGContext
*s
, TCGTemp
*ts
)
3663 temp_free_or_dead(s
, ts
, 1);
3666 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
3667 registers needs to be allocated to store a constant. If 'free_or_dead'
3668 is non-zero, subsequently release the temporary; if it is positive, the
3669 temp is dead; if it is negative, the temp is free. */
3670 static void temp_sync(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
,
3671 TCGRegSet preferred_regs
, int free_or_dead
)
3673 if (!temp_readonly(ts
) && !ts
->mem_coherent
) {
3674 if (!ts
->mem_allocated
) {
3675 temp_allocate_frame(s
, ts
);
3677 switch (ts
->val_type
) {
3678 case TEMP_VAL_CONST
:
3679 /* If we're going to free the temp immediately, then we won't
3680 require it later in a register, so attempt to store the
3681 constant to memory directly. */
3683 && tcg_out_sti(s
, ts
->type
, ts
->val
,
3684 ts
->mem_base
->reg
, ts
->mem_offset
)) {
3687 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
3688 allocated_regs
, preferred_regs
);
3692 tcg_out_st(s
, ts
->type
, ts
->reg
,
3693 ts
->mem_base
->reg
, ts
->mem_offset
);
3703 ts
->mem_coherent
= 1;
3706 temp_free_or_dead(s
, ts
, free_or_dead
);
3710 /* free register 'reg' by spilling the corresponding temporary if necessary */
3711 static void tcg_reg_free(TCGContext
*s
, TCGReg reg
, TCGRegSet allocated_regs
)
3713 TCGTemp
*ts
= s
->reg_to_temp
[reg
];
3715 temp_sync(s
, ts
, allocated_regs
, 0, -1);
3721 * @required_regs: Set of registers in which we must allocate.
3722 * @allocated_regs: Set of registers which must be avoided.
3723 * @preferred_regs: Set of registers we should prefer.
3724 * @rev: True if we search the registers in "indirect" order.
3726 * The allocated register must be in @required_regs & ~@allocated_regs,
3727 * but if we can put it in @preferred_regs we may save a move later.
3729 static TCGReg
tcg_reg_alloc(TCGContext
*s
, TCGRegSet required_regs
,
3730 TCGRegSet allocated_regs
,
3731 TCGRegSet preferred_regs
, bool rev
)
3733 int i
, j
, f
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
3734 TCGRegSet reg_ct
[2];
3737 reg_ct
[1] = required_regs
& ~allocated_regs
;
3738 tcg_debug_assert(reg_ct
[1] != 0);
3739 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
3741 /* Skip the preferred_regs option if it cannot be satisfied,
3742 or if the preference made no difference. */
3743 f
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
3745 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
3747 /* Try free registers, preferences first. */
3748 for (j
= f
; j
< 2; j
++) {
3749 TCGRegSet set
= reg_ct
[j
];
3751 if (tcg_regset_single(set
)) {
3752 /* One register in the set. */
3753 TCGReg reg
= tcg_regset_first(set
);
3754 if (s
->reg_to_temp
[reg
] == NULL
) {
3758 for (i
= 0; i
< n
; i
++) {
3759 TCGReg reg
= order
[i
];
3760 if (s
->reg_to_temp
[reg
] == NULL
&&
3761 tcg_regset_test_reg(set
, reg
)) {
3768 /* We must spill something. */
3769 for (j
= f
; j
< 2; j
++) {
3770 TCGRegSet set
= reg_ct
[j
];
3772 if (tcg_regset_single(set
)) {
3773 /* One register in the set. */
3774 TCGReg reg
= tcg_regset_first(set
);
3775 tcg_reg_free(s
, reg
, allocated_regs
);
3778 for (i
= 0; i
< n
; i
++) {
3779 TCGReg reg
= order
[i
];
3780 if (tcg_regset_test_reg(set
, reg
)) {
3781 tcg_reg_free(s
, reg
, allocated_regs
);
3791 static TCGReg
tcg_reg_alloc_pair(TCGContext
*s
, TCGRegSet required_regs
,
3792 TCGRegSet allocated_regs
,
3793 TCGRegSet preferred_regs
, bool rev
)
3795 int i
, j
, k
, fmin
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
3796 TCGRegSet reg_ct
[2];
3799 /* Ensure that if I is not in allocated_regs, I+1 is not either. */
3800 reg_ct
[1] = required_regs
& ~(allocated_regs
| (allocated_regs
>> 1));
3801 tcg_debug_assert(reg_ct
[1] != 0);
3802 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
3804 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
3807 * Skip the preferred_regs option if it cannot be satisfied,
3808 * or if the preference made no difference.
3810 k
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
3813 * Minimize the number of flushes by looking for 2 free registers first,
3814 * then a single flush, then two flushes.
3816 for (fmin
= 2; fmin
>= 0; fmin
--) {
3817 for (j
= k
; j
< 2; j
++) {
3818 TCGRegSet set
= reg_ct
[j
];
3820 for (i
= 0; i
< n
; i
++) {
3821 TCGReg reg
= order
[i
];
3823 if (tcg_regset_test_reg(set
, reg
)) {
3824 int f
= !s
->reg_to_temp
[reg
] + !s
->reg_to_temp
[reg
+ 1];
3826 tcg_reg_free(s
, reg
, allocated_regs
);
3827 tcg_reg_free(s
, reg
+ 1, allocated_regs
);
3837 /* Make sure the temporary is in a register. If needed, allocate the register
3838 from DESIRED while avoiding ALLOCATED. */
3839 static void temp_load(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet desired_regs
,
3840 TCGRegSet allocated_regs
, TCGRegSet preferred_regs
)
3844 switch (ts
->val_type
) {
3847 case TEMP_VAL_CONST
:
3848 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
3849 preferred_regs
, ts
->indirect_base
);
3850 if (ts
->type
<= TCG_TYPE_I64
) {
3851 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
3853 uint64_t val
= ts
->val
;
3857 * Find the minimal vector element that matches the constant.
3858 * The targets will, in general, have to do this search anyway,
3859 * do this generically.
3861 if (val
== dup_const(MO_8
, val
)) {
3863 } else if (val
== dup_const(MO_16
, val
)) {
3865 } else if (val
== dup_const(MO_32
, val
)) {
3869 tcg_out_dupi_vec(s
, ts
->type
, vece
, reg
, ts
->val
);
3871 ts
->mem_coherent
= 0;
3874 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
3875 preferred_regs
, ts
->indirect_base
);
3876 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_base
->reg
, ts
->mem_offset
);
3877 ts
->mem_coherent
= 1;
3883 set_temp_val_reg(s
, ts
, reg
);
3886 /* Save a temporary to memory. 'allocated_regs' is used in case a
3887 temporary registers needs to be allocated to store a constant. */
3888 static void temp_save(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
)
3890 /* The liveness analysis already ensures that globals are back
3891 in memory. Keep an tcg_debug_assert for safety. */
3892 tcg_debug_assert(ts
->val_type
== TEMP_VAL_MEM
|| temp_readonly(ts
));
3895 /* save globals to their canonical location and assume they can be
3896 modified be the following code. 'allocated_regs' is used in case a
3897 temporary registers needs to be allocated to store a constant. */
3898 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
3902 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
3903 temp_save(s
, &s
->temps
[i
], allocated_regs
);
3907 /* sync globals to their canonical location and assume they can be
3908 read by the following code. 'allocated_regs' is used in case a
3909 temporary registers needs to be allocated to store a constant. */
3910 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
3914 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
3915 TCGTemp
*ts
= &s
->temps
[i
];
3916 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
3917 || ts
->kind
== TEMP_FIXED
3918 || ts
->mem_coherent
);
3922 /* at the end of a basic block, we assume all temporaries are dead and
3923 all globals are stored at their canonical location. */
3924 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
3928 for (i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
3929 TCGTemp
*ts
= &s
->temps
[i
];
3933 temp_save(s
, ts
, allocated_regs
);
3936 /* The liveness analysis already ensures that temps are dead.
3937 Keep an tcg_debug_assert for safety. */
3938 tcg_debug_assert(ts
->val_type
== TEMP_VAL_DEAD
);
3941 /* Similarly, we should have freed any allocated register. */
3942 tcg_debug_assert(ts
->val_type
== TEMP_VAL_CONST
);
3945 g_assert_not_reached();
3949 save_globals(s
, allocated_regs
);
3953 * At a conditional branch, we assume all temporaries are dead unless
3954 * explicitly live-across-conditional-branch; all globals and local
3955 * temps are synced to their location.
3957 static void tcg_reg_alloc_cbranch(TCGContext
*s
, TCGRegSet allocated_regs
)
3959 sync_globals(s
, allocated_regs
);
3961 for (int i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
3962 TCGTemp
*ts
= &s
->temps
[i
];
3964 * The liveness analysis already ensures that temps are dead.
3965 * Keep tcg_debug_asserts for safety.
3969 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
|| ts
->mem_coherent
);
3975 g_assert_not_reached();
3981 * Specialized code generation for INDEX_op_mov_* with a constant.
3983 static void tcg_reg_alloc_do_movi(TCGContext
*s
, TCGTemp
*ots
,
3984 tcg_target_ulong val
, TCGLifeData arg_life
,
3985 TCGRegSet preferred_regs
)
3987 /* ENV should not be modified. */
3988 tcg_debug_assert(!temp_readonly(ots
));
3990 /* The movi is not explicitly generated here. */
3991 set_temp_val_nonreg(s
, ots
, TEMP_VAL_CONST
);
3993 ots
->mem_coherent
= 0;
3994 if (NEED_SYNC_ARG(0)) {
3995 temp_sync(s
, ots
, s
->reserved_regs
, preferred_regs
, IS_DEAD_ARG(0));
3996 } else if (IS_DEAD_ARG(0)) {
4002 * Specialized code generation for INDEX_op_mov_*.
4004 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOp
*op
)
4006 const TCGLifeData arg_life
= op
->life
;
4007 TCGRegSet allocated_regs
, preferred_regs
;
4009 TCGType otype
, itype
;
4012 allocated_regs
= s
->reserved_regs
;
4013 preferred_regs
= output_pref(op
, 0);
4014 ots
= arg_temp(op
->args
[0]);
4015 ts
= arg_temp(op
->args
[1]);
4017 /* ENV should not be modified. */
4018 tcg_debug_assert(!temp_readonly(ots
));
4020 /* Note that otype != itype for no-op truncation. */
4024 if (ts
->val_type
== TEMP_VAL_CONST
) {
4025 /* propagate constant or generate sti */
4026 tcg_target_ulong val
= ts
->val
;
4027 if (IS_DEAD_ARG(1)) {
4030 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, preferred_regs
);
4034 /* If the source value is in memory we're going to be forced
4035 to have it in a register in order to perform the copy. Copy
4036 the SOURCE value into its own register first, that way we
4037 don't have to reload SOURCE the next time it is used. */
4038 if (ts
->val_type
== TEMP_VAL_MEM
) {
4039 temp_load(s
, ts
, tcg_target_available_regs
[itype
],
4040 allocated_regs
, preferred_regs
);
4042 tcg_debug_assert(ts
->val_type
== TEMP_VAL_REG
);
4045 if (IS_DEAD_ARG(0)) {
4046 /* mov to a non-saved dead register makes no sense (even with
4047 liveness analysis disabled). */
4048 tcg_debug_assert(NEED_SYNC_ARG(0));
4049 if (!ots
->mem_allocated
) {
4050 temp_allocate_frame(s
, ots
);
4052 tcg_out_st(s
, otype
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4053 if (IS_DEAD_ARG(1)) {
4060 if (IS_DEAD_ARG(1) && ts
->kind
!= TEMP_FIXED
) {
4062 * The mov can be suppressed. Kill input first, so that it
4063 * is unlinked from reg_to_temp, then set the output to the
4064 * reg that we saved from the input.
4069 if (ots
->val_type
== TEMP_VAL_REG
) {
4072 /* Make sure to not spill the input register during allocation. */
4073 oreg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
4074 allocated_regs
| ((TCGRegSet
)1 << ireg
),
4075 preferred_regs
, ots
->indirect_base
);
4077 if (!tcg_out_mov(s
, otype
, oreg
, ireg
)) {
4079 * Cross register class move not supported.
4080 * Store the source register into the destination slot
4081 * and leave the destination temp as TEMP_VAL_MEM.
4083 assert(!temp_readonly(ots
));
4084 if (!ts
->mem_allocated
) {
4085 temp_allocate_frame(s
, ots
);
4087 tcg_out_st(s
, ts
->type
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4088 set_temp_val_nonreg(s
, ts
, TEMP_VAL_MEM
);
4089 ots
->mem_coherent
= 1;
4093 set_temp_val_reg(s
, ots
, oreg
);
4094 ots
->mem_coherent
= 0;
4096 if (NEED_SYNC_ARG(0)) {
4097 temp_sync(s
, ots
, allocated_regs
, 0, 0);
4102 * Specialized code generation for INDEX_op_dup_vec.
4104 static void tcg_reg_alloc_dup(TCGContext
*s
, const TCGOp
*op
)
4106 const TCGLifeData arg_life
= op
->life
;
4107 TCGRegSet dup_out_regs
, dup_in_regs
;
4109 TCGType itype
, vtype
;
4114 ots
= arg_temp(op
->args
[0]);
4115 its
= arg_temp(op
->args
[1]);
4117 /* ENV should not be modified. */
4118 tcg_debug_assert(!temp_readonly(ots
));
4121 vece
= TCGOP_VECE(op
);
4122 vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4124 if (its
->val_type
== TEMP_VAL_CONST
) {
4125 /* Propagate constant via movi -> dupi. */
4126 tcg_target_ulong val
= its
->val
;
4127 if (IS_DEAD_ARG(1)) {
4130 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, output_pref(op
, 0));
4134 dup_out_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4135 dup_in_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[1].regs
;
4137 /* Allocate the output register now. */
4138 if (ots
->val_type
!= TEMP_VAL_REG
) {
4139 TCGRegSet allocated_regs
= s
->reserved_regs
;
4142 if (!IS_DEAD_ARG(1) && its
->val_type
== TEMP_VAL_REG
) {
4143 /* Make sure to not spill the input register. */
4144 tcg_regset_set_reg(allocated_regs
, its
->reg
);
4146 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4147 output_pref(op
, 0), ots
->indirect_base
);
4148 set_temp_val_reg(s
, ots
, oreg
);
4151 switch (its
->val_type
) {
4154 * The dup constriaints must be broad, covering all possible VECE.
4155 * However, tcg_op_dup_vec() gets to see the VECE and we allow it
4156 * to fail, indicating that extra moves are required for that case.
4158 if (tcg_regset_test_reg(dup_in_regs
, its
->reg
)) {
4159 if (tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, its
->reg
)) {
4162 /* Try again from memory or a vector input register. */
4164 if (!its
->mem_coherent
) {
4166 * The input register is not synced, and so an extra store
4167 * would be required to use memory. Attempt an integer-vector
4168 * register move first. We do not have a TCGRegSet for this.
4170 if (tcg_out_mov(s
, itype
, ots
->reg
, its
->reg
)) {
4173 /* Sync the temp back to its slot and load from there. */
4174 temp_sync(s
, its
, s
->reserved_regs
, 0, 0);
4180 if (HOST_BIG_ENDIAN
) {
4181 lowpart_ofs
= tcg_type_size(itype
) - (1 << vece
);
4183 if (tcg_out_dupm_vec(s
, vtype
, vece
, ots
->reg
, its
->mem_base
->reg
,
4184 its
->mem_offset
+ lowpart_ofs
)) {
4187 /* Load the input into the destination vector register. */
4188 tcg_out_ld(s
, itype
, ots
->reg
, its
->mem_base
->reg
, its
->mem_offset
);
4192 g_assert_not_reached();
4195 /* We now have a vector input register, so dup must succeed. */
4196 ok
= tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, ots
->reg
);
4197 tcg_debug_assert(ok
);
4200 ots
->mem_coherent
= 0;
4201 if (IS_DEAD_ARG(1)) {
4204 if (NEED_SYNC_ARG(0)) {
4205 temp_sync(s
, ots
, s
->reserved_regs
, 0, 0);
4207 if (IS_DEAD_ARG(0)) {
4212 static void tcg_reg_alloc_op(TCGContext
*s
, const TCGOp
*op
)
4214 const TCGLifeData arg_life
= op
->life
;
4215 const TCGOpDef
* const def
= &tcg_op_defs
[op
->opc
];
4216 TCGRegSet i_allocated_regs
;
4217 TCGRegSet o_allocated_regs
;
4218 int i
, k
, nb_iargs
, nb_oargs
;
4221 const TCGArgConstraint
*arg_ct
;
4223 TCGArg new_args
[TCG_MAX_OP_ARGS
];
4224 int const_args
[TCG_MAX_OP_ARGS
];
4226 nb_oargs
= def
->nb_oargs
;
4227 nb_iargs
= def
->nb_iargs
;
4229 /* copy constants */
4230 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
4231 op
->args
+ nb_oargs
+ nb_iargs
,
4232 sizeof(TCGArg
) * def
->nb_cargs
);
4234 i_allocated_regs
= s
->reserved_regs
;
4235 o_allocated_regs
= s
->reserved_regs
;
4237 /* satisfy input constraints */
4238 for (k
= 0; k
< nb_iargs
; k
++) {
4239 TCGRegSet i_preferred_regs
, i_required_regs
;
4240 bool allocate_new_reg
, copyto_new_reg
;
4244 i
= def
->args_ct
[nb_oargs
+ k
].sort_index
;
4246 arg_ct
= &def
->args_ct
[i
];
4249 if (ts
->val_type
== TEMP_VAL_CONST
4250 && tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
->ct
)) {
4251 /* constant is OK for instruction */
4253 new_args
[i
] = ts
->val
;
4258 i_preferred_regs
= 0;
4259 i_required_regs
= arg_ct
->regs
;
4260 allocate_new_reg
= false;
4261 copyto_new_reg
= false;
4263 switch (arg_ct
->pair
) {
4264 case 0: /* not paired */
4265 if (arg_ct
->ialias
) {
4266 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4269 * If the input is readonly, then it cannot also be an
4270 * output and aliased to itself. If the input is not
4271 * dead after the instruction, we must allocate a new
4272 * register and move it.
4274 if (temp_readonly(ts
) || !IS_DEAD_ARG(i
)) {
4275 allocate_new_reg
= true;
4276 } else if (ts
->val_type
== TEMP_VAL_REG
) {
4278 * Check if the current register has already been
4279 * allocated for another input.
4282 tcg_regset_test_reg(i_allocated_regs
, reg
);
4285 if (!allocate_new_reg
) {
4286 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4289 allocate_new_reg
= !tcg_regset_test_reg(i_required_regs
, reg
);
4291 if (allocate_new_reg
) {
4293 * Allocate a new register matching the constraint
4294 * and move the temporary register into it.
4296 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4297 i_allocated_regs
, 0);
4298 reg
= tcg_reg_alloc(s
, i_required_regs
, i_allocated_regs
,
4299 i_preferred_regs
, ts
->indirect_base
);
4300 copyto_new_reg
= true;
4305 /* First of an input pair; if i1 == i2, the second is an output. */
4307 i2
= arg_ct
->pair_index
;
4308 ts2
= i1
!= i2
? arg_temp(op
->args
[i2
]) : NULL
;
4311 * It is easier to default to allocating a new pair
4312 * and to identify a few cases where it's not required.
4314 if (arg_ct
->ialias
) {
4315 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4316 if (IS_DEAD_ARG(i1
) &&
4318 !temp_readonly(ts
) &&
4319 ts
->val_type
== TEMP_VAL_REG
&&
4320 ts
->reg
< TCG_TARGET_NB_REGS
- 1 &&
4321 tcg_regset_test_reg(i_required_regs
, reg
) &&
4322 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4323 !tcg_regset_test_reg(i_allocated_regs
, reg
+ 1) &&
4325 ? ts2
->val_type
== TEMP_VAL_REG
&&
4326 ts2
->reg
== reg
+ 1 &&
4328 : s
->reg_to_temp
[reg
+ 1] == NULL
)) {
4332 /* Without aliasing, the pair must also be an input. */
4333 tcg_debug_assert(ts2
);
4334 if (ts
->val_type
== TEMP_VAL_REG
&&
4335 ts2
->val_type
== TEMP_VAL_REG
&&
4336 ts2
->reg
== reg
+ 1 &&
4337 tcg_regset_test_reg(i_required_regs
, reg
)) {
4341 reg
= tcg_reg_alloc_pair(s
, i_required_regs
, i_allocated_regs
,
4342 0, ts
->indirect_base
);
4345 case 2: /* pair second */
4346 reg
= new_args
[arg_ct
->pair_index
] + 1;
4349 case 3: /* ialias with second output, no first input */
4350 tcg_debug_assert(arg_ct
->ialias
);
4351 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4353 if (IS_DEAD_ARG(i
) &&
4354 !temp_readonly(ts
) &&
4355 ts
->val_type
== TEMP_VAL_REG
&&
4357 s
->reg_to_temp
[reg
- 1] == NULL
&&
4358 tcg_regset_test_reg(i_required_regs
, reg
) &&
4359 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4360 !tcg_regset_test_reg(i_allocated_regs
, reg
- 1)) {
4361 tcg_regset_set_reg(i_allocated_regs
, reg
- 1);
4364 reg
= tcg_reg_alloc_pair(s
, i_required_regs
>> 1,
4365 i_allocated_regs
, 0,
4367 tcg_regset_set_reg(i_allocated_regs
, reg
);
4373 * If an aliased input is not dead after the instruction,
4374 * we must allocate a new register and move it.
4376 if (arg_ct
->ialias
&& (!IS_DEAD_ARG(i
) || temp_readonly(ts
))) {
4377 TCGRegSet t_allocated_regs
= i_allocated_regs
;
4380 * Because of the alias, and the continued life, make sure
4381 * that the temp is somewhere *other* than the reg pair,
4382 * and we get a copy in reg.
4384 tcg_regset_set_reg(t_allocated_regs
, reg
);
4385 tcg_regset_set_reg(t_allocated_regs
, reg
+ 1);
4386 if (ts
->val_type
== TEMP_VAL_REG
&& ts
->reg
== reg
) {
4387 /* If ts was already in reg, copy it somewhere else. */
4391 tcg_debug_assert(ts
->kind
!= TEMP_FIXED
);
4392 nr
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
4393 t_allocated_regs
, 0, ts
->indirect_base
);
4394 ok
= tcg_out_mov(s
, ts
->type
, nr
, reg
);
4395 tcg_debug_assert(ok
);
4397 set_temp_val_reg(s
, ts
, nr
);
4399 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4400 t_allocated_regs
, 0);
4401 copyto_new_reg
= true;
4404 /* Preferably allocate to reg, otherwise copy. */
4405 i_required_regs
= (TCGRegSet
)1 << reg
;
4406 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4408 copyto_new_reg
= ts
->reg
!= reg
;
4413 g_assert_not_reached();
4416 if (copyto_new_reg
) {
4417 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4419 * Cross register class move not supported. Sync the
4420 * temp back to its slot and load from there.
4422 temp_sync(s
, ts
, i_allocated_regs
, 0, 0);
4423 tcg_out_ld(s
, ts
->type
, reg
,
4424 ts
->mem_base
->reg
, ts
->mem_offset
);
4429 tcg_regset_set_reg(i_allocated_regs
, reg
);
4432 /* mark dead temporaries and free the associated registers */
4433 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
4434 if (IS_DEAD_ARG(i
)) {
4435 temp_dead(s
, arg_temp(op
->args
[i
]));
4439 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
4440 tcg_reg_alloc_cbranch(s
, i_allocated_regs
);
4441 } else if (def
->flags
& TCG_OPF_BB_END
) {
4442 tcg_reg_alloc_bb_end(s
, i_allocated_regs
);
4444 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
4445 /* XXX: permit generic clobber register list ? */
4446 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
4447 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
4448 tcg_reg_free(s
, i
, i_allocated_regs
);
4452 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
4453 /* sync globals if the op has side effects and might trigger
4455 sync_globals(s
, i_allocated_regs
);
4458 /* satisfy the output constraints */
4459 for(k
= 0; k
< nb_oargs
; k
++) {
4460 i
= def
->args_ct
[k
].sort_index
;
4462 arg_ct
= &def
->args_ct
[i
];
4465 /* ENV should not be modified. */
4466 tcg_debug_assert(!temp_readonly(ts
));
4468 switch (arg_ct
->pair
) {
4469 case 0: /* not paired */
4470 if (arg_ct
->oalias
&& !const_args
[arg_ct
->alias_index
]) {
4471 reg
= new_args
[arg_ct
->alias_index
];
4472 } else if (arg_ct
->newreg
) {
4473 reg
= tcg_reg_alloc(s
, arg_ct
->regs
,
4474 i_allocated_regs
| o_allocated_regs
,
4475 output_pref(op
, k
), ts
->indirect_base
);
4477 reg
= tcg_reg_alloc(s
, arg_ct
->regs
, o_allocated_regs
,
4478 output_pref(op
, k
), ts
->indirect_base
);
4482 case 1: /* first of pair */
4483 tcg_debug_assert(!arg_ct
->newreg
);
4484 if (arg_ct
->oalias
) {
4485 reg
= new_args
[arg_ct
->alias_index
];
4488 reg
= tcg_reg_alloc_pair(s
, arg_ct
->regs
, o_allocated_regs
,
4489 output_pref(op
, k
), ts
->indirect_base
);
4492 case 2: /* second of pair */
4493 tcg_debug_assert(!arg_ct
->newreg
);
4494 if (arg_ct
->oalias
) {
4495 reg
= new_args
[arg_ct
->alias_index
];
4497 reg
= new_args
[arg_ct
->pair_index
] + 1;
4501 case 3: /* first of pair, aliasing with a second input */
4502 tcg_debug_assert(!arg_ct
->newreg
);
4503 reg
= new_args
[arg_ct
->pair_index
] - 1;
4507 g_assert_not_reached();
4509 tcg_regset_set_reg(o_allocated_regs
, reg
);
4510 set_temp_val_reg(s
, ts
, reg
);
4511 ts
->mem_coherent
= 0;
4516 /* emit instruction */
4517 if (def
->flags
& TCG_OPF_VECTOR
) {
4518 tcg_out_vec_op(s
, op
->opc
, TCGOP_VECL(op
), TCGOP_VECE(op
),
4519 new_args
, const_args
);
4521 tcg_out_op(s
, op
->opc
, new_args
, const_args
);
4524 /* move the outputs in the correct register if needed */
4525 for(i
= 0; i
< nb_oargs
; i
++) {
4526 ts
= arg_temp(op
->args
[i
]);
4528 /* ENV should not be modified. */
4529 tcg_debug_assert(!temp_readonly(ts
));
4531 if (NEED_SYNC_ARG(i
)) {
4532 temp_sync(s
, ts
, o_allocated_regs
, 0, IS_DEAD_ARG(i
));
4533 } else if (IS_DEAD_ARG(i
)) {
4539 static bool tcg_reg_alloc_dup2(TCGContext
*s
, const TCGOp
*op
)
4541 const TCGLifeData arg_life
= op
->life
;
4542 TCGTemp
*ots
, *itsl
, *itsh
;
4543 TCGType vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4545 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
4546 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
4547 tcg_debug_assert(TCGOP_VECE(op
) == MO_64
);
4549 ots
= arg_temp(op
->args
[0]);
4550 itsl
= arg_temp(op
->args
[1]);
4551 itsh
= arg_temp(op
->args
[2]);
4553 /* ENV should not be modified. */
4554 tcg_debug_assert(!temp_readonly(ots
));
4556 /* Allocate the output register now. */
4557 if (ots
->val_type
!= TEMP_VAL_REG
) {
4558 TCGRegSet allocated_regs
= s
->reserved_regs
;
4559 TCGRegSet dup_out_regs
=
4560 tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4563 /* Make sure to not spill the input registers. */
4564 if (!IS_DEAD_ARG(1) && itsl
->val_type
== TEMP_VAL_REG
) {
4565 tcg_regset_set_reg(allocated_regs
, itsl
->reg
);
4567 if (!IS_DEAD_ARG(2) && itsh
->val_type
== TEMP_VAL_REG
) {
4568 tcg_regset_set_reg(allocated_regs
, itsh
->reg
);
4571 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4572 output_pref(op
, 0), ots
->indirect_base
);
4573 set_temp_val_reg(s
, ots
, oreg
);
4576 /* Promote dup2 of immediates to dupi_vec. */
4577 if (itsl
->val_type
== TEMP_VAL_CONST
&& itsh
->val_type
== TEMP_VAL_CONST
) {
4578 uint64_t val
= deposit64(itsl
->val
, 32, 32, itsh
->val
);
4581 if (val
== dup_const(MO_8
, val
)) {
4583 } else if (val
== dup_const(MO_16
, val
)) {
4585 } else if (val
== dup_const(MO_32
, val
)) {
4589 tcg_out_dupi_vec(s
, vtype
, vece
, ots
->reg
, val
);
4593 /* If the two inputs form one 64-bit value, try dupm_vec. */
4594 if (itsl
->temp_subindex
== HOST_BIG_ENDIAN
&&
4595 itsh
->temp_subindex
== !HOST_BIG_ENDIAN
&&
4596 itsl
== itsh
+ (HOST_BIG_ENDIAN
? 1 : -1)) {
4597 TCGTemp
*its
= itsl
- HOST_BIG_ENDIAN
;
4599 temp_sync(s
, its
+ 0, s
->reserved_regs
, 0, 0);
4600 temp_sync(s
, its
+ 1, s
->reserved_regs
, 0, 0);
4602 if (tcg_out_dupm_vec(s
, vtype
, MO_64
, ots
->reg
,
4603 its
->mem_base
->reg
, its
->mem_offset
)) {
4608 /* Fall back to generic expansion. */
4612 ots
->mem_coherent
= 0;
4613 if (IS_DEAD_ARG(1)) {
4616 if (IS_DEAD_ARG(2)) {
4619 if (NEED_SYNC_ARG(0)) {
4620 temp_sync(s
, ots
, s
->reserved_regs
, 0, IS_DEAD_ARG(0));
4621 } else if (IS_DEAD_ARG(0)) {
4627 static void load_arg_reg(TCGContext
*s
, TCGReg reg
, TCGTemp
*ts
,
4628 TCGRegSet allocated_regs
)
4630 if (ts
->val_type
== TEMP_VAL_REG
) {
4631 if (ts
->reg
!= reg
) {
4632 tcg_reg_free(s
, reg
, allocated_regs
);
4633 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4635 * Cross register class move not supported. Sync the
4636 * temp back to its slot and load from there.
4638 temp_sync(s
, ts
, allocated_regs
, 0, 0);
4639 tcg_out_ld(s
, ts
->type
, reg
,
4640 ts
->mem_base
->reg
, ts
->mem_offset
);
4644 TCGRegSet arg_set
= 0;
4646 tcg_reg_free(s
, reg
, allocated_regs
);
4647 tcg_regset_set_reg(arg_set
, reg
);
4648 temp_load(s
, ts
, arg_set
, allocated_regs
, 0);
4652 static void load_arg_stk(TCGContext
*s
, int stk_slot
, TCGTemp
*ts
,
4653 TCGRegSet allocated_regs
)
4656 * When the destination is on the stack, load up the temp and store.
4657 * If there are many call-saved registers, the temp might live to
4658 * see another use; otherwise it'll be discarded.
4660 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
], allocated_regs
, 0);
4661 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
,
4662 TCG_TARGET_CALL_STACK_OFFSET
+
4663 stk_slot
* sizeof(tcg_target_long
));
4666 static void load_arg_normal(TCGContext
*s
, const TCGCallArgumentLoc
*l
,
4667 TCGTemp
*ts
, TCGRegSet
*allocated_regs
)
4670 TCGReg reg
= tcg_target_call_iarg_regs
[l
->arg_slot
];
4671 load_arg_reg(s
, reg
, ts
, *allocated_regs
);
4672 tcg_regset_set_reg(*allocated_regs
, reg
);
4674 load_arg_stk(s
, l
->arg_slot
- ARRAY_SIZE(tcg_target_call_iarg_regs
),
4675 ts
, *allocated_regs
);
4679 static void load_arg_ref(TCGContext
*s
, int arg_slot
, TCGReg ref_base
,
4680 intptr_t ref_off
, TCGRegSet
*allocated_regs
)
4683 int stk_slot
= arg_slot
- ARRAY_SIZE(tcg_target_call_iarg_regs
);
4686 reg
= tcg_target_call_iarg_regs
[arg_slot
];
4687 tcg_reg_free(s
, reg
, *allocated_regs
);
4688 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
4689 tcg_regset_set_reg(*allocated_regs
, reg
);
4691 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[TCG_TYPE_PTR
],
4692 *allocated_regs
, 0, false);
4693 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
4694 tcg_out_st(s
, TCG_TYPE_PTR
, reg
, TCG_REG_CALL_STACK
,
4695 TCG_TARGET_CALL_STACK_OFFSET
4696 + stk_slot
* sizeof(tcg_target_long
));
4700 static void tcg_reg_alloc_call(TCGContext
*s
, TCGOp
*op
)
4702 const int nb_oargs
= TCGOP_CALLO(op
);
4703 const int nb_iargs
= TCGOP_CALLI(op
);
4704 const TCGLifeData arg_life
= op
->life
;
4705 const TCGHelperInfo
*info
= tcg_call_info(op
);
4706 TCGRegSet allocated_regs
= s
->reserved_regs
;
4710 * Move inputs into place in reverse order,
4711 * so that we place stacked arguments first.
4713 for (i
= nb_iargs
- 1; i
>= 0; --i
) {
4714 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
4715 TCGTemp
*ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
4717 switch (loc
->kind
) {
4718 case TCG_CALL_ARG_NORMAL
:
4719 case TCG_CALL_ARG_EXTEND_U
:
4720 case TCG_CALL_ARG_EXTEND_S
:
4721 load_arg_normal(s
, loc
, ts
, &allocated_regs
);
4723 case TCG_CALL_ARG_BY_REF
:
4724 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
4725 load_arg_ref(s
, loc
->arg_slot
, TCG_REG_CALL_STACK
,
4726 TCG_TARGET_CALL_STACK_OFFSET
4727 + loc
->ref_slot
* sizeof(tcg_target_long
),
4730 case TCG_CALL_ARG_BY_REF_N
:
4731 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
4734 g_assert_not_reached();
4738 /* Mark dead temporaries and free the associated registers. */
4739 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
4740 if (IS_DEAD_ARG(i
)) {
4741 temp_dead(s
, arg_temp(op
->args
[i
]));
4745 /* Clobber call registers. */
4746 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
4747 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
4748 tcg_reg_free(s
, i
, allocated_regs
);
4753 * Save globals if they might be written by the helper,
4754 * sync them if they might be read.
4756 if (info
->flags
& TCG_CALL_NO_READ_GLOBALS
) {
4758 } else if (info
->flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
4759 sync_globals(s
, allocated_regs
);
4761 save_globals(s
, allocated_regs
);
4765 * If the ABI passes a pointer to the returned struct as the first
4766 * argument, load that now. Pass a pointer to the output home slot.
4768 if (info
->out_kind
== TCG_CALL_RET_BY_REF
) {
4769 TCGTemp
*ts
= arg_temp(op
->args
[0]);
4771 if (!ts
->mem_allocated
) {
4772 temp_allocate_frame(s
, ts
);
4774 load_arg_ref(s
, 0, ts
->mem_base
->reg
, ts
->mem_offset
, &allocated_regs
);
4777 tcg_out_call(s
, tcg_call_func(op
), info
);
4779 /* Assign output registers and emit moves if needed. */
4780 switch (info
->out_kind
) {
4781 case TCG_CALL_RET_NORMAL
:
4782 for (i
= 0; i
< nb_oargs
; i
++) {
4783 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
4784 TCGReg reg
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, i
);
4786 /* ENV should not be modified. */
4787 tcg_debug_assert(!temp_readonly(ts
));
4789 set_temp_val_reg(s
, ts
, reg
);
4790 ts
->mem_coherent
= 0;
4794 case TCG_CALL_RET_BY_VEC
:
4796 TCGTemp
*ts
= arg_temp(op
->args
[0]);
4798 tcg_debug_assert(ts
->base_type
== TCG_TYPE_I128
);
4799 tcg_debug_assert(ts
->temp_subindex
== 0);
4800 if (!ts
->mem_allocated
) {
4801 temp_allocate_frame(s
, ts
);
4803 tcg_out_st(s
, TCG_TYPE_V128
,
4804 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
4805 ts
->mem_base
->reg
, ts
->mem_offset
);
4807 /* fall through to mark all parts in memory */
4809 case TCG_CALL_RET_BY_REF
:
4810 /* The callee has performed a write through the reference. */
4811 for (i
= 0; i
< nb_oargs
; i
++) {
4812 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
4813 ts
->val_type
= TEMP_VAL_MEM
;
4818 g_assert_not_reached();
4821 /* Flush or discard output registers as needed. */
4822 for (i
= 0; i
< nb_oargs
; i
++) {
4823 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
4824 if (NEED_SYNC_ARG(i
)) {
4825 temp_sync(s
, ts
, s
->reserved_regs
, 0, IS_DEAD_ARG(i
));
4826 } else if (IS_DEAD_ARG(i
)) {
4832 #ifdef CONFIG_PROFILER
4834 /* avoid copy/paste errors */
4835 #define PROF_ADD(to, from, field) \
4837 (to)->field += qatomic_read(&((from)->field)); \
4840 #define PROF_MAX(to, from, field) \
4842 typeof((from)->field) val__ = qatomic_read(&((from)->field)); \
4843 if (val__ > (to)->field) { \
4844 (to)->field = val__; \
4848 /* Pass in a zero'ed @prof */
4850 void tcg_profile_snapshot(TCGProfile
*prof
, bool counters
, bool table
)
4852 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
4855 for (i
= 0; i
< n_ctxs
; i
++) {
4856 TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
4857 const TCGProfile
*orig
= &s
->prof
;
4860 PROF_ADD(prof
, orig
, cpu_exec_time
);
4861 PROF_ADD(prof
, orig
, tb_count1
);
4862 PROF_ADD(prof
, orig
, tb_count
);
4863 PROF_ADD(prof
, orig
, op_count
);
4864 PROF_MAX(prof
, orig
, op_count_max
);
4865 PROF_ADD(prof
, orig
, temp_count
);
4866 PROF_MAX(prof
, orig
, temp_count_max
);
4867 PROF_ADD(prof
, orig
, del_op_count
);
4868 PROF_ADD(prof
, orig
, code_in_len
);
4869 PROF_ADD(prof
, orig
, code_out_len
);
4870 PROF_ADD(prof
, orig
, search_out_len
);
4871 PROF_ADD(prof
, orig
, interm_time
);
4872 PROF_ADD(prof
, orig
, code_time
);
4873 PROF_ADD(prof
, orig
, la_time
);
4874 PROF_ADD(prof
, orig
, opt_time
);
4875 PROF_ADD(prof
, orig
, restore_count
);
4876 PROF_ADD(prof
, orig
, restore_time
);
4881 for (i
= 0; i
< NB_OPS
; i
++) {
4882 PROF_ADD(prof
, orig
, table_op_count
[i
]);
4891 static void tcg_profile_snapshot_counters(TCGProfile
*prof
)
4893 tcg_profile_snapshot(prof
, true, false);
4896 static void tcg_profile_snapshot_table(TCGProfile
*prof
)
4898 tcg_profile_snapshot(prof
, false, true);
4901 void tcg_dump_op_count(GString
*buf
)
4903 TCGProfile prof
= {};
4906 tcg_profile_snapshot_table(&prof
);
4907 for (i
= 0; i
< NB_OPS
; i
++) {
4908 g_string_append_printf(buf
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
4909 prof
.table_op_count
[i
]);
4913 int64_t tcg_cpu_exec_time(void)
4915 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
4919 for (i
= 0; i
< n_ctxs
; i
++) {
4920 const TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
4921 const TCGProfile
*prof
= &s
->prof
;
4923 ret
+= qatomic_read(&prof
->cpu_exec_time
);
4928 void tcg_dump_op_count(GString
*buf
)
4930 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
4933 int64_t tcg_cpu_exec_time(void)
4935 error_report("%s: TCG profiler not compiled", __func__
);
4941 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
, target_ulong pc_start
)
4943 #ifdef CONFIG_PROFILER
4944 TCGProfile
*prof
= &s
->prof
;
4949 #ifdef CONFIG_PROFILER
4953 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
4956 qatomic_set(&prof
->op_count
, prof
->op_count
+ n
);
4957 if (n
> prof
->op_count_max
) {
4958 qatomic_set(&prof
->op_count_max
, n
);
4962 qatomic_set(&prof
->temp_count
, prof
->temp_count
+ n
);
4963 if (n
> prof
->temp_count_max
) {
4964 qatomic_set(&prof
->temp_count_max
, n
);
4970 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)
4971 && qemu_log_in_addr_range(pc_start
))) {
4972 FILE *logfile
= qemu_log_trylock();
4974 fprintf(logfile
, "OP:\n");
4975 tcg_dump_ops(s
, logfile
, false);
4976 fprintf(logfile
, "\n");
4977 qemu_log_unlock(logfile
);
4982 #ifdef CONFIG_DEBUG_TCG
4983 /* Ensure all labels referenced have been emitted. */
4988 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
4989 if (unlikely(!l
->present
) && !QSIMPLEQ_EMPTY(&l
->branches
)) {
4990 qemu_log_mask(CPU_LOG_TB_OP
,
4991 "$L%d referenced but not present.\n", l
->id
);
4999 #ifdef CONFIG_PROFILER
5000 qatomic_set(&prof
->opt_time
, prof
->opt_time
- profile_getclock());
5003 #ifdef USE_TCG_OPTIMIZATIONS
5007 #ifdef CONFIG_PROFILER
5008 qatomic_set(&prof
->opt_time
, prof
->opt_time
+ profile_getclock());
5009 qatomic_set(&prof
->la_time
, prof
->la_time
- profile_getclock());
5012 reachable_code_pass(s
);
5016 if (s
->nb_indirects
> 0) {
5018 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND
)
5019 && qemu_log_in_addr_range(pc_start
))) {
5020 FILE *logfile
= qemu_log_trylock();
5022 fprintf(logfile
, "OP before indirect lowering:\n");
5023 tcg_dump_ops(s
, logfile
, false);
5024 fprintf(logfile
, "\n");
5025 qemu_log_unlock(logfile
);
5029 /* Replace indirect temps with direct temps. */
5030 if (liveness_pass_2(s
)) {
5031 /* If changes were made, re-run liveness. */
5036 #ifdef CONFIG_PROFILER
5037 qatomic_set(&prof
->la_time
, prof
->la_time
+ profile_getclock());
5041 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
)
5042 && qemu_log_in_addr_range(pc_start
))) {
5043 FILE *logfile
= qemu_log_trylock();
5045 fprintf(logfile
, "OP after optimization and liveness analysis:\n");
5046 tcg_dump_ops(s
, logfile
, true);
5047 fprintf(logfile
, "\n");
5048 qemu_log_unlock(logfile
);
5053 /* Initialize goto_tb jump offsets. */
5054 tb
->jmp_reset_offset
[0] = TB_JMP_OFFSET_INVALID
;
5055 tb
->jmp_reset_offset
[1] = TB_JMP_OFFSET_INVALID
;
5056 tb
->jmp_insn_offset
[0] = TB_JMP_OFFSET_INVALID
;
5057 tb
->jmp_insn_offset
[1] = TB_JMP_OFFSET_INVALID
;
5059 tcg_reg_alloc_start(s
);
5062 * Reset the buffer pointers when restarting after overflow.
5063 * TODO: Move this into translate-all.c with the rest of the
5064 * buffer management. Having only this done here is confusing.
5066 s
->code_buf
= tcg_splitwx_to_rw(tb
->tc
.ptr
);
5067 s
->code_ptr
= s
->code_buf
;
5069 #ifdef TCG_TARGET_NEED_LDST_LABELS
5070 QSIMPLEQ_INIT(&s
->ldst_labels
);
5072 #ifdef TCG_TARGET_NEED_POOL_LABELS
5073 s
->pool_labels
= NULL
;
5077 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
5078 TCGOpcode opc
= op
->opc
;
5080 #ifdef CONFIG_PROFILER
5081 qatomic_set(&prof
->table_op_count
[opc
], prof
->table_op_count
[opc
] + 1);
5085 case INDEX_op_mov_i32
:
5086 case INDEX_op_mov_i64
:
5087 case INDEX_op_mov_vec
:
5088 tcg_reg_alloc_mov(s
, op
);
5090 case INDEX_op_dup_vec
:
5091 tcg_reg_alloc_dup(s
, op
);
5093 case INDEX_op_insn_start
:
5094 if (num_insns
>= 0) {
5095 size_t off
= tcg_current_code_size(s
);
5096 s
->gen_insn_end_off
[num_insns
] = off
;
5097 /* Assert that we do not overflow our stored offset. */
5098 assert(s
->gen_insn_end_off
[num_insns
] == off
);
5101 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
5103 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
5104 a
= deposit64(op
->args
[i
* 2], 32, 32, op
->args
[i
* 2 + 1]);
5108 s
->gen_insn_data
[num_insns
][i
] = a
;
5111 case INDEX_op_discard
:
5112 temp_dead(s
, arg_temp(op
->args
[0]));
5114 case INDEX_op_set_label
:
5115 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
5116 tcg_out_label(s
, arg_label(op
->args
[0]));
5119 tcg_reg_alloc_call(s
, op
);
5121 case INDEX_op_exit_tb
:
5122 tcg_out_exit_tb(s
, op
->args
[0]);
5124 case INDEX_op_goto_tb
:
5125 tcg_out_goto_tb(s
, op
->args
[0]);
5127 case INDEX_op_dup2_vec
:
5128 if (tcg_reg_alloc_dup2(s
, op
)) {
5133 /* Sanity check that we've not introduced any unhandled opcodes. */
5134 tcg_debug_assert(tcg_op_supported(opc
));
5135 /* Note: in order to speed up the code, it would be much
5136 faster to have specialized register allocator functions for
5137 some common argument patterns */
5138 tcg_reg_alloc_op(s
, op
);
5141 /* Test for (pending) buffer overflow. The assumption is that any
5142 one operation beginning below the high water mark cannot overrun
5143 the buffer completely. Thus we can test for overflow after
5144 generating code without having to check during generation. */
5145 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
5148 /* Test for TB overflow, as seen by gen_insn_end_off. */
5149 if (unlikely(tcg_current_code_size(s
) > UINT16_MAX
)) {
5153 tcg_debug_assert(num_insns
>= 0);
5154 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
5156 /* Generate TB finalization at the end of block */
5157 #ifdef TCG_TARGET_NEED_LDST_LABELS
5158 i
= tcg_out_ldst_finalize(s
);
5163 #ifdef TCG_TARGET_NEED_POOL_LABELS
5164 i
= tcg_out_pool_finalize(s
);
5169 if (!tcg_resolve_relocs(s
)) {
5173 #ifndef CONFIG_TCG_INTERPRETER
5174 /* flush instruction cache */
5175 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
5176 (uintptr_t)s
->code_buf
,
5177 tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
));
5180 return tcg_current_code_size(s
);
5183 #ifdef CONFIG_PROFILER
5184 void tcg_dump_info(GString
*buf
)
5186 TCGProfile prof
= {};
5187 const TCGProfile
*s
;
5189 int64_t tb_div_count
;
5192 tcg_profile_snapshot_counters(&prof
);
5194 tb_count
= s
->tb_count
;
5195 tb_div_count
= tb_count
? tb_count
: 1;
5196 tot
= s
->interm_time
+ s
->code_time
;
5198 g_string_append_printf(buf
, "JIT cycles %" PRId64
5199 " (%0.3f s at 2.4 GHz)\n",
5201 g_string_append_printf(buf
, "translated TBs %" PRId64
5202 " (aborted=%" PRId64
" %0.1f%%)\n",
5203 tb_count
, s
->tb_count1
- tb_count
,
5204 (double)(s
->tb_count1
- s
->tb_count
)
5205 / (s
->tb_count1
? s
->tb_count1
: 1) * 100.0);
5206 g_string_append_printf(buf
, "avg ops/TB %0.1f max=%d\n",
5207 (double)s
->op_count
/ tb_div_count
, s
->op_count_max
);
5208 g_string_append_printf(buf
, "deleted ops/TB %0.2f\n",
5209 (double)s
->del_op_count
/ tb_div_count
);
5210 g_string_append_printf(buf
, "avg temps/TB %0.2f max=%d\n",
5211 (double)s
->temp_count
/ tb_div_count
,
5213 g_string_append_printf(buf
, "avg host code/TB %0.1f\n",
5214 (double)s
->code_out_len
/ tb_div_count
);
5215 g_string_append_printf(buf
, "avg search data/TB %0.1f\n",
5216 (double)s
->search_out_len
/ tb_div_count
);
5218 g_string_append_printf(buf
, "cycles/op %0.1f\n",
5219 s
->op_count
? (double)tot
/ s
->op_count
: 0);
5220 g_string_append_printf(buf
, "cycles/in byte %0.1f\n",
5221 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
5222 g_string_append_printf(buf
, "cycles/out byte %0.1f\n",
5223 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
5224 g_string_append_printf(buf
, "cycles/search byte %0.1f\n",
5226 (double)tot
/ s
->search_out_len
: 0);
5230 g_string_append_printf(buf
, " gen_interm time %0.1f%%\n",
5231 (double)s
->interm_time
/ tot
* 100.0);
5232 g_string_append_printf(buf
, " gen_code time %0.1f%%\n",
5233 (double)s
->code_time
/ tot
* 100.0);
5234 g_string_append_printf(buf
, "optim./code time %0.1f%%\n",
5235 (double)s
->opt_time
/ (s
->code_time
?
5238 g_string_append_printf(buf
, "liveness/code time %0.1f%%\n",
5239 (double)s
->la_time
/ (s
->code_time
?
5240 s
->code_time
: 1) * 100.0);
5241 g_string_append_printf(buf
, "cpu_restore count %" PRId64
"\n",
5243 g_string_append_printf(buf
, " avg cycles %0.1f\n",
5245 (double)s
->restore_time
/ s
->restore_count
: 0);
5248 void tcg_dump_info(GString
*buf
)
5250 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
5254 #ifdef ELF_HOST_MACHINE
5255 /* In order to use this feature, the backend needs to do three things:
5257 (1) Define ELF_HOST_MACHINE to indicate both what value to
5258 put into the ELF image and to indicate support for the feature.
5260 (2) Define tcg_register_jit. This should create a buffer containing
5261 the contents of a .debug_frame section that describes the post-
5262 prologue unwind info for the tcg machine.
5264 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
5267 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
5274 struct jit_code_entry
{
5275 struct jit_code_entry
*next_entry
;
5276 struct jit_code_entry
*prev_entry
;
5277 const void *symfile_addr
;
5278 uint64_t symfile_size
;
5281 struct jit_descriptor
{
5283 uint32_t action_flag
;
5284 struct jit_code_entry
*relevant_entry
;
5285 struct jit_code_entry
*first_entry
;
5288 void __jit_debug_register_code(void) __attribute__((noinline
));
5289 void __jit_debug_register_code(void)
5294 /* Must statically initialize the version, because GDB may check
5295 the version before we can set it. */
5296 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
5298 /* End GDB interface. */
5300 static int find_string(const char *strtab
, const char *str
)
5302 const char *p
= strtab
+ 1;
5305 if (strcmp(p
, str
) == 0) {
5312 static void tcg_register_jit_int(const void *buf_ptr
, size_t buf_size
,
5313 const void *debug_frame
,
5314 size_t debug_frame_size
)
5316 struct __attribute__((packed
)) DebugInfo
{
5323 uintptr_t cu_low_pc
;
5324 uintptr_t cu_high_pc
;
5327 uintptr_t fn_low_pc
;
5328 uintptr_t fn_high_pc
;
5337 struct DebugInfo di
;
5342 struct ElfImage
*img
;
5344 static const struct ElfImage img_template
= {
5346 .e_ident
[EI_MAG0
] = ELFMAG0
,
5347 .e_ident
[EI_MAG1
] = ELFMAG1
,
5348 .e_ident
[EI_MAG2
] = ELFMAG2
,
5349 .e_ident
[EI_MAG3
] = ELFMAG3
,
5350 .e_ident
[EI_CLASS
] = ELF_CLASS
,
5351 .e_ident
[EI_DATA
] = ELF_DATA
,
5352 .e_ident
[EI_VERSION
] = EV_CURRENT
,
5354 .e_machine
= ELF_HOST_MACHINE
,
5355 .e_version
= EV_CURRENT
,
5356 .e_phoff
= offsetof(struct ElfImage
, phdr
),
5357 .e_shoff
= offsetof(struct ElfImage
, shdr
),
5358 .e_ehsize
= sizeof(ElfW(Shdr
)),
5359 .e_phentsize
= sizeof(ElfW(Phdr
)),
5361 .e_shentsize
= sizeof(ElfW(Shdr
)),
5362 .e_shnum
= ARRAY_SIZE(img
->shdr
),
5363 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
5364 #ifdef ELF_HOST_FLAGS
5365 .e_flags
= ELF_HOST_FLAGS
,
5368 .e_ident
[EI_OSABI
] = ELF_OSABI
,
5376 [0] = { .sh_type
= SHT_NULL
},
5377 /* Trick: The contents of code_gen_buffer are not present in
5378 this fake ELF file; that got allocated elsewhere. Therefore
5379 we mark .text as SHT_NOBITS (similar to .bss) so that readers
5380 will not look for contents. We can record any address. */
5382 .sh_type
= SHT_NOBITS
,
5383 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
5385 [2] = { /* .debug_info */
5386 .sh_type
= SHT_PROGBITS
,
5387 .sh_offset
= offsetof(struct ElfImage
, di
),
5388 .sh_size
= sizeof(struct DebugInfo
),
5390 [3] = { /* .debug_abbrev */
5391 .sh_type
= SHT_PROGBITS
,
5392 .sh_offset
= offsetof(struct ElfImage
, da
),
5393 .sh_size
= sizeof(img
->da
),
5395 [4] = { /* .debug_frame */
5396 .sh_type
= SHT_PROGBITS
,
5397 .sh_offset
= sizeof(struct ElfImage
),
5399 [5] = { /* .symtab */
5400 .sh_type
= SHT_SYMTAB
,
5401 .sh_offset
= offsetof(struct ElfImage
, sym
),
5402 .sh_size
= sizeof(img
->sym
),
5404 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
5405 .sh_entsize
= sizeof(ElfW(Sym
)),
5407 [6] = { /* .strtab */
5408 .sh_type
= SHT_STRTAB
,
5409 .sh_offset
= offsetof(struct ElfImage
, str
),
5410 .sh_size
= sizeof(img
->str
),
5414 [1] = { /* code_gen_buffer */
5415 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
5420 .len
= sizeof(struct DebugInfo
) - 4,
5422 .ptr_size
= sizeof(void *),
5424 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
5426 .fn_name
= "code_gen_buffer"
5429 1, /* abbrev number (the cu) */
5430 0x11, 1, /* DW_TAG_compile_unit, has children */
5431 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
5432 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
5433 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
5434 0, 0, /* end of abbrev */
5435 2, /* abbrev number (the fn) */
5436 0x2e, 0, /* DW_TAG_subprogram, no children */
5437 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
5438 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
5439 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
5440 0, 0, /* end of abbrev */
5441 0 /* no more abbrev */
5443 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
5444 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
5447 /* We only need a single jit entry; statically allocate it. */
5448 static struct jit_code_entry one_entry
;
5450 uintptr_t buf
= (uintptr_t)buf_ptr
;
5451 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
5452 DebugFrameHeader
*dfh
;
5454 img
= g_malloc(img_size
);
5455 *img
= img_template
;
5457 img
->phdr
.p_vaddr
= buf
;
5458 img
->phdr
.p_paddr
= buf
;
5459 img
->phdr
.p_memsz
= buf_size
;
5461 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
5462 img
->shdr
[1].sh_addr
= buf
;
5463 img
->shdr
[1].sh_size
= buf_size
;
5465 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
5466 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
5468 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
5469 img
->shdr
[4].sh_size
= debug_frame_size
;
5471 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
5472 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
5474 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
5475 img
->sym
[1].st_value
= buf
;
5476 img
->sym
[1].st_size
= buf_size
;
5478 img
->di
.cu_low_pc
= buf
;
5479 img
->di
.cu_high_pc
= buf
+ buf_size
;
5480 img
->di
.fn_low_pc
= buf
;
5481 img
->di
.fn_high_pc
= buf
+ buf_size
;
5483 dfh
= (DebugFrameHeader
*)(img
+ 1);
5484 memcpy(dfh
, debug_frame
, debug_frame_size
);
5485 dfh
->fde
.func_start
= buf
;
5486 dfh
->fde
.func_len
= buf_size
;
5489 /* Enable this block to be able to debug the ELF image file creation.
5490 One can use readelf, objdump, or other inspection utilities. */
5492 g_autofree
char *jit
= g_strdup_printf("%s/qemu.jit", g_get_tmp_dir());
5493 FILE *f
= fopen(jit
, "w+b");
5495 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
5496 /* Avoid stupid unused return value warning for fwrite. */
5503 one_entry
.symfile_addr
= img
;
5504 one_entry
.symfile_size
= img_size
;
5506 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
5507 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
5508 __jit_debug_descriptor
.first_entry
= &one_entry
;
5509 __jit_debug_register_code();
5512 /* No support for the feature. Provide the entry point expected by exec.c,
5513 and implement the internal function we declared earlier. */
5515 static void tcg_register_jit_int(const void *buf
, size_t size
,
5516 const void *debug_frame
,
5517 size_t debug_frame_size
)
5521 void tcg_register_jit(const void *buf
, size_t buf_size
)
5524 #endif /* ELF_HOST_MACHINE */
5526 #if !TCG_TARGET_MAYBE_vec
5527 void tcg_expand_vec_op(TCGOpcode o
, TCGType t
, unsigned e
, TCGArg a0
, ...)
5529 g_assert_not_reached();