2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_TCG_OPTIMIZATIONS
28 #include "qemu/osdep.h"
30 /* Define to jump the ELF file used to communicate with GDB. */
33 #include "qemu/error-report.h"
34 #include "qemu/cutils.h"
35 #include "qemu/host-utils.h"
36 #include "qemu/qemu-print.h"
37 #include "qemu/cacheflush.h"
38 #include "qemu/cacheinfo.h"
39 #include "qemu/timer.h"
41 /* Note: the long term plan is to reduce the dependencies on the QEMU
42 CPU definitions. Currently they are used for qemu_ld/st
44 #define NO_CPU_IO_DEFS
46 #include "exec/exec-all.h"
47 #include "tcg/tcg-op.h"
49 #if UINTPTR_MAX == UINT32_MAX
50 # define ELF_CLASS ELFCLASS32
52 # define ELF_CLASS ELFCLASS64
55 # define ELF_DATA ELFDATA2MSB
57 # define ELF_DATA ELFDATA2LSB
62 #include "tcg/tcg-ldst.h"
63 #include "tcg/tcg-temp-internal.h"
64 #include "tcg-internal.h"
65 #include "accel/tcg/perf.h"
67 /* Forward declarations for functions declared in tcg-target.c.inc and
69 static void tcg_target_init(TCGContext
*s
);
70 static void tcg_target_qemu_prologue(TCGContext
*s
);
71 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
72 intptr_t value
, intptr_t addend
);
74 /* The CIE and FDE header definitions will be common to all hosts. */
76 uint32_t len
__attribute__((aligned((sizeof(void *)))));
82 uint8_t return_column
;
85 typedef struct QEMU_PACKED
{
86 uint32_t len
__attribute__((aligned((sizeof(void *)))));
90 } DebugFrameFDEHeader
;
92 typedef struct QEMU_PACKED
{
94 DebugFrameFDEHeader fde
;
97 typedef struct TCGLabelQemuLdst
{
98 bool is_ld
; /* qemu_ld: true, qemu_st: false */
100 TCGType type
; /* result type of a load */
101 TCGReg addrlo_reg
; /* reg index for low word of guest virtual addr */
102 TCGReg addrhi_reg
; /* reg index for high word of guest virtual addr */
103 TCGReg datalo_reg
; /* reg index for low word to be loaded or stored */
104 TCGReg datahi_reg
; /* reg index for high word to be loaded or stored */
105 const tcg_insn_unit
*raddr
; /* addr of the next IR of qemu_ld/st IR */
106 tcg_insn_unit
*label_ptr
[2]; /* label pointers to be updated */
107 QSIMPLEQ_ENTRY(TCGLabelQemuLdst
) next
;
110 static void tcg_register_jit_int(const void *buf
, size_t size
,
111 const void *debug_frame
,
112 size_t debug_frame_size
)
113 __attribute__((unused
));
115 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
116 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
118 static bool tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
119 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
120 TCGReg ret
, tcg_target_long arg
);
121 static void tcg_out_ext8s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
122 static void tcg_out_ext16s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
123 static void tcg_out_ext8u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
124 static void tcg_out_ext16u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
125 static void tcg_out_ext32s(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
126 static void tcg_out_ext32u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
127 static void tcg_out_exts_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
128 static void tcg_out_extu_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
129 static void tcg_out_extrl_i64_i32(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
130 static void tcg_out_addi_ptr(TCGContext
*s
, TCGReg
, TCGReg
, tcg_target_long
);
131 static bool tcg_out_xchg(TCGContext
*s
, TCGType type
, TCGReg r1
, TCGReg r2
);
132 static void tcg_out_exit_tb(TCGContext
*s
, uintptr_t arg
);
133 static void tcg_out_goto_tb(TCGContext
*s
, int which
);
134 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
135 const TCGArg args
[TCG_MAX_OP_ARGS
],
136 const int const_args
[TCG_MAX_OP_ARGS
]);
137 #if TCG_TARGET_MAYBE_vec
138 static bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
139 TCGReg dst
, TCGReg src
);
140 static bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
141 TCGReg dst
, TCGReg base
, intptr_t offset
);
142 static void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
143 TCGReg dst
, int64_t arg
);
144 static void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
145 unsigned vecl
, unsigned vece
,
146 const TCGArg args
[TCG_MAX_OP_ARGS
],
147 const int const_args
[TCG_MAX_OP_ARGS
]);
149 static inline bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
150 TCGReg dst
, TCGReg src
)
152 g_assert_not_reached();
154 static inline bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
155 TCGReg dst
, TCGReg base
, intptr_t offset
)
157 g_assert_not_reached();
159 static inline void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
160 TCGReg dst
, int64_t arg
)
162 g_assert_not_reached();
164 static inline void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
165 unsigned vecl
, unsigned vece
,
166 const TCGArg args
[TCG_MAX_OP_ARGS
],
167 const int const_args
[TCG_MAX_OP_ARGS
])
169 g_assert_not_reached();
172 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
174 static bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
175 TCGReg base
, intptr_t ofs
);
176 static void tcg_out_call(TCGContext
*s
, const tcg_insn_unit
*target
,
177 const TCGHelperInfo
*info
);
178 static TCGReg
tcg_target_call_oarg_reg(TCGCallReturnKind kind
, int slot
);
179 static bool tcg_target_const_match(int64_t val
, TCGType type
, int ct
);
180 #ifdef TCG_TARGET_NEED_LDST_LABELS
181 static int tcg_out_ldst_finalize(TCGContext
*s
);
184 typedef struct TCGLdstHelperParam
{
185 TCGReg (*ra_gen
)(TCGContext
*s
, const TCGLabelQemuLdst
*l
, int arg_reg
);
188 } TCGLdstHelperParam
;
190 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
191 const TCGLdstHelperParam
*p
)
192 __attribute__((unused
));
193 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
194 bool load_sign
, const TCGLdstHelperParam
*p
)
195 __attribute__((unused
));
196 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
197 const TCGLdstHelperParam
*p
)
198 __attribute__((unused
));
200 static void * const qemu_ld_helpers
[MO_SSIZE
+ 1] __attribute__((unused
)) = {
201 [MO_UB
] = helper_ldub_mmu
,
202 [MO_SB
] = helper_ldsb_mmu
,
203 [MO_UW
] = helper_lduw_mmu
,
204 [MO_SW
] = helper_ldsw_mmu
,
205 [MO_UL
] = helper_ldul_mmu
,
206 [MO_UQ
] = helper_ldq_mmu
,
207 #if TCG_TARGET_REG_BITS == 64
208 [MO_SL
] = helper_ldsl_mmu
,
212 static void * const qemu_st_helpers
[MO_SIZE
+ 1] __attribute__((unused
)) = {
213 [MO_8
] = helper_stb_mmu
,
214 [MO_16
] = helper_stw_mmu
,
215 [MO_32
] = helper_stl_mmu
,
216 [MO_64
] = helper_stq_mmu
,
219 TCGContext tcg_init_ctx
;
220 __thread TCGContext
*tcg_ctx
;
222 TCGContext
**tcg_ctxs
;
223 unsigned int tcg_cur_ctxs
;
224 unsigned int tcg_max_ctxs
;
225 TCGv_env cpu_env
= 0;
226 const void *tcg_code_gen_epilogue
;
227 uintptr_t tcg_splitwx_diff
;
229 #ifndef CONFIG_TCG_INTERPRETER
230 tcg_prologue_fn
*tcg_qemu_tb_exec
;
233 static TCGRegSet tcg_target_available_regs
[TCG_TYPE_COUNT
];
234 static TCGRegSet tcg_target_call_clobber_regs
;
236 #if TCG_TARGET_INSN_UNIT_SIZE == 1
237 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
242 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
249 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
250 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
252 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
255 tcg_insn_unit
*p
= s
->code_ptr
;
256 memcpy(p
, &v
, sizeof(v
));
257 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
261 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
264 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
267 memcpy(p
, &v
, sizeof(v
));
272 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
273 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
275 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
278 tcg_insn_unit
*p
= s
->code_ptr
;
279 memcpy(p
, &v
, sizeof(v
));
280 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
284 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
287 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
290 memcpy(p
, &v
, sizeof(v
));
295 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
296 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
298 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
301 tcg_insn_unit
*p
= s
->code_ptr
;
302 memcpy(p
, &v
, sizeof(v
));
303 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
307 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
310 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
313 memcpy(p
, &v
, sizeof(v
));
318 /* label relocation processing */
320 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
321 TCGLabel
*l
, intptr_t addend
)
323 TCGRelocation
*r
= tcg_malloc(sizeof(TCGRelocation
));
328 QSIMPLEQ_INSERT_TAIL(&l
->relocs
, r
, next
);
331 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
)
333 tcg_debug_assert(!l
->has_value
);
335 l
->u
.value_ptr
= tcg_splitwx_to_rx(s
->code_ptr
);
338 TCGLabel
*gen_new_label(void)
340 TCGContext
*s
= tcg_ctx
;
341 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
343 memset(l
, 0, sizeof(TCGLabel
));
344 l
->id
= s
->nb_labels
++;
345 QSIMPLEQ_INIT(&l
->branches
);
346 QSIMPLEQ_INIT(&l
->relocs
);
348 QSIMPLEQ_INSERT_TAIL(&s
->labels
, l
, next
);
353 static bool tcg_resolve_relocs(TCGContext
*s
)
357 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
359 uintptr_t value
= l
->u
.value
;
361 QSIMPLEQ_FOREACH(r
, &l
->relocs
, next
) {
362 if (!patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
)) {
370 static void set_jmp_reset_offset(TCGContext
*s
, int which
)
373 * We will check for overflow at the end of the opcode loop in
374 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
376 s
->gen_tb
->jmp_reset_offset
[which
] = tcg_current_code_size(s
);
379 static void G_GNUC_UNUSED
set_jmp_insn_offset(TCGContext
*s
, int which
)
382 * We will check for overflow at the end of the opcode loop in
383 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
385 s
->gen_tb
->jmp_insn_offset
[which
] = tcg_current_code_size(s
);
388 static uintptr_t G_GNUC_UNUSED
get_jmp_target_addr(TCGContext
*s
, int which
)
391 * Return the read-execute version of the pointer, for the benefit
392 * of any pc-relative addressing mode.
394 return (uintptr_t)tcg_splitwx_to_rx(&s
->gen_tb
->jmp_target_addr
[which
]);
397 /* Signal overflow, starting over with fewer guest insns. */
399 void tcg_raise_tb_overflow(TCGContext
*s
)
401 siglongjmp(s
->jmp_trans
, -2);
405 * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext.
406 * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg.
408 * However, tcg_out_helper_load_slots reuses this field to hold an
409 * argument slot number (which may designate a argument register or an
410 * argument stack slot), converting to TCGReg once all arguments that
411 * are destined for the stack are processed.
413 typedef struct TCGMovExtend
{
422 * tcg_out_movext -- move and extend
424 * @dst_type: integral type for destination
425 * @dst: destination register
426 * @src_type: integral type for source
427 * @src_ext: extension to apply to source
428 * @src: source register
430 * Move or extend @src into @dst, depending on @src_ext and the types.
432 static void tcg_out_movext(TCGContext
*s
, TCGType dst_type
, TCGReg dst
,
433 TCGType src_type
, MemOp src_ext
, TCGReg src
)
437 tcg_out_ext8u(s
, dst
, src
);
440 tcg_out_ext8s(s
, dst_type
, dst
, src
);
443 tcg_out_ext16u(s
, dst
, src
);
446 tcg_out_ext16s(s
, dst_type
, dst
, src
);
450 if (dst_type
== TCG_TYPE_I32
) {
451 if (src_type
== TCG_TYPE_I32
) {
452 tcg_out_mov(s
, TCG_TYPE_I32
, dst
, src
);
454 tcg_out_extrl_i64_i32(s
, dst
, src
);
456 } else if (src_type
== TCG_TYPE_I32
) {
457 if (src_ext
& MO_SIGN
) {
458 tcg_out_exts_i32_i64(s
, dst
, src
);
460 tcg_out_extu_i32_i64(s
, dst
, src
);
463 if (src_ext
& MO_SIGN
) {
464 tcg_out_ext32s(s
, dst
, src
);
466 tcg_out_ext32u(s
, dst
, src
);
471 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
472 if (dst_type
== TCG_TYPE_I32
) {
473 tcg_out_extrl_i64_i32(s
, dst
, src
);
475 tcg_out_mov(s
, TCG_TYPE_I64
, dst
, src
);
479 g_assert_not_reached();
483 /* Minor variations on a theme, using a structure. */
484 static void tcg_out_movext1_new_src(TCGContext
*s
, const TCGMovExtend
*i
,
487 tcg_out_movext(s
, i
->dst_type
, i
->dst
, i
->src_type
, i
->src_ext
, src
);
490 static void tcg_out_movext1(TCGContext
*s
, const TCGMovExtend
*i
)
492 tcg_out_movext1_new_src(s
, i
, i
->src
);
496 * tcg_out_movext2 -- move and extend two pair
498 * @i1: first move description
499 * @i2: second move description
500 * @scratch: temporary register, or -1 for none
502 * As tcg_out_movext, for both @i1 and @i2, caring for overlap
503 * between the sources and destinations.
506 static void tcg_out_movext2(TCGContext
*s
, const TCGMovExtend
*i1
,
507 const TCGMovExtend
*i2
, int scratch
)
509 TCGReg src1
= i1
->src
;
510 TCGReg src2
= i2
->src
;
512 if (i1
->dst
!= src2
) {
513 tcg_out_movext1(s
, i1
);
514 tcg_out_movext1(s
, i2
);
517 if (i2
->dst
== src1
) {
518 TCGType src1_type
= i1
->src_type
;
519 TCGType src2_type
= i2
->src_type
;
521 if (tcg_out_xchg(s
, MAX(src1_type
, src2_type
), src1
, src2
)) {
522 /* The data is now in the correct registers, now extend. */
526 tcg_debug_assert(scratch
>= 0);
527 tcg_out_mov(s
, src1_type
, scratch
, src1
);
531 tcg_out_movext1_new_src(s
, i2
, src2
);
532 tcg_out_movext1_new_src(s
, i1
, src1
);
536 * tcg_out_movext3 -- move and extend three pair
538 * @i1: first move description
539 * @i2: second move description
540 * @i3: third move description
541 * @scratch: temporary register, or -1 for none
543 * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap
544 * between the sources and destinations.
547 static void tcg_out_movext3(TCGContext
*s
, const TCGMovExtend
*i1
,
548 const TCGMovExtend
*i2
, const TCGMovExtend
*i3
,
551 TCGReg src1
= i1
->src
;
552 TCGReg src2
= i2
->src
;
553 TCGReg src3
= i3
->src
;
555 if (i1
->dst
!= src2
&& i1
->dst
!= src3
) {
556 tcg_out_movext1(s
, i1
);
557 tcg_out_movext2(s
, i2
, i3
, scratch
);
560 if (i2
->dst
!= src1
&& i2
->dst
!= src3
) {
561 tcg_out_movext1(s
, i2
);
562 tcg_out_movext2(s
, i1
, i3
, scratch
);
565 if (i3
->dst
!= src1
&& i3
->dst
!= src2
) {
566 tcg_out_movext1(s
, i3
);
567 tcg_out_movext2(s
, i1
, i2
, scratch
);
572 * There is a cycle. Since there are only 3 nodes, the cycle is
573 * either "clockwise" or "anti-clockwise", and can be solved with
574 * a single scratch or two xchg.
576 if (i1
->dst
== src2
&& i2
->dst
== src3
&& i3
->dst
== src1
) {
578 if (tcg_out_xchg(s
, MAX(i1
->src_type
, i2
->src_type
), src1
, src2
)) {
579 tcg_out_xchg(s
, MAX(i2
->src_type
, i3
->src_type
), src2
, src3
);
580 /* The data is now in the correct registers, now extend. */
581 tcg_out_movext1_new_src(s
, i1
, i1
->dst
);
582 tcg_out_movext1_new_src(s
, i2
, i2
->dst
);
583 tcg_out_movext1_new_src(s
, i3
, i3
->dst
);
585 tcg_debug_assert(scratch
>= 0);
586 tcg_out_mov(s
, i1
->src_type
, scratch
, src1
);
587 tcg_out_movext1(s
, i3
);
588 tcg_out_movext1(s
, i2
);
589 tcg_out_movext1_new_src(s
, i1
, scratch
);
591 } else if (i1
->dst
== src3
&& i2
->dst
== src1
&& i3
->dst
== src2
) {
592 /* "Anti-clockwise" */
593 if (tcg_out_xchg(s
, MAX(i2
->src_type
, i3
->src_type
), src2
, src3
)) {
594 tcg_out_xchg(s
, MAX(i1
->src_type
, i2
->src_type
), src1
, src2
);
595 /* The data is now in the correct registers, now extend. */
596 tcg_out_movext1_new_src(s
, i1
, i1
->dst
);
597 tcg_out_movext1_new_src(s
, i2
, i2
->dst
);
598 tcg_out_movext1_new_src(s
, i3
, i3
->dst
);
600 tcg_debug_assert(scratch
>= 0);
601 tcg_out_mov(s
, i1
->src_type
, scratch
, src1
);
602 tcg_out_movext1(s
, i2
);
603 tcg_out_movext1(s
, i3
);
604 tcg_out_movext1_new_src(s
, i1
, scratch
);
607 g_assert_not_reached();
611 #define C_PFX1(P, A) P##A
612 #define C_PFX2(P, A, B) P##A##_##B
613 #define C_PFX3(P, A, B, C) P##A##_##B##_##C
614 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
615 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
616 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
618 /* Define an enumeration for the various combinations. */
620 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
621 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
622 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
623 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
625 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
626 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
627 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
628 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
630 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
632 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
633 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
634 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
635 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
638 #include "tcg-target-con-set.h"
639 } TCGConstraintSetIndex
;
641 static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode
);
657 /* Put all of the constraint sets into an array, indexed by the enum. */
659 #define C_O0_I1(I1) { .args_ct_str = { #I1 } },
660 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
661 #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
662 #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
664 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
665 #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
666 #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
667 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
669 #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
671 #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
672 #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
673 #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
674 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
676 static const TCGTargetOpDef constraint_sets
[] = {
677 #include "tcg-target-con-set.h"
695 /* Expand the enumerator to be returned from tcg_target_op_def(). */
697 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
698 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
699 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
700 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
702 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
703 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
704 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
705 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
707 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
709 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
710 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
711 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
712 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
714 #include "tcg-target.c.inc"
716 static void alloc_tcg_plugin_context(TCGContext
*s
)
719 s
->plugin_tb
= g_new0(struct qemu_plugin_tb
, 1);
720 s
->plugin_tb
->insns
=
721 g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn
);
726 * All TCG threads except the parent (i.e. the one that called tcg_context_init
727 * and registered the target's TCG globals) must register with this function
728 * before initiating translation.
730 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation
731 * of tcg_region_init() for the reasoning behind this.
733 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in
734 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context
735 * is not used anymore for translation once this function is called.
737 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates
738 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode.
740 #ifdef CONFIG_USER_ONLY
741 void tcg_register_thread(void)
743 tcg_ctx
= &tcg_init_ctx
;
746 void tcg_register_thread(void)
748 TCGContext
*s
= g_malloc(sizeof(*s
));
753 /* Relink mem_base. */
754 for (i
= 0, n
= tcg_init_ctx
.nb_globals
; i
< n
; ++i
) {
755 if (tcg_init_ctx
.temps
[i
].mem_base
) {
756 ptrdiff_t b
= tcg_init_ctx
.temps
[i
].mem_base
- tcg_init_ctx
.temps
;
757 tcg_debug_assert(b
>= 0 && b
< n
);
758 s
->temps
[i
].mem_base
= &s
->temps
[b
];
762 /* Claim an entry in tcg_ctxs */
763 n
= qatomic_fetch_inc(&tcg_cur_ctxs
);
764 g_assert(n
< tcg_max_ctxs
);
765 qatomic_set(&tcg_ctxs
[n
], s
);
768 alloc_tcg_plugin_context(s
);
769 tcg_region_initial_alloc(s
);
774 #endif /* !CONFIG_USER_ONLY */
776 /* pool based memory allocation */
777 void *tcg_malloc_internal(TCGContext
*s
, int size
)
782 if (size
> TCG_POOL_CHUNK_SIZE
) {
783 /* big malloc: insert a new pool (XXX: could optimize) */
784 p
= g_malloc(sizeof(TCGPool
) + size
);
786 p
->next
= s
->pool_first_large
;
787 s
->pool_first_large
= p
;
798 pool_size
= TCG_POOL_CHUNK_SIZE
;
799 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
802 if (s
->pool_current
) {
803 s
->pool_current
->next
= p
;
813 s
->pool_cur
= p
->data
+ size
;
814 s
->pool_end
= p
->data
+ p
->size
;
818 void tcg_pool_reset(TCGContext
*s
)
821 for (p
= s
->pool_first_large
; p
; p
= t
) {
825 s
->pool_first_large
= NULL
;
826 s
->pool_cur
= s
->pool_end
= NULL
;
827 s
->pool_current
= NULL
;
830 #include "exec/helper-proto.h"
832 static TCGHelperInfo all_helpers
[] = {
833 #include "exec/helper-tcg.h"
835 static GHashTable
*helper_table
;
838 * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions,
839 * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N.
840 * We only use these for layout in tcg_out_ld_helper_ret and
841 * tcg_out_st_helper_args, and share them between several of
842 * the helpers, with the end result that it's easier to build manually.
845 #if TCG_TARGET_REG_BITS == 32
846 # define dh_typecode_ttl dh_typecode_i32
848 # define dh_typecode_ttl dh_typecode_i64
851 static TCGHelperInfo info_helper_ld32_mmu
= {
852 .flags
= TCG_CALL_NO_WG
,
853 .typemask
= dh_typemask(ttl
, 0) /* return tcg_target_ulong */
854 | dh_typemask(env
, 1)
855 | dh_typemask(tl
, 2) /* target_ulong addr */
856 | dh_typemask(i32
, 3) /* unsigned oi */
857 | dh_typemask(ptr
, 4) /* uintptr_t ra */
860 static TCGHelperInfo info_helper_ld64_mmu
= {
861 .flags
= TCG_CALL_NO_WG
,
862 .typemask
= dh_typemask(i64
, 0) /* return uint64_t */
863 | dh_typemask(env
, 1)
864 | dh_typemask(tl
, 2) /* target_ulong addr */
865 | dh_typemask(i32
, 3) /* unsigned oi */
866 | dh_typemask(ptr
, 4) /* uintptr_t ra */
869 static TCGHelperInfo info_helper_st32_mmu
= {
870 .flags
= TCG_CALL_NO_WG
,
871 .typemask
= dh_typemask(void, 0)
872 | dh_typemask(env
, 1)
873 | dh_typemask(tl
, 2) /* target_ulong addr */
874 | dh_typemask(i32
, 3) /* uint32_t data */
875 | dh_typemask(i32
, 4) /* unsigned oi */
876 | dh_typemask(ptr
, 5) /* uintptr_t ra */
879 static TCGHelperInfo info_helper_st64_mmu
= {
880 .flags
= TCG_CALL_NO_WG
,
881 .typemask
= dh_typemask(void, 0)
882 | dh_typemask(env
, 1)
883 | dh_typemask(tl
, 2) /* target_ulong addr */
884 | dh_typemask(i64
, 3) /* uint64_t data */
885 | dh_typemask(i32
, 4) /* unsigned oi */
886 | dh_typemask(ptr
, 5) /* uintptr_t ra */
889 #ifdef CONFIG_TCG_INTERPRETER
890 static ffi_type
*typecode_to_ffi(int argmask
)
893 * libffi does not support __int128_t, so we have forced Int128
894 * to use the structure definition instead of the builtin type.
896 static ffi_type
*ffi_type_i128_elements
[3] = {
901 static ffi_type ffi_type_i128
= {
903 .alignment
= __alignof__(Int128
),
904 .type
= FFI_TYPE_STRUCT
,
905 .elements
= ffi_type_i128_elements
,
909 case dh_typecode_void
:
910 return &ffi_type_void
;
911 case dh_typecode_i32
:
912 return &ffi_type_uint32
;
913 case dh_typecode_s32
:
914 return &ffi_type_sint32
;
915 case dh_typecode_i64
:
916 return &ffi_type_uint64
;
917 case dh_typecode_s64
:
918 return &ffi_type_sint64
;
919 case dh_typecode_ptr
:
920 return &ffi_type_pointer
;
921 case dh_typecode_i128
:
922 return &ffi_type_i128
;
924 g_assert_not_reached();
927 static void init_ffi_layouts(void)
929 /* g_direct_hash/equal for direct comparisons on uint32_t. */
930 GHashTable
*ffi_table
= g_hash_table_new(NULL
, NULL
);
932 for (int i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
933 TCGHelperInfo
*info
= &all_helpers
[i
];
934 unsigned typemask
= info
->typemask
;
935 gpointer hash
= (gpointer
)(uintptr_t)typemask
;
944 cif
= g_hash_table_lookup(ffi_table
, hash
);
950 /* Ignoring the return type, find the last non-zero field. */
951 nargs
= 32 - clz32(typemask
>> 3);
952 nargs
= DIV_ROUND_UP(nargs
, 3);
953 assert(nargs
<= MAX_CALL_IARGS
);
955 ca
= g_malloc0(sizeof(*ca
) + nargs
* sizeof(ffi_type
*));
956 ca
->cif
.rtype
= typecode_to_ffi(typemask
& 7);
957 ca
->cif
.nargs
= nargs
;
960 ca
->cif
.arg_types
= ca
->args
;
961 for (int j
= 0; j
< nargs
; ++j
) {
962 int typecode
= extract32(typemask
, (j
+ 1) * 3, 3);
963 ca
->args
[j
] = typecode_to_ffi(typecode
);
967 status
= ffi_prep_cif(&ca
->cif
, FFI_DEFAULT_ABI
, nargs
,
968 ca
->cif
.rtype
, ca
->cif
.arg_types
);
969 assert(status
== FFI_OK
);
973 g_hash_table_insert(ffi_table
, hash
, (gpointer
)cif
);
976 g_hash_table_destroy(ffi_table
);
978 #endif /* CONFIG_TCG_INTERPRETER */
980 static inline bool arg_slot_reg_p(unsigned arg_slot
)
983 * Split the sizeof away from the comparison to avoid Werror from
984 * "unsigned < 0 is always false", when iarg_regs is empty.
986 unsigned nreg
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
987 return arg_slot
< nreg
;
990 static inline int arg_slot_stk_ofs(unsigned arg_slot
)
992 unsigned max
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
993 unsigned stk_slot
= arg_slot
- ARRAY_SIZE(tcg_target_call_iarg_regs
);
995 tcg_debug_assert(stk_slot
< max
);
996 return TCG_TARGET_CALL_STACK_OFFSET
+ stk_slot
* sizeof(tcg_target_long
);
999 typedef struct TCGCumulativeArgs
{
1000 int arg_idx
; /* tcg_gen_callN args[] */
1001 int info_in_idx
; /* TCGHelperInfo in[] */
1002 int arg_slot
; /* regs+stack slot */
1003 int ref_slot
; /* stack slots for references */
1004 } TCGCumulativeArgs
;
1006 static void layout_arg_even(TCGCumulativeArgs
*cum
)
1008 cum
->arg_slot
+= cum
->arg_slot
& 1;
1011 static void layout_arg_1(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
,
1012 TCGCallArgumentKind kind
)
1014 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1016 *loc
= (TCGCallArgumentLoc
){
1018 .arg_idx
= cum
->arg_idx
,
1019 .arg_slot
= cum
->arg_slot
,
1025 static void layout_arg_normal_n(TCGCumulativeArgs
*cum
,
1026 TCGHelperInfo
*info
, int n
)
1028 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1030 for (int i
= 0; i
< n
; ++i
) {
1031 /* Layout all using the same arg_idx, adjusting the subindex. */
1032 loc
[i
] = (TCGCallArgumentLoc
){
1033 .kind
= TCG_CALL_ARG_NORMAL
,
1034 .arg_idx
= cum
->arg_idx
,
1036 .arg_slot
= cum
->arg_slot
+ i
,
1039 cum
->info_in_idx
+= n
;
1043 static void layout_arg_by_ref(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
)
1045 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
1046 int n
= 128 / TCG_TARGET_REG_BITS
;
1048 /* The first subindex carries the pointer. */
1049 layout_arg_1(cum
, info
, TCG_CALL_ARG_BY_REF
);
1052 * The callee is allowed to clobber memory associated with
1053 * structure pass by-reference. Therefore we must make copies.
1054 * Allocate space from "ref_slot", which will be adjusted to
1055 * follow the parameters on the stack.
1057 loc
[0].ref_slot
= cum
->ref_slot
;
1060 * Subsequent words also go into the reference slot, but
1061 * do not accumulate into the regular arguments.
1063 for (int i
= 1; i
< n
; ++i
) {
1064 loc
[i
] = (TCGCallArgumentLoc
){
1065 .kind
= TCG_CALL_ARG_BY_REF_N
,
1066 .arg_idx
= cum
->arg_idx
,
1068 .ref_slot
= cum
->ref_slot
+ i
,
1071 cum
->info_in_idx
+= n
;
1075 static void init_call_layout(TCGHelperInfo
*info
)
1077 int max_reg_slots
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
1078 int max_stk_slots
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
1079 unsigned typemask
= info
->typemask
;
1081 TCGCumulativeArgs cum
= { };
1084 * Parse and place any function return value.
1086 typecode
= typemask
& 7;
1088 case dh_typecode_void
:
1091 case dh_typecode_i32
:
1092 case dh_typecode_s32
:
1093 case dh_typecode_ptr
:
1095 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1097 case dh_typecode_i64
:
1098 case dh_typecode_s64
:
1099 info
->nr_out
= 64 / TCG_TARGET_REG_BITS
;
1100 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1101 /* Query the last register now to trigger any assert early. */
1102 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1104 case dh_typecode_i128
:
1105 info
->nr_out
= 128 / TCG_TARGET_REG_BITS
;
1106 info
->out_kind
= TCG_TARGET_CALL_RET_I128
;
1107 switch (TCG_TARGET_CALL_RET_I128
) {
1108 case TCG_CALL_RET_NORMAL
:
1109 /* Query the last register now to trigger any assert early. */
1110 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1112 case TCG_CALL_RET_BY_VEC
:
1113 /* Query the single register now to trigger any assert early. */
1114 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0);
1116 case TCG_CALL_RET_BY_REF
:
1118 * Allocate the first argument to the output.
1119 * We don't need to store this anywhere, just make it
1120 * unavailable for use in the input loop below.
1125 qemu_build_not_reached();
1129 g_assert_not_reached();
1133 * Parse and place function arguments.
1135 for (typemask
>>= 3; typemask
; typemask
>>= 3, cum
.arg_idx
++) {
1136 TCGCallArgumentKind kind
;
1139 typecode
= typemask
& 7;
1141 case dh_typecode_i32
:
1142 case dh_typecode_s32
:
1143 type
= TCG_TYPE_I32
;
1145 case dh_typecode_i64
:
1146 case dh_typecode_s64
:
1147 type
= TCG_TYPE_I64
;
1149 case dh_typecode_ptr
:
1150 type
= TCG_TYPE_PTR
;
1152 case dh_typecode_i128
:
1153 type
= TCG_TYPE_I128
;
1156 g_assert_not_reached();
1161 switch (TCG_TARGET_CALL_ARG_I32
) {
1162 case TCG_CALL_ARG_EVEN
:
1163 layout_arg_even(&cum
);
1165 case TCG_CALL_ARG_NORMAL
:
1166 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1168 case TCG_CALL_ARG_EXTEND
:
1169 kind
= TCG_CALL_ARG_EXTEND_U
+ (typecode
& 1);
1170 layout_arg_1(&cum
, info
, kind
);
1173 qemu_build_not_reached();
1178 switch (TCG_TARGET_CALL_ARG_I64
) {
1179 case TCG_CALL_ARG_EVEN
:
1180 layout_arg_even(&cum
);
1182 case TCG_CALL_ARG_NORMAL
:
1183 if (TCG_TARGET_REG_BITS
== 32) {
1184 layout_arg_normal_n(&cum
, info
, 2);
1186 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1190 qemu_build_not_reached();
1195 switch (TCG_TARGET_CALL_ARG_I128
) {
1196 case TCG_CALL_ARG_EVEN
:
1197 layout_arg_even(&cum
);
1199 case TCG_CALL_ARG_NORMAL
:
1200 layout_arg_normal_n(&cum
, info
, 128 / TCG_TARGET_REG_BITS
);
1202 case TCG_CALL_ARG_BY_REF
:
1203 layout_arg_by_ref(&cum
, info
);
1206 qemu_build_not_reached();
1211 g_assert_not_reached();
1214 info
->nr_in
= cum
.info_in_idx
;
1216 /* Validate that we didn't overrun the input array. */
1217 assert(cum
.info_in_idx
<= ARRAY_SIZE(info
->in
));
1218 /* Validate the backend has enough argument space. */
1219 assert(cum
.arg_slot
<= max_reg_slots
+ max_stk_slots
);
1222 * Relocate the "ref_slot" area to the end of the parameters.
1223 * Minimizing this stack offset helps code size for x86,
1224 * which has a signed 8-bit offset encoding.
1226 if (cum
.ref_slot
!= 0) {
1229 if (cum
.arg_slot
> max_reg_slots
) {
1230 int align
= __alignof(Int128
) / sizeof(tcg_target_long
);
1232 ref_base
= cum
.arg_slot
- max_reg_slots
;
1234 ref_base
= ROUND_UP(ref_base
, align
);
1237 assert(ref_base
+ cum
.ref_slot
<= max_stk_slots
);
1238 ref_base
+= max_reg_slots
;
1240 if (ref_base
!= 0) {
1241 for (int i
= cum
.info_in_idx
- 1; i
>= 0; --i
) {
1242 TCGCallArgumentLoc
*loc
= &info
->in
[i
];
1243 switch (loc
->kind
) {
1244 case TCG_CALL_ARG_BY_REF
:
1245 case TCG_CALL_ARG_BY_REF_N
:
1246 loc
->ref_slot
+= ref_base
;
1256 static int indirect_reg_alloc_order
[ARRAY_SIZE(tcg_target_reg_alloc_order
)];
1257 static void process_op_defs(TCGContext
*s
);
1258 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1259 TCGReg reg
, const char *name
);
1261 static void tcg_context_init(unsigned max_cpus
)
1263 TCGContext
*s
= &tcg_init_ctx
;
1264 int op
, total_args
, n
, i
;
1266 TCGArgConstraint
*args_ct
;
1269 memset(s
, 0, sizeof(*s
));
1272 /* Count total number of arguments and allocate the corresponding
1275 for(op
= 0; op
< NB_OPS
; op
++) {
1276 def
= &tcg_op_defs
[op
];
1277 n
= def
->nb_iargs
+ def
->nb_oargs
;
1281 args_ct
= g_new0(TCGArgConstraint
, total_args
);
1283 for(op
= 0; op
< NB_OPS
; op
++) {
1284 def
= &tcg_op_defs
[op
];
1285 def
->args_ct
= args_ct
;
1286 n
= def
->nb_iargs
+ def
->nb_oargs
;
1290 /* Register helpers. */
1291 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
1292 helper_table
= g_hash_table_new(NULL
, NULL
);
1294 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
1295 init_call_layout(&all_helpers
[i
]);
1296 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
1297 (gpointer
)&all_helpers
[i
]);
1300 init_call_layout(&info_helper_ld32_mmu
);
1301 init_call_layout(&info_helper_ld64_mmu
);
1302 init_call_layout(&info_helper_st32_mmu
);
1303 init_call_layout(&info_helper_st64_mmu
);
1305 #ifdef CONFIG_TCG_INTERPRETER
1312 /* Reverse the order of the saved registers, assuming they're all at
1313 the start of tcg_target_reg_alloc_order. */
1314 for (n
= 0; n
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++n
) {
1315 int r
= tcg_target_reg_alloc_order
[n
];
1316 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, r
)) {
1320 for (i
= 0; i
< n
; ++i
) {
1321 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[n
- 1 - i
];
1323 for (; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++i
) {
1324 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[i
];
1327 alloc_tcg_plugin_context(s
);
1331 * In user-mode we simply share the init context among threads, since we
1332 * use a single region. See the documentation tcg_region_init() for the
1333 * reasoning behind this.
1334 * In softmmu we will have at most max_cpus TCG threads.
1336 #ifdef CONFIG_USER_ONLY
1337 tcg_ctxs
= &tcg_ctx
;
1341 tcg_max_ctxs
= max_cpus
;
1342 tcg_ctxs
= g_new0(TCGContext
*, max_cpus
);
1345 tcg_debug_assert(!tcg_regset_test_reg(s
->reserved_regs
, TCG_AREG0
));
1346 ts
= tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, TCG_AREG0
, "env");
1347 cpu_env
= temp_tcgv_ptr(ts
);
1350 void tcg_init(size_t tb_size
, int splitwx
, unsigned max_cpus
)
1352 tcg_context_init(max_cpus
);
1353 tcg_region_init(tb_size
, splitwx
, max_cpus
);
1357 * Allocate TBs right before their corresponding translated code, making
1358 * sure that TBs and code are on different cache lines.
1360 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
)
1362 uintptr_t align
= qemu_icache_linesize
;
1363 TranslationBlock
*tb
;
1367 tb
= (void *)ROUND_UP((uintptr_t)s
->code_gen_ptr
, align
);
1368 next
= (void *)ROUND_UP((uintptr_t)(tb
+ 1), align
);
1370 if (unlikely(next
> s
->code_gen_highwater
)) {
1371 if (tcg_region_alloc(s
)) {
1376 qatomic_set(&s
->code_gen_ptr
, next
);
1377 s
->data_gen_ptr
= NULL
;
1381 void tcg_prologue_init(TCGContext
*s
)
1383 size_t prologue_size
;
1385 s
->code_ptr
= s
->code_gen_ptr
;
1386 s
->code_buf
= s
->code_gen_ptr
;
1387 s
->data_gen_ptr
= NULL
;
1389 #ifndef CONFIG_TCG_INTERPRETER
1390 tcg_qemu_tb_exec
= (tcg_prologue_fn
*)tcg_splitwx_to_rx(s
->code_ptr
);
1393 #ifdef TCG_TARGET_NEED_POOL_LABELS
1394 s
->pool_labels
= NULL
;
1397 qemu_thread_jit_write();
1398 /* Generate the prologue. */
1399 tcg_target_qemu_prologue(s
);
1401 #ifdef TCG_TARGET_NEED_POOL_LABELS
1402 /* Allow the prologue to put e.g. guest_base into a pool entry. */
1404 int result
= tcg_out_pool_finalize(s
);
1405 tcg_debug_assert(result
== 0);
1409 prologue_size
= tcg_current_code_size(s
);
1410 perf_report_prologue(s
->code_gen_ptr
, prologue_size
);
1412 #ifndef CONFIG_TCG_INTERPRETER
1413 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
1414 (uintptr_t)s
->code_buf
, prologue_size
);
1418 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
1419 FILE *logfile
= qemu_log_trylock();
1421 fprintf(logfile
, "PROLOGUE: [size=%zu]\n", prologue_size
);
1422 if (s
->data_gen_ptr
) {
1423 size_t code_size
= s
->data_gen_ptr
- s
->code_gen_ptr
;
1424 size_t data_size
= prologue_size
- code_size
;
1427 disas(logfile
, s
->code_gen_ptr
, code_size
);
1429 for (i
= 0; i
< data_size
; i
+= sizeof(tcg_target_ulong
)) {
1430 if (sizeof(tcg_target_ulong
) == 8) {
1432 "0x%08" PRIxPTR
": .quad 0x%016" PRIx64
"\n",
1433 (uintptr_t)s
->data_gen_ptr
+ i
,
1434 *(uint64_t *)(s
->data_gen_ptr
+ i
));
1437 "0x%08" PRIxPTR
": .long 0x%08x\n",
1438 (uintptr_t)s
->data_gen_ptr
+ i
,
1439 *(uint32_t *)(s
->data_gen_ptr
+ i
));
1443 disas(logfile
, s
->code_gen_ptr
, prologue_size
);
1445 fprintf(logfile
, "\n");
1446 qemu_log_unlock(logfile
);
1451 #ifndef CONFIG_TCG_INTERPRETER
1453 * Assert that goto_ptr is implemented completely, setting an epilogue.
1454 * For tci, we use NULL as the signal to return from the interpreter,
1455 * so skip this check.
1457 tcg_debug_assert(tcg_code_gen_epilogue
!= NULL
);
1460 tcg_region_prologue_set(s
);
1463 void tcg_func_start(TCGContext
*s
)
1466 s
->nb_temps
= s
->nb_globals
;
1468 /* No temps have been previously allocated for size or locality. */
1469 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
1471 /* No constant temps have been previously allocated. */
1472 for (int i
= 0; i
< TCG_TYPE_COUNT
; ++i
) {
1473 if (s
->const_table
[i
]) {
1474 g_hash_table_remove_all(s
->const_table
[i
]);
1480 s
->current_frame_offset
= s
->frame_start
;
1482 #ifdef CONFIG_DEBUG_TCG
1483 s
->goto_tb_issue_mask
= 0;
1486 QTAILQ_INIT(&s
->ops
);
1487 QTAILQ_INIT(&s
->free_ops
);
1488 QSIMPLEQ_INIT(&s
->labels
);
1491 static TCGTemp
*tcg_temp_alloc(TCGContext
*s
)
1493 int n
= s
->nb_temps
++;
1495 if (n
>= TCG_MAX_TEMPS
) {
1496 tcg_raise_tb_overflow(s
);
1498 return memset(&s
->temps
[n
], 0, sizeof(TCGTemp
));
1501 static TCGTemp
*tcg_global_alloc(TCGContext
*s
)
1505 tcg_debug_assert(s
->nb_globals
== s
->nb_temps
);
1506 tcg_debug_assert(s
->nb_globals
< TCG_MAX_TEMPS
);
1508 ts
= tcg_temp_alloc(s
);
1509 ts
->kind
= TEMP_GLOBAL
;
1514 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1515 TCGReg reg
, const char *name
)
1519 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
1521 ts
= tcg_global_alloc(s
);
1522 ts
->base_type
= type
;
1524 ts
->kind
= TEMP_FIXED
;
1527 tcg_regset_set_reg(s
->reserved_regs
, reg
);
1532 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
)
1534 s
->frame_start
= start
;
1535 s
->frame_end
= start
+ size
;
1537 = tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, reg
, "_frame");
1540 TCGTemp
*tcg_global_mem_new_internal(TCGType type
, TCGv_ptr base
,
1541 intptr_t offset
, const char *name
)
1543 TCGContext
*s
= tcg_ctx
;
1544 TCGTemp
*base_ts
= tcgv_ptr_temp(base
);
1545 TCGTemp
*ts
= tcg_global_alloc(s
);
1546 int indirect_reg
= 0;
1548 switch (base_ts
->kind
) {
1552 /* We do not support double-indirect registers. */
1553 tcg_debug_assert(!base_ts
->indirect_reg
);
1554 base_ts
->indirect_base
= 1;
1555 s
->nb_indirects
+= (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
1560 g_assert_not_reached();
1563 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1564 TCGTemp
*ts2
= tcg_global_alloc(s
);
1567 ts
->base_type
= TCG_TYPE_I64
;
1568 ts
->type
= TCG_TYPE_I32
;
1569 ts
->indirect_reg
= indirect_reg
;
1570 ts
->mem_allocated
= 1;
1571 ts
->mem_base
= base_ts
;
1572 ts
->mem_offset
= offset
;
1573 pstrcpy(buf
, sizeof(buf
), name
);
1574 pstrcat(buf
, sizeof(buf
), "_0");
1575 ts
->name
= strdup(buf
);
1577 tcg_debug_assert(ts2
== ts
+ 1);
1578 ts2
->base_type
= TCG_TYPE_I64
;
1579 ts2
->type
= TCG_TYPE_I32
;
1580 ts2
->indirect_reg
= indirect_reg
;
1581 ts2
->mem_allocated
= 1;
1582 ts2
->mem_base
= base_ts
;
1583 ts2
->mem_offset
= offset
+ 4;
1584 ts2
->temp_subindex
= 1;
1585 pstrcpy(buf
, sizeof(buf
), name
);
1586 pstrcat(buf
, sizeof(buf
), "_1");
1587 ts2
->name
= strdup(buf
);
1589 ts
->base_type
= type
;
1591 ts
->indirect_reg
= indirect_reg
;
1592 ts
->mem_allocated
= 1;
1593 ts
->mem_base
= base_ts
;
1594 ts
->mem_offset
= offset
;
1600 TCGTemp
*tcg_temp_new_internal(TCGType type
, TCGTempKind kind
)
1602 TCGContext
*s
= tcg_ctx
;
1606 if (kind
== TEMP_EBB
) {
1607 int idx
= find_first_bit(s
->free_temps
[type
].l
, TCG_MAX_TEMPS
);
1609 if (idx
< TCG_MAX_TEMPS
) {
1610 /* There is already an available temp with the right type. */
1611 clear_bit(idx
, s
->free_temps
[type
].l
);
1613 ts
= &s
->temps
[idx
];
1614 ts
->temp_allocated
= 1;
1615 tcg_debug_assert(ts
->base_type
== type
);
1616 tcg_debug_assert(ts
->kind
== kind
);
1620 tcg_debug_assert(kind
== TEMP_TB
);
1631 n
= 64 / TCG_TARGET_REG_BITS
;
1634 n
= 128 / TCG_TARGET_REG_BITS
;
1637 g_assert_not_reached();
1640 ts
= tcg_temp_alloc(s
);
1641 ts
->base_type
= type
;
1642 ts
->temp_allocated
= 1;
1648 ts
->type
= TCG_TYPE_REG
;
1650 for (int i
= 1; i
< n
; ++i
) {
1651 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1653 tcg_debug_assert(ts2
== ts
+ i
);
1654 ts2
->base_type
= type
;
1655 ts2
->type
= TCG_TYPE_REG
;
1656 ts2
->temp_allocated
= 1;
1657 ts2
->temp_subindex
= i
;
1664 TCGv_vec
tcg_temp_new_vec(TCGType type
)
1668 #ifdef CONFIG_DEBUG_TCG
1671 assert(TCG_TARGET_HAS_v64
);
1674 assert(TCG_TARGET_HAS_v128
);
1677 assert(TCG_TARGET_HAS_v256
);
1680 g_assert_not_reached();
1684 t
= tcg_temp_new_internal(type
, TEMP_EBB
);
1685 return temp_tcgv_vec(t
);
1688 /* Create a new temp of the same type as an existing temp. */
1689 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
)
1691 TCGTemp
*t
= tcgv_vec_temp(match
);
1693 tcg_debug_assert(t
->temp_allocated
!= 0);
1695 t
= tcg_temp_new_internal(t
->base_type
, TEMP_EBB
);
1696 return temp_tcgv_vec(t
);
1699 void tcg_temp_free_internal(TCGTemp
*ts
)
1701 TCGContext
*s
= tcg_ctx
;
1706 /* Silently ignore free. */
1709 tcg_debug_assert(ts
->temp_allocated
!= 0);
1710 ts
->temp_allocated
= 0;
1711 set_bit(temp_idx(ts
), s
->free_temps
[ts
->base_type
].l
);
1714 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */
1715 g_assert_not_reached();
1719 TCGTemp
*tcg_constant_internal(TCGType type
, int64_t val
)
1721 TCGContext
*s
= tcg_ctx
;
1722 GHashTable
*h
= s
->const_table
[type
];
1726 h
= g_hash_table_new(g_int64_hash
, g_int64_equal
);
1727 s
->const_table
[type
] = h
;
1730 ts
= g_hash_table_lookup(h
, &val
);
1734 ts
= tcg_temp_alloc(s
);
1736 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1737 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1739 tcg_debug_assert(ts2
== ts
+ 1);
1741 ts
->base_type
= TCG_TYPE_I64
;
1742 ts
->type
= TCG_TYPE_I32
;
1743 ts
->kind
= TEMP_CONST
;
1744 ts
->temp_allocated
= 1;
1746 ts2
->base_type
= TCG_TYPE_I64
;
1747 ts2
->type
= TCG_TYPE_I32
;
1748 ts2
->kind
= TEMP_CONST
;
1749 ts2
->temp_allocated
= 1;
1750 ts2
->temp_subindex
= 1;
1753 * Retain the full value of the 64-bit constant in the low
1754 * part, so that the hash table works. Actual uses will
1755 * truncate the value to the low part.
1757 ts
[HOST_BIG_ENDIAN
].val
= val
;
1758 ts
[!HOST_BIG_ENDIAN
].val
= val
>> 32;
1759 val_ptr
= &ts
[HOST_BIG_ENDIAN
].val
;
1761 ts
->base_type
= type
;
1763 ts
->kind
= TEMP_CONST
;
1764 ts
->temp_allocated
= 1;
1768 g_hash_table_insert(h
, val_ptr
, ts
);
1774 TCGv_vec
tcg_constant_vec(TCGType type
, unsigned vece
, int64_t val
)
1776 val
= dup_const(vece
, val
);
1777 return temp_tcgv_vec(tcg_constant_internal(type
, val
));
1780 TCGv_vec
tcg_constant_vec_matching(TCGv_vec match
, unsigned vece
, int64_t val
)
1782 TCGTemp
*t
= tcgv_vec_temp(match
);
1784 tcg_debug_assert(t
->temp_allocated
!= 0);
1785 return tcg_constant_vec(t
->base_type
, vece
, val
);
1788 /* Return true if OP may appear in the opcode stream.
1789 Test the runtime variable that controls each opcode. */
1790 bool tcg_op_supported(TCGOpcode op
)
1793 = TCG_TARGET_HAS_v64
| TCG_TARGET_HAS_v128
| TCG_TARGET_HAS_v256
;
1796 case INDEX_op_discard
:
1797 case INDEX_op_set_label
:
1801 case INDEX_op_insn_start
:
1802 case INDEX_op_exit_tb
:
1803 case INDEX_op_goto_tb
:
1804 case INDEX_op_goto_ptr
:
1805 case INDEX_op_qemu_ld_i32
:
1806 case INDEX_op_qemu_st_i32
:
1807 case INDEX_op_qemu_ld_i64
:
1808 case INDEX_op_qemu_st_i64
:
1811 case INDEX_op_qemu_st8_i32
:
1812 return TCG_TARGET_HAS_qemu_st8_i32
;
1814 case INDEX_op_qemu_ld_i128
:
1815 case INDEX_op_qemu_st_i128
:
1816 return TCG_TARGET_HAS_qemu_ldst_i128
;
1818 case INDEX_op_mov_i32
:
1819 case INDEX_op_setcond_i32
:
1820 case INDEX_op_brcond_i32
:
1821 case INDEX_op_ld8u_i32
:
1822 case INDEX_op_ld8s_i32
:
1823 case INDEX_op_ld16u_i32
:
1824 case INDEX_op_ld16s_i32
:
1825 case INDEX_op_ld_i32
:
1826 case INDEX_op_st8_i32
:
1827 case INDEX_op_st16_i32
:
1828 case INDEX_op_st_i32
:
1829 case INDEX_op_add_i32
:
1830 case INDEX_op_sub_i32
:
1831 case INDEX_op_mul_i32
:
1832 case INDEX_op_and_i32
:
1833 case INDEX_op_or_i32
:
1834 case INDEX_op_xor_i32
:
1835 case INDEX_op_shl_i32
:
1836 case INDEX_op_shr_i32
:
1837 case INDEX_op_sar_i32
:
1840 case INDEX_op_movcond_i32
:
1841 return TCG_TARGET_HAS_movcond_i32
;
1842 case INDEX_op_div_i32
:
1843 case INDEX_op_divu_i32
:
1844 return TCG_TARGET_HAS_div_i32
;
1845 case INDEX_op_rem_i32
:
1846 case INDEX_op_remu_i32
:
1847 return TCG_TARGET_HAS_rem_i32
;
1848 case INDEX_op_div2_i32
:
1849 case INDEX_op_divu2_i32
:
1850 return TCG_TARGET_HAS_div2_i32
;
1851 case INDEX_op_rotl_i32
:
1852 case INDEX_op_rotr_i32
:
1853 return TCG_TARGET_HAS_rot_i32
;
1854 case INDEX_op_deposit_i32
:
1855 return TCG_TARGET_HAS_deposit_i32
;
1856 case INDEX_op_extract_i32
:
1857 return TCG_TARGET_HAS_extract_i32
;
1858 case INDEX_op_sextract_i32
:
1859 return TCG_TARGET_HAS_sextract_i32
;
1860 case INDEX_op_extract2_i32
:
1861 return TCG_TARGET_HAS_extract2_i32
;
1862 case INDEX_op_add2_i32
:
1863 return TCG_TARGET_HAS_add2_i32
;
1864 case INDEX_op_sub2_i32
:
1865 return TCG_TARGET_HAS_sub2_i32
;
1866 case INDEX_op_mulu2_i32
:
1867 return TCG_TARGET_HAS_mulu2_i32
;
1868 case INDEX_op_muls2_i32
:
1869 return TCG_TARGET_HAS_muls2_i32
;
1870 case INDEX_op_muluh_i32
:
1871 return TCG_TARGET_HAS_muluh_i32
;
1872 case INDEX_op_mulsh_i32
:
1873 return TCG_TARGET_HAS_mulsh_i32
;
1874 case INDEX_op_ext8s_i32
:
1875 return TCG_TARGET_HAS_ext8s_i32
;
1876 case INDEX_op_ext16s_i32
:
1877 return TCG_TARGET_HAS_ext16s_i32
;
1878 case INDEX_op_ext8u_i32
:
1879 return TCG_TARGET_HAS_ext8u_i32
;
1880 case INDEX_op_ext16u_i32
:
1881 return TCG_TARGET_HAS_ext16u_i32
;
1882 case INDEX_op_bswap16_i32
:
1883 return TCG_TARGET_HAS_bswap16_i32
;
1884 case INDEX_op_bswap32_i32
:
1885 return TCG_TARGET_HAS_bswap32_i32
;
1886 case INDEX_op_not_i32
:
1887 return TCG_TARGET_HAS_not_i32
;
1888 case INDEX_op_neg_i32
:
1889 return TCG_TARGET_HAS_neg_i32
;
1890 case INDEX_op_andc_i32
:
1891 return TCG_TARGET_HAS_andc_i32
;
1892 case INDEX_op_orc_i32
:
1893 return TCG_TARGET_HAS_orc_i32
;
1894 case INDEX_op_eqv_i32
:
1895 return TCG_TARGET_HAS_eqv_i32
;
1896 case INDEX_op_nand_i32
:
1897 return TCG_TARGET_HAS_nand_i32
;
1898 case INDEX_op_nor_i32
:
1899 return TCG_TARGET_HAS_nor_i32
;
1900 case INDEX_op_clz_i32
:
1901 return TCG_TARGET_HAS_clz_i32
;
1902 case INDEX_op_ctz_i32
:
1903 return TCG_TARGET_HAS_ctz_i32
;
1904 case INDEX_op_ctpop_i32
:
1905 return TCG_TARGET_HAS_ctpop_i32
;
1907 case INDEX_op_brcond2_i32
:
1908 case INDEX_op_setcond2_i32
:
1909 return TCG_TARGET_REG_BITS
== 32;
1911 case INDEX_op_mov_i64
:
1912 case INDEX_op_setcond_i64
:
1913 case INDEX_op_brcond_i64
:
1914 case INDEX_op_ld8u_i64
:
1915 case INDEX_op_ld8s_i64
:
1916 case INDEX_op_ld16u_i64
:
1917 case INDEX_op_ld16s_i64
:
1918 case INDEX_op_ld32u_i64
:
1919 case INDEX_op_ld32s_i64
:
1920 case INDEX_op_ld_i64
:
1921 case INDEX_op_st8_i64
:
1922 case INDEX_op_st16_i64
:
1923 case INDEX_op_st32_i64
:
1924 case INDEX_op_st_i64
:
1925 case INDEX_op_add_i64
:
1926 case INDEX_op_sub_i64
:
1927 case INDEX_op_mul_i64
:
1928 case INDEX_op_and_i64
:
1929 case INDEX_op_or_i64
:
1930 case INDEX_op_xor_i64
:
1931 case INDEX_op_shl_i64
:
1932 case INDEX_op_shr_i64
:
1933 case INDEX_op_sar_i64
:
1934 case INDEX_op_ext_i32_i64
:
1935 case INDEX_op_extu_i32_i64
:
1936 return TCG_TARGET_REG_BITS
== 64;
1938 case INDEX_op_movcond_i64
:
1939 return TCG_TARGET_HAS_movcond_i64
;
1940 case INDEX_op_div_i64
:
1941 case INDEX_op_divu_i64
:
1942 return TCG_TARGET_HAS_div_i64
;
1943 case INDEX_op_rem_i64
:
1944 case INDEX_op_remu_i64
:
1945 return TCG_TARGET_HAS_rem_i64
;
1946 case INDEX_op_div2_i64
:
1947 case INDEX_op_divu2_i64
:
1948 return TCG_TARGET_HAS_div2_i64
;
1949 case INDEX_op_rotl_i64
:
1950 case INDEX_op_rotr_i64
:
1951 return TCG_TARGET_HAS_rot_i64
;
1952 case INDEX_op_deposit_i64
:
1953 return TCG_TARGET_HAS_deposit_i64
;
1954 case INDEX_op_extract_i64
:
1955 return TCG_TARGET_HAS_extract_i64
;
1956 case INDEX_op_sextract_i64
:
1957 return TCG_TARGET_HAS_sextract_i64
;
1958 case INDEX_op_extract2_i64
:
1959 return TCG_TARGET_HAS_extract2_i64
;
1960 case INDEX_op_extrl_i64_i32
:
1961 return TCG_TARGET_HAS_extrl_i64_i32
;
1962 case INDEX_op_extrh_i64_i32
:
1963 return TCG_TARGET_HAS_extrh_i64_i32
;
1964 case INDEX_op_ext8s_i64
:
1965 return TCG_TARGET_HAS_ext8s_i64
;
1966 case INDEX_op_ext16s_i64
:
1967 return TCG_TARGET_HAS_ext16s_i64
;
1968 case INDEX_op_ext32s_i64
:
1969 return TCG_TARGET_HAS_ext32s_i64
;
1970 case INDEX_op_ext8u_i64
:
1971 return TCG_TARGET_HAS_ext8u_i64
;
1972 case INDEX_op_ext16u_i64
:
1973 return TCG_TARGET_HAS_ext16u_i64
;
1974 case INDEX_op_ext32u_i64
:
1975 return TCG_TARGET_HAS_ext32u_i64
;
1976 case INDEX_op_bswap16_i64
:
1977 return TCG_TARGET_HAS_bswap16_i64
;
1978 case INDEX_op_bswap32_i64
:
1979 return TCG_TARGET_HAS_bswap32_i64
;
1980 case INDEX_op_bswap64_i64
:
1981 return TCG_TARGET_HAS_bswap64_i64
;
1982 case INDEX_op_not_i64
:
1983 return TCG_TARGET_HAS_not_i64
;
1984 case INDEX_op_neg_i64
:
1985 return TCG_TARGET_HAS_neg_i64
;
1986 case INDEX_op_andc_i64
:
1987 return TCG_TARGET_HAS_andc_i64
;
1988 case INDEX_op_orc_i64
:
1989 return TCG_TARGET_HAS_orc_i64
;
1990 case INDEX_op_eqv_i64
:
1991 return TCG_TARGET_HAS_eqv_i64
;
1992 case INDEX_op_nand_i64
:
1993 return TCG_TARGET_HAS_nand_i64
;
1994 case INDEX_op_nor_i64
:
1995 return TCG_TARGET_HAS_nor_i64
;
1996 case INDEX_op_clz_i64
:
1997 return TCG_TARGET_HAS_clz_i64
;
1998 case INDEX_op_ctz_i64
:
1999 return TCG_TARGET_HAS_ctz_i64
;
2000 case INDEX_op_ctpop_i64
:
2001 return TCG_TARGET_HAS_ctpop_i64
;
2002 case INDEX_op_add2_i64
:
2003 return TCG_TARGET_HAS_add2_i64
;
2004 case INDEX_op_sub2_i64
:
2005 return TCG_TARGET_HAS_sub2_i64
;
2006 case INDEX_op_mulu2_i64
:
2007 return TCG_TARGET_HAS_mulu2_i64
;
2008 case INDEX_op_muls2_i64
:
2009 return TCG_TARGET_HAS_muls2_i64
;
2010 case INDEX_op_muluh_i64
:
2011 return TCG_TARGET_HAS_muluh_i64
;
2012 case INDEX_op_mulsh_i64
:
2013 return TCG_TARGET_HAS_mulsh_i64
;
2015 case INDEX_op_mov_vec
:
2016 case INDEX_op_dup_vec
:
2017 case INDEX_op_dupm_vec
:
2018 case INDEX_op_ld_vec
:
2019 case INDEX_op_st_vec
:
2020 case INDEX_op_add_vec
:
2021 case INDEX_op_sub_vec
:
2022 case INDEX_op_and_vec
:
2023 case INDEX_op_or_vec
:
2024 case INDEX_op_xor_vec
:
2025 case INDEX_op_cmp_vec
:
2027 case INDEX_op_dup2_vec
:
2028 return have_vec
&& TCG_TARGET_REG_BITS
== 32;
2029 case INDEX_op_not_vec
:
2030 return have_vec
&& TCG_TARGET_HAS_not_vec
;
2031 case INDEX_op_neg_vec
:
2032 return have_vec
&& TCG_TARGET_HAS_neg_vec
;
2033 case INDEX_op_abs_vec
:
2034 return have_vec
&& TCG_TARGET_HAS_abs_vec
;
2035 case INDEX_op_andc_vec
:
2036 return have_vec
&& TCG_TARGET_HAS_andc_vec
;
2037 case INDEX_op_orc_vec
:
2038 return have_vec
&& TCG_TARGET_HAS_orc_vec
;
2039 case INDEX_op_nand_vec
:
2040 return have_vec
&& TCG_TARGET_HAS_nand_vec
;
2041 case INDEX_op_nor_vec
:
2042 return have_vec
&& TCG_TARGET_HAS_nor_vec
;
2043 case INDEX_op_eqv_vec
:
2044 return have_vec
&& TCG_TARGET_HAS_eqv_vec
;
2045 case INDEX_op_mul_vec
:
2046 return have_vec
&& TCG_TARGET_HAS_mul_vec
;
2047 case INDEX_op_shli_vec
:
2048 case INDEX_op_shri_vec
:
2049 case INDEX_op_sari_vec
:
2050 return have_vec
&& TCG_TARGET_HAS_shi_vec
;
2051 case INDEX_op_shls_vec
:
2052 case INDEX_op_shrs_vec
:
2053 case INDEX_op_sars_vec
:
2054 return have_vec
&& TCG_TARGET_HAS_shs_vec
;
2055 case INDEX_op_shlv_vec
:
2056 case INDEX_op_shrv_vec
:
2057 case INDEX_op_sarv_vec
:
2058 return have_vec
&& TCG_TARGET_HAS_shv_vec
;
2059 case INDEX_op_rotli_vec
:
2060 return have_vec
&& TCG_TARGET_HAS_roti_vec
;
2061 case INDEX_op_rotls_vec
:
2062 return have_vec
&& TCG_TARGET_HAS_rots_vec
;
2063 case INDEX_op_rotlv_vec
:
2064 case INDEX_op_rotrv_vec
:
2065 return have_vec
&& TCG_TARGET_HAS_rotv_vec
;
2066 case INDEX_op_ssadd_vec
:
2067 case INDEX_op_usadd_vec
:
2068 case INDEX_op_sssub_vec
:
2069 case INDEX_op_ussub_vec
:
2070 return have_vec
&& TCG_TARGET_HAS_sat_vec
;
2071 case INDEX_op_smin_vec
:
2072 case INDEX_op_umin_vec
:
2073 case INDEX_op_smax_vec
:
2074 case INDEX_op_umax_vec
:
2075 return have_vec
&& TCG_TARGET_HAS_minmax_vec
;
2076 case INDEX_op_bitsel_vec
:
2077 return have_vec
&& TCG_TARGET_HAS_bitsel_vec
;
2078 case INDEX_op_cmpsel_vec
:
2079 return have_vec
&& TCG_TARGET_HAS_cmpsel_vec
;
2082 tcg_debug_assert(op
> INDEX_op_last_generic
&& op
< NB_OPS
);
2087 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
);
2089 void tcg_gen_callN(void *func
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
)
2091 const TCGHelperInfo
*info
;
2092 TCGv_i64 extend_free
[MAX_CALL_IARGS
];
2095 int i
, n
, pi
= 0, total_args
;
2097 info
= g_hash_table_lookup(helper_table
, (gpointer
)func
);
2098 total_args
= info
->nr_out
+ info
->nr_in
+ 2;
2099 op
= tcg_op_alloc(INDEX_op_call
, total_args
);
2101 #ifdef CONFIG_PLUGIN
2102 /* Flag helpers that may affect guest state */
2103 if (tcg_ctx
->plugin_insn
&&
2104 !(info
->flags
& TCG_CALL_PLUGIN
) &&
2105 !(info
->flags
& TCG_CALL_NO_SIDE_EFFECTS
)) {
2106 tcg_ctx
->plugin_insn
->calls_helpers
= true;
2110 TCGOP_CALLO(op
) = n
= info
->nr_out
;
2113 tcg_debug_assert(ret
== NULL
);
2116 tcg_debug_assert(ret
!= NULL
);
2117 op
->args
[pi
++] = temp_arg(ret
);
2121 tcg_debug_assert(ret
!= NULL
);
2122 tcg_debug_assert(ret
->base_type
== ret
->type
+ ctz32(n
));
2123 tcg_debug_assert(ret
->temp_subindex
== 0);
2124 for (i
= 0; i
< n
; ++i
) {
2125 op
->args
[pi
++] = temp_arg(ret
+ i
);
2129 g_assert_not_reached();
2132 TCGOP_CALLI(op
) = n
= info
->nr_in
;
2133 for (i
= 0; i
< n
; i
++) {
2134 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
2135 TCGTemp
*ts
= args
[loc
->arg_idx
] + loc
->tmp_subindex
;
2137 switch (loc
->kind
) {
2138 case TCG_CALL_ARG_NORMAL
:
2139 case TCG_CALL_ARG_BY_REF
:
2140 case TCG_CALL_ARG_BY_REF_N
:
2141 op
->args
[pi
++] = temp_arg(ts
);
2144 case TCG_CALL_ARG_EXTEND_U
:
2145 case TCG_CALL_ARG_EXTEND_S
:
2147 TCGv_i64 temp
= tcg_temp_ebb_new_i64();
2148 TCGv_i32 orig
= temp_tcgv_i32(ts
);
2150 if (loc
->kind
== TCG_CALL_ARG_EXTEND_S
) {
2151 tcg_gen_ext_i32_i64(temp
, orig
);
2153 tcg_gen_extu_i32_i64(temp
, orig
);
2155 op
->args
[pi
++] = tcgv_i64_arg(temp
);
2156 extend_free
[n_extend
++] = temp
;
2161 g_assert_not_reached();
2164 op
->args
[pi
++] = (uintptr_t)func
;
2165 op
->args
[pi
++] = (uintptr_t)info
;
2166 tcg_debug_assert(pi
== total_args
);
2168 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2170 tcg_debug_assert(n_extend
< ARRAY_SIZE(extend_free
));
2171 for (i
= 0; i
< n_extend
; ++i
) {
2172 tcg_temp_free_i64(extend_free
[i
]);
2176 static void tcg_reg_alloc_start(TCGContext
*s
)
2180 for (i
= 0, n
= s
->nb_temps
; i
< n
; i
++) {
2181 TCGTemp
*ts
= &s
->temps
[i
];
2182 TCGTempVal val
= TEMP_VAL_MEM
;
2186 val
= TEMP_VAL_CONST
;
2194 val
= TEMP_VAL_DEAD
;
2197 ts
->mem_allocated
= 0;
2200 g_assert_not_reached();
2205 memset(s
->reg_to_temp
, 0, sizeof(s
->reg_to_temp
));
2208 static char *tcg_get_arg_str_ptr(TCGContext
*s
, char *buf
, int buf_size
,
2211 int idx
= temp_idx(ts
);
2216 pstrcpy(buf
, buf_size
, ts
->name
);
2219 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
2222 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
2227 snprintf(buf
, buf_size
, "$0x%x", (int32_t)ts
->val
);
2229 #if TCG_TARGET_REG_BITS > 32
2231 snprintf(buf
, buf_size
, "$0x%" PRIx64
, ts
->val
);
2237 snprintf(buf
, buf_size
, "v%d$0x%" PRIx64
,
2238 64 << (ts
->type
- TCG_TYPE_V64
), ts
->val
);
2241 g_assert_not_reached();
2248 static char *tcg_get_arg_str(TCGContext
*s
, char *buf
,
2249 int buf_size
, TCGArg arg
)
2251 return tcg_get_arg_str_ptr(s
, buf
, buf_size
, arg_temp(arg
));
2254 static const char * const cond_name
[] =
2256 [TCG_COND_NEVER
] = "never",
2257 [TCG_COND_ALWAYS
] = "always",
2258 [TCG_COND_EQ
] = "eq",
2259 [TCG_COND_NE
] = "ne",
2260 [TCG_COND_LT
] = "lt",
2261 [TCG_COND_GE
] = "ge",
2262 [TCG_COND_LE
] = "le",
2263 [TCG_COND_GT
] = "gt",
2264 [TCG_COND_LTU
] = "ltu",
2265 [TCG_COND_GEU
] = "geu",
2266 [TCG_COND_LEU
] = "leu",
2267 [TCG_COND_GTU
] = "gtu"
2270 static const char * const ldst_name
[(MO_BSWAP
| MO_SSIZE
) + 1] =
2284 [MO_128
+ MO_BE
] = "beo",
2285 [MO_128
+ MO_LE
] = "leo",
2288 static const char * const alignment_name
[(MO_AMASK
>> MO_ASHIFT
) + 1] = {
2289 [MO_UNALN
>> MO_ASHIFT
] = "un+",
2290 [MO_ALIGN
>> MO_ASHIFT
] = "al+",
2291 [MO_ALIGN_2
>> MO_ASHIFT
] = "al2+",
2292 [MO_ALIGN_4
>> MO_ASHIFT
] = "al4+",
2293 [MO_ALIGN_8
>> MO_ASHIFT
] = "al8+",
2294 [MO_ALIGN_16
>> MO_ASHIFT
] = "al16+",
2295 [MO_ALIGN_32
>> MO_ASHIFT
] = "al32+",
2296 [MO_ALIGN_64
>> MO_ASHIFT
] = "al64+",
2299 static const char * const atom_name
[(MO_ATOM_MASK
>> MO_ATOM_SHIFT
) + 1] = {
2300 [MO_ATOM_IFALIGN
>> MO_ATOM_SHIFT
] = "",
2301 [MO_ATOM_IFALIGN_PAIR
>> MO_ATOM_SHIFT
] = "pair+",
2302 [MO_ATOM_WITHIN16
>> MO_ATOM_SHIFT
] = "w16+",
2303 [MO_ATOM_WITHIN16_PAIR
>> MO_ATOM_SHIFT
] = "w16p+",
2304 [MO_ATOM_SUBALIGN
>> MO_ATOM_SHIFT
] = "sub+",
2305 [MO_ATOM_NONE
>> MO_ATOM_SHIFT
] = "noat+",
2308 static const char bswap_flag_name
[][6] = {
2309 [TCG_BSWAP_IZ
] = "iz",
2310 [TCG_BSWAP_OZ
] = "oz",
2311 [TCG_BSWAP_OS
] = "os",
2312 [TCG_BSWAP_IZ
| TCG_BSWAP_OZ
] = "iz,oz",
2313 [TCG_BSWAP_IZ
| TCG_BSWAP_OS
] = "iz,os",
2316 static inline bool tcg_regset_single(TCGRegSet d
)
2318 return (d
& (d
- 1)) == 0;
2321 static inline TCGReg
tcg_regset_first(TCGRegSet d
)
2323 if (TCG_TARGET_NB_REGS
<= 32) {
2330 /* Return only the number of characters output -- no error return. */
2331 #define ne_fprintf(...) \
2332 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; })
2334 static void tcg_dump_ops(TCGContext
*s
, FILE *f
, bool have_prefs
)
2339 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
2340 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
2341 const TCGOpDef
*def
;
2346 def
= &tcg_op_defs
[c
];
2348 if (c
== INDEX_op_insn_start
) {
2350 col
+= ne_fprintf(f
, "\n ----");
2352 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
2354 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2355 a
= deposit64(op
->args
[i
* 2], 32, 32, op
->args
[i
* 2 + 1]);
2359 col
+= ne_fprintf(f
, " " TARGET_FMT_lx
, a
);
2361 } else if (c
== INDEX_op_call
) {
2362 const TCGHelperInfo
*info
= tcg_call_info(op
);
2363 void *func
= tcg_call_func(op
);
2365 /* variable number of arguments */
2366 nb_oargs
= TCGOP_CALLO(op
);
2367 nb_iargs
= TCGOP_CALLI(op
);
2368 nb_cargs
= def
->nb_cargs
;
2370 col
+= ne_fprintf(f
, " %s ", def
->name
);
2373 * Print the function name from TCGHelperInfo, if available.
2374 * Note that plugins have a template function for the info,
2375 * but the actual function pointer comes from the plugin.
2377 if (func
== info
->func
) {
2378 col
+= ne_fprintf(f
, "%s", info
->name
);
2380 col
+= ne_fprintf(f
, "plugin(%p)", func
);
2383 col
+= ne_fprintf(f
, ",$0x%x,$%d", info
->flags
, nb_oargs
);
2384 for (i
= 0; i
< nb_oargs
; i
++) {
2385 col
+= ne_fprintf(f
, ",%s", tcg_get_arg_str(s
, buf
, sizeof(buf
),
2388 for (i
= 0; i
< nb_iargs
; i
++) {
2389 TCGArg arg
= op
->args
[nb_oargs
+ i
];
2390 const char *t
= tcg_get_arg_str(s
, buf
, sizeof(buf
), arg
);
2391 col
+= ne_fprintf(f
, ",%s", t
);
2394 col
+= ne_fprintf(f
, " %s ", def
->name
);
2396 nb_oargs
= def
->nb_oargs
;
2397 nb_iargs
= def
->nb_iargs
;
2398 nb_cargs
= def
->nb_cargs
;
2400 if (def
->flags
& TCG_OPF_VECTOR
) {
2401 col
+= ne_fprintf(f
, "v%d,e%d,", 64 << TCGOP_VECL(op
),
2402 8 << TCGOP_VECE(op
));
2406 for (i
= 0; i
< nb_oargs
; i
++) {
2407 const char *sep
= k
? "," : "";
2408 col
+= ne_fprintf(f
, "%s%s", sep
,
2409 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2412 for (i
= 0; i
< nb_iargs
; i
++) {
2413 const char *sep
= k
? "," : "";
2414 col
+= ne_fprintf(f
, "%s%s", sep
,
2415 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2419 case INDEX_op_brcond_i32
:
2420 case INDEX_op_setcond_i32
:
2421 case INDEX_op_movcond_i32
:
2422 case INDEX_op_brcond2_i32
:
2423 case INDEX_op_setcond2_i32
:
2424 case INDEX_op_brcond_i64
:
2425 case INDEX_op_setcond_i64
:
2426 case INDEX_op_movcond_i64
:
2427 case INDEX_op_cmp_vec
:
2428 case INDEX_op_cmpsel_vec
:
2429 if (op
->args
[k
] < ARRAY_SIZE(cond_name
)
2430 && cond_name
[op
->args
[k
]]) {
2431 col
+= ne_fprintf(f
, ",%s", cond_name
[op
->args
[k
++]]);
2433 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, op
->args
[k
++]);
2437 case INDEX_op_qemu_ld_i32
:
2438 case INDEX_op_qemu_st_i32
:
2439 case INDEX_op_qemu_st8_i32
:
2440 case INDEX_op_qemu_ld_i64
:
2441 case INDEX_op_qemu_st_i64
:
2442 case INDEX_op_qemu_ld_i128
:
2443 case INDEX_op_qemu_st_i128
:
2445 const char *s_al
, *s_op
, *s_at
;
2446 MemOpIdx oi
= op
->args
[k
++];
2447 MemOp op
= get_memop(oi
);
2448 unsigned ix
= get_mmuidx(oi
);
2450 s_al
= alignment_name
[(op
& MO_AMASK
) >> MO_ASHIFT
];
2451 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
2452 s_at
= atom_name
[(op
& MO_ATOM_MASK
) >> MO_ATOM_SHIFT
];
2453 op
&= ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
| MO_ATOM_MASK
);
2455 /* If all fields are accounted for, print symbolically. */
2456 if (!op
&& s_al
&& s_op
&& s_at
) {
2457 col
+= ne_fprintf(f
, ",%s%s%s,%u",
2458 s_at
, s_al
, s_op
, ix
);
2461 col
+= ne_fprintf(f
, ",$0x%x,%u", op
, ix
);
2466 case INDEX_op_bswap16_i32
:
2467 case INDEX_op_bswap16_i64
:
2468 case INDEX_op_bswap32_i32
:
2469 case INDEX_op_bswap32_i64
:
2470 case INDEX_op_bswap64_i64
:
2472 TCGArg flags
= op
->args
[k
];
2473 const char *name
= NULL
;
2475 if (flags
< ARRAY_SIZE(bswap_flag_name
)) {
2476 name
= bswap_flag_name
[flags
];
2479 col
+= ne_fprintf(f
, ",%s", name
);
2481 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, flags
);
2491 case INDEX_op_set_label
:
2493 case INDEX_op_brcond_i32
:
2494 case INDEX_op_brcond_i64
:
2495 case INDEX_op_brcond2_i32
:
2496 col
+= ne_fprintf(f
, "%s$L%d", k
? "," : "",
2497 arg_label(op
->args
[k
])->id
);
2502 TCGBar membar
= op
->args
[k
];
2503 const char *b_op
, *m_op
;
2505 switch (membar
& TCG_BAR_SC
) {
2519 g_assert_not_reached();
2522 switch (membar
& TCG_MO_ALL
) {
2538 case TCG_MO_LD_LD
| TCG_MO_LD_ST
:
2541 case TCG_MO_LD_LD
| TCG_MO_ST_LD
:
2544 case TCG_MO_LD_LD
| TCG_MO_ST_ST
:
2547 case TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2550 case TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2553 case TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2556 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2559 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2562 case TCG_MO_LD_LD
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2565 case TCG_MO_LD_ST
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2572 g_assert_not_reached();
2575 col
+= ne_fprintf(f
, "%s%s:%s", (k
? "," : ""), b_op
, m_op
);
2582 for (; i
< nb_cargs
; i
++, k
++) {
2583 col
+= ne_fprintf(f
, "%s$0x%" TCG_PRIlx
, k
? "," : "",
2588 if (have_prefs
|| op
->life
) {
2589 for (; col
< 40; ++col
) {
2595 unsigned life
= op
->life
;
2597 if (life
& (SYNC_ARG
* 3)) {
2598 ne_fprintf(f
, " sync:");
2599 for (i
= 0; i
< 2; ++i
) {
2600 if (life
& (SYNC_ARG
<< i
)) {
2601 ne_fprintf(f
, " %d", i
);
2607 ne_fprintf(f
, " dead:");
2608 for (i
= 0; life
; ++i
, life
>>= 1) {
2610 ne_fprintf(f
, " %d", i
);
2617 for (i
= 0; i
< nb_oargs
; ++i
) {
2618 TCGRegSet set
= output_pref(op
, i
);
2621 ne_fprintf(f
, " pref=");
2626 ne_fprintf(f
, "none");
2627 } else if (set
== MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS
)) {
2628 ne_fprintf(f
, "all");
2629 #ifdef CONFIG_DEBUG_TCG
2630 } else if (tcg_regset_single(set
)) {
2631 TCGReg reg
= tcg_regset_first(set
);
2632 ne_fprintf(f
, "%s", tcg_target_reg_names
[reg
]);
2634 } else if (TCG_TARGET_NB_REGS
<= 32) {
2635 ne_fprintf(f
, "0x%x", (uint32_t)set
);
2637 ne_fprintf(f
, "0x%" PRIx64
, (uint64_t)set
);
2646 /* we give more priority to constraints with less registers */
2647 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
2649 const TCGArgConstraint
*arg_ct
= &def
->args_ct
[k
];
2650 int n
= ctpop64(arg_ct
->regs
);
2653 * Sort constraints of a single register first, which includes output
2654 * aliases (which must exactly match the input already allocated).
2656 if (n
== 1 || arg_ct
->oalias
) {
2661 * Sort register pairs next, first then second immediately after.
2662 * Arbitrarily sort multiple pairs by the index of the first reg;
2663 * there shouldn't be many pairs.
2665 switch (arg_ct
->pair
) {
2670 return (arg_ct
->pair_index
+ 1) * 2 - 1;
2673 /* Finally, sort by decreasing register count. */
2678 /* sort from highest priority to lowest */
2679 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
2682 TCGArgConstraint
*a
= def
->args_ct
;
2684 for (i
= 0; i
< n
; i
++) {
2685 a
[start
+ i
].sort_index
= start
+ i
;
2690 for (i
= 0; i
< n
- 1; i
++) {
2691 for (j
= i
+ 1; j
< n
; j
++) {
2692 int p1
= get_constraint_priority(def
, a
[start
+ i
].sort_index
);
2693 int p2
= get_constraint_priority(def
, a
[start
+ j
].sort_index
);
2695 int tmp
= a
[start
+ i
].sort_index
;
2696 a
[start
+ i
].sort_index
= a
[start
+ j
].sort_index
;
2697 a
[start
+ j
].sort_index
= tmp
;
2703 static void process_op_defs(TCGContext
*s
)
2707 for (op
= 0; op
< NB_OPS
; op
++) {
2708 TCGOpDef
*def
= &tcg_op_defs
[op
];
2709 const TCGTargetOpDef
*tdefs
;
2710 bool saw_alias_pair
= false;
2711 int i
, o
, i2
, o2
, nb_args
;
2713 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2717 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
2723 * Macro magic should make it impossible, but double-check that
2724 * the array index is in range. Since the signness of an enum
2725 * is implementation defined, force the result to unsigned.
2727 unsigned con_set
= tcg_target_op_def(op
);
2728 tcg_debug_assert(con_set
< ARRAY_SIZE(constraint_sets
));
2729 tdefs
= &constraint_sets
[con_set
];
2731 for (i
= 0; i
< nb_args
; i
++) {
2732 const char *ct_str
= tdefs
->args_ct_str
[i
];
2733 bool input_p
= i
>= def
->nb_oargs
;
2735 /* Incomplete TCGTargetOpDef entry. */
2736 tcg_debug_assert(ct_str
!= NULL
);
2741 tcg_debug_assert(input_p
);
2742 tcg_debug_assert(o
< def
->nb_oargs
);
2743 tcg_debug_assert(def
->args_ct
[o
].regs
!= 0);
2744 tcg_debug_assert(!def
->args_ct
[o
].oalias
);
2745 def
->args_ct
[i
] = def
->args_ct
[o
];
2746 /* The output sets oalias. */
2747 def
->args_ct
[o
].oalias
= 1;
2748 def
->args_ct
[o
].alias_index
= i
;
2749 /* The input sets ialias. */
2750 def
->args_ct
[i
].ialias
= 1;
2751 def
->args_ct
[i
].alias_index
= o
;
2752 if (def
->args_ct
[i
].pair
) {
2753 saw_alias_pair
= true;
2755 tcg_debug_assert(ct_str
[1] == '\0');
2759 tcg_debug_assert(!input_p
);
2760 def
->args_ct
[i
].newreg
= true;
2764 case 'p': /* plus */
2765 /* Allocate to the register after the previous. */
2766 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2768 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2769 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2770 def
->args_ct
[i
] = (TCGArgConstraint
){
2773 .regs
= def
->args_ct
[o
].regs
<< 1,
2775 def
->args_ct
[o
].pair
= 1;
2776 def
->args_ct
[o
].pair_index
= i
;
2777 tcg_debug_assert(ct_str
[1] == '\0');
2780 case 'm': /* minus */
2781 /* Allocate to the register before the previous. */
2782 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2784 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2785 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2786 def
->args_ct
[i
] = (TCGArgConstraint
){
2789 .regs
= def
->args_ct
[o
].regs
>> 1,
2791 def
->args_ct
[o
].pair
= 2;
2792 def
->args_ct
[o
].pair_index
= i
;
2793 tcg_debug_assert(ct_str
[1] == '\0');
2800 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
2803 /* Include all of the target-specific constraints. */
2806 #define CONST(CASE, MASK) \
2807 case CASE: def->args_ct[i].ct |= MASK; break;
2808 #define REGS(CASE, MASK) \
2809 case CASE: def->args_ct[i].regs |= MASK; break;
2811 #include "tcg-target-con-str.h"
2820 /* Typo in TCGTargetOpDef constraint. */
2821 g_assert_not_reached();
2823 } while (*++ct_str
!= '\0');
2826 /* TCGTargetOpDef entry with too much information? */
2827 tcg_debug_assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
2830 * Fix up output pairs that are aliased with inputs.
2831 * When we created the alias, we copied pair from the output.
2832 * There are three cases:
2833 * (1a) Pairs of inputs alias pairs of outputs.
2834 * (1b) One input aliases the first of a pair of outputs.
2835 * (2) One input aliases the second of a pair of outputs.
2837 * Case 1a is handled by making sure that the pair_index'es are
2838 * properly updated so that they appear the same as a pair of inputs.
2840 * Case 1b is handled by setting the pair_index of the input to
2841 * itself, simply so it doesn't point to an unrelated argument.
2842 * Since we don't encounter the "second" during the input allocation
2843 * phase, nothing happens with the second half of the input pair.
2845 * Case 2 is handled by setting the second input to pair=3, the
2846 * first output to pair=3, and the pair_index'es to match.
2848 if (saw_alias_pair
) {
2849 for (i
= def
->nb_oargs
; i
< nb_args
; i
++) {
2851 * Since [0-9pm] must be alone in the constraint string,
2852 * the only way they can both be set is if the pair comes
2853 * from the output alias.
2855 if (!def
->args_ct
[i
].ialias
) {
2858 switch (def
->args_ct
[i
].pair
) {
2862 o
= def
->args_ct
[i
].alias_index
;
2863 o2
= def
->args_ct
[o
].pair_index
;
2864 tcg_debug_assert(def
->args_ct
[o
].pair
== 1);
2865 tcg_debug_assert(def
->args_ct
[o2
].pair
== 2);
2866 if (def
->args_ct
[o2
].oalias
) {
2868 i2
= def
->args_ct
[o2
].alias_index
;
2869 tcg_debug_assert(def
->args_ct
[i2
].pair
== 2);
2870 def
->args_ct
[i2
].pair_index
= i
;
2871 def
->args_ct
[i
].pair_index
= i2
;
2874 def
->args_ct
[i
].pair_index
= i
;
2878 o
= def
->args_ct
[i
].alias_index
;
2879 o2
= def
->args_ct
[o
].pair_index
;
2880 tcg_debug_assert(def
->args_ct
[o
].pair
== 2);
2881 tcg_debug_assert(def
->args_ct
[o2
].pair
== 1);
2882 if (def
->args_ct
[o2
].oalias
) {
2884 i2
= def
->args_ct
[o2
].alias_index
;
2885 tcg_debug_assert(def
->args_ct
[i2
].pair
== 1);
2886 def
->args_ct
[i2
].pair_index
= i
;
2887 def
->args_ct
[i
].pair_index
= i2
;
2890 def
->args_ct
[i
].pair
= 3;
2891 def
->args_ct
[o2
].pair
= 3;
2892 def
->args_ct
[i
].pair_index
= o2
;
2893 def
->args_ct
[o2
].pair_index
= i
;
2897 g_assert_not_reached();
2902 /* sort the constraints (XXX: this is just an heuristic) */
2903 sort_constraints(def
, 0, def
->nb_oargs
);
2904 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
2908 static void remove_label_use(TCGOp
*op
, int idx
)
2910 TCGLabel
*label
= arg_label(op
->args
[idx
]);
2913 QSIMPLEQ_FOREACH(use
, &label
->branches
, next
) {
2914 if (use
->op
== op
) {
2915 QSIMPLEQ_REMOVE(&label
->branches
, use
, TCGLabelUse
, next
);
2919 g_assert_not_reached();
2922 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
2926 remove_label_use(op
, 0);
2928 case INDEX_op_brcond_i32
:
2929 case INDEX_op_brcond_i64
:
2930 remove_label_use(op
, 3);
2932 case INDEX_op_brcond2_i32
:
2933 remove_label_use(op
, 5);
2939 QTAILQ_REMOVE(&s
->ops
, op
, link
);
2940 QTAILQ_INSERT_TAIL(&s
->free_ops
, op
, link
);
2943 #ifdef CONFIG_PROFILER
2944 qatomic_set(&s
->prof
.del_op_count
, s
->prof
.del_op_count
+ 1);
2948 void tcg_remove_ops_after(TCGOp
*op
)
2950 TCGContext
*s
= tcg_ctx
;
2953 TCGOp
*last
= tcg_last_op();
2957 tcg_op_remove(s
, last
);
2961 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
)
2963 TCGContext
*s
= tcg_ctx
;
2966 if (unlikely(!QTAILQ_EMPTY(&s
->free_ops
))) {
2967 QTAILQ_FOREACH(op
, &s
->free_ops
, link
) {
2968 if (nargs
<= op
->nargs
) {
2969 QTAILQ_REMOVE(&s
->free_ops
, op
, link
);
2976 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */
2977 nargs
= MAX(4, nargs
);
2978 op
= tcg_malloc(sizeof(TCGOp
) + sizeof(TCGArg
) * nargs
);
2981 memset(op
, 0, offsetof(TCGOp
, link
));
2985 /* Check for bitfield overflow. */
2986 tcg_debug_assert(op
->nargs
== nargs
);
2992 TCGOp
*tcg_emit_op(TCGOpcode opc
, unsigned nargs
)
2994 TCGOp
*op
= tcg_op_alloc(opc
, nargs
);
2995 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2999 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*old_op
,
3000 TCGOpcode opc
, unsigned nargs
)
3002 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
3003 QTAILQ_INSERT_BEFORE(old_op
, new_op
, link
);
3007 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*old_op
,
3008 TCGOpcode opc
, unsigned nargs
)
3010 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
3011 QTAILQ_INSERT_AFTER(&s
->ops
, old_op
, new_op
, link
);
3015 static void move_label_uses(TCGLabel
*to
, TCGLabel
*from
)
3019 QSIMPLEQ_FOREACH(u
, &from
->branches
, next
) {
3023 op
->args
[0] = label_arg(to
);
3025 case INDEX_op_brcond_i32
:
3026 case INDEX_op_brcond_i64
:
3027 op
->args
[3] = label_arg(to
);
3029 case INDEX_op_brcond2_i32
:
3030 op
->args
[5] = label_arg(to
);
3033 g_assert_not_reached();
3037 QSIMPLEQ_CONCAT(&to
->branches
, &from
->branches
);
3040 /* Reachable analysis : remove unreachable code. */
3041 static void __attribute__((noinline
))
3042 reachable_code_pass(TCGContext
*s
)
3044 TCGOp
*op
, *op_next
, *op_prev
;
3047 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3052 case INDEX_op_set_label
:
3053 label
= arg_label(op
->args
[0]);
3056 * Note that the first op in the TB is always a load,
3057 * so there is always something before a label.
3059 op_prev
= QTAILQ_PREV(op
, link
);
3062 * If we find two sequential labels, move all branches to
3063 * reference the second label and remove the first label.
3064 * Do this before branch to next optimization, so that the
3065 * middle label is out of the way.
3067 if (op_prev
->opc
== INDEX_op_set_label
) {
3068 move_label_uses(label
, arg_label(op_prev
->args
[0]));
3069 tcg_op_remove(s
, op_prev
);
3070 op_prev
= QTAILQ_PREV(op
, link
);
3074 * Optimization can fold conditional branches to unconditional.
3075 * If we find a label which is preceded by an unconditional
3076 * branch to next, remove the branch. We couldn't do this when
3077 * processing the branch because any dead code between the branch
3078 * and label had not yet been removed.
3080 if (op_prev
->opc
== INDEX_op_br
&&
3081 label
== arg_label(op_prev
->args
[0])) {
3082 tcg_op_remove(s
, op_prev
);
3083 /* Fall through means insns become live again. */
3087 if (QSIMPLEQ_EMPTY(&label
->branches
)) {
3089 * While there is an occasional backward branch, virtually
3090 * all branches generated by the translators are forward.
3091 * Which means that generally we will have already removed
3092 * all references to the label that will be, and there is
3093 * little to be gained by iterating.
3097 /* Once we see a label, insns become live again. */
3104 case INDEX_op_exit_tb
:
3105 case INDEX_op_goto_ptr
:
3106 /* Unconditional branches; everything following is dead. */
3111 /* Notice noreturn helper calls, raising exceptions. */
3112 if (tcg_call_flags(op
) & TCG_CALL_NO_RETURN
) {
3117 case INDEX_op_insn_start
:
3118 /* Never remove -- we need to keep these for unwind. */
3127 tcg_op_remove(s
, op
);
3135 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
3136 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
3138 /* For liveness_pass_1, the register preferences for a given temp. */
3139 static inline TCGRegSet
*la_temp_pref(TCGTemp
*ts
)
3141 return ts
->state_ptr
;
3144 /* For liveness_pass_1, reset the preferences for a given temp to the
3145 * maximal regset for its type.
3147 static inline void la_reset_pref(TCGTemp
*ts
)
3150 = (ts
->state
== TS_DEAD
? 0 : tcg_target_available_regs
[ts
->type
]);
3153 /* liveness analysis: end of function: all temps are dead, and globals
3154 should be in memory. */
3155 static void la_func_end(TCGContext
*s
, int ng
, int nt
)
3159 for (i
= 0; i
< ng
; ++i
) {
3160 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3161 la_reset_pref(&s
->temps
[i
]);
3163 for (i
= ng
; i
< nt
; ++i
) {
3164 s
->temps
[i
].state
= TS_DEAD
;
3165 la_reset_pref(&s
->temps
[i
]);
3169 /* liveness analysis: end of basic block: all temps are dead, globals
3170 and local temps should be in memory. */
3171 static void la_bb_end(TCGContext
*s
, int ng
, int nt
)
3175 for (i
= 0; i
< nt
; ++i
) {
3176 TCGTemp
*ts
= &s
->temps
[i
];
3183 state
= TS_DEAD
| TS_MEM
;
3190 g_assert_not_reached();
3197 /* liveness analysis: sync globals back to memory. */
3198 static void la_global_sync(TCGContext
*s
, int ng
)
3202 for (i
= 0; i
< ng
; ++i
) {
3203 int state
= s
->temps
[i
].state
;
3204 s
->temps
[i
].state
= state
| TS_MEM
;
3205 if (state
== TS_DEAD
) {
3206 /* If the global was previously dead, reset prefs. */
3207 la_reset_pref(&s
->temps
[i
]);
3213 * liveness analysis: conditional branch: all temps are dead unless
3214 * explicitly live-across-conditional-branch, globals and local temps
3217 static void la_bb_sync(TCGContext
*s
, int ng
, int nt
)
3219 la_global_sync(s
, ng
);
3221 for (int i
= ng
; i
< nt
; ++i
) {
3222 TCGTemp
*ts
= &s
->temps
[i
];
3228 ts
->state
= state
| TS_MEM
;
3229 if (state
!= TS_DEAD
) {
3237 g_assert_not_reached();
3239 la_reset_pref(&s
->temps
[i
]);
3243 /* liveness analysis: sync globals back to memory and kill. */
3244 static void la_global_kill(TCGContext
*s
, int ng
)
3248 for (i
= 0; i
< ng
; i
++) {
3249 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3250 la_reset_pref(&s
->temps
[i
]);
3254 /* liveness analysis: note live globals crossing calls. */
3255 static void la_cross_call(TCGContext
*s
, int nt
)
3257 TCGRegSet mask
= ~tcg_target_call_clobber_regs
;
3260 for (i
= 0; i
< nt
; i
++) {
3261 TCGTemp
*ts
= &s
->temps
[i
];
3262 if (!(ts
->state
& TS_DEAD
)) {
3263 TCGRegSet
*pset
= la_temp_pref(ts
);
3264 TCGRegSet set
= *pset
;
3267 /* If the combination is not possible, restart. */
3269 set
= tcg_target_available_regs
[ts
->type
] & mask
;
3277 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce
3278 * to TEMP_EBB, if possible.
3280 static void __attribute__((noinline
))
3281 liveness_pass_0(TCGContext
*s
)
3283 void * const multiple_ebb
= (void *)(uintptr_t)-1;
3284 int nb_temps
= s
->nb_temps
;
3287 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3288 s
->temps
[i
].state_ptr
= NULL
;
3292 * Represent each EBB by the op at which it begins. In the case of
3293 * the first EBB, this is the first op, otherwise it is a label.
3294 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use
3295 * within a single EBB, else MULTIPLE_EBB.
3297 ebb
= QTAILQ_FIRST(&s
->ops
);
3298 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
3299 const TCGOpDef
*def
;
3300 int nb_oargs
, nb_iargs
;
3303 case INDEX_op_set_label
:
3306 case INDEX_op_discard
:
3309 nb_oargs
= TCGOP_CALLO(op
);
3310 nb_iargs
= TCGOP_CALLI(op
);
3313 def
= &tcg_op_defs
[op
->opc
];
3314 nb_oargs
= def
->nb_oargs
;
3315 nb_iargs
= def
->nb_iargs
;
3319 for (int i
= 0; i
< nb_oargs
+ nb_iargs
; ++i
) {
3320 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
3322 if (ts
->kind
!= TEMP_TB
) {
3325 if (ts
->state_ptr
== NULL
) {
3326 ts
->state_ptr
= ebb
;
3327 } else if (ts
->state_ptr
!= ebb
) {
3328 ts
->state_ptr
= multiple_ebb
;
3334 * For TEMP_TB that turned out not to be used beyond one EBB,
3335 * reduce the liveness to TEMP_EBB.
3337 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3338 TCGTemp
*ts
= &s
->temps
[i
];
3339 if (ts
->kind
== TEMP_TB
&& ts
->state_ptr
!= multiple_ebb
) {
3340 ts
->kind
= TEMP_EBB
;
3345 /* Liveness analysis : update the opc_arg_life array to tell if a
3346 given input arguments is dead. Instructions updating dead
3347 temporaries are removed. */
3348 static void __attribute__((noinline
))
3349 liveness_pass_1(TCGContext
*s
)
3351 int nb_globals
= s
->nb_globals
;
3352 int nb_temps
= s
->nb_temps
;
3353 TCGOp
*op
, *op_prev
;
3357 prefs
= tcg_malloc(sizeof(TCGRegSet
) * nb_temps
);
3358 for (i
= 0; i
< nb_temps
; ++i
) {
3359 s
->temps
[i
].state_ptr
= prefs
+ i
;
3362 /* ??? Should be redundant with the exit_tb that ends the TB. */
3363 la_func_end(s
, nb_globals
, nb_temps
);
3365 QTAILQ_FOREACH_REVERSE_SAFE(op
, &s
->ops
, link
, op_prev
) {
3366 int nb_iargs
, nb_oargs
;
3367 TCGOpcode opc_new
, opc_new2
;
3369 TCGLifeData arg_life
= 0;
3371 TCGOpcode opc
= op
->opc
;
3372 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3377 const TCGHelperInfo
*info
= tcg_call_info(op
);
3378 int call_flags
= tcg_call_flags(op
);
3380 nb_oargs
= TCGOP_CALLO(op
);
3381 nb_iargs
= TCGOP_CALLI(op
);
3383 /* pure functions can be removed if their result is unused */
3384 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
3385 for (i
= 0; i
< nb_oargs
; i
++) {
3386 ts
= arg_temp(op
->args
[i
]);
3387 if (ts
->state
!= TS_DEAD
) {
3388 goto do_not_remove_call
;
3395 /* Output args are dead. */
3396 for (i
= 0; i
< nb_oargs
; i
++) {
3397 ts
= arg_temp(op
->args
[i
]);
3398 if (ts
->state
& TS_DEAD
) {
3399 arg_life
|= DEAD_ARG
<< i
;
3401 if (ts
->state
& TS_MEM
) {
3402 arg_life
|= SYNC_ARG
<< i
;
3404 ts
->state
= TS_DEAD
;
3408 /* Not used -- it will be tcg_target_call_oarg_reg(). */
3409 memset(op
->output_pref
, 0, sizeof(op
->output_pref
));
3411 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
3412 TCG_CALL_NO_READ_GLOBALS
))) {
3413 la_global_kill(s
, nb_globals
);
3414 } else if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
3415 la_global_sync(s
, nb_globals
);
3418 /* Record arguments that die in this helper. */
3419 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3420 ts
= arg_temp(op
->args
[i
]);
3421 if (ts
->state
& TS_DEAD
) {
3422 arg_life
|= DEAD_ARG
<< i
;
3426 /* For all live registers, remove call-clobbered prefs. */
3427 la_cross_call(s
, nb_temps
);
3430 * Input arguments are live for preceding opcodes.
3432 * For those arguments that die, and will be allocated in
3433 * registers, clear the register set for that arg, to be
3434 * filled in below. For args that will be on the stack,
3435 * reset to any available reg. Process arguments in reverse
3436 * order so that if a temp is used more than once, the stack
3437 * reset to max happens before the register reset to 0.
3439 for (i
= nb_iargs
- 1; i
>= 0; i
--) {
3440 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3441 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3443 if (ts
->state
& TS_DEAD
) {
3444 switch (loc
->kind
) {
3445 case TCG_CALL_ARG_NORMAL
:
3446 case TCG_CALL_ARG_EXTEND_U
:
3447 case TCG_CALL_ARG_EXTEND_S
:
3448 if (arg_slot_reg_p(loc
->arg_slot
)) {
3449 *la_temp_pref(ts
) = 0;
3455 tcg_target_available_regs
[ts
->type
];
3458 ts
->state
&= ~TS_DEAD
;
3463 * For each input argument, add its input register to prefs.
3464 * If a temp is used once, this produces a single set bit;
3465 * if a temp is used multiple times, this produces a set.
3467 for (i
= 0; i
< nb_iargs
; i
++) {
3468 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3469 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3471 switch (loc
->kind
) {
3472 case TCG_CALL_ARG_NORMAL
:
3473 case TCG_CALL_ARG_EXTEND_U
:
3474 case TCG_CALL_ARG_EXTEND_S
:
3475 if (arg_slot_reg_p(loc
->arg_slot
)) {
3476 tcg_regset_set_reg(*la_temp_pref(ts
),
3477 tcg_target_call_iarg_regs
[loc
->arg_slot
]);
3486 case INDEX_op_insn_start
:
3488 case INDEX_op_discard
:
3489 /* mark the temporary as dead */
3490 ts
= arg_temp(op
->args
[0]);
3491 ts
->state
= TS_DEAD
;
3495 case INDEX_op_add2_i32
:
3496 opc_new
= INDEX_op_add_i32
;
3498 case INDEX_op_sub2_i32
:
3499 opc_new
= INDEX_op_sub_i32
;
3501 case INDEX_op_add2_i64
:
3502 opc_new
= INDEX_op_add_i64
;
3504 case INDEX_op_sub2_i64
:
3505 opc_new
= INDEX_op_sub_i64
;
3509 /* Test if the high part of the operation is dead, but not
3510 the low part. The result can be optimized to a simple
3511 add or sub. This happens often for x86_64 guest when the
3512 cpu mode is set to 32 bit. */
3513 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3514 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3517 /* Replace the opcode and adjust the args in place,
3518 leaving 3 unused args at the end. */
3519 op
->opc
= opc
= opc_new
;
3520 op
->args
[1] = op
->args
[2];
3521 op
->args
[2] = op
->args
[4];
3522 /* Fall through and mark the single-word operation live. */
3528 case INDEX_op_mulu2_i32
:
3529 opc_new
= INDEX_op_mul_i32
;
3530 opc_new2
= INDEX_op_muluh_i32
;
3531 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
3533 case INDEX_op_muls2_i32
:
3534 opc_new
= INDEX_op_mul_i32
;
3535 opc_new2
= INDEX_op_mulsh_i32
;
3536 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
3538 case INDEX_op_mulu2_i64
:
3539 opc_new
= INDEX_op_mul_i64
;
3540 opc_new2
= INDEX_op_muluh_i64
;
3541 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
3543 case INDEX_op_muls2_i64
:
3544 opc_new
= INDEX_op_mul_i64
;
3545 opc_new2
= INDEX_op_mulsh_i64
;
3546 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
3551 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3552 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3553 /* Both parts of the operation are dead. */
3556 /* The high part of the operation is dead; generate the low. */
3557 op
->opc
= opc
= opc_new
;
3558 op
->args
[1] = op
->args
[2];
3559 op
->args
[2] = op
->args
[3];
3560 } else if (arg_temp(op
->args
[0])->state
== TS_DEAD
&& have_opc_new2
) {
3561 /* The low part of the operation is dead; generate the high. */
3562 op
->opc
= opc
= opc_new2
;
3563 op
->args
[0] = op
->args
[1];
3564 op
->args
[1] = op
->args
[2];
3565 op
->args
[2] = op
->args
[3];
3569 /* Mark the single-word operation live. */
3574 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
3575 nb_iargs
= def
->nb_iargs
;
3576 nb_oargs
= def
->nb_oargs
;
3578 /* Test if the operation can be removed because all
3579 its outputs are dead. We assume that nb_oargs == 0
3580 implies side effects */
3581 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
3582 for (i
= 0; i
< nb_oargs
; i
++) {
3583 if (arg_temp(op
->args
[i
])->state
!= TS_DEAD
) {
3592 tcg_op_remove(s
, op
);
3596 for (i
= 0; i
< nb_oargs
; i
++) {
3597 ts
= arg_temp(op
->args
[i
]);
3599 /* Remember the preference of the uses that followed. */
3600 if (i
< ARRAY_SIZE(op
->output_pref
)) {
3601 op
->output_pref
[i
] = *la_temp_pref(ts
);
3604 /* Output args are dead. */
3605 if (ts
->state
& TS_DEAD
) {
3606 arg_life
|= DEAD_ARG
<< i
;
3608 if (ts
->state
& TS_MEM
) {
3609 arg_life
|= SYNC_ARG
<< i
;
3611 ts
->state
= TS_DEAD
;
3615 /* If end of basic block, update. */
3616 if (def
->flags
& TCG_OPF_BB_EXIT
) {
3617 la_func_end(s
, nb_globals
, nb_temps
);
3618 } else if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3619 la_bb_sync(s
, nb_globals
, nb_temps
);
3620 } else if (def
->flags
& TCG_OPF_BB_END
) {
3621 la_bb_end(s
, nb_globals
, nb_temps
);
3622 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3623 la_global_sync(s
, nb_globals
);
3624 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
3625 la_cross_call(s
, nb_temps
);
3629 /* Record arguments that die in this opcode. */
3630 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3631 ts
= arg_temp(op
->args
[i
]);
3632 if (ts
->state
& TS_DEAD
) {
3633 arg_life
|= DEAD_ARG
<< i
;
3637 /* Input arguments are live for preceding opcodes. */
3638 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3639 ts
= arg_temp(op
->args
[i
]);
3640 if (ts
->state
& TS_DEAD
) {
3641 /* For operands that were dead, initially allow
3642 all regs for the type. */
3643 *la_temp_pref(ts
) = tcg_target_available_regs
[ts
->type
];
3644 ts
->state
&= ~TS_DEAD
;
3648 /* Incorporate constraints for this operand. */
3650 case INDEX_op_mov_i32
:
3651 case INDEX_op_mov_i64
:
3652 /* Note that these are TCG_OPF_NOT_PRESENT and do not
3653 have proper constraints. That said, special case
3654 moves to propagate preferences backward. */
3655 if (IS_DEAD_ARG(1)) {
3656 *la_temp_pref(arg_temp(op
->args
[0]))
3657 = *la_temp_pref(arg_temp(op
->args
[1]));
3662 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3663 const TCGArgConstraint
*ct
= &def
->args_ct
[i
];
3664 TCGRegSet set
, *pset
;
3666 ts
= arg_temp(op
->args
[i
]);
3667 pset
= la_temp_pref(ts
);
3672 set
&= output_pref(op
, ct
->alias_index
);
3674 /* If the combination is not possible, restart. */
3684 op
->life
= arg_life
;
3688 /* Liveness analysis: Convert indirect regs to direct temporaries. */
3689 static bool __attribute__((noinline
))
3690 liveness_pass_2(TCGContext
*s
)
3692 int nb_globals
= s
->nb_globals
;
3694 bool changes
= false;
3695 TCGOp
*op
, *op_next
;
3697 /* Create a temporary for each indirect global. */
3698 for (i
= 0; i
< nb_globals
; ++i
) {
3699 TCGTemp
*its
= &s
->temps
[i
];
3700 if (its
->indirect_reg
) {
3701 TCGTemp
*dts
= tcg_temp_alloc(s
);
3702 dts
->type
= its
->type
;
3703 dts
->base_type
= its
->base_type
;
3704 dts
->temp_subindex
= its
->temp_subindex
;
3705 dts
->kind
= TEMP_EBB
;
3706 its
->state_ptr
= dts
;
3708 its
->state_ptr
= NULL
;
3710 /* All globals begin dead. */
3711 its
->state
= TS_DEAD
;
3713 for (nb_temps
= s
->nb_temps
; i
< nb_temps
; ++i
) {
3714 TCGTemp
*its
= &s
->temps
[i
];
3715 its
->state_ptr
= NULL
;
3716 its
->state
= TS_DEAD
;
3719 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3720 TCGOpcode opc
= op
->opc
;
3721 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3722 TCGLifeData arg_life
= op
->life
;
3723 int nb_iargs
, nb_oargs
, call_flags
;
3724 TCGTemp
*arg_ts
, *dir_ts
;
3726 if (opc
== INDEX_op_call
) {
3727 nb_oargs
= TCGOP_CALLO(op
);
3728 nb_iargs
= TCGOP_CALLI(op
);
3729 call_flags
= tcg_call_flags(op
);
3731 nb_iargs
= def
->nb_iargs
;
3732 nb_oargs
= def
->nb_oargs
;
3734 /* Set flags similar to how calls require. */
3735 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3736 /* Like reading globals: sync_globals */
3737 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3738 } else if (def
->flags
& TCG_OPF_BB_END
) {
3739 /* Like writing globals: save_globals */
3741 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3742 /* Like reading globals: sync_globals */
3743 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3745 /* No effect on globals. */
3746 call_flags
= (TCG_CALL_NO_READ_GLOBALS
|
3747 TCG_CALL_NO_WRITE_GLOBALS
);
3751 /* Make sure that input arguments are available. */
3752 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3753 arg_ts
= arg_temp(op
->args
[i
]);
3754 dir_ts
= arg_ts
->state_ptr
;
3755 if (dir_ts
&& arg_ts
->state
== TS_DEAD
) {
3756 TCGOpcode lopc
= (arg_ts
->type
== TCG_TYPE_I32
3759 TCGOp
*lop
= tcg_op_insert_before(s
, op
, lopc
, 3);
3761 lop
->args
[0] = temp_arg(dir_ts
);
3762 lop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3763 lop
->args
[2] = arg_ts
->mem_offset
;
3765 /* Loaded, but synced with memory. */
3766 arg_ts
->state
= TS_MEM
;
3770 /* Perform input replacement, and mark inputs that became dead.
3771 No action is required except keeping temp_state up to date
3772 so that we reload when needed. */
3773 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3774 arg_ts
= arg_temp(op
->args
[i
]);
3775 dir_ts
= arg_ts
->state_ptr
;
3777 op
->args
[i
] = temp_arg(dir_ts
);
3779 if (IS_DEAD_ARG(i
)) {
3780 arg_ts
->state
= TS_DEAD
;
3785 /* Liveness analysis should ensure that the following are
3786 all correct, for call sites and basic block end points. */
3787 if (call_flags
& TCG_CALL_NO_READ_GLOBALS
) {
3789 } else if (call_flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
3790 for (i
= 0; i
< nb_globals
; ++i
) {
3791 /* Liveness should see that globals are synced back,
3792 that is, either TS_DEAD or TS_MEM. */
3793 arg_ts
= &s
->temps
[i
];
3794 tcg_debug_assert(arg_ts
->state_ptr
== 0
3795 || arg_ts
->state
!= 0);
3798 for (i
= 0; i
< nb_globals
; ++i
) {
3799 /* Liveness should see that globals are saved back,
3800 that is, TS_DEAD, waiting to be reloaded. */
3801 arg_ts
= &s
->temps
[i
];
3802 tcg_debug_assert(arg_ts
->state_ptr
== 0
3803 || arg_ts
->state
== TS_DEAD
);
3807 /* Outputs become available. */
3808 if (opc
== INDEX_op_mov_i32
|| opc
== INDEX_op_mov_i64
) {
3809 arg_ts
= arg_temp(op
->args
[0]);
3810 dir_ts
= arg_ts
->state_ptr
;
3812 op
->args
[0] = temp_arg(dir_ts
);
3815 /* The output is now live and modified. */
3818 if (NEED_SYNC_ARG(0)) {
3819 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3822 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3823 TCGTemp
*out_ts
= dir_ts
;
3825 if (IS_DEAD_ARG(0)) {
3826 out_ts
= arg_temp(op
->args
[1]);
3827 arg_ts
->state
= TS_DEAD
;
3828 tcg_op_remove(s
, op
);
3830 arg_ts
->state
= TS_MEM
;
3833 sop
->args
[0] = temp_arg(out_ts
);
3834 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3835 sop
->args
[2] = arg_ts
->mem_offset
;
3837 tcg_debug_assert(!IS_DEAD_ARG(0));
3841 for (i
= 0; i
< nb_oargs
; i
++) {
3842 arg_ts
= arg_temp(op
->args
[i
]);
3843 dir_ts
= arg_ts
->state_ptr
;
3847 op
->args
[i
] = temp_arg(dir_ts
);
3850 /* The output is now live and modified. */
3853 /* Sync outputs upon their last write. */
3854 if (NEED_SYNC_ARG(i
)) {
3855 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3858 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3860 sop
->args
[0] = temp_arg(dir_ts
);
3861 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3862 sop
->args
[2] = arg_ts
->mem_offset
;
3864 arg_ts
->state
= TS_MEM
;
3866 /* Drop outputs that are dead. */
3867 if (IS_DEAD_ARG(i
)) {
3868 arg_ts
->state
= TS_DEAD
;
3877 static void temp_allocate_frame(TCGContext
*s
, TCGTemp
*ts
)
3882 /* When allocating an object, look at the full type. */
3883 size
= tcg_type_size(ts
->base_type
);
3884 switch (ts
->base_type
) {
3896 * Note that we do not require aligned storage for V256,
3897 * and that we provide alignment for I128 to match V128,
3898 * even if that's above what the host ABI requires.
3903 g_assert_not_reached();
3907 * Assume the stack is sufficiently aligned.
3908 * This affects e.g. ARM NEON, where we have 8 byte stack alignment
3909 * and do not require 16 byte vector alignment. This seems slightly
3910 * easier than fully parameterizing the above switch statement.
3912 align
= MIN(TCG_TARGET_STACK_ALIGN
, align
);
3913 off
= ROUND_UP(s
->current_frame_offset
, align
);
3915 /* If we've exhausted the stack frame, restart with a smaller TB. */
3916 if (off
+ size
> s
->frame_end
) {
3917 tcg_raise_tb_overflow(s
);
3919 s
->current_frame_offset
= off
+ size
;
3920 #if defined(__sparc__)
3921 off
+= TCG_TARGET_STACK_BIAS
;
3924 /* If the object was subdivided, assign memory to all the parts. */
3925 if (ts
->base_type
!= ts
->type
) {
3926 int part_size
= tcg_type_size(ts
->type
);
3927 int part_count
= size
/ part_size
;
3930 * Each part is allocated sequentially in tcg_temp_new_internal.
3931 * Jump back to the first part by subtracting the current index.
3933 ts
-= ts
->temp_subindex
;
3934 for (int i
= 0; i
< part_count
; ++i
) {
3935 ts
[i
].mem_offset
= off
+ i
* part_size
;
3936 ts
[i
].mem_base
= s
->frame_temp
;
3937 ts
[i
].mem_allocated
= 1;
3940 ts
->mem_offset
= off
;
3941 ts
->mem_base
= s
->frame_temp
;
3942 ts
->mem_allocated
= 1;
3946 /* Assign @reg to @ts, and update reg_to_temp[]. */
3947 static void set_temp_val_reg(TCGContext
*s
, TCGTemp
*ts
, TCGReg reg
)
3949 if (ts
->val_type
== TEMP_VAL_REG
) {
3950 TCGReg old
= ts
->reg
;
3951 tcg_debug_assert(s
->reg_to_temp
[old
] == ts
);
3955 s
->reg_to_temp
[old
] = NULL
;
3957 tcg_debug_assert(s
->reg_to_temp
[reg
] == NULL
);
3958 s
->reg_to_temp
[reg
] = ts
;
3959 ts
->val_type
= TEMP_VAL_REG
;
3963 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */
3964 static void set_temp_val_nonreg(TCGContext
*s
, TCGTemp
*ts
, TCGTempVal type
)
3966 tcg_debug_assert(type
!= TEMP_VAL_REG
);
3967 if (ts
->val_type
== TEMP_VAL_REG
) {
3968 TCGReg reg
= ts
->reg
;
3969 tcg_debug_assert(s
->reg_to_temp
[reg
] == ts
);
3970 s
->reg_to_temp
[reg
] = NULL
;
3972 ts
->val_type
= type
;
3975 static void temp_load(TCGContext
*, TCGTemp
*, TCGRegSet
, TCGRegSet
, TCGRegSet
);
3977 /* Mark a temporary as free or dead. If 'free_or_dead' is negative,
3978 mark it free; otherwise mark it dead. */
3979 static void temp_free_or_dead(TCGContext
*s
, TCGTemp
*ts
, int free_or_dead
)
3981 TCGTempVal new_type
;
3988 new_type
= TEMP_VAL_MEM
;
3991 new_type
= free_or_dead
< 0 ? TEMP_VAL_MEM
: TEMP_VAL_DEAD
;
3994 new_type
= TEMP_VAL_CONST
;
3997 g_assert_not_reached();
3999 set_temp_val_nonreg(s
, ts
, new_type
);
4002 /* Mark a temporary as dead. */
4003 static inline void temp_dead(TCGContext
*s
, TCGTemp
*ts
)
4005 temp_free_or_dead(s
, ts
, 1);
4008 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
4009 registers needs to be allocated to store a constant. If 'free_or_dead'
4010 is non-zero, subsequently release the temporary; if it is positive, the
4011 temp is dead; if it is negative, the temp is free. */
4012 static void temp_sync(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
,
4013 TCGRegSet preferred_regs
, int free_or_dead
)
4015 if (!temp_readonly(ts
) && !ts
->mem_coherent
) {
4016 if (!ts
->mem_allocated
) {
4017 temp_allocate_frame(s
, ts
);
4019 switch (ts
->val_type
) {
4020 case TEMP_VAL_CONST
:
4021 /* If we're going to free the temp immediately, then we won't
4022 require it later in a register, so attempt to store the
4023 constant to memory directly. */
4025 && tcg_out_sti(s
, ts
->type
, ts
->val
,
4026 ts
->mem_base
->reg
, ts
->mem_offset
)) {
4029 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4030 allocated_regs
, preferred_regs
);
4034 tcg_out_st(s
, ts
->type
, ts
->reg
,
4035 ts
->mem_base
->reg
, ts
->mem_offset
);
4043 g_assert_not_reached();
4045 ts
->mem_coherent
= 1;
4048 temp_free_or_dead(s
, ts
, free_or_dead
);
4052 /* free register 'reg' by spilling the corresponding temporary if necessary */
4053 static void tcg_reg_free(TCGContext
*s
, TCGReg reg
, TCGRegSet allocated_regs
)
4055 TCGTemp
*ts
= s
->reg_to_temp
[reg
];
4057 temp_sync(s
, ts
, allocated_regs
, 0, -1);
4063 * @required_regs: Set of registers in which we must allocate.
4064 * @allocated_regs: Set of registers which must be avoided.
4065 * @preferred_regs: Set of registers we should prefer.
4066 * @rev: True if we search the registers in "indirect" order.
4068 * The allocated register must be in @required_regs & ~@allocated_regs,
4069 * but if we can put it in @preferred_regs we may save a move later.
4071 static TCGReg
tcg_reg_alloc(TCGContext
*s
, TCGRegSet required_regs
,
4072 TCGRegSet allocated_regs
,
4073 TCGRegSet preferred_regs
, bool rev
)
4075 int i
, j
, f
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4076 TCGRegSet reg_ct
[2];
4079 reg_ct
[1] = required_regs
& ~allocated_regs
;
4080 tcg_debug_assert(reg_ct
[1] != 0);
4081 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4083 /* Skip the preferred_regs option if it cannot be satisfied,
4084 or if the preference made no difference. */
4085 f
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4087 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4089 /* Try free registers, preferences first. */
4090 for (j
= f
; j
< 2; j
++) {
4091 TCGRegSet set
= reg_ct
[j
];
4093 if (tcg_regset_single(set
)) {
4094 /* One register in the set. */
4095 TCGReg reg
= tcg_regset_first(set
);
4096 if (s
->reg_to_temp
[reg
] == NULL
) {
4100 for (i
= 0; i
< n
; i
++) {
4101 TCGReg reg
= order
[i
];
4102 if (s
->reg_to_temp
[reg
] == NULL
&&
4103 tcg_regset_test_reg(set
, reg
)) {
4110 /* We must spill something. */
4111 for (j
= f
; j
< 2; j
++) {
4112 TCGRegSet set
= reg_ct
[j
];
4114 if (tcg_regset_single(set
)) {
4115 /* One register in the set. */
4116 TCGReg reg
= tcg_regset_first(set
);
4117 tcg_reg_free(s
, reg
, allocated_regs
);
4120 for (i
= 0; i
< n
; i
++) {
4121 TCGReg reg
= order
[i
];
4122 if (tcg_regset_test_reg(set
, reg
)) {
4123 tcg_reg_free(s
, reg
, allocated_regs
);
4130 g_assert_not_reached();
4133 static TCGReg
tcg_reg_alloc_pair(TCGContext
*s
, TCGRegSet required_regs
,
4134 TCGRegSet allocated_regs
,
4135 TCGRegSet preferred_regs
, bool rev
)
4137 int i
, j
, k
, fmin
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4138 TCGRegSet reg_ct
[2];
4141 /* Ensure that if I is not in allocated_regs, I+1 is not either. */
4142 reg_ct
[1] = required_regs
& ~(allocated_regs
| (allocated_regs
>> 1));
4143 tcg_debug_assert(reg_ct
[1] != 0);
4144 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4146 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4149 * Skip the preferred_regs option if it cannot be satisfied,
4150 * or if the preference made no difference.
4152 k
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4155 * Minimize the number of flushes by looking for 2 free registers first,
4156 * then a single flush, then two flushes.
4158 for (fmin
= 2; fmin
>= 0; fmin
--) {
4159 for (j
= k
; j
< 2; j
++) {
4160 TCGRegSet set
= reg_ct
[j
];
4162 for (i
= 0; i
< n
; i
++) {
4163 TCGReg reg
= order
[i
];
4165 if (tcg_regset_test_reg(set
, reg
)) {
4166 int f
= !s
->reg_to_temp
[reg
] + !s
->reg_to_temp
[reg
+ 1];
4168 tcg_reg_free(s
, reg
, allocated_regs
);
4169 tcg_reg_free(s
, reg
+ 1, allocated_regs
);
4176 g_assert_not_reached();
4179 /* Make sure the temporary is in a register. If needed, allocate the register
4180 from DESIRED while avoiding ALLOCATED. */
4181 static void temp_load(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet desired_regs
,
4182 TCGRegSet allocated_regs
, TCGRegSet preferred_regs
)
4186 switch (ts
->val_type
) {
4189 case TEMP_VAL_CONST
:
4190 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4191 preferred_regs
, ts
->indirect_base
);
4192 if (ts
->type
<= TCG_TYPE_I64
) {
4193 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
4195 uint64_t val
= ts
->val
;
4199 * Find the minimal vector element that matches the constant.
4200 * The targets will, in general, have to do this search anyway,
4201 * do this generically.
4203 if (val
== dup_const(MO_8
, val
)) {
4205 } else if (val
== dup_const(MO_16
, val
)) {
4207 } else if (val
== dup_const(MO_32
, val
)) {
4211 tcg_out_dupi_vec(s
, ts
->type
, vece
, reg
, ts
->val
);
4213 ts
->mem_coherent
= 0;
4216 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4217 preferred_regs
, ts
->indirect_base
);
4218 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_base
->reg
, ts
->mem_offset
);
4219 ts
->mem_coherent
= 1;
4223 g_assert_not_reached();
4225 set_temp_val_reg(s
, ts
, reg
);
4228 /* Save a temporary to memory. 'allocated_regs' is used in case a
4229 temporary registers needs to be allocated to store a constant. */
4230 static void temp_save(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
)
4232 /* The liveness analysis already ensures that globals are back
4233 in memory. Keep an tcg_debug_assert for safety. */
4234 tcg_debug_assert(ts
->val_type
== TEMP_VAL_MEM
|| temp_readonly(ts
));
4237 /* save globals to their canonical location and assume they can be
4238 modified be the following code. 'allocated_regs' is used in case a
4239 temporary registers needs to be allocated to store a constant. */
4240 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4244 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4245 temp_save(s
, &s
->temps
[i
], allocated_regs
);
4249 /* sync globals to their canonical location and assume they can be
4250 read by the following code. 'allocated_regs' is used in case a
4251 temporary registers needs to be allocated to store a constant. */
4252 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4256 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4257 TCGTemp
*ts
= &s
->temps
[i
];
4258 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
4259 || ts
->kind
== TEMP_FIXED
4260 || ts
->mem_coherent
);
4264 /* at the end of a basic block, we assume all temporaries are dead and
4265 all globals are stored at their canonical location. */
4266 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
4270 for (i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4271 TCGTemp
*ts
= &s
->temps
[i
];
4275 temp_save(s
, ts
, allocated_regs
);
4278 /* The liveness analysis already ensures that temps are dead.
4279 Keep an tcg_debug_assert for safety. */
4280 tcg_debug_assert(ts
->val_type
== TEMP_VAL_DEAD
);
4283 /* Similarly, we should have freed any allocated register. */
4284 tcg_debug_assert(ts
->val_type
== TEMP_VAL_CONST
);
4287 g_assert_not_reached();
4291 save_globals(s
, allocated_regs
);
4295 * At a conditional branch, we assume all temporaries are dead unless
4296 * explicitly live-across-conditional-branch; all globals and local
4297 * temps are synced to their location.
4299 static void tcg_reg_alloc_cbranch(TCGContext
*s
, TCGRegSet allocated_regs
)
4301 sync_globals(s
, allocated_regs
);
4303 for (int i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4304 TCGTemp
*ts
= &s
->temps
[i
];
4306 * The liveness analysis already ensures that temps are dead.
4307 * Keep tcg_debug_asserts for safety.
4311 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
|| ts
->mem_coherent
);
4317 g_assert_not_reached();
4323 * Specialized code generation for INDEX_op_mov_* with a constant.
4325 static void tcg_reg_alloc_do_movi(TCGContext
*s
, TCGTemp
*ots
,
4326 tcg_target_ulong val
, TCGLifeData arg_life
,
4327 TCGRegSet preferred_regs
)
4329 /* ENV should not be modified. */
4330 tcg_debug_assert(!temp_readonly(ots
));
4332 /* The movi is not explicitly generated here. */
4333 set_temp_val_nonreg(s
, ots
, TEMP_VAL_CONST
);
4335 ots
->mem_coherent
= 0;
4336 if (NEED_SYNC_ARG(0)) {
4337 temp_sync(s
, ots
, s
->reserved_regs
, preferred_regs
, IS_DEAD_ARG(0));
4338 } else if (IS_DEAD_ARG(0)) {
4344 * Specialized code generation for INDEX_op_mov_*.
4346 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOp
*op
)
4348 const TCGLifeData arg_life
= op
->life
;
4349 TCGRegSet allocated_regs
, preferred_regs
;
4351 TCGType otype
, itype
;
4354 allocated_regs
= s
->reserved_regs
;
4355 preferred_regs
= output_pref(op
, 0);
4356 ots
= arg_temp(op
->args
[0]);
4357 ts
= arg_temp(op
->args
[1]);
4359 /* ENV should not be modified. */
4360 tcg_debug_assert(!temp_readonly(ots
));
4362 /* Note that otype != itype for no-op truncation. */
4366 if (ts
->val_type
== TEMP_VAL_CONST
) {
4367 /* propagate constant or generate sti */
4368 tcg_target_ulong val
= ts
->val
;
4369 if (IS_DEAD_ARG(1)) {
4372 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, preferred_regs
);
4376 /* If the source value is in memory we're going to be forced
4377 to have it in a register in order to perform the copy. Copy
4378 the SOURCE value into its own register first, that way we
4379 don't have to reload SOURCE the next time it is used. */
4380 if (ts
->val_type
== TEMP_VAL_MEM
) {
4381 temp_load(s
, ts
, tcg_target_available_regs
[itype
],
4382 allocated_regs
, preferred_regs
);
4384 tcg_debug_assert(ts
->val_type
== TEMP_VAL_REG
);
4387 if (IS_DEAD_ARG(0)) {
4388 /* mov to a non-saved dead register makes no sense (even with
4389 liveness analysis disabled). */
4390 tcg_debug_assert(NEED_SYNC_ARG(0));
4391 if (!ots
->mem_allocated
) {
4392 temp_allocate_frame(s
, ots
);
4394 tcg_out_st(s
, otype
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4395 if (IS_DEAD_ARG(1)) {
4402 if (IS_DEAD_ARG(1) && ts
->kind
!= TEMP_FIXED
) {
4404 * The mov can be suppressed. Kill input first, so that it
4405 * is unlinked from reg_to_temp, then set the output to the
4406 * reg that we saved from the input.
4411 if (ots
->val_type
== TEMP_VAL_REG
) {
4414 /* Make sure to not spill the input register during allocation. */
4415 oreg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
4416 allocated_regs
| ((TCGRegSet
)1 << ireg
),
4417 preferred_regs
, ots
->indirect_base
);
4419 if (!tcg_out_mov(s
, otype
, oreg
, ireg
)) {
4421 * Cross register class move not supported.
4422 * Store the source register into the destination slot
4423 * and leave the destination temp as TEMP_VAL_MEM.
4425 assert(!temp_readonly(ots
));
4426 if (!ts
->mem_allocated
) {
4427 temp_allocate_frame(s
, ots
);
4429 tcg_out_st(s
, ts
->type
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4430 set_temp_val_nonreg(s
, ts
, TEMP_VAL_MEM
);
4431 ots
->mem_coherent
= 1;
4435 set_temp_val_reg(s
, ots
, oreg
);
4436 ots
->mem_coherent
= 0;
4438 if (NEED_SYNC_ARG(0)) {
4439 temp_sync(s
, ots
, allocated_regs
, 0, 0);
4444 * Specialized code generation for INDEX_op_dup_vec.
4446 static void tcg_reg_alloc_dup(TCGContext
*s
, const TCGOp
*op
)
4448 const TCGLifeData arg_life
= op
->life
;
4449 TCGRegSet dup_out_regs
, dup_in_regs
;
4451 TCGType itype
, vtype
;
4456 ots
= arg_temp(op
->args
[0]);
4457 its
= arg_temp(op
->args
[1]);
4459 /* ENV should not be modified. */
4460 tcg_debug_assert(!temp_readonly(ots
));
4463 vece
= TCGOP_VECE(op
);
4464 vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4466 if (its
->val_type
== TEMP_VAL_CONST
) {
4467 /* Propagate constant via movi -> dupi. */
4468 tcg_target_ulong val
= its
->val
;
4469 if (IS_DEAD_ARG(1)) {
4472 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, output_pref(op
, 0));
4476 dup_out_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4477 dup_in_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[1].regs
;
4479 /* Allocate the output register now. */
4480 if (ots
->val_type
!= TEMP_VAL_REG
) {
4481 TCGRegSet allocated_regs
= s
->reserved_regs
;
4484 if (!IS_DEAD_ARG(1) && its
->val_type
== TEMP_VAL_REG
) {
4485 /* Make sure to not spill the input register. */
4486 tcg_regset_set_reg(allocated_regs
, its
->reg
);
4488 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4489 output_pref(op
, 0), ots
->indirect_base
);
4490 set_temp_val_reg(s
, ots
, oreg
);
4493 switch (its
->val_type
) {
4496 * The dup constriaints must be broad, covering all possible VECE.
4497 * However, tcg_op_dup_vec() gets to see the VECE and we allow it
4498 * to fail, indicating that extra moves are required for that case.
4500 if (tcg_regset_test_reg(dup_in_regs
, its
->reg
)) {
4501 if (tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, its
->reg
)) {
4504 /* Try again from memory or a vector input register. */
4506 if (!its
->mem_coherent
) {
4508 * The input register is not synced, and so an extra store
4509 * would be required to use memory. Attempt an integer-vector
4510 * register move first. We do not have a TCGRegSet for this.
4512 if (tcg_out_mov(s
, itype
, ots
->reg
, its
->reg
)) {
4515 /* Sync the temp back to its slot and load from there. */
4516 temp_sync(s
, its
, s
->reserved_regs
, 0, 0);
4522 if (HOST_BIG_ENDIAN
) {
4523 lowpart_ofs
= tcg_type_size(itype
) - (1 << vece
);
4525 if (tcg_out_dupm_vec(s
, vtype
, vece
, ots
->reg
, its
->mem_base
->reg
,
4526 its
->mem_offset
+ lowpart_ofs
)) {
4529 /* Load the input into the destination vector register. */
4530 tcg_out_ld(s
, itype
, ots
->reg
, its
->mem_base
->reg
, its
->mem_offset
);
4534 g_assert_not_reached();
4537 /* We now have a vector input register, so dup must succeed. */
4538 ok
= tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, ots
->reg
);
4539 tcg_debug_assert(ok
);
4542 ots
->mem_coherent
= 0;
4543 if (IS_DEAD_ARG(1)) {
4546 if (NEED_SYNC_ARG(0)) {
4547 temp_sync(s
, ots
, s
->reserved_regs
, 0, 0);
4549 if (IS_DEAD_ARG(0)) {
4554 static void tcg_reg_alloc_op(TCGContext
*s
, const TCGOp
*op
)
4556 const TCGLifeData arg_life
= op
->life
;
4557 const TCGOpDef
* const def
= &tcg_op_defs
[op
->opc
];
4558 TCGRegSet i_allocated_regs
;
4559 TCGRegSet o_allocated_regs
;
4560 int i
, k
, nb_iargs
, nb_oargs
;
4563 const TCGArgConstraint
*arg_ct
;
4565 TCGArg new_args
[TCG_MAX_OP_ARGS
];
4566 int const_args
[TCG_MAX_OP_ARGS
];
4568 nb_oargs
= def
->nb_oargs
;
4569 nb_iargs
= def
->nb_iargs
;
4571 /* copy constants */
4572 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
4573 op
->args
+ nb_oargs
+ nb_iargs
,
4574 sizeof(TCGArg
) * def
->nb_cargs
);
4576 i_allocated_regs
= s
->reserved_regs
;
4577 o_allocated_regs
= s
->reserved_regs
;
4579 /* satisfy input constraints */
4580 for (k
= 0; k
< nb_iargs
; k
++) {
4581 TCGRegSet i_preferred_regs
, i_required_regs
;
4582 bool allocate_new_reg
, copyto_new_reg
;
4586 i
= def
->args_ct
[nb_oargs
+ k
].sort_index
;
4588 arg_ct
= &def
->args_ct
[i
];
4591 if (ts
->val_type
== TEMP_VAL_CONST
4592 && tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
->ct
)) {
4593 /* constant is OK for instruction */
4595 new_args
[i
] = ts
->val
;
4600 i_preferred_regs
= 0;
4601 i_required_regs
= arg_ct
->regs
;
4602 allocate_new_reg
= false;
4603 copyto_new_reg
= false;
4605 switch (arg_ct
->pair
) {
4606 case 0: /* not paired */
4607 if (arg_ct
->ialias
) {
4608 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4611 * If the input is readonly, then it cannot also be an
4612 * output and aliased to itself. If the input is not
4613 * dead after the instruction, we must allocate a new
4614 * register and move it.
4616 if (temp_readonly(ts
) || !IS_DEAD_ARG(i
)) {
4617 allocate_new_reg
= true;
4618 } else if (ts
->val_type
== TEMP_VAL_REG
) {
4620 * Check if the current register has already been
4621 * allocated for another input.
4624 tcg_regset_test_reg(i_allocated_regs
, reg
);
4627 if (!allocate_new_reg
) {
4628 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4631 allocate_new_reg
= !tcg_regset_test_reg(i_required_regs
, reg
);
4633 if (allocate_new_reg
) {
4635 * Allocate a new register matching the constraint
4636 * and move the temporary register into it.
4638 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4639 i_allocated_regs
, 0);
4640 reg
= tcg_reg_alloc(s
, i_required_regs
, i_allocated_regs
,
4641 i_preferred_regs
, ts
->indirect_base
);
4642 copyto_new_reg
= true;
4647 /* First of an input pair; if i1 == i2, the second is an output. */
4649 i2
= arg_ct
->pair_index
;
4650 ts2
= i1
!= i2
? arg_temp(op
->args
[i2
]) : NULL
;
4653 * It is easier to default to allocating a new pair
4654 * and to identify a few cases where it's not required.
4656 if (arg_ct
->ialias
) {
4657 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4658 if (IS_DEAD_ARG(i1
) &&
4660 !temp_readonly(ts
) &&
4661 ts
->val_type
== TEMP_VAL_REG
&&
4662 ts
->reg
< TCG_TARGET_NB_REGS
- 1 &&
4663 tcg_regset_test_reg(i_required_regs
, reg
) &&
4664 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4665 !tcg_regset_test_reg(i_allocated_regs
, reg
+ 1) &&
4667 ? ts2
->val_type
== TEMP_VAL_REG
&&
4668 ts2
->reg
== reg
+ 1 &&
4670 : s
->reg_to_temp
[reg
+ 1] == NULL
)) {
4674 /* Without aliasing, the pair must also be an input. */
4675 tcg_debug_assert(ts2
);
4676 if (ts
->val_type
== TEMP_VAL_REG
&&
4677 ts2
->val_type
== TEMP_VAL_REG
&&
4678 ts2
->reg
== reg
+ 1 &&
4679 tcg_regset_test_reg(i_required_regs
, reg
)) {
4683 reg
= tcg_reg_alloc_pair(s
, i_required_regs
, i_allocated_regs
,
4684 0, ts
->indirect_base
);
4687 case 2: /* pair second */
4688 reg
= new_args
[arg_ct
->pair_index
] + 1;
4691 case 3: /* ialias with second output, no first input */
4692 tcg_debug_assert(arg_ct
->ialias
);
4693 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4695 if (IS_DEAD_ARG(i
) &&
4696 !temp_readonly(ts
) &&
4697 ts
->val_type
== TEMP_VAL_REG
&&
4699 s
->reg_to_temp
[reg
- 1] == NULL
&&
4700 tcg_regset_test_reg(i_required_regs
, reg
) &&
4701 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4702 !tcg_regset_test_reg(i_allocated_regs
, reg
- 1)) {
4703 tcg_regset_set_reg(i_allocated_regs
, reg
- 1);
4706 reg
= tcg_reg_alloc_pair(s
, i_required_regs
>> 1,
4707 i_allocated_regs
, 0,
4709 tcg_regset_set_reg(i_allocated_regs
, reg
);
4715 * If an aliased input is not dead after the instruction,
4716 * we must allocate a new register and move it.
4718 if (arg_ct
->ialias
&& (!IS_DEAD_ARG(i
) || temp_readonly(ts
))) {
4719 TCGRegSet t_allocated_regs
= i_allocated_regs
;
4722 * Because of the alias, and the continued life, make sure
4723 * that the temp is somewhere *other* than the reg pair,
4724 * and we get a copy in reg.
4726 tcg_regset_set_reg(t_allocated_regs
, reg
);
4727 tcg_regset_set_reg(t_allocated_regs
, reg
+ 1);
4728 if (ts
->val_type
== TEMP_VAL_REG
&& ts
->reg
== reg
) {
4729 /* If ts was already in reg, copy it somewhere else. */
4733 tcg_debug_assert(ts
->kind
!= TEMP_FIXED
);
4734 nr
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
4735 t_allocated_regs
, 0, ts
->indirect_base
);
4736 ok
= tcg_out_mov(s
, ts
->type
, nr
, reg
);
4737 tcg_debug_assert(ok
);
4739 set_temp_val_reg(s
, ts
, nr
);
4741 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4742 t_allocated_regs
, 0);
4743 copyto_new_reg
= true;
4746 /* Preferably allocate to reg, otherwise copy. */
4747 i_required_regs
= (TCGRegSet
)1 << reg
;
4748 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4750 copyto_new_reg
= ts
->reg
!= reg
;
4755 g_assert_not_reached();
4758 if (copyto_new_reg
) {
4759 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4761 * Cross register class move not supported. Sync the
4762 * temp back to its slot and load from there.
4764 temp_sync(s
, ts
, i_allocated_regs
, 0, 0);
4765 tcg_out_ld(s
, ts
->type
, reg
,
4766 ts
->mem_base
->reg
, ts
->mem_offset
);
4771 tcg_regset_set_reg(i_allocated_regs
, reg
);
4774 /* mark dead temporaries and free the associated registers */
4775 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
4776 if (IS_DEAD_ARG(i
)) {
4777 temp_dead(s
, arg_temp(op
->args
[i
]));
4781 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
4782 tcg_reg_alloc_cbranch(s
, i_allocated_regs
);
4783 } else if (def
->flags
& TCG_OPF_BB_END
) {
4784 tcg_reg_alloc_bb_end(s
, i_allocated_regs
);
4786 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
4787 /* XXX: permit generic clobber register list ? */
4788 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
4789 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
4790 tcg_reg_free(s
, i
, i_allocated_regs
);
4794 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
4795 /* sync globals if the op has side effects and might trigger
4797 sync_globals(s
, i_allocated_regs
);
4800 /* satisfy the output constraints */
4801 for(k
= 0; k
< nb_oargs
; k
++) {
4802 i
= def
->args_ct
[k
].sort_index
;
4804 arg_ct
= &def
->args_ct
[i
];
4807 /* ENV should not be modified. */
4808 tcg_debug_assert(!temp_readonly(ts
));
4810 switch (arg_ct
->pair
) {
4811 case 0: /* not paired */
4812 if (arg_ct
->oalias
&& !const_args
[arg_ct
->alias_index
]) {
4813 reg
= new_args
[arg_ct
->alias_index
];
4814 } else if (arg_ct
->newreg
) {
4815 reg
= tcg_reg_alloc(s
, arg_ct
->regs
,
4816 i_allocated_regs
| o_allocated_regs
,
4817 output_pref(op
, k
), ts
->indirect_base
);
4819 reg
= tcg_reg_alloc(s
, arg_ct
->regs
, o_allocated_regs
,
4820 output_pref(op
, k
), ts
->indirect_base
);
4824 case 1: /* first of pair */
4825 tcg_debug_assert(!arg_ct
->newreg
);
4826 if (arg_ct
->oalias
) {
4827 reg
= new_args
[arg_ct
->alias_index
];
4830 reg
= tcg_reg_alloc_pair(s
, arg_ct
->regs
, o_allocated_regs
,
4831 output_pref(op
, k
), ts
->indirect_base
);
4834 case 2: /* second of pair */
4835 tcg_debug_assert(!arg_ct
->newreg
);
4836 if (arg_ct
->oalias
) {
4837 reg
= new_args
[arg_ct
->alias_index
];
4839 reg
= new_args
[arg_ct
->pair_index
] + 1;
4843 case 3: /* first of pair, aliasing with a second input */
4844 tcg_debug_assert(!arg_ct
->newreg
);
4845 reg
= new_args
[arg_ct
->pair_index
] - 1;
4849 g_assert_not_reached();
4851 tcg_regset_set_reg(o_allocated_regs
, reg
);
4852 set_temp_val_reg(s
, ts
, reg
);
4853 ts
->mem_coherent
= 0;
4858 /* emit instruction */
4860 case INDEX_op_ext8s_i32
:
4861 tcg_out_ext8s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
4863 case INDEX_op_ext8s_i64
:
4864 tcg_out_ext8s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
4866 case INDEX_op_ext8u_i32
:
4867 case INDEX_op_ext8u_i64
:
4868 tcg_out_ext8u(s
, new_args
[0], new_args
[1]);
4870 case INDEX_op_ext16s_i32
:
4871 tcg_out_ext16s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
4873 case INDEX_op_ext16s_i64
:
4874 tcg_out_ext16s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
4876 case INDEX_op_ext16u_i32
:
4877 case INDEX_op_ext16u_i64
:
4878 tcg_out_ext16u(s
, new_args
[0], new_args
[1]);
4880 case INDEX_op_ext32s_i64
:
4881 tcg_out_ext32s(s
, new_args
[0], new_args
[1]);
4883 case INDEX_op_ext32u_i64
:
4884 tcg_out_ext32u(s
, new_args
[0], new_args
[1]);
4886 case INDEX_op_ext_i32_i64
:
4887 tcg_out_exts_i32_i64(s
, new_args
[0], new_args
[1]);
4889 case INDEX_op_extu_i32_i64
:
4890 tcg_out_extu_i32_i64(s
, new_args
[0], new_args
[1]);
4892 case INDEX_op_extrl_i64_i32
:
4893 tcg_out_extrl_i64_i32(s
, new_args
[0], new_args
[1]);
4896 if (def
->flags
& TCG_OPF_VECTOR
) {
4897 tcg_out_vec_op(s
, op
->opc
, TCGOP_VECL(op
), TCGOP_VECE(op
),
4898 new_args
, const_args
);
4900 tcg_out_op(s
, op
->opc
, new_args
, const_args
);
4905 /* move the outputs in the correct register if needed */
4906 for(i
= 0; i
< nb_oargs
; i
++) {
4907 ts
= arg_temp(op
->args
[i
]);
4909 /* ENV should not be modified. */
4910 tcg_debug_assert(!temp_readonly(ts
));
4912 if (NEED_SYNC_ARG(i
)) {
4913 temp_sync(s
, ts
, o_allocated_regs
, 0, IS_DEAD_ARG(i
));
4914 } else if (IS_DEAD_ARG(i
)) {
4920 static bool tcg_reg_alloc_dup2(TCGContext
*s
, const TCGOp
*op
)
4922 const TCGLifeData arg_life
= op
->life
;
4923 TCGTemp
*ots
, *itsl
, *itsh
;
4924 TCGType vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4926 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
4927 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
4928 tcg_debug_assert(TCGOP_VECE(op
) == MO_64
);
4930 ots
= arg_temp(op
->args
[0]);
4931 itsl
= arg_temp(op
->args
[1]);
4932 itsh
= arg_temp(op
->args
[2]);
4934 /* ENV should not be modified. */
4935 tcg_debug_assert(!temp_readonly(ots
));
4937 /* Allocate the output register now. */
4938 if (ots
->val_type
!= TEMP_VAL_REG
) {
4939 TCGRegSet allocated_regs
= s
->reserved_regs
;
4940 TCGRegSet dup_out_regs
=
4941 tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4944 /* Make sure to not spill the input registers. */
4945 if (!IS_DEAD_ARG(1) && itsl
->val_type
== TEMP_VAL_REG
) {
4946 tcg_regset_set_reg(allocated_regs
, itsl
->reg
);
4948 if (!IS_DEAD_ARG(2) && itsh
->val_type
== TEMP_VAL_REG
) {
4949 tcg_regset_set_reg(allocated_regs
, itsh
->reg
);
4952 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4953 output_pref(op
, 0), ots
->indirect_base
);
4954 set_temp_val_reg(s
, ots
, oreg
);
4957 /* Promote dup2 of immediates to dupi_vec. */
4958 if (itsl
->val_type
== TEMP_VAL_CONST
&& itsh
->val_type
== TEMP_VAL_CONST
) {
4959 uint64_t val
= deposit64(itsl
->val
, 32, 32, itsh
->val
);
4962 if (val
== dup_const(MO_8
, val
)) {
4964 } else if (val
== dup_const(MO_16
, val
)) {
4966 } else if (val
== dup_const(MO_32
, val
)) {
4970 tcg_out_dupi_vec(s
, vtype
, vece
, ots
->reg
, val
);
4974 /* If the two inputs form one 64-bit value, try dupm_vec. */
4975 if (itsl
->temp_subindex
== HOST_BIG_ENDIAN
&&
4976 itsh
->temp_subindex
== !HOST_BIG_ENDIAN
&&
4977 itsl
== itsh
+ (HOST_BIG_ENDIAN
? 1 : -1)) {
4978 TCGTemp
*its
= itsl
- HOST_BIG_ENDIAN
;
4980 temp_sync(s
, its
+ 0, s
->reserved_regs
, 0, 0);
4981 temp_sync(s
, its
+ 1, s
->reserved_regs
, 0, 0);
4983 if (tcg_out_dupm_vec(s
, vtype
, MO_64
, ots
->reg
,
4984 its
->mem_base
->reg
, its
->mem_offset
)) {
4989 /* Fall back to generic expansion. */
4993 ots
->mem_coherent
= 0;
4994 if (IS_DEAD_ARG(1)) {
4997 if (IS_DEAD_ARG(2)) {
5000 if (NEED_SYNC_ARG(0)) {
5001 temp_sync(s
, ots
, s
->reserved_regs
, 0, IS_DEAD_ARG(0));
5002 } else if (IS_DEAD_ARG(0)) {
5008 static void load_arg_reg(TCGContext
*s
, TCGReg reg
, TCGTemp
*ts
,
5009 TCGRegSet allocated_regs
)
5011 if (ts
->val_type
== TEMP_VAL_REG
) {
5012 if (ts
->reg
!= reg
) {
5013 tcg_reg_free(s
, reg
, allocated_regs
);
5014 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
5016 * Cross register class move not supported. Sync the
5017 * temp back to its slot and load from there.
5019 temp_sync(s
, ts
, allocated_regs
, 0, 0);
5020 tcg_out_ld(s
, ts
->type
, reg
,
5021 ts
->mem_base
->reg
, ts
->mem_offset
);
5025 TCGRegSet arg_set
= 0;
5027 tcg_reg_free(s
, reg
, allocated_regs
);
5028 tcg_regset_set_reg(arg_set
, reg
);
5029 temp_load(s
, ts
, arg_set
, allocated_regs
, 0);
5033 static void load_arg_stk(TCGContext
*s
, unsigned arg_slot
, TCGTemp
*ts
,
5034 TCGRegSet allocated_regs
)
5037 * When the destination is on the stack, load up the temp and store.
5038 * If there are many call-saved registers, the temp might live to
5039 * see another use; otherwise it'll be discarded.
5041 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
], allocated_regs
, 0);
5042 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
,
5043 arg_slot_stk_ofs(arg_slot
));
5046 static void load_arg_normal(TCGContext
*s
, const TCGCallArgumentLoc
*l
,
5047 TCGTemp
*ts
, TCGRegSet
*allocated_regs
)
5049 if (arg_slot_reg_p(l
->arg_slot
)) {
5050 TCGReg reg
= tcg_target_call_iarg_regs
[l
->arg_slot
];
5051 load_arg_reg(s
, reg
, ts
, *allocated_regs
);
5052 tcg_regset_set_reg(*allocated_regs
, reg
);
5054 load_arg_stk(s
, l
->arg_slot
, ts
, *allocated_regs
);
5058 static void load_arg_ref(TCGContext
*s
, unsigned arg_slot
, TCGReg ref_base
,
5059 intptr_t ref_off
, TCGRegSet
*allocated_regs
)
5063 if (arg_slot_reg_p(arg_slot
)) {
5064 reg
= tcg_target_call_iarg_regs
[arg_slot
];
5065 tcg_reg_free(s
, reg
, *allocated_regs
);
5066 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
5067 tcg_regset_set_reg(*allocated_regs
, reg
);
5069 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[TCG_TYPE_PTR
],
5070 *allocated_regs
, 0, false);
5071 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
5072 tcg_out_st(s
, TCG_TYPE_PTR
, reg
, TCG_REG_CALL_STACK
,
5073 arg_slot_stk_ofs(arg_slot
));
5077 static void tcg_reg_alloc_call(TCGContext
*s
, TCGOp
*op
)
5079 const int nb_oargs
= TCGOP_CALLO(op
);
5080 const int nb_iargs
= TCGOP_CALLI(op
);
5081 const TCGLifeData arg_life
= op
->life
;
5082 const TCGHelperInfo
*info
= tcg_call_info(op
);
5083 TCGRegSet allocated_regs
= s
->reserved_regs
;
5087 * Move inputs into place in reverse order,
5088 * so that we place stacked arguments first.
5090 for (i
= nb_iargs
- 1; i
>= 0; --i
) {
5091 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
5092 TCGTemp
*ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
5094 switch (loc
->kind
) {
5095 case TCG_CALL_ARG_NORMAL
:
5096 case TCG_CALL_ARG_EXTEND_U
:
5097 case TCG_CALL_ARG_EXTEND_S
:
5098 load_arg_normal(s
, loc
, ts
, &allocated_regs
);
5100 case TCG_CALL_ARG_BY_REF
:
5101 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
5102 load_arg_ref(s
, loc
->arg_slot
, TCG_REG_CALL_STACK
,
5103 arg_slot_stk_ofs(loc
->ref_slot
),
5106 case TCG_CALL_ARG_BY_REF_N
:
5107 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
5110 g_assert_not_reached();
5114 /* Mark dead temporaries and free the associated registers. */
5115 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
5116 if (IS_DEAD_ARG(i
)) {
5117 temp_dead(s
, arg_temp(op
->args
[i
]));
5121 /* Clobber call registers. */
5122 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
5123 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
5124 tcg_reg_free(s
, i
, allocated_regs
);
5129 * Save globals if they might be written by the helper,
5130 * sync them if they might be read.
5132 if (info
->flags
& TCG_CALL_NO_READ_GLOBALS
) {
5134 } else if (info
->flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
5135 sync_globals(s
, allocated_regs
);
5137 save_globals(s
, allocated_regs
);
5141 * If the ABI passes a pointer to the returned struct as the first
5142 * argument, load that now. Pass a pointer to the output home slot.
5144 if (info
->out_kind
== TCG_CALL_RET_BY_REF
) {
5145 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5147 if (!ts
->mem_allocated
) {
5148 temp_allocate_frame(s
, ts
);
5150 load_arg_ref(s
, 0, ts
->mem_base
->reg
, ts
->mem_offset
, &allocated_regs
);
5153 tcg_out_call(s
, tcg_call_func(op
), info
);
5155 /* Assign output registers and emit moves if needed. */
5156 switch (info
->out_kind
) {
5157 case TCG_CALL_RET_NORMAL
:
5158 for (i
= 0; i
< nb_oargs
; i
++) {
5159 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5160 TCGReg reg
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, i
);
5162 /* ENV should not be modified. */
5163 tcg_debug_assert(!temp_readonly(ts
));
5165 set_temp_val_reg(s
, ts
, reg
);
5166 ts
->mem_coherent
= 0;
5170 case TCG_CALL_RET_BY_VEC
:
5172 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5174 tcg_debug_assert(ts
->base_type
== TCG_TYPE_I128
);
5175 tcg_debug_assert(ts
->temp_subindex
== 0);
5176 if (!ts
->mem_allocated
) {
5177 temp_allocate_frame(s
, ts
);
5179 tcg_out_st(s
, TCG_TYPE_V128
,
5180 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
5181 ts
->mem_base
->reg
, ts
->mem_offset
);
5183 /* fall through to mark all parts in memory */
5185 case TCG_CALL_RET_BY_REF
:
5186 /* The callee has performed a write through the reference. */
5187 for (i
= 0; i
< nb_oargs
; i
++) {
5188 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5189 ts
->val_type
= TEMP_VAL_MEM
;
5194 g_assert_not_reached();
5197 /* Flush or discard output registers as needed. */
5198 for (i
= 0; i
< nb_oargs
; i
++) {
5199 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5200 if (NEED_SYNC_ARG(i
)) {
5201 temp_sync(s
, ts
, s
->reserved_regs
, 0, IS_DEAD_ARG(i
));
5202 } else if (IS_DEAD_ARG(i
)) {
5209 * Similarly for qemu_ld/st slow path helpers.
5210 * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously,
5211 * using only the provided backend tcg_out_* functions.
5214 static int tcg_out_helper_stk_ofs(TCGType type
, unsigned slot
)
5216 int ofs
= arg_slot_stk_ofs(slot
);
5219 * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not
5220 * require extension to uint64_t, adjust the address for uint32_t.
5222 if (HOST_BIG_ENDIAN
&&
5223 TCG_TARGET_REG_BITS
== 64 &&
5224 type
== TCG_TYPE_I32
) {
5230 static void tcg_out_helper_load_slots(TCGContext
*s
,
5231 unsigned nmov
, TCGMovExtend
*mov
,
5232 const TCGLdstHelperParam
*parm
)
5238 * Start from the end, storing to the stack first.
5239 * This frees those registers, so we need not consider overlap.
5241 for (i
= nmov
; i
-- > 0; ) {
5242 unsigned slot
= mov
[i
].dst
;
5244 if (arg_slot_reg_p(slot
)) {
5248 TCGReg src
= mov
[i
].src
;
5249 TCGType dst_type
= mov
[i
].dst_type
;
5250 MemOp dst_mo
= dst_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5252 /* The argument is going onto the stack; extend into scratch. */
5253 if ((mov
[i
].src_ext
& MO_SIZE
) != dst_mo
) {
5254 tcg_debug_assert(parm
->ntmp
!= 0);
5255 mov
[i
].dst
= src
= parm
->tmp
[0];
5256 tcg_out_movext1(s
, &mov
[i
]);
5259 tcg_out_st(s
, dst_type
, src
, TCG_REG_CALL_STACK
,
5260 tcg_out_helper_stk_ofs(dst_type
, slot
));
5266 * The remaining arguments are in registers.
5267 * Convert slot numbers to argument registers.
5270 for (i
= 0; i
< nmov
; ++i
) {
5271 mov
[i
].dst
= tcg_target_call_iarg_regs
[mov
[i
].dst
];
5276 /* The backend must have provided enough temps for the worst case. */
5277 tcg_debug_assert(parm
->ntmp
>= 2);
5280 for (unsigned j
= 0; j
< 3; ++j
) {
5281 if (dst3
== mov
[j
].src
) {
5283 * Conflict. Copy the source to a temporary, perform the
5284 * remaining moves, then the extension from our scratch
5287 TCGReg scratch
= parm
->tmp
[1];
5289 tcg_out_mov(s
, mov
[3].src_type
, scratch
, mov
[3].src
);
5290 tcg_out_movext3(s
, mov
, mov
+ 1, mov
+ 2, parm
->tmp
[0]);
5291 tcg_out_movext1_new_src(s
, &mov
[3], scratch
);
5296 /* No conflicts: perform this move and continue. */
5297 tcg_out_movext1(s
, &mov
[3]);
5301 tcg_out_movext3(s
, mov
, mov
+ 1, mov
+ 2,
5302 parm
->ntmp
? parm
->tmp
[0] : -1);
5305 tcg_out_movext2(s
, mov
, mov
+ 1,
5306 parm
->ntmp
? parm
->tmp
[0] : -1);
5309 tcg_out_movext1(s
, mov
);
5312 g_assert_not_reached();
5316 static void tcg_out_helper_load_imm(TCGContext
*s
, unsigned slot
,
5317 TCGType type
, tcg_target_long imm
,
5318 const TCGLdstHelperParam
*parm
)
5320 if (arg_slot_reg_p(slot
)) {
5321 tcg_out_movi(s
, type
, tcg_target_call_iarg_regs
[slot
], imm
);
5323 int ofs
= tcg_out_helper_stk_ofs(type
, slot
);
5324 if (!tcg_out_sti(s
, type
, imm
, TCG_REG_CALL_STACK
, ofs
)) {
5325 tcg_debug_assert(parm
->ntmp
!= 0);
5326 tcg_out_movi(s
, type
, parm
->tmp
[0], imm
);
5327 tcg_out_st(s
, type
, parm
->tmp
[0], TCG_REG_CALL_STACK
, ofs
);
5332 static void tcg_out_helper_load_common_args(TCGContext
*s
,
5333 const TCGLabelQemuLdst
*ldst
,
5334 const TCGLdstHelperParam
*parm
,
5335 const TCGHelperInfo
*info
,
5338 TCGMovExtend ptr_mov
= {
5339 .dst_type
= TCG_TYPE_PTR
,
5340 .src_type
= TCG_TYPE_PTR
,
5341 .src_ext
= sizeof(void *) == 4 ? MO_32
: MO_64
5343 const TCGCallArgumentLoc
*loc
= &info
->in
[0];
5346 tcg_target_ulong imm
;
5349 * Handle env, which is always first.
5351 ptr_mov
.dst
= loc
->arg_slot
;
5352 ptr_mov
.src
= TCG_AREG0
;
5353 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5359 loc
= &info
->in
[next_arg
];
5360 type
= TCG_TYPE_I32
;
5361 switch (loc
->kind
) {
5362 case TCG_CALL_ARG_NORMAL
:
5364 case TCG_CALL_ARG_EXTEND_U
:
5365 case TCG_CALL_ARG_EXTEND_S
:
5366 /* No extension required for MemOpIdx. */
5367 tcg_debug_assert(imm
<= INT32_MAX
);
5368 type
= TCG_TYPE_REG
;
5371 g_assert_not_reached();
5373 tcg_out_helper_load_imm(s
, loc
->arg_slot
, type
, imm
, parm
);
5379 loc
= &info
->in
[next_arg
];
5380 slot
= loc
->arg_slot
;
5385 if (arg_slot_reg_p(slot
)) {
5386 arg_reg
= tcg_target_call_iarg_regs
[slot
];
5388 ra_reg
= parm
->ra_gen(s
, ldst
, arg_reg
);
5391 ptr_mov
.src
= ra_reg
;
5392 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5394 imm
= (uintptr_t)ldst
->raddr
;
5395 tcg_out_helper_load_imm(s
, slot
, TCG_TYPE_PTR
, imm
, parm
);
5399 static unsigned tcg_out_helper_add_mov(TCGMovExtend
*mov
,
5400 const TCGCallArgumentLoc
*loc
,
5401 TCGType dst_type
, TCGType src_type
,
5402 TCGReg lo
, TCGReg hi
)
5404 if (dst_type
<= TCG_TYPE_REG
) {
5407 switch (loc
->kind
) {
5408 case TCG_CALL_ARG_NORMAL
:
5409 src_ext
= src_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5411 case TCG_CALL_ARG_EXTEND_U
:
5412 dst_type
= TCG_TYPE_REG
;
5415 case TCG_CALL_ARG_EXTEND_S
:
5416 dst_type
= TCG_TYPE_REG
;
5420 g_assert_not_reached();
5423 mov
[0].dst
= loc
->arg_slot
;
5424 mov
[0].dst_type
= dst_type
;
5426 mov
[0].src_type
= src_type
;
5427 mov
[0].src_ext
= src_ext
;
5431 assert(TCG_TARGET_REG_BITS
== 32);
5433 mov
[0].dst
= loc
[HOST_BIG_ENDIAN
].arg_slot
;
5435 mov
[0].dst_type
= TCG_TYPE_I32
;
5436 mov
[0].src_type
= TCG_TYPE_I32
;
5437 mov
[0].src_ext
= MO_32
;
5439 mov
[1].dst
= loc
[!HOST_BIG_ENDIAN
].arg_slot
;
5441 mov
[1].dst_type
= TCG_TYPE_I32
;
5442 mov
[1].src_type
= TCG_TYPE_I32
;
5443 mov
[1].src_ext
= MO_32
;
5448 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5449 const TCGLdstHelperParam
*parm
)
5451 const TCGHelperInfo
*info
;
5452 const TCGCallArgumentLoc
*loc
;
5453 TCGMovExtend mov
[2];
5454 unsigned next_arg
, nmov
;
5455 MemOp mop
= get_memop(ldst
->oi
);
5457 switch (mop
& MO_SIZE
) {
5461 info
= &info_helper_ld32_mmu
;
5464 info
= &info_helper_ld64_mmu
;
5467 g_assert_not_reached();
5470 /* Defer env argument. */
5473 loc
= &info
->in
[next_arg
];
5474 nmov
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_TL
, TCG_TYPE_TL
,
5475 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5478 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5480 /* No special attention for 32 and 64-bit return values. */
5481 tcg_debug_assert(info
->out_kind
== TCG_CALL_RET_NORMAL
);
5483 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5486 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5488 const TCGLdstHelperParam
*parm
)
5490 TCGMovExtend mov
[2];
5492 if (ldst
->type
<= TCG_TYPE_REG
) {
5493 MemOp mop
= get_memop(ldst
->oi
);
5495 mov
[0].dst
= ldst
->datalo_reg
;
5496 mov
[0].src
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, 0);
5497 mov
[0].dst_type
= ldst
->type
;
5498 mov
[0].src_type
= TCG_TYPE_REG
;
5501 * If load_sign, then we allowed the helper to perform the
5502 * appropriate sign extension to tcg_target_ulong, and all
5503 * we need now is a plain move.
5505 * If they do not, then we expect the relevant extension
5506 * instruction to be no more expensive than a move, and
5507 * we thus save the icache etc by only using one of two
5510 if (load_sign
|| !(mop
& MO_SIGN
)) {
5511 if (TCG_TARGET_REG_BITS
== 32 || ldst
->type
== TCG_TYPE_I32
) {
5512 mov
[0].src_ext
= MO_32
;
5514 mov
[0].src_ext
= MO_64
;
5517 mov
[0].src_ext
= mop
& MO_SSIZE
;
5519 tcg_out_movext1(s
, mov
);
5521 assert(TCG_TARGET_REG_BITS
== 32);
5523 mov
[0].dst
= ldst
->datalo_reg
;
5525 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, HOST_BIG_ENDIAN
);
5526 mov
[0].dst_type
= TCG_TYPE_I32
;
5527 mov
[0].src_type
= TCG_TYPE_I32
;
5528 mov
[0].src_ext
= MO_32
;
5530 mov
[1].dst
= ldst
->datahi_reg
;
5532 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, !HOST_BIG_ENDIAN
);
5533 mov
[1].dst_type
= TCG_TYPE_REG
;
5534 mov
[1].src_type
= TCG_TYPE_REG
;
5535 mov
[1].src_ext
= MO_32
;
5537 tcg_out_movext2(s
, mov
, mov
+ 1, parm
->ntmp
? parm
->tmp
[0] : -1);
5541 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5542 const TCGLdstHelperParam
*parm
)
5544 const TCGHelperInfo
*info
;
5545 const TCGCallArgumentLoc
*loc
;
5546 TCGMovExtend mov
[4];
5548 unsigned next_arg
, nmov
, n
;
5549 MemOp mop
= get_memop(ldst
->oi
);
5551 switch (mop
& MO_SIZE
) {
5555 info
= &info_helper_st32_mmu
;
5556 data_type
= TCG_TYPE_I32
;
5559 info
= &info_helper_st64_mmu
;
5560 data_type
= TCG_TYPE_I64
;
5563 g_assert_not_reached();
5566 /* Defer env argument. */
5570 /* Handle addr argument. */
5571 loc
= &info
->in
[next_arg
];
5572 n
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_TL
, TCG_TYPE_TL
,
5573 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5577 /* Handle data argument. */
5578 loc
= &info
->in
[next_arg
];
5579 n
= tcg_out_helper_add_mov(mov
+ nmov
, loc
, data_type
, ldst
->type
,
5580 ldst
->datalo_reg
, ldst
->datahi_reg
);
5583 tcg_debug_assert(nmov
<= ARRAY_SIZE(mov
));
5585 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5586 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5589 #ifdef CONFIG_PROFILER
5591 /* avoid copy/paste errors */
5592 #define PROF_ADD(to, from, field) \
5594 (to)->field += qatomic_read(&((from)->field)); \
5597 #define PROF_MAX(to, from, field) \
5599 typeof((from)->field) val__ = qatomic_read(&((from)->field)); \
5600 if (val__ > (to)->field) { \
5601 (to)->field = val__; \
5605 /* Pass in a zero'ed @prof */
5607 void tcg_profile_snapshot(TCGProfile
*prof
, bool counters
, bool table
)
5609 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
5612 for (i
= 0; i
< n_ctxs
; i
++) {
5613 TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
5614 const TCGProfile
*orig
= &s
->prof
;
5617 PROF_ADD(prof
, orig
, cpu_exec_time
);
5618 PROF_ADD(prof
, orig
, tb_count1
);
5619 PROF_ADD(prof
, orig
, tb_count
);
5620 PROF_ADD(prof
, orig
, op_count
);
5621 PROF_MAX(prof
, orig
, op_count_max
);
5622 PROF_ADD(prof
, orig
, temp_count
);
5623 PROF_MAX(prof
, orig
, temp_count_max
);
5624 PROF_ADD(prof
, orig
, del_op_count
);
5625 PROF_ADD(prof
, orig
, code_in_len
);
5626 PROF_ADD(prof
, orig
, code_out_len
);
5627 PROF_ADD(prof
, orig
, search_out_len
);
5628 PROF_ADD(prof
, orig
, interm_time
);
5629 PROF_ADD(prof
, orig
, code_time
);
5630 PROF_ADD(prof
, orig
, la_time
);
5631 PROF_ADD(prof
, orig
, opt_time
);
5632 PROF_ADD(prof
, orig
, restore_count
);
5633 PROF_ADD(prof
, orig
, restore_time
);
5638 for (i
= 0; i
< NB_OPS
; i
++) {
5639 PROF_ADD(prof
, orig
, table_op_count
[i
]);
5648 static void tcg_profile_snapshot_counters(TCGProfile
*prof
)
5650 tcg_profile_snapshot(prof
, true, false);
5653 static void tcg_profile_snapshot_table(TCGProfile
*prof
)
5655 tcg_profile_snapshot(prof
, false, true);
5658 void tcg_dump_op_count(GString
*buf
)
5660 TCGProfile prof
= {};
5663 tcg_profile_snapshot_table(&prof
);
5664 for (i
= 0; i
< NB_OPS
; i
++) {
5665 g_string_append_printf(buf
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
5666 prof
.table_op_count
[i
]);
5670 int64_t tcg_cpu_exec_time(void)
5672 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
5676 for (i
= 0; i
< n_ctxs
; i
++) {
5677 const TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
5678 const TCGProfile
*prof
= &s
->prof
;
5680 ret
+= qatomic_read(&prof
->cpu_exec_time
);
5685 void tcg_dump_op_count(GString
*buf
)
5687 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
5690 int64_t tcg_cpu_exec_time(void)
5692 error_report("%s: TCG profiler not compiled", __func__
);
5698 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
, target_ulong pc_start
)
5700 #ifdef CONFIG_PROFILER
5701 TCGProfile
*prof
= &s
->prof
;
5706 #ifdef CONFIG_PROFILER
5710 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
5713 qatomic_set(&prof
->op_count
, prof
->op_count
+ n
);
5714 if (n
> prof
->op_count_max
) {
5715 qatomic_set(&prof
->op_count_max
, n
);
5719 qatomic_set(&prof
->temp_count
, prof
->temp_count
+ n
);
5720 if (n
> prof
->temp_count_max
) {
5721 qatomic_set(&prof
->temp_count_max
, n
);
5727 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)
5728 && qemu_log_in_addr_range(pc_start
))) {
5729 FILE *logfile
= qemu_log_trylock();
5731 fprintf(logfile
, "OP:\n");
5732 tcg_dump_ops(s
, logfile
, false);
5733 fprintf(logfile
, "\n");
5734 qemu_log_unlock(logfile
);
5739 #ifdef CONFIG_DEBUG_TCG
5740 /* Ensure all labels referenced have been emitted. */
5745 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
5746 if (unlikely(!l
->present
) && !QSIMPLEQ_EMPTY(&l
->branches
)) {
5747 qemu_log_mask(CPU_LOG_TB_OP
,
5748 "$L%d referenced but not present.\n", l
->id
);
5756 #ifdef CONFIG_PROFILER
5757 qatomic_set(&prof
->opt_time
, prof
->opt_time
- profile_getclock());
5760 #ifdef USE_TCG_OPTIMIZATIONS
5764 #ifdef CONFIG_PROFILER
5765 qatomic_set(&prof
->opt_time
, prof
->opt_time
+ profile_getclock());
5766 qatomic_set(&prof
->la_time
, prof
->la_time
- profile_getclock());
5769 reachable_code_pass(s
);
5773 if (s
->nb_indirects
> 0) {
5775 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND
)
5776 && qemu_log_in_addr_range(pc_start
))) {
5777 FILE *logfile
= qemu_log_trylock();
5779 fprintf(logfile
, "OP before indirect lowering:\n");
5780 tcg_dump_ops(s
, logfile
, false);
5781 fprintf(logfile
, "\n");
5782 qemu_log_unlock(logfile
);
5786 /* Replace indirect temps with direct temps. */
5787 if (liveness_pass_2(s
)) {
5788 /* If changes were made, re-run liveness. */
5793 #ifdef CONFIG_PROFILER
5794 qatomic_set(&prof
->la_time
, prof
->la_time
+ profile_getclock());
5798 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
)
5799 && qemu_log_in_addr_range(pc_start
))) {
5800 FILE *logfile
= qemu_log_trylock();
5802 fprintf(logfile
, "OP after optimization and liveness analysis:\n");
5803 tcg_dump_ops(s
, logfile
, true);
5804 fprintf(logfile
, "\n");
5805 qemu_log_unlock(logfile
);
5810 /* Initialize goto_tb jump offsets. */
5811 tb
->jmp_reset_offset
[0] = TB_JMP_OFFSET_INVALID
;
5812 tb
->jmp_reset_offset
[1] = TB_JMP_OFFSET_INVALID
;
5813 tb
->jmp_insn_offset
[0] = TB_JMP_OFFSET_INVALID
;
5814 tb
->jmp_insn_offset
[1] = TB_JMP_OFFSET_INVALID
;
5816 tcg_reg_alloc_start(s
);
5819 * Reset the buffer pointers when restarting after overflow.
5820 * TODO: Move this into translate-all.c with the rest of the
5821 * buffer management. Having only this done here is confusing.
5823 s
->code_buf
= tcg_splitwx_to_rw(tb
->tc
.ptr
);
5824 s
->code_ptr
= s
->code_buf
;
5826 #ifdef TCG_TARGET_NEED_LDST_LABELS
5827 QSIMPLEQ_INIT(&s
->ldst_labels
);
5829 #ifdef TCG_TARGET_NEED_POOL_LABELS
5830 s
->pool_labels
= NULL
;
5834 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
5835 TCGOpcode opc
= op
->opc
;
5837 #ifdef CONFIG_PROFILER
5838 qatomic_set(&prof
->table_op_count
[opc
], prof
->table_op_count
[opc
] + 1);
5842 case INDEX_op_mov_i32
:
5843 case INDEX_op_mov_i64
:
5844 case INDEX_op_mov_vec
:
5845 tcg_reg_alloc_mov(s
, op
);
5847 case INDEX_op_dup_vec
:
5848 tcg_reg_alloc_dup(s
, op
);
5850 case INDEX_op_insn_start
:
5851 if (num_insns
>= 0) {
5852 size_t off
= tcg_current_code_size(s
);
5853 s
->gen_insn_end_off
[num_insns
] = off
;
5854 /* Assert that we do not overflow our stored offset. */
5855 assert(s
->gen_insn_end_off
[num_insns
] == off
);
5858 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
5860 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
5861 a
= deposit64(op
->args
[i
* 2], 32, 32, op
->args
[i
* 2 + 1]);
5865 s
->gen_insn_data
[num_insns
][i
] = a
;
5868 case INDEX_op_discard
:
5869 temp_dead(s
, arg_temp(op
->args
[0]));
5871 case INDEX_op_set_label
:
5872 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
5873 tcg_out_label(s
, arg_label(op
->args
[0]));
5876 tcg_reg_alloc_call(s
, op
);
5878 case INDEX_op_exit_tb
:
5879 tcg_out_exit_tb(s
, op
->args
[0]);
5881 case INDEX_op_goto_tb
:
5882 tcg_out_goto_tb(s
, op
->args
[0]);
5884 case INDEX_op_dup2_vec
:
5885 if (tcg_reg_alloc_dup2(s
, op
)) {
5890 /* Sanity check that we've not introduced any unhandled opcodes. */
5891 tcg_debug_assert(tcg_op_supported(opc
));
5892 /* Note: in order to speed up the code, it would be much
5893 faster to have specialized register allocator functions for
5894 some common argument patterns */
5895 tcg_reg_alloc_op(s
, op
);
5898 /* Test for (pending) buffer overflow. The assumption is that any
5899 one operation beginning below the high water mark cannot overrun
5900 the buffer completely. Thus we can test for overflow after
5901 generating code without having to check during generation. */
5902 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
5905 /* Test for TB overflow, as seen by gen_insn_end_off. */
5906 if (unlikely(tcg_current_code_size(s
) > UINT16_MAX
)) {
5910 tcg_debug_assert(num_insns
>= 0);
5911 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
5913 /* Generate TB finalization at the end of block */
5914 #ifdef TCG_TARGET_NEED_LDST_LABELS
5915 i
= tcg_out_ldst_finalize(s
);
5920 #ifdef TCG_TARGET_NEED_POOL_LABELS
5921 i
= tcg_out_pool_finalize(s
);
5926 if (!tcg_resolve_relocs(s
)) {
5930 #ifndef CONFIG_TCG_INTERPRETER
5931 /* flush instruction cache */
5932 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
5933 (uintptr_t)s
->code_buf
,
5934 tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
));
5937 return tcg_current_code_size(s
);
5940 #ifdef CONFIG_PROFILER
5941 void tcg_dump_info(GString
*buf
)
5943 TCGProfile prof
= {};
5944 const TCGProfile
*s
;
5946 int64_t tb_div_count
;
5949 tcg_profile_snapshot_counters(&prof
);
5951 tb_count
= s
->tb_count
;
5952 tb_div_count
= tb_count
? tb_count
: 1;
5953 tot
= s
->interm_time
+ s
->code_time
;
5955 g_string_append_printf(buf
, "JIT cycles %" PRId64
5956 " (%0.3f s at 2.4 GHz)\n",
5958 g_string_append_printf(buf
, "translated TBs %" PRId64
5959 " (aborted=%" PRId64
" %0.1f%%)\n",
5960 tb_count
, s
->tb_count1
- tb_count
,
5961 (double)(s
->tb_count1
- s
->tb_count
)
5962 / (s
->tb_count1
? s
->tb_count1
: 1) * 100.0);
5963 g_string_append_printf(buf
, "avg ops/TB %0.1f max=%d\n",
5964 (double)s
->op_count
/ tb_div_count
, s
->op_count_max
);
5965 g_string_append_printf(buf
, "deleted ops/TB %0.2f\n",
5966 (double)s
->del_op_count
/ tb_div_count
);
5967 g_string_append_printf(buf
, "avg temps/TB %0.2f max=%d\n",
5968 (double)s
->temp_count
/ tb_div_count
,
5970 g_string_append_printf(buf
, "avg host code/TB %0.1f\n",
5971 (double)s
->code_out_len
/ tb_div_count
);
5972 g_string_append_printf(buf
, "avg search data/TB %0.1f\n",
5973 (double)s
->search_out_len
/ tb_div_count
);
5975 g_string_append_printf(buf
, "cycles/op %0.1f\n",
5976 s
->op_count
? (double)tot
/ s
->op_count
: 0);
5977 g_string_append_printf(buf
, "cycles/in byte %0.1f\n",
5978 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
5979 g_string_append_printf(buf
, "cycles/out byte %0.1f\n",
5980 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
5981 g_string_append_printf(buf
, "cycles/search byte %0.1f\n",
5983 (double)tot
/ s
->search_out_len
: 0);
5987 g_string_append_printf(buf
, " gen_interm time %0.1f%%\n",
5988 (double)s
->interm_time
/ tot
* 100.0);
5989 g_string_append_printf(buf
, " gen_code time %0.1f%%\n",
5990 (double)s
->code_time
/ tot
* 100.0);
5991 g_string_append_printf(buf
, "optim./code time %0.1f%%\n",
5992 (double)s
->opt_time
/ (s
->code_time
?
5995 g_string_append_printf(buf
, "liveness/code time %0.1f%%\n",
5996 (double)s
->la_time
/ (s
->code_time
?
5997 s
->code_time
: 1) * 100.0);
5998 g_string_append_printf(buf
, "cpu_restore count %" PRId64
"\n",
6000 g_string_append_printf(buf
, " avg cycles %0.1f\n",
6002 (double)s
->restore_time
/ s
->restore_count
: 0);
6005 void tcg_dump_info(GString
*buf
)
6007 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
6011 #ifdef ELF_HOST_MACHINE
6012 /* In order to use this feature, the backend needs to do three things:
6014 (1) Define ELF_HOST_MACHINE to indicate both what value to
6015 put into the ELF image and to indicate support for the feature.
6017 (2) Define tcg_register_jit. This should create a buffer containing
6018 the contents of a .debug_frame section that describes the post-
6019 prologue unwind info for the tcg machine.
6021 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
6024 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
6031 struct jit_code_entry
{
6032 struct jit_code_entry
*next_entry
;
6033 struct jit_code_entry
*prev_entry
;
6034 const void *symfile_addr
;
6035 uint64_t symfile_size
;
6038 struct jit_descriptor
{
6040 uint32_t action_flag
;
6041 struct jit_code_entry
*relevant_entry
;
6042 struct jit_code_entry
*first_entry
;
6045 void __jit_debug_register_code(void) __attribute__((noinline
));
6046 void __jit_debug_register_code(void)
6051 /* Must statically initialize the version, because GDB may check
6052 the version before we can set it. */
6053 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
6055 /* End GDB interface. */
6057 static int find_string(const char *strtab
, const char *str
)
6059 const char *p
= strtab
+ 1;
6062 if (strcmp(p
, str
) == 0) {
6069 static void tcg_register_jit_int(const void *buf_ptr
, size_t buf_size
,
6070 const void *debug_frame
,
6071 size_t debug_frame_size
)
6073 struct __attribute__((packed
)) DebugInfo
{
6080 uintptr_t cu_low_pc
;
6081 uintptr_t cu_high_pc
;
6084 uintptr_t fn_low_pc
;
6085 uintptr_t fn_high_pc
;
6094 struct DebugInfo di
;
6099 struct ElfImage
*img
;
6101 static const struct ElfImage img_template
= {
6103 .e_ident
[EI_MAG0
] = ELFMAG0
,
6104 .e_ident
[EI_MAG1
] = ELFMAG1
,
6105 .e_ident
[EI_MAG2
] = ELFMAG2
,
6106 .e_ident
[EI_MAG3
] = ELFMAG3
,
6107 .e_ident
[EI_CLASS
] = ELF_CLASS
,
6108 .e_ident
[EI_DATA
] = ELF_DATA
,
6109 .e_ident
[EI_VERSION
] = EV_CURRENT
,
6111 .e_machine
= ELF_HOST_MACHINE
,
6112 .e_version
= EV_CURRENT
,
6113 .e_phoff
= offsetof(struct ElfImage
, phdr
),
6114 .e_shoff
= offsetof(struct ElfImage
, shdr
),
6115 .e_ehsize
= sizeof(ElfW(Shdr
)),
6116 .e_phentsize
= sizeof(ElfW(Phdr
)),
6118 .e_shentsize
= sizeof(ElfW(Shdr
)),
6119 .e_shnum
= ARRAY_SIZE(img
->shdr
),
6120 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
6121 #ifdef ELF_HOST_FLAGS
6122 .e_flags
= ELF_HOST_FLAGS
,
6125 .e_ident
[EI_OSABI
] = ELF_OSABI
,
6133 [0] = { .sh_type
= SHT_NULL
},
6134 /* Trick: The contents of code_gen_buffer are not present in
6135 this fake ELF file; that got allocated elsewhere. Therefore
6136 we mark .text as SHT_NOBITS (similar to .bss) so that readers
6137 will not look for contents. We can record any address. */
6139 .sh_type
= SHT_NOBITS
,
6140 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
6142 [2] = { /* .debug_info */
6143 .sh_type
= SHT_PROGBITS
,
6144 .sh_offset
= offsetof(struct ElfImage
, di
),
6145 .sh_size
= sizeof(struct DebugInfo
),
6147 [3] = { /* .debug_abbrev */
6148 .sh_type
= SHT_PROGBITS
,
6149 .sh_offset
= offsetof(struct ElfImage
, da
),
6150 .sh_size
= sizeof(img
->da
),
6152 [4] = { /* .debug_frame */
6153 .sh_type
= SHT_PROGBITS
,
6154 .sh_offset
= sizeof(struct ElfImage
),
6156 [5] = { /* .symtab */
6157 .sh_type
= SHT_SYMTAB
,
6158 .sh_offset
= offsetof(struct ElfImage
, sym
),
6159 .sh_size
= sizeof(img
->sym
),
6161 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
6162 .sh_entsize
= sizeof(ElfW(Sym
)),
6164 [6] = { /* .strtab */
6165 .sh_type
= SHT_STRTAB
,
6166 .sh_offset
= offsetof(struct ElfImage
, str
),
6167 .sh_size
= sizeof(img
->str
),
6171 [1] = { /* code_gen_buffer */
6172 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
6177 .len
= sizeof(struct DebugInfo
) - 4,
6179 .ptr_size
= sizeof(void *),
6181 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
6183 .fn_name
= "code_gen_buffer"
6186 1, /* abbrev number (the cu) */
6187 0x11, 1, /* DW_TAG_compile_unit, has children */
6188 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
6189 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6190 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6191 0, 0, /* end of abbrev */
6192 2, /* abbrev number (the fn) */
6193 0x2e, 0, /* DW_TAG_subprogram, no children */
6194 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
6195 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6196 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6197 0, 0, /* end of abbrev */
6198 0 /* no more abbrev */
6200 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
6201 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
6204 /* We only need a single jit entry; statically allocate it. */
6205 static struct jit_code_entry one_entry
;
6207 uintptr_t buf
= (uintptr_t)buf_ptr
;
6208 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
6209 DebugFrameHeader
*dfh
;
6211 img
= g_malloc(img_size
);
6212 *img
= img_template
;
6214 img
->phdr
.p_vaddr
= buf
;
6215 img
->phdr
.p_paddr
= buf
;
6216 img
->phdr
.p_memsz
= buf_size
;
6218 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
6219 img
->shdr
[1].sh_addr
= buf
;
6220 img
->shdr
[1].sh_size
= buf_size
;
6222 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
6223 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
6225 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
6226 img
->shdr
[4].sh_size
= debug_frame_size
;
6228 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
6229 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
6231 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
6232 img
->sym
[1].st_value
= buf
;
6233 img
->sym
[1].st_size
= buf_size
;
6235 img
->di
.cu_low_pc
= buf
;
6236 img
->di
.cu_high_pc
= buf
+ buf_size
;
6237 img
->di
.fn_low_pc
= buf
;
6238 img
->di
.fn_high_pc
= buf
+ buf_size
;
6240 dfh
= (DebugFrameHeader
*)(img
+ 1);
6241 memcpy(dfh
, debug_frame
, debug_frame_size
);
6242 dfh
->fde
.func_start
= buf
;
6243 dfh
->fde
.func_len
= buf_size
;
6246 /* Enable this block to be able to debug the ELF image file creation.
6247 One can use readelf, objdump, or other inspection utilities. */
6249 g_autofree
char *jit
= g_strdup_printf("%s/qemu.jit", g_get_tmp_dir());
6250 FILE *f
= fopen(jit
, "w+b");
6252 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
6253 /* Avoid stupid unused return value warning for fwrite. */
6260 one_entry
.symfile_addr
= img
;
6261 one_entry
.symfile_size
= img_size
;
6263 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
6264 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
6265 __jit_debug_descriptor
.first_entry
= &one_entry
;
6266 __jit_debug_register_code();
6269 /* No support for the feature. Provide the entry point expected by exec.c,
6270 and implement the internal function we declared earlier. */
6272 static void tcg_register_jit_int(const void *buf
, size_t size
,
6273 const void *debug_frame
,
6274 size_t debug_frame_size
)
6278 void tcg_register_jit(const void *buf
, size_t buf_size
)
6281 #endif /* ELF_HOST_MACHINE */
6283 #if !TCG_TARGET_MAYBE_vec
6284 void tcg_expand_vec_op(TCGOpcode o
, TCGType t
, unsigned e
, TCGArg a0
, ...)
6286 g_assert_not_reached();