2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-common.h"
30 #include "exec/tb-context.h"
31 #include "qemu/bitops.h"
32 #include "tcg-target.h"
34 /* XXX: make safe guess about sizes */
35 #define MAX_OP_PER_INSTR 266
37 #if HOST_LONG_BITS == 32
38 #define MAX_OPC_PARAM_PER_ARG 2
40 #define MAX_OPC_PARAM_PER_ARG 1
42 #define MAX_OPC_PARAM_IARGS 5
43 #define MAX_OPC_PARAM_OARGS 1
44 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
46 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
47 * and up to 4 + N parameters on 64-bit archs
48 * (N = number of input arguments + output arguments). */
49 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
50 #define OPC_BUF_SIZE 640
51 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
53 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
55 #define CPU_TEMP_BUF_NLONGS 128
57 /* Default target word size to pointer size. */
58 #ifndef TCG_TARGET_REG_BITS
59 # if UINTPTR_MAX == UINT32_MAX
60 # define TCG_TARGET_REG_BITS 32
61 # elif UINTPTR_MAX == UINT64_MAX
62 # define TCG_TARGET_REG_BITS 64
64 # error Unknown pointer size for tcg target
68 #if TCG_TARGET_REG_BITS == 32
69 typedef int32_t tcg_target_long
;
70 typedef uint32_t tcg_target_ulong
;
71 #define TCG_PRIlx PRIx32
72 #define TCG_PRIld PRId32
73 #elif TCG_TARGET_REG_BITS == 64
74 typedef int64_t tcg_target_long
;
75 typedef uint64_t tcg_target_ulong
;
76 #define TCG_PRIlx PRIx64
77 #define TCG_PRIld PRId64
82 #if TCG_TARGET_NB_REGS <= 32
83 typedef uint32_t TCGRegSet
;
84 #elif TCG_TARGET_NB_REGS <= 64
85 typedef uint64_t TCGRegSet
;
90 #if TCG_TARGET_REG_BITS == 32
91 /* Turn some undef macros into false macros. */
92 #define TCG_TARGET_HAS_extrl_i64_i32 0
93 #define TCG_TARGET_HAS_extrh_i64_i32 0
94 #define TCG_TARGET_HAS_div_i64 0
95 #define TCG_TARGET_HAS_rem_i64 0
96 #define TCG_TARGET_HAS_div2_i64 0
97 #define TCG_TARGET_HAS_rot_i64 0
98 #define TCG_TARGET_HAS_ext8s_i64 0
99 #define TCG_TARGET_HAS_ext16s_i64 0
100 #define TCG_TARGET_HAS_ext32s_i64 0
101 #define TCG_TARGET_HAS_ext8u_i64 0
102 #define TCG_TARGET_HAS_ext16u_i64 0
103 #define TCG_TARGET_HAS_ext32u_i64 0
104 #define TCG_TARGET_HAS_bswap16_i64 0
105 #define TCG_TARGET_HAS_bswap32_i64 0
106 #define TCG_TARGET_HAS_bswap64_i64 0
107 #define TCG_TARGET_HAS_neg_i64 0
108 #define TCG_TARGET_HAS_not_i64 0
109 #define TCG_TARGET_HAS_andc_i64 0
110 #define TCG_TARGET_HAS_orc_i64 0
111 #define TCG_TARGET_HAS_eqv_i64 0
112 #define TCG_TARGET_HAS_nand_i64 0
113 #define TCG_TARGET_HAS_nor_i64 0
114 #define TCG_TARGET_HAS_deposit_i64 0
115 #define TCG_TARGET_HAS_extract_i64 0
116 #define TCG_TARGET_HAS_sextract_i64 0
117 #define TCG_TARGET_HAS_movcond_i64 0
118 #define TCG_TARGET_HAS_add2_i64 0
119 #define TCG_TARGET_HAS_sub2_i64 0
120 #define TCG_TARGET_HAS_mulu2_i64 0
121 #define TCG_TARGET_HAS_muls2_i64 0
122 #define TCG_TARGET_HAS_muluh_i64 0
123 #define TCG_TARGET_HAS_mulsh_i64 0
124 /* Turn some undef macros into true macros. */
125 #define TCG_TARGET_HAS_add2_i32 1
126 #define TCG_TARGET_HAS_sub2_i32 1
129 #ifndef TCG_TARGET_deposit_i32_valid
130 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
132 #ifndef TCG_TARGET_deposit_i64_valid
133 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
135 #ifndef TCG_TARGET_extract_i32_valid
136 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
138 #ifndef TCG_TARGET_extract_i64_valid
139 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
142 /* Only one of DIV or DIV2 should be defined. */
143 #if defined(TCG_TARGET_HAS_div_i32)
144 #define TCG_TARGET_HAS_div2_i32 0
145 #elif defined(TCG_TARGET_HAS_div2_i32)
146 #define TCG_TARGET_HAS_div_i32 0
147 #define TCG_TARGET_HAS_rem_i32 0
149 #if defined(TCG_TARGET_HAS_div_i64)
150 #define TCG_TARGET_HAS_div2_i64 0
151 #elif defined(TCG_TARGET_HAS_div2_i64)
152 #define TCG_TARGET_HAS_div_i64 0
153 #define TCG_TARGET_HAS_rem_i64 0
156 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
157 #if TCG_TARGET_REG_BITS == 32 \
158 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
159 || defined(TCG_TARGET_HAS_muluh_i32))
160 # error "Missing unsigned widening multiply"
163 #ifndef TARGET_INSN_START_EXTRA_WORDS
164 # define TARGET_INSN_START_WORDS 1
166 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
169 typedef enum TCGOpcode
{
170 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
176 #define tcg_regset_clear(d) (d) = 0
177 #define tcg_regset_set(d, s) (d) = (s)
178 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
179 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
180 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
181 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
182 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
183 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
184 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
185 #define tcg_regset_not(d, a) (d) = ~(a)
187 #ifndef TCG_TARGET_INSN_UNIT_SIZE
188 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
189 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
190 typedef uint8_t tcg_insn_unit
;
191 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
192 typedef uint16_t tcg_insn_unit
;
193 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
194 typedef uint32_t tcg_insn_unit
;
195 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
196 typedef uint64_t tcg_insn_unit
;
198 /* The port better have done this. */
202 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
203 # define tcg_debug_assert(X) do { assert(X); } while (0)
204 #elif QEMU_GNUC_PREREQ(4, 5)
205 # define tcg_debug_assert(X) \
206 do { if (!(X)) { __builtin_unreachable(); } } while (0)
208 # define tcg_debug_assert(X) do { (void)(X); } while (0)
211 typedef struct TCGRelocation
{
212 struct TCGRelocation
*next
;
218 typedef struct TCGLabel
{
219 unsigned has_value
: 1;
223 tcg_insn_unit
*value_ptr
;
224 TCGRelocation
*first_reloc
;
228 typedef struct TCGPool
{
229 struct TCGPool
*next
;
231 uint8_t data
[0] __attribute__ ((aligned
));
234 #define TCG_POOL_CHUNK_SIZE 32768
236 #define TCG_MAX_TEMPS 512
237 #define TCG_MAX_INSNS 512
239 /* when the size of the arguments of a called function is smaller than
240 this value, they are statically allocated in the TB stack frame */
241 #define TCG_STATIC_CALL_ARGS_SIZE 128
243 typedef enum TCGType
{
246 TCG_TYPE_COUNT
, /* number of different types */
248 /* An alias for the size of the host register. */
249 #if TCG_TARGET_REG_BITS == 32
250 TCG_TYPE_REG
= TCG_TYPE_I32
,
252 TCG_TYPE_REG
= TCG_TYPE_I64
,
255 /* An alias for the size of the native pointer. */
256 #if UINTPTR_MAX == UINT32_MAX
257 TCG_TYPE_PTR
= TCG_TYPE_I32
,
259 TCG_TYPE_PTR
= TCG_TYPE_I64
,
262 /* An alias for the size of the target "long", aka register. */
263 #if TARGET_LONG_BITS == 64
264 TCG_TYPE_TL
= TCG_TYPE_I64
,
266 TCG_TYPE_TL
= TCG_TYPE_I32
,
270 /* Constants for qemu_ld and qemu_st for the Memory Operation field. */
271 typedef enum TCGMemOp
{
276 MO_SIZE
= 3, /* Mask for the above. */
278 MO_SIGN
= 4, /* Sign-extended, otherwise zero-extended. */
280 MO_BSWAP
= 8, /* Host reverse endian. */
281 #ifdef HOST_WORDS_BIGENDIAN
288 #ifdef TARGET_WORDS_BIGENDIAN
294 /* MO_UNALN accesses are never checked for alignment.
295 * MO_ALIGN accesses will result in a call to the CPU's
296 * do_unaligned_access hook if the guest address is not aligned.
297 * The default depends on whether the target CPU defines ALIGNED_ONLY.
299 * Some architectures (e.g. ARMv8) need the address which is aligned
300 * to a size more than the size of the memory access.
301 * Some architectures (e.g. SPARCv9) need an address which is aligned,
302 * but less strictly than the natural alignment.
304 * MO_ALIGN supposes the alignment size is the size of a memory access.
306 * There are three options:
307 * - unaligned access permitted (MO_UNALN).
308 * - an alignment to the size of an access (MO_ALIGN);
309 * - an alignment to a specified size, which may be more or less than
310 * the access size (MO_ALIGN_x where 'x' is a size in bytes);
313 MO_AMASK
= 7 << MO_ASHIFT
,
321 MO_ALIGN_2
= 1 << MO_ASHIFT
,
322 MO_ALIGN_4
= 2 << MO_ASHIFT
,
323 MO_ALIGN_8
= 3 << MO_ASHIFT
,
324 MO_ALIGN_16
= 4 << MO_ASHIFT
,
325 MO_ALIGN_32
= 5 << MO_ASHIFT
,
326 MO_ALIGN_64
= 6 << MO_ASHIFT
,
328 /* Combinations of the above, for ease of use. */
332 MO_SB
= MO_SIGN
| MO_8
,
333 MO_SW
= MO_SIGN
| MO_16
,
334 MO_SL
= MO_SIGN
| MO_32
,
337 MO_LEUW
= MO_LE
| MO_UW
,
338 MO_LEUL
= MO_LE
| MO_UL
,
339 MO_LESW
= MO_LE
| MO_SW
,
340 MO_LESL
= MO_LE
| MO_SL
,
341 MO_LEQ
= MO_LE
| MO_Q
,
343 MO_BEUW
= MO_BE
| MO_UW
,
344 MO_BEUL
= MO_BE
| MO_UL
,
345 MO_BESW
= MO_BE
| MO_SW
,
346 MO_BESL
= MO_BE
| MO_SL
,
347 MO_BEQ
= MO_BE
| MO_Q
,
349 MO_TEUW
= MO_TE
| MO_UW
,
350 MO_TEUL
= MO_TE
| MO_UL
,
351 MO_TESW
= MO_TE
| MO_SW
,
352 MO_TESL
= MO_TE
| MO_SL
,
353 MO_TEQ
= MO_TE
| MO_Q
,
355 MO_SSIZE
= MO_SIZE
| MO_SIGN
,
360 * @memop: TCGMemOp value
362 * Extract the alignment size from the memop.
364 static inline unsigned get_alignment_bits(TCGMemOp memop
)
366 unsigned a
= memop
& MO_AMASK
;
369 /* No alignment required. */
371 } else if (a
== MO_ALIGN
) {
372 /* A natural alignment requirement. */
375 /* A specific alignment requirement. */
378 #if defined(CONFIG_SOFTMMU)
379 /* The requested alignment cannot overlap the TLB flags. */
380 tcg_debug_assert((TLB_FLAGS_MASK
& ((1 << a
) - 1)) == 0);
385 typedef tcg_target_ulong TCGArg
;
387 /* Define type and accessor macros for TCG variables.
389 TCG variables are the inputs and outputs of TCG ops, as described
390 in tcg/README. Target CPU front-end code uses these types to deal
391 with TCG variables as it emits TCG code via the tcg_gen_* functions.
392 They come in several flavours:
393 * TCGv_i32 : 32 bit integer type
394 * TCGv_i64 : 64 bit integer type
395 * TCGv_ptr : a host pointer type
396 * TCGv : an integer type the same size as target_ulong
397 (an alias for either TCGv_i32 or TCGv_i64)
398 The compiler's type checking will complain if you mix them
399 up and pass the wrong sized TCGv to a function.
401 Users of tcg_gen_* don't need to know about any of the internal
402 details of these, and should treat them as opaque types.
403 You won't be able to look inside them in a debugger either.
405 Internal implementation details follow:
407 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
408 This is deliberate, because the values we store in variables of type
409 TCGv_i32 are not really pointers-to-structures. They're just small
410 integers, but keeping them in pointer types like this means that the
411 compiler will complain if you accidentally pass a TCGv_i32 to a
412 function which takes a TCGv_i64, and so on. Only the internals of
413 TCG need to care about the actual contents of the types, and they always
414 box and unbox via the MAKE_TCGV_* and GET_TCGV_* functions.
415 Converting to and from intptr_t rather than int reduces the number
416 of sign-extension instructions that get implied on 64-bit hosts. */
418 typedef struct TCGv_i32_d
*TCGv_i32
;
419 typedef struct TCGv_i64_d
*TCGv_i64
;
420 typedef struct TCGv_ptr_d
*TCGv_ptr
;
421 typedef TCGv_ptr TCGv_env
;
422 #if TARGET_LONG_BITS == 32
423 #define TCGv TCGv_i32
424 #elif TARGET_LONG_BITS == 64
425 #define TCGv TCGv_i64
427 #error Unhandled TARGET_LONG_BITS value
430 static inline TCGv_i32 QEMU_ARTIFICIAL
MAKE_TCGV_I32(intptr_t i
)
435 static inline TCGv_i64 QEMU_ARTIFICIAL
MAKE_TCGV_I64(intptr_t i
)
440 static inline TCGv_ptr QEMU_ARTIFICIAL
MAKE_TCGV_PTR(intptr_t i
)
445 static inline intptr_t QEMU_ARTIFICIAL
GET_TCGV_I32(TCGv_i32 t
)
450 static inline intptr_t QEMU_ARTIFICIAL
GET_TCGV_I64(TCGv_i64 t
)
455 static inline intptr_t QEMU_ARTIFICIAL
GET_TCGV_PTR(TCGv_ptr t
)
460 #if TCG_TARGET_REG_BITS == 32
461 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
462 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
465 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
466 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
467 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
469 /* Dummy definition to avoid compiler warnings. */
470 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
471 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
472 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
474 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
475 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
476 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
479 /* Helper does not read globals (either directly or through an exception). It
480 implies TCG_CALL_NO_WRITE_GLOBALS. */
481 #define TCG_CALL_NO_READ_GLOBALS 0x0010
482 /* Helper does not write globals */
483 #define TCG_CALL_NO_WRITE_GLOBALS 0x0020
484 /* Helper can be safely suppressed if the return value is not used. */
485 #define TCG_CALL_NO_SIDE_EFFECTS 0x0040
487 /* convenience version of most used call flags */
488 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
489 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
490 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
491 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
492 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
494 /* used to align parameters */
495 #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1)
496 #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
499 /* Used to indicate the type of accesses on which ordering
500 is to be ensured. Modeled after SPARC barriers. */
505 TCG_MO_ALL
= 0x0F, /* OR of the above */
507 /* Used to indicate the kind of ordering which is to be ensured by the
508 instruction. These types are derived from x86/aarch64 instructions.
509 It should be noted that these are different from C11 semantics. */
510 TCG_BAR_LDAQ
= 0x10, /* Following ops will not come forward */
511 TCG_BAR_STRL
= 0x20, /* Previous ops will not be delayed */
512 TCG_BAR_SC
= 0x30, /* No ops cross barrier; OR of the above */
515 /* Conditions. Note that these are laid out for easy manipulation by
517 bit 0 is used for inverting;
520 bit 3 is used with bit 0 for swapping signed/unsigned. */
523 TCG_COND_NEVER
= 0 | 0 | 0 | 0,
524 TCG_COND_ALWAYS
= 0 | 0 | 0 | 1,
525 TCG_COND_EQ
= 8 | 0 | 0 | 0,
526 TCG_COND_NE
= 8 | 0 | 0 | 1,
528 TCG_COND_LT
= 0 | 0 | 2 | 0,
529 TCG_COND_GE
= 0 | 0 | 2 | 1,
530 TCG_COND_LE
= 8 | 0 | 2 | 0,
531 TCG_COND_GT
= 8 | 0 | 2 | 1,
533 TCG_COND_LTU
= 0 | 4 | 0 | 0,
534 TCG_COND_GEU
= 0 | 4 | 0 | 1,
535 TCG_COND_LEU
= 8 | 4 | 0 | 0,
536 TCG_COND_GTU
= 8 | 4 | 0 | 1,
539 /* Invert the sense of the comparison. */
540 static inline TCGCond
tcg_invert_cond(TCGCond c
)
542 return (TCGCond
)(c
^ 1);
545 /* Swap the operands in a comparison. */
546 static inline TCGCond
tcg_swap_cond(TCGCond c
)
548 return c
& 6 ? (TCGCond
)(c
^ 9) : c
;
551 /* Create an "unsigned" version of a "signed" comparison. */
552 static inline TCGCond
tcg_unsigned_cond(TCGCond c
)
554 return c
& 2 ? (TCGCond
)(c
^ 6) : c
;
557 /* Must a comparison be considered unsigned? */
558 static inline bool is_unsigned_cond(TCGCond c
)
563 /* Create a "high" version of a double-word comparison.
564 This removes equality from a LTE or GTE comparison. */
565 static inline TCGCond
tcg_high_cond(TCGCond c
)
572 return (TCGCond
)(c
^ 8);
578 typedef enum TCGTempVal
{
585 typedef struct TCGTemp
{
587 TCGTempVal val_type
:8;
590 unsigned int fixed_reg
:1;
591 unsigned int indirect_reg
:1;
592 unsigned int indirect_base
:1;
593 unsigned int mem_coherent
:1;
594 unsigned int mem_allocated
:1;
595 unsigned int temp_local
:1; /* If true, the temp is saved across
596 basic blocks. Otherwise, it is not
597 preserved across basic blocks. */
598 unsigned int temp_allocated
:1; /* never used for code gen */
601 struct TCGTemp
*mem_base
;
606 typedef struct TCGContext TCGContext
;
608 typedef struct TCGTempSet
{
609 unsigned long l
[BITS_TO_LONGS(TCG_MAX_TEMPS
)];
612 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
613 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
614 There are never more than 2 outputs, which means that we can store all
615 dead + sync data within 16 bits. */
618 typedef uint16_t TCGLifeData
;
620 /* The layout here is designed to avoid crossing of a 32-bit boundary.
621 If we do so, gcc adds padding, expanding the size to 12. */
622 typedef struct TCGOp
{
623 TCGOpcode opc
: 8; /* 8 */
625 /* Index of the prev/next op, or 0 for the end of the list. */
626 unsigned prev
: 10; /* 18 */
627 unsigned next
: 10; /* 28 */
629 /* The number of out and in parameter for a call. */
630 unsigned calli
: 4; /* 32 */
631 unsigned callo
: 2; /* 34 */
633 /* Index of the arguments for this op, or 0 for zero-operand ops. */
634 unsigned args
: 14; /* 48 */
636 /* Lifetime data of the operands. */
637 unsigned life
: 16; /* 64 */
640 /* Make sure operands fit in the bitfields above. */
641 QEMU_BUILD_BUG_ON(NB_OPS
> (1 << 8));
642 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE
> (1 << 10));
643 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE
> (1 << 14));
645 /* Make sure that we don't overflow 64 bits without noticing. */
646 QEMU_BUILD_BUG_ON(sizeof(TCGOp
) > 8);
649 uint8_t *pool_cur
, *pool_end
;
650 TCGPool
*pool_first
, *pool_current
, *pool_first_large
;
656 /* goto_tb support */
657 tcg_insn_unit
*code_buf
;
658 uint16_t *tb_jmp_reset_offset
; /* tb->jmp_reset_offset */
659 uint16_t *tb_jmp_insn_offset
; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */
660 uintptr_t *tb_jmp_target_addr
; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */
662 TCGRegSet reserved_regs
;
663 intptr_t current_frame_offset
;
664 intptr_t frame_start
;
668 tcg_insn_unit
*code_ptr
;
672 #ifdef CONFIG_PROFILER
676 int64_t op_count
; /* total insn count */
677 int op_count_max
; /* max insn per TB */
680 int64_t del_op_count
;
682 int64_t code_out_len
;
683 int64_t search_out_len
;
688 int64_t restore_count
;
689 int64_t restore_time
;
692 #ifdef CONFIG_DEBUG_TCG
694 int goto_tb_issue_mask
;
698 int gen_next_parm_idx
;
700 /* Code generation. Note that we specifically do not use tcg_insn_unit
701 here, because there's too much arithmetic throughout that relies
702 on addition and subtraction working on bytes. Rely on the GCC
703 extension that allows arithmetic on void*. */
704 int code_gen_max_blocks
;
705 void *code_gen_prologue
;
706 void *code_gen_buffer
;
707 size_t code_gen_buffer_size
;
710 /* Threshold to flush the translated code buffer. */
711 void *code_gen_highwater
;
715 /* Track which vCPU triggers events */
716 CPUState
*cpu
; /* *_trans */
717 TCGv_env tcg_env
; /* *_exec */
719 /* The TCGBackendData structure is private to tcg-target.inc.c. */
720 struct TCGBackendData
*be
;
722 TCGTempSet free_temps
[TCG_TYPE_COUNT
* 2];
723 TCGTemp temps
[TCG_MAX_TEMPS
]; /* globals first, temps after */
725 /* Tells which temporary holds a given register.
726 It does not take into account fixed registers */
727 TCGTemp
*reg_to_temp
[TCG_TARGET_NB_REGS
];
729 TCGOp gen_op_buf
[OPC_BUF_SIZE
];
730 TCGArg gen_opparam_buf
[OPPARAM_BUF_SIZE
];
732 uint16_t gen_insn_end_off
[TCG_MAX_INSNS
];
733 target_ulong gen_insn_data
[TCG_MAX_INSNS
][TARGET_INSN_START_WORDS
];
736 extern TCGContext tcg_ctx
;
737 extern bool parallel_cpus
;
739 static inline void tcg_set_insn_param(int op_idx
, int arg
, TCGArg v
)
741 int op_argi
= tcg_ctx
.gen_op_buf
[op_idx
].args
;
742 tcg_ctx
.gen_opparam_buf
[op_argi
+ arg
] = v
;
745 /* The number of opcodes emitted so far. */
746 static inline int tcg_op_buf_count(void)
748 return tcg_ctx
.gen_next_op_idx
;
751 /* Test for whether to terminate the TB for using too many opcodes. */
752 static inline bool tcg_op_buf_full(void)
754 return tcg_op_buf_count() >= OPC_MAX_SIZE
;
757 /* pool based memory allocation */
759 /* tb_lock must be held for tcg_malloc_internal. */
760 void *tcg_malloc_internal(TCGContext
*s
, int size
);
761 void tcg_pool_reset(TCGContext
*s
);
764 void tb_unlock(void);
765 void tb_lock_reset(void);
767 /* Called with tb_lock held. */
768 static inline void *tcg_malloc(int size
)
770 TCGContext
*s
= &tcg_ctx
;
771 uint8_t *ptr
, *ptr_end
;
772 size
= (size
+ sizeof(long) - 1) & ~(sizeof(long) - 1);
774 ptr_end
= ptr
+ size
;
775 if (unlikely(ptr_end
> s
->pool_end
)) {
776 return tcg_malloc_internal(&tcg_ctx
, size
);
778 s
->pool_cur
= ptr_end
;
783 void tcg_context_init(TCGContext
*s
);
784 void tcg_prologue_init(TCGContext
*s
);
785 void tcg_func_start(TCGContext
*s
);
787 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
);
789 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
);
791 int tcg_global_mem_new_internal(TCGType
, TCGv_ptr
, intptr_t, const char *);
793 TCGv_i32
tcg_global_reg_new_i32(TCGReg reg
, const char *name
);
794 TCGv_i64
tcg_global_reg_new_i64(TCGReg reg
, const char *name
);
796 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
);
797 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
);
799 void tcg_temp_free_i32(TCGv_i32 arg
);
800 void tcg_temp_free_i64(TCGv_i64 arg
);
802 static inline TCGv_i32
tcg_global_mem_new_i32(TCGv_ptr reg
, intptr_t offset
,
805 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
806 return MAKE_TCGV_I32(idx
);
809 static inline TCGv_i32
tcg_temp_new_i32(void)
811 return tcg_temp_new_internal_i32(0);
814 static inline TCGv_i32
tcg_temp_local_new_i32(void)
816 return tcg_temp_new_internal_i32(1);
819 static inline TCGv_i64
tcg_global_mem_new_i64(TCGv_ptr reg
, intptr_t offset
,
822 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
823 return MAKE_TCGV_I64(idx
);
826 static inline TCGv_i64
tcg_temp_new_i64(void)
828 return tcg_temp_new_internal_i64(0);
831 static inline TCGv_i64
tcg_temp_local_new_i64(void)
833 return tcg_temp_new_internal_i64(1);
836 #if defined(CONFIG_DEBUG_TCG)
837 /* If you call tcg_clear_temp_count() at the start of a section of
838 * code which is not supposed to leak any TCG temporaries, then
839 * calling tcg_check_temp_count() at the end of the section will
840 * return 1 if the section did in fact leak a temporary.
842 void tcg_clear_temp_count(void);
843 int tcg_check_temp_count(void);
845 #define tcg_clear_temp_count() do { } while (0)
846 #define tcg_check_temp_count() 0
849 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
);
850 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
);
852 #define TCG_CT_ALIAS 0x80
853 #define TCG_CT_IALIAS 0x40
854 #define TCG_CT_REG 0x01
855 #define TCG_CT_CONST 0x02 /* any constant of register size */
857 typedef struct TCGArgConstraint
{
865 #define TCG_MAX_OP_ARGS 16
867 /* Bits for TCGOpDef->flags, 8 bits available. */
869 /* Instruction defines the end of a basic block. */
870 TCG_OPF_BB_END
= 0x01,
871 /* Instruction clobbers call registers and potentially update globals. */
872 TCG_OPF_CALL_CLOBBER
= 0x02,
873 /* Instruction has side effects: it cannot be removed if its outputs
874 are not used, and might trigger exceptions. */
875 TCG_OPF_SIDE_EFFECTS
= 0x04,
876 /* Instruction operands are 64-bits (otherwise 32-bits). */
877 TCG_OPF_64BIT
= 0x08,
878 /* Instruction is optional and not implemented by the host, or insn
879 is generic and should not be implemened by the host. */
880 TCG_OPF_NOT_PRESENT
= 0x10,
883 typedef struct TCGOpDef
{
885 uint8_t nb_oargs
, nb_iargs
, nb_cargs
, nb_args
;
887 TCGArgConstraint
*args_ct
;
889 #if defined(CONFIG_DEBUG_TCG)
894 extern TCGOpDef tcg_op_defs
[];
895 extern const size_t tcg_op_defs_max
;
897 typedef struct TCGTargetOpDef
{
899 const char *args_ct_str
[TCG_MAX_OP_ARGS
];
902 #define tcg_abort() \
904 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
908 void tcg_add_target_add_op_defs(const TCGTargetOpDef
*tdefs
);
910 #if UINTPTR_MAX == UINT32_MAX
911 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
912 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
914 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
915 #define tcg_global_reg_new_ptr(R, N) \
916 TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
917 #define tcg_global_mem_new_ptr(R, O, N) \
918 TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
919 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
920 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
922 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
923 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
925 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
926 #define tcg_global_reg_new_ptr(R, N) \
927 TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
928 #define tcg_global_mem_new_ptr(R, O, N) \
929 TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
930 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
931 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
934 void tcg_gen_callN(TCGContext
*s
, void *func
,
935 TCGArg ret
, int nargs
, TCGArg
*args
);
937 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
);
938 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
, int narg
);
939 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
, int narg
);
941 void tcg_optimize(TCGContext
*s
);
943 /* only used for debugging purposes */
944 void tcg_dump_ops(TCGContext
*s
);
946 TCGv_i32
tcg_const_i32(int32_t val
);
947 TCGv_i64
tcg_const_i64(int64_t val
);
948 TCGv_i32
tcg_const_local_i32(int32_t val
);
949 TCGv_i64
tcg_const_local_i64(int64_t val
);
951 TCGLabel
*gen_new_label(void);
957 * Encode a label for storage in the TCG opcode stream.
960 static inline TCGArg
label_arg(TCGLabel
*l
)
969 * The opposite of label_arg. Retrieve a label from the
970 * encoding of the TCG opcode stream.
973 static inline TCGLabel
*arg_label(TCGArg i
)
975 return (TCGLabel
*)(uintptr_t)i
;
980 * @a, @b: addresses to be differenced
982 * There are many places within the TCG backends where we need a byte
983 * difference between two pointers. While this can be accomplished
984 * with local casting, it's easy to get wrong -- especially if one is
985 * concerned with the signedness of the result.
987 * This version relies on GCC's void pointer arithmetic to get the
991 static inline ptrdiff_t tcg_ptr_byte_diff(void *a
, void *b
)
998 * @s: the tcg context
999 * @target: address of the target
1001 * Produce a pc-relative difference, from the current code_ptr
1002 * to the destination address.
1005 static inline ptrdiff_t tcg_pcrel_diff(TCGContext
*s
, void *target
)
1007 return tcg_ptr_byte_diff(target
, s
->code_ptr
);
1011 * tcg_current_code_size
1012 * @s: the tcg context
1014 * Compute the current code size within the translation block.
1015 * This is used to fill in qemu's data structures for goto_tb.
1018 static inline size_t tcg_current_code_size(TCGContext
*s
)
1020 return tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
);
1023 /* Combine the TCGMemOp and mmu_idx parameters into a single value. */
1024 typedef uint32_t TCGMemOpIdx
;
1028 * @op: memory operation
1031 * Encode these values into a single parameter.
1033 static inline TCGMemOpIdx
make_memop_idx(TCGMemOp op
, unsigned idx
)
1035 tcg_debug_assert(idx
<= 15);
1036 return (op
<< 4) | idx
;
1041 * @oi: combined op/idx parameter
1043 * Extract the memory operation from the combined value.
1045 static inline TCGMemOp
get_memop(TCGMemOpIdx oi
)
1052 * @oi: combined op/idx parameter
1054 * Extract the mmu index from the combined value.
1056 static inline unsigned get_mmuidx(TCGMemOpIdx oi
)
1063 * @env: pointer to CPUArchState for the CPU
1064 * @tb_ptr: address of generated code for the TB to execute
1066 * Start executing code from a given translation block.
1067 * Where translation blocks have been linked, execution
1068 * may proceed from the given TB into successive ones.
1069 * Control eventually returns only when some action is needed
1070 * from the top-level loop: either control must pass to a TB
1071 * which has not yet been directly linked, or an asynchronous
1072 * event such as an interrupt needs handling.
1074 * Return: The return value is the value passed to the corresponding
1075 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1076 * The value is either zero or a 4-byte aligned pointer to that TB combined
1077 * with additional information in its two least significant bits. The
1078 * additional information is encoded as follows:
1079 * 0, 1: the link between this TB and the next is via the specified
1080 * TB index (0 or 1). That is, we left the TB via (the equivalent
1081 * of) "goto_tb <index>". The main loop uses this to determine
1082 * how to link the TB just executed to the next.
1083 * 2: we are using instruction counting code generation, and we
1084 * did not start executing this TB because the instruction counter
1085 * would hit zero midway through it. In this case the pointer
1086 * returned is the TB we were about to execute, and the caller must
1087 * arrange to execute the remaining count of instructions.
1088 * 3: we stopped because the CPU's exit_request flag was set
1089 * (usually meaning that there is an interrupt that needs to be
1090 * handled). The pointer returned is the TB we were about to execute
1091 * when we noticed the pending exit request.
1093 * If the bottom two bits indicate an exit-via-index then the CPU
1094 * state is correctly synchronised and ready for execution of the next
1095 * TB (and in particular the guest PC is the address to execute next).
1096 * Otherwise, we gave up on execution of this TB before it started, and
1097 * the caller must fix up the CPU state by calling the CPU's
1098 * synchronize_from_tb() method with the TB pointer we return (falling
1099 * back to calling the CPU's set_pc method with tb->pb if no
1100 * synchronize_from_tb() method exists).
1102 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1103 * to this default (which just calls the prologue.code emitted by
1104 * tcg_target_qemu_prologue()).
1106 #define TB_EXIT_MASK 3
1107 #define TB_EXIT_IDX0 0
1108 #define TB_EXIT_IDX1 1
1109 #define TB_EXIT_ICOUNT_EXPIRED 2
1110 #define TB_EXIT_REQUESTED 3
1112 #ifdef HAVE_TCG_QEMU_TB_EXEC
1113 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
);
1115 # define tcg_qemu_tb_exec(env, tb_ptr) \
1116 ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
1119 void tcg_register_jit(void *buf
, size_t buf_size
);
1122 * Memory helpers that will be used by TCG generated code.
1124 #ifdef CONFIG_SOFTMMU
1125 /* Value zero-extended to tcg register size. */
1126 tcg_target_ulong
helper_ret_ldub_mmu(CPUArchState
*env
, target_ulong addr
,
1127 TCGMemOpIdx oi
, uintptr_t retaddr
);
1128 tcg_target_ulong
helper_le_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1129 TCGMemOpIdx oi
, uintptr_t retaddr
);
1130 tcg_target_ulong
helper_le_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1131 TCGMemOpIdx oi
, uintptr_t retaddr
);
1132 uint64_t helper_le_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1133 TCGMemOpIdx oi
, uintptr_t retaddr
);
1134 tcg_target_ulong
helper_be_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1135 TCGMemOpIdx oi
, uintptr_t retaddr
);
1136 tcg_target_ulong
helper_be_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1137 TCGMemOpIdx oi
, uintptr_t retaddr
);
1138 uint64_t helper_be_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1139 TCGMemOpIdx oi
, uintptr_t retaddr
);
1141 /* Value sign-extended to tcg register size. */
1142 tcg_target_ulong
helper_ret_ldsb_mmu(CPUArchState
*env
, target_ulong addr
,
1143 TCGMemOpIdx oi
, uintptr_t retaddr
);
1144 tcg_target_ulong
helper_le_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1145 TCGMemOpIdx oi
, uintptr_t retaddr
);
1146 tcg_target_ulong
helper_le_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1147 TCGMemOpIdx oi
, uintptr_t retaddr
);
1148 tcg_target_ulong
helper_be_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1149 TCGMemOpIdx oi
, uintptr_t retaddr
);
1150 tcg_target_ulong
helper_be_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1151 TCGMemOpIdx oi
, uintptr_t retaddr
);
1153 void helper_ret_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
1154 TCGMemOpIdx oi
, uintptr_t retaddr
);
1155 void helper_le_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1156 TCGMemOpIdx oi
, uintptr_t retaddr
);
1157 void helper_le_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1158 TCGMemOpIdx oi
, uintptr_t retaddr
);
1159 void helper_le_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1160 TCGMemOpIdx oi
, uintptr_t retaddr
);
1161 void helper_be_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1162 TCGMemOpIdx oi
, uintptr_t retaddr
);
1163 void helper_be_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1164 TCGMemOpIdx oi
, uintptr_t retaddr
);
1165 void helper_be_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1166 TCGMemOpIdx oi
, uintptr_t retaddr
);
1168 uint8_t helper_ret_ldb_cmmu(CPUArchState
*env
, target_ulong addr
,
1169 TCGMemOpIdx oi
, uintptr_t retaddr
);
1170 uint16_t helper_le_ldw_cmmu(CPUArchState
*env
, target_ulong addr
,
1171 TCGMemOpIdx oi
, uintptr_t retaddr
);
1172 uint32_t helper_le_ldl_cmmu(CPUArchState
*env
, target_ulong addr
,
1173 TCGMemOpIdx oi
, uintptr_t retaddr
);
1174 uint64_t helper_le_ldq_cmmu(CPUArchState
*env
, target_ulong addr
,
1175 TCGMemOpIdx oi
, uintptr_t retaddr
);
1176 uint16_t helper_be_ldw_cmmu(CPUArchState
*env
, target_ulong addr
,
1177 TCGMemOpIdx oi
, uintptr_t retaddr
);
1178 uint32_t helper_be_ldl_cmmu(CPUArchState
*env
, target_ulong addr
,
1179 TCGMemOpIdx oi
, uintptr_t retaddr
);
1180 uint64_t helper_be_ldq_cmmu(CPUArchState
*env
, target_ulong addr
,
1181 TCGMemOpIdx oi
, uintptr_t retaddr
);
1183 /* Temporary aliases until backends are converted. */
1184 #ifdef TARGET_WORDS_BIGENDIAN
1185 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1186 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1187 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1188 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1189 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1190 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1191 # define helper_ret_stw_mmu helper_be_stw_mmu
1192 # define helper_ret_stl_mmu helper_be_stl_mmu
1193 # define helper_ret_stq_mmu helper_be_stq_mmu
1194 # define helper_ret_ldw_cmmu helper_be_ldw_cmmu
1195 # define helper_ret_ldl_cmmu helper_be_ldl_cmmu
1196 # define helper_ret_ldq_cmmu helper_be_ldq_cmmu
1198 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1199 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1200 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1201 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1202 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1203 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1204 # define helper_ret_stw_mmu helper_le_stw_mmu
1205 # define helper_ret_stl_mmu helper_le_stl_mmu
1206 # define helper_ret_stq_mmu helper_le_stq_mmu
1207 # define helper_ret_ldw_cmmu helper_le_ldw_cmmu
1208 # define helper_ret_ldl_cmmu helper_le_ldl_cmmu
1209 # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
1212 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState
*env
, target_ulong addr
,
1213 uint32_t cmpv
, uint32_t newv
,
1214 TCGMemOpIdx oi
, uintptr_t retaddr
);
1215 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState
*env
, target_ulong addr
,
1216 uint32_t cmpv
, uint32_t newv
,
1217 TCGMemOpIdx oi
, uintptr_t retaddr
);
1218 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState
*env
, target_ulong addr
,
1219 uint32_t cmpv
, uint32_t newv
,
1220 TCGMemOpIdx oi
, uintptr_t retaddr
);
1221 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState
*env
, target_ulong addr
,
1222 uint64_t cmpv
, uint64_t newv
,
1223 TCGMemOpIdx oi
, uintptr_t retaddr
);
1224 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState
*env
, target_ulong addr
,
1225 uint32_t cmpv
, uint32_t newv
,
1226 TCGMemOpIdx oi
, uintptr_t retaddr
);
1227 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState
*env
, target_ulong addr
,
1228 uint32_t cmpv
, uint32_t newv
,
1229 TCGMemOpIdx oi
, uintptr_t retaddr
);
1230 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState
*env
, target_ulong addr
,
1231 uint64_t cmpv
, uint64_t newv
,
1232 TCGMemOpIdx oi
, uintptr_t retaddr
);
1234 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
1235 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
1236 (CPUArchState *env, target_ulong addr, TYPE val, \
1237 TCGMemOpIdx oi, uintptr_t retaddr);
1239 #ifdef CONFIG_ATOMIC64
1240 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1241 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1242 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1243 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1244 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1245 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
1246 GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
1247 GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1249 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1250 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1251 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1252 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1253 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1254 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1257 GEN_ATOMIC_HELPER_ALL(fetch_add
)
1258 GEN_ATOMIC_HELPER_ALL(fetch_sub
)
1259 GEN_ATOMIC_HELPER_ALL(fetch_and
)
1260 GEN_ATOMIC_HELPER_ALL(fetch_or
)
1261 GEN_ATOMIC_HELPER_ALL(fetch_xor
)
1263 GEN_ATOMIC_HELPER_ALL(add_fetch
)
1264 GEN_ATOMIC_HELPER_ALL(sub_fetch
)
1265 GEN_ATOMIC_HELPER_ALL(and_fetch
)
1266 GEN_ATOMIC_HELPER_ALL(or_fetch
)
1267 GEN_ATOMIC_HELPER_ALL(xor_fetch
)
1269 GEN_ATOMIC_HELPER_ALL(xchg
)
1271 #undef GEN_ATOMIC_HELPER_ALL
1272 #undef GEN_ATOMIC_HELPER
1273 #endif /* CONFIG_SOFTMMU */
1275 #ifdef CONFIG_ATOMIC128
1276 #include "qemu/int128.h"
1278 /* These aren't really a "proper" helpers because TCG cannot manage Int128.
1279 However, use the same format as the others, for use by the backends. */
1280 Int128
helper_atomic_cmpxchgo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1281 Int128 cmpv
, Int128 newv
,
1282 TCGMemOpIdx oi
, uintptr_t retaddr
);
1283 Int128
helper_atomic_cmpxchgo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1284 Int128 cmpv
, Int128 newv
,
1285 TCGMemOpIdx oi
, uintptr_t retaddr
);
1287 Int128
helper_atomic_ldo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1288 TCGMemOpIdx oi
, uintptr_t retaddr
);
1289 Int128
helper_atomic_ldo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1290 TCGMemOpIdx oi
, uintptr_t retaddr
);
1291 void helper_atomic_sto_le_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1292 TCGMemOpIdx oi
, uintptr_t retaddr
);
1293 void helper_atomic_sto_be_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1294 TCGMemOpIdx oi
, uintptr_t retaddr
);
1296 #endif /* CONFIG_ATOMIC128 */