2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-common.h"
30 #include "exec/tb-context.h"
31 #include "qemu/bitops.h"
32 #include "qemu/queue.h"
34 #include "tcg-target.h"
36 /* XXX: make safe guess about sizes */
37 #define MAX_OP_PER_INSTR 266
39 #if HOST_LONG_BITS == 32
40 #define MAX_OPC_PARAM_PER_ARG 2
42 #define MAX_OPC_PARAM_PER_ARG 1
44 #define MAX_OPC_PARAM_IARGS 6
45 #define MAX_OPC_PARAM_OARGS 1
46 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
48 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
49 * and up to 4 + N parameters on 64-bit archs
50 * (N = number of input arguments + output arguments). */
51 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
53 #define CPU_TEMP_BUF_NLONGS 128
55 /* Default target word size to pointer size. */
56 #ifndef TCG_TARGET_REG_BITS
57 # if UINTPTR_MAX == UINT32_MAX
58 # define TCG_TARGET_REG_BITS 32
59 # elif UINTPTR_MAX == UINT64_MAX
60 # define TCG_TARGET_REG_BITS 64
62 # error Unknown pointer size for tcg target
66 #if TCG_TARGET_REG_BITS == 32
67 typedef int32_t tcg_target_long
;
68 typedef uint32_t tcg_target_ulong
;
69 #define TCG_PRIlx PRIx32
70 #define TCG_PRIld PRId32
71 #elif TCG_TARGET_REG_BITS == 64
72 typedef int64_t tcg_target_long
;
73 typedef uint64_t tcg_target_ulong
;
74 #define TCG_PRIlx PRIx64
75 #define TCG_PRIld PRId64
80 /* Oversized TCG guests make things like MTTCG hard
81 * as we can't use atomics for cputlb updates.
83 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
84 #define TCG_OVERSIZED_GUEST 1
86 #define TCG_OVERSIZED_GUEST 0
89 #if TCG_TARGET_NB_REGS <= 32
90 typedef uint32_t TCGRegSet
;
91 #elif TCG_TARGET_NB_REGS <= 64
92 typedef uint64_t TCGRegSet
;
97 #if TCG_TARGET_REG_BITS == 32
98 /* Turn some undef macros into false macros. */
99 #define TCG_TARGET_HAS_extrl_i64_i32 0
100 #define TCG_TARGET_HAS_extrh_i64_i32 0
101 #define TCG_TARGET_HAS_div_i64 0
102 #define TCG_TARGET_HAS_rem_i64 0
103 #define TCG_TARGET_HAS_div2_i64 0
104 #define TCG_TARGET_HAS_rot_i64 0
105 #define TCG_TARGET_HAS_ext8s_i64 0
106 #define TCG_TARGET_HAS_ext16s_i64 0
107 #define TCG_TARGET_HAS_ext32s_i64 0
108 #define TCG_TARGET_HAS_ext8u_i64 0
109 #define TCG_TARGET_HAS_ext16u_i64 0
110 #define TCG_TARGET_HAS_ext32u_i64 0
111 #define TCG_TARGET_HAS_bswap16_i64 0
112 #define TCG_TARGET_HAS_bswap32_i64 0
113 #define TCG_TARGET_HAS_bswap64_i64 0
114 #define TCG_TARGET_HAS_neg_i64 0
115 #define TCG_TARGET_HAS_not_i64 0
116 #define TCG_TARGET_HAS_andc_i64 0
117 #define TCG_TARGET_HAS_orc_i64 0
118 #define TCG_TARGET_HAS_eqv_i64 0
119 #define TCG_TARGET_HAS_nand_i64 0
120 #define TCG_TARGET_HAS_nor_i64 0
121 #define TCG_TARGET_HAS_clz_i64 0
122 #define TCG_TARGET_HAS_ctz_i64 0
123 #define TCG_TARGET_HAS_ctpop_i64 0
124 #define TCG_TARGET_HAS_deposit_i64 0
125 #define TCG_TARGET_HAS_extract_i64 0
126 #define TCG_TARGET_HAS_sextract_i64 0
127 #define TCG_TARGET_HAS_movcond_i64 0
128 #define TCG_TARGET_HAS_add2_i64 0
129 #define TCG_TARGET_HAS_sub2_i64 0
130 #define TCG_TARGET_HAS_mulu2_i64 0
131 #define TCG_TARGET_HAS_muls2_i64 0
132 #define TCG_TARGET_HAS_muluh_i64 0
133 #define TCG_TARGET_HAS_mulsh_i64 0
134 /* Turn some undef macros into true macros. */
135 #define TCG_TARGET_HAS_add2_i32 1
136 #define TCG_TARGET_HAS_sub2_i32 1
139 #ifndef TCG_TARGET_deposit_i32_valid
140 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
142 #ifndef TCG_TARGET_deposit_i64_valid
143 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
145 #ifndef TCG_TARGET_extract_i32_valid
146 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
148 #ifndef TCG_TARGET_extract_i64_valid
149 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
152 /* Only one of DIV or DIV2 should be defined. */
153 #if defined(TCG_TARGET_HAS_div_i32)
154 #define TCG_TARGET_HAS_div2_i32 0
155 #elif defined(TCG_TARGET_HAS_div2_i32)
156 #define TCG_TARGET_HAS_div_i32 0
157 #define TCG_TARGET_HAS_rem_i32 0
159 #if defined(TCG_TARGET_HAS_div_i64)
160 #define TCG_TARGET_HAS_div2_i64 0
161 #elif defined(TCG_TARGET_HAS_div2_i64)
162 #define TCG_TARGET_HAS_div_i64 0
163 #define TCG_TARGET_HAS_rem_i64 0
166 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
167 #if TCG_TARGET_REG_BITS == 32 \
168 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
169 || defined(TCG_TARGET_HAS_muluh_i32))
170 # error "Missing unsigned widening multiply"
173 #if !defined(TCG_TARGET_HAS_v64) \
174 && !defined(TCG_TARGET_HAS_v128) \
175 && !defined(TCG_TARGET_HAS_v256)
176 #define TCG_TARGET_MAYBE_vec 0
177 #define TCG_TARGET_HAS_neg_vec 0
178 #define TCG_TARGET_HAS_not_vec 0
179 #define TCG_TARGET_HAS_andc_vec 0
180 #define TCG_TARGET_HAS_orc_vec 0
181 #define TCG_TARGET_HAS_shi_vec 0
182 #define TCG_TARGET_HAS_shs_vec 0
183 #define TCG_TARGET_HAS_shv_vec 0
185 #define TCG_TARGET_MAYBE_vec 1
187 #ifndef TCG_TARGET_HAS_v64
188 #define TCG_TARGET_HAS_v64 0
190 #ifndef TCG_TARGET_HAS_v128
191 #define TCG_TARGET_HAS_v128 0
193 #ifndef TCG_TARGET_HAS_v256
194 #define TCG_TARGET_HAS_v256 0
197 #ifndef TARGET_INSN_START_EXTRA_WORDS
198 # define TARGET_INSN_START_WORDS 1
200 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
203 typedef enum TCGOpcode
{
204 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
210 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
211 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
212 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
214 #ifndef TCG_TARGET_INSN_UNIT_SIZE
215 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
216 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
217 typedef uint8_t tcg_insn_unit
;
218 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
219 typedef uint16_t tcg_insn_unit
;
220 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
221 typedef uint32_t tcg_insn_unit
;
222 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
223 typedef uint64_t tcg_insn_unit
;
225 /* The port better have done this. */
229 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
230 # define tcg_debug_assert(X) do { assert(X); } while (0)
231 #elif QEMU_GNUC_PREREQ(4, 5)
232 # define tcg_debug_assert(X) \
233 do { if (!(X)) { __builtin_unreachable(); } } while (0)
235 # define tcg_debug_assert(X) do { (void)(X); } while (0)
238 typedef struct TCGRelocation
{
239 struct TCGRelocation
*next
;
245 typedef struct TCGLabel
{
246 unsigned has_value
: 1;
250 tcg_insn_unit
*value_ptr
;
251 TCGRelocation
*first_reloc
;
255 typedef struct TCGPool
{
256 struct TCGPool
*next
;
258 uint8_t data
[0] __attribute__ ((aligned
));
261 #define TCG_POOL_CHUNK_SIZE 32768
263 #define TCG_MAX_TEMPS 512
264 #define TCG_MAX_INSNS 512
266 /* when the size of the arguments of a called function is smaller than
267 this value, they are statically allocated in the TB stack frame */
268 #define TCG_STATIC_CALL_ARGS_SIZE 128
270 typedef enum TCGType
{
278 TCG_TYPE_COUNT
, /* number of different types */
280 /* An alias for the size of the host register. */
281 #if TCG_TARGET_REG_BITS == 32
282 TCG_TYPE_REG
= TCG_TYPE_I32
,
284 TCG_TYPE_REG
= TCG_TYPE_I64
,
287 /* An alias for the size of the native pointer. */
288 #if UINTPTR_MAX == UINT32_MAX
289 TCG_TYPE_PTR
= TCG_TYPE_I32
,
291 TCG_TYPE_PTR
= TCG_TYPE_I64
,
294 /* An alias for the size of the target "long", aka register. */
295 #if TARGET_LONG_BITS == 64
296 TCG_TYPE_TL
= TCG_TYPE_I64
,
298 TCG_TYPE_TL
= TCG_TYPE_I32
,
302 /* Constants for qemu_ld and qemu_st for the Memory Operation field. */
303 typedef enum TCGMemOp
{
308 MO_SIZE
= 3, /* Mask for the above. */
310 MO_SIGN
= 4, /* Sign-extended, otherwise zero-extended. */
312 MO_BSWAP
= 8, /* Host reverse endian. */
313 #ifdef HOST_WORDS_BIGENDIAN
320 #ifdef TARGET_WORDS_BIGENDIAN
326 /* MO_UNALN accesses are never checked for alignment.
327 * MO_ALIGN accesses will result in a call to the CPU's
328 * do_unaligned_access hook if the guest address is not aligned.
329 * The default depends on whether the target CPU defines ALIGNED_ONLY.
331 * Some architectures (e.g. ARMv8) need the address which is aligned
332 * to a size more than the size of the memory access.
333 * Some architectures (e.g. SPARCv9) need an address which is aligned,
334 * but less strictly than the natural alignment.
336 * MO_ALIGN supposes the alignment size is the size of a memory access.
338 * There are three options:
339 * - unaligned access permitted (MO_UNALN).
340 * - an alignment to the size of an access (MO_ALIGN);
341 * - an alignment to a specified size, which may be more or less than
342 * the access size (MO_ALIGN_x where 'x' is a size in bytes);
345 MO_AMASK
= 7 << MO_ASHIFT
,
353 MO_ALIGN_2
= 1 << MO_ASHIFT
,
354 MO_ALIGN_4
= 2 << MO_ASHIFT
,
355 MO_ALIGN_8
= 3 << MO_ASHIFT
,
356 MO_ALIGN_16
= 4 << MO_ASHIFT
,
357 MO_ALIGN_32
= 5 << MO_ASHIFT
,
358 MO_ALIGN_64
= 6 << MO_ASHIFT
,
360 /* Combinations of the above, for ease of use. */
364 MO_SB
= MO_SIGN
| MO_8
,
365 MO_SW
= MO_SIGN
| MO_16
,
366 MO_SL
= MO_SIGN
| MO_32
,
369 MO_LEUW
= MO_LE
| MO_UW
,
370 MO_LEUL
= MO_LE
| MO_UL
,
371 MO_LESW
= MO_LE
| MO_SW
,
372 MO_LESL
= MO_LE
| MO_SL
,
373 MO_LEQ
= MO_LE
| MO_Q
,
375 MO_BEUW
= MO_BE
| MO_UW
,
376 MO_BEUL
= MO_BE
| MO_UL
,
377 MO_BESW
= MO_BE
| MO_SW
,
378 MO_BESL
= MO_BE
| MO_SL
,
379 MO_BEQ
= MO_BE
| MO_Q
,
381 MO_TEUW
= MO_TE
| MO_UW
,
382 MO_TEUL
= MO_TE
| MO_UL
,
383 MO_TESW
= MO_TE
| MO_SW
,
384 MO_TESL
= MO_TE
| MO_SL
,
385 MO_TEQ
= MO_TE
| MO_Q
,
387 MO_SSIZE
= MO_SIZE
| MO_SIGN
,
392 * @memop: TCGMemOp value
394 * Extract the alignment size from the memop.
396 static inline unsigned get_alignment_bits(TCGMemOp memop
)
398 unsigned a
= memop
& MO_AMASK
;
401 /* No alignment required. */
403 } else if (a
== MO_ALIGN
) {
404 /* A natural alignment requirement. */
407 /* A specific alignment requirement. */
410 #if defined(CONFIG_SOFTMMU)
411 /* The requested alignment cannot overlap the TLB flags. */
412 tcg_debug_assert((TLB_FLAGS_MASK
& ((1 << a
) - 1)) == 0);
417 typedef tcg_target_ulong TCGArg
;
419 /* Define type and accessor macros for TCG variables.
421 TCG variables are the inputs and outputs of TCG ops, as described
422 in tcg/README. Target CPU front-end code uses these types to deal
423 with TCG variables as it emits TCG code via the tcg_gen_* functions.
424 They come in several flavours:
425 * TCGv_i32 : 32 bit integer type
426 * TCGv_i64 : 64 bit integer type
427 * TCGv_ptr : a host pointer type
428 * TCGv_vec : a host vector type; the exact size is not exposed
429 to the CPU front-end code.
430 * TCGv : an integer type the same size as target_ulong
431 (an alias for either TCGv_i32 or TCGv_i64)
432 The compiler's type checking will complain if you mix them
433 up and pass the wrong sized TCGv to a function.
435 Users of tcg_gen_* don't need to know about any of the internal
436 details of these, and should treat them as opaque types.
437 You won't be able to look inside them in a debugger either.
439 Internal implementation details follow:
441 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
442 This is deliberate, because the values we store in variables of type
443 TCGv_i32 are not really pointers-to-structures. They're just small
444 integers, but keeping them in pointer types like this means that the
445 compiler will complain if you accidentally pass a TCGv_i32 to a
446 function which takes a TCGv_i64, and so on. Only the internals of
447 TCG need to care about the actual contents of the types. */
449 typedef struct TCGv_i32_d
*TCGv_i32
;
450 typedef struct TCGv_i64_d
*TCGv_i64
;
451 typedef struct TCGv_ptr_d
*TCGv_ptr
;
452 typedef struct TCGv_vec_d
*TCGv_vec
;
453 typedef TCGv_ptr TCGv_env
;
454 #if TARGET_LONG_BITS == 32
455 #define TCGv TCGv_i32
456 #elif TARGET_LONG_BITS == 64
457 #define TCGv TCGv_i64
459 #error Unhandled TARGET_LONG_BITS value
463 /* Helper does not read globals (either directly or through an exception). It
464 implies TCG_CALL_NO_WRITE_GLOBALS. */
465 #define TCG_CALL_NO_READ_GLOBALS 0x0010
466 /* Helper does not write globals */
467 #define TCG_CALL_NO_WRITE_GLOBALS 0x0020
468 /* Helper can be safely suppressed if the return value is not used. */
469 #define TCG_CALL_NO_SIDE_EFFECTS 0x0040
471 /* convenience version of most used call flags */
472 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
473 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
474 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
475 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
476 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
478 /* Used to align parameters. See the comment before tcgv_i32_temp. */
479 #define TCG_CALL_DUMMY_ARG ((TCGArg)0)
481 /* Conditions. Note that these are laid out for easy manipulation by
483 bit 0 is used for inverting;
486 bit 3 is used with bit 0 for swapping signed/unsigned. */
489 TCG_COND_NEVER
= 0 | 0 | 0 | 0,
490 TCG_COND_ALWAYS
= 0 | 0 | 0 | 1,
491 TCG_COND_EQ
= 8 | 0 | 0 | 0,
492 TCG_COND_NE
= 8 | 0 | 0 | 1,
494 TCG_COND_LT
= 0 | 0 | 2 | 0,
495 TCG_COND_GE
= 0 | 0 | 2 | 1,
496 TCG_COND_LE
= 8 | 0 | 2 | 0,
497 TCG_COND_GT
= 8 | 0 | 2 | 1,
499 TCG_COND_LTU
= 0 | 4 | 0 | 0,
500 TCG_COND_GEU
= 0 | 4 | 0 | 1,
501 TCG_COND_LEU
= 8 | 4 | 0 | 0,
502 TCG_COND_GTU
= 8 | 4 | 0 | 1,
505 /* Invert the sense of the comparison. */
506 static inline TCGCond
tcg_invert_cond(TCGCond c
)
508 return (TCGCond
)(c
^ 1);
511 /* Swap the operands in a comparison. */
512 static inline TCGCond
tcg_swap_cond(TCGCond c
)
514 return c
& 6 ? (TCGCond
)(c
^ 9) : c
;
517 /* Create an "unsigned" version of a "signed" comparison. */
518 static inline TCGCond
tcg_unsigned_cond(TCGCond c
)
520 return c
& 2 ? (TCGCond
)(c
^ 6) : c
;
523 /* Create a "signed" version of an "unsigned" comparison. */
524 static inline TCGCond
tcg_signed_cond(TCGCond c
)
526 return c
& 4 ? (TCGCond
)(c
^ 6) : c
;
529 /* Must a comparison be considered unsigned? */
530 static inline bool is_unsigned_cond(TCGCond c
)
535 /* Create a "high" version of a double-word comparison.
536 This removes equality from a LTE or GTE comparison. */
537 static inline TCGCond
tcg_high_cond(TCGCond c
)
544 return (TCGCond
)(c
^ 8);
550 typedef enum TCGTempVal
{
557 typedef struct TCGTemp
{
559 TCGTempVal val_type
:8;
562 unsigned int fixed_reg
:1;
563 unsigned int indirect_reg
:1;
564 unsigned int indirect_base
:1;
565 unsigned int mem_coherent
:1;
566 unsigned int mem_allocated
:1;
567 /* If true, the temp is saved across both basic blocks and
568 translation blocks. */
569 unsigned int temp_global
:1;
570 /* If true, the temp is saved across basic blocks but dead
571 at the end of translation blocks. If false, the temp is
572 dead at the end of basic blocks. */
573 unsigned int temp_local
:1;
574 unsigned int temp_allocated
:1;
577 struct TCGTemp
*mem_base
;
581 /* Pass-specific information that can be stored for a temporary.
582 One word worth of integer data, and one pointer to data
583 allocated separately. */
588 typedef struct TCGContext TCGContext
;
590 typedef struct TCGTempSet
{
591 unsigned long l
[BITS_TO_LONGS(TCG_MAX_TEMPS
)];
594 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
595 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
596 There are never more than 2 outputs, which means that we can store all
597 dead + sync data within 16 bits. */
600 typedef uint16_t TCGLifeData
;
602 /* The layout here is designed to avoid a bitfield crossing of
603 a 32-bit boundary, which would cause GCC to add extra padding. */
604 typedef struct TCGOp
{
605 TCGOpcode opc
: 8; /* 8 */
607 /* Parameters for this opcode. See below. */
608 unsigned param1
: 4; /* 12 */
609 unsigned param2
: 4; /* 16 */
611 /* Lifetime data of the operands. */
612 unsigned life
: 16; /* 32 */
614 /* Next and previous opcodes. */
615 QTAILQ_ENTRY(TCGOp
) link
;
617 /* Arguments for the opcode. */
618 TCGArg args
[MAX_OPC_PARAM
];
621 #define TCGOP_CALLI(X) (X)->param1
622 #define TCGOP_CALLO(X) (X)->param2
624 #define TCGOP_VECL(X) (X)->param1
625 #define TCGOP_VECE(X) (X)->param2
627 /* Make sure operands fit in the bitfields above. */
628 QEMU_BUILD_BUG_ON(NB_OPS
> (1 << 8));
630 typedef struct TCGProfile
{
633 int64_t op_count
; /* total insn count */
634 int op_count_max
; /* max insn per TB */
637 int64_t del_op_count
;
639 int64_t code_out_len
;
640 int64_t search_out_len
;
645 int64_t restore_count
;
646 int64_t restore_time
;
647 int64_t table_op_count
[NB_OPS
];
651 uint8_t *pool_cur
, *pool_end
;
652 TCGPool
*pool_first
, *pool_current
, *pool_first_large
;
658 /* goto_tb support */
659 tcg_insn_unit
*code_buf
;
660 uint16_t *tb_jmp_reset_offset
; /* tb->jmp_reset_offset */
661 uintptr_t *tb_jmp_insn_offset
; /* tb->jmp_target_arg if direct_jump */
662 uintptr_t *tb_jmp_target_addr
; /* tb->jmp_target_arg if !direct_jump */
664 TCGRegSet reserved_regs
;
665 uint32_t tb_cflags
; /* cflags of the current TB */
666 intptr_t current_frame_offset
;
667 intptr_t frame_start
;
671 tcg_insn_unit
*code_ptr
;
673 #ifdef CONFIG_PROFILER
677 #ifdef CONFIG_DEBUG_TCG
679 int goto_tb_issue_mask
;
682 /* Code generation. Note that we specifically do not use tcg_insn_unit
683 here, because there's too much arithmetic throughout that relies
684 on addition and subtraction working on bytes. Rely on the GCC
685 extension that allows arithmetic on void*. */
686 void *code_gen_prologue
;
687 void *code_gen_epilogue
;
688 void *code_gen_buffer
;
689 size_t code_gen_buffer_size
;
693 /* Threshold to flush the translated code buffer. */
694 void *code_gen_highwater
;
696 /* Track which vCPU triggers events */
697 CPUState
*cpu
; /* *_trans */
699 /* These structures are private to tcg-target.inc.c. */
700 #ifdef TCG_TARGET_NEED_LDST_LABELS
701 struct TCGLabelQemuLdst
*ldst_labels
;
703 #ifdef TCG_TARGET_NEED_POOL_LABELS
704 struct TCGLabelPoolData
*pool_labels
;
707 TCGLabel
*exitreq_label
;
709 TCGTempSet free_temps
[TCG_TYPE_COUNT
* 2];
710 TCGTemp temps
[TCG_MAX_TEMPS
]; /* globals first, temps after */
712 QTAILQ_HEAD(TCGOpHead
, TCGOp
) ops
, free_ops
;
714 /* Tells which temporary holds a given register.
715 It does not take into account fixed registers */
716 TCGTemp
*reg_to_temp
[TCG_TARGET_NB_REGS
];
718 uint16_t gen_insn_end_off
[TCG_MAX_INSNS
];
719 target_ulong gen_insn_data
[TCG_MAX_INSNS
][TARGET_INSN_START_WORDS
];
722 extern TCGContext tcg_init_ctx
;
723 extern __thread TCGContext
*tcg_ctx
;
724 extern TCGv_env cpu_env
;
726 static inline size_t temp_idx(TCGTemp
*ts
)
728 ptrdiff_t n
= ts
- tcg_ctx
->temps
;
729 tcg_debug_assert(n
>= 0 && n
< tcg_ctx
->nb_temps
);
733 static inline TCGArg
temp_arg(TCGTemp
*ts
)
735 return (uintptr_t)ts
;
738 static inline TCGTemp
*arg_temp(TCGArg a
)
740 return (TCGTemp
*)(uintptr_t)a
;
743 /* Using the offset of a temporary, relative to TCGContext, rather than
744 its index means that we don't use 0. That leaves offset 0 free for
745 a NULL representation without having to leave index 0 unused. */
746 static inline TCGTemp
*tcgv_i32_temp(TCGv_i32 v
)
748 uintptr_t o
= (uintptr_t)v
;
749 TCGTemp
*t
= (void *)tcg_ctx
+ o
;
750 tcg_debug_assert(offsetof(TCGContext
, temps
[temp_idx(t
)]) == o
);
754 static inline TCGTemp
*tcgv_i64_temp(TCGv_i64 v
)
756 return tcgv_i32_temp((TCGv_i32
)v
);
759 static inline TCGTemp
*tcgv_ptr_temp(TCGv_ptr v
)
761 return tcgv_i32_temp((TCGv_i32
)v
);
764 static inline TCGTemp
*tcgv_vec_temp(TCGv_vec v
)
766 return tcgv_i32_temp((TCGv_i32
)v
);
769 static inline TCGArg
tcgv_i32_arg(TCGv_i32 v
)
771 return temp_arg(tcgv_i32_temp(v
));
774 static inline TCGArg
tcgv_i64_arg(TCGv_i64 v
)
776 return temp_arg(tcgv_i64_temp(v
));
779 static inline TCGArg
tcgv_ptr_arg(TCGv_ptr v
)
781 return temp_arg(tcgv_ptr_temp(v
));
784 static inline TCGArg
tcgv_vec_arg(TCGv_vec v
)
786 return temp_arg(tcgv_vec_temp(v
));
789 static inline TCGv_i32
temp_tcgv_i32(TCGTemp
*t
)
791 (void)temp_idx(t
); /* trigger embedded assert */
792 return (TCGv_i32
)((void *)t
- (void *)tcg_ctx
);
795 static inline TCGv_i64
temp_tcgv_i64(TCGTemp
*t
)
797 return (TCGv_i64
)temp_tcgv_i32(t
);
800 static inline TCGv_ptr
temp_tcgv_ptr(TCGTemp
*t
)
802 return (TCGv_ptr
)temp_tcgv_i32(t
);
805 static inline TCGv_vec
temp_tcgv_vec(TCGTemp
*t
)
807 return (TCGv_vec
)temp_tcgv_i32(t
);
810 #if TCG_TARGET_REG_BITS == 32
811 static inline TCGv_i32
TCGV_LOW(TCGv_i64 t
)
813 return temp_tcgv_i32(tcgv_i64_temp(t
));
816 static inline TCGv_i32
TCGV_HIGH(TCGv_i64 t
)
818 return temp_tcgv_i32(tcgv_i64_temp(t
) + 1);
822 static inline void tcg_set_insn_param(TCGOp
*op
, int arg
, TCGArg v
)
827 /* The last op that was emitted. */
828 static inline TCGOp
*tcg_last_op(void)
830 return QTAILQ_LAST(&tcg_ctx
->ops
, TCGOpHead
);
833 /* Test for whether to terminate the TB for using too many opcodes. */
834 static inline bool tcg_op_buf_full(void)
839 /* pool based memory allocation */
841 /* user-mode: tb_lock must be held for tcg_malloc_internal. */
842 void *tcg_malloc_internal(TCGContext
*s
, int size
);
843 void tcg_pool_reset(TCGContext
*s
);
844 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
);
846 void tcg_region_init(void);
847 void tcg_region_reset_all(void);
849 size_t tcg_code_size(void);
850 size_t tcg_code_capacity(void);
852 /* user-mode: Called with tb_lock held. */
853 static inline void *tcg_malloc(int size
)
855 TCGContext
*s
= tcg_ctx
;
856 uint8_t *ptr
, *ptr_end
;
858 /* ??? This is a weak placeholder for minimum malloc alignment. */
859 size
= QEMU_ALIGN_UP(size
, 8);
862 ptr_end
= ptr
+ size
;
863 if (unlikely(ptr_end
> s
->pool_end
)) {
864 return tcg_malloc_internal(tcg_ctx
, size
);
866 s
->pool_cur
= ptr_end
;
871 void tcg_context_init(TCGContext
*s
);
872 void tcg_register_thread(void);
873 void tcg_prologue_init(TCGContext
*s
);
874 void tcg_func_start(TCGContext
*s
);
876 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
);
878 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
);
880 TCGTemp
*tcg_global_mem_new_internal(TCGType
, TCGv_ptr
,
881 intptr_t, const char *);
883 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
);
884 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
);
885 TCGv_vec
tcg_temp_new_vec(TCGType type
);
886 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
);
888 void tcg_temp_free_i32(TCGv_i32 arg
);
889 void tcg_temp_free_i64(TCGv_i64 arg
);
890 void tcg_temp_free_vec(TCGv_vec arg
);
892 static inline TCGv_i32
tcg_global_mem_new_i32(TCGv_ptr reg
, intptr_t offset
,
895 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
896 return temp_tcgv_i32(t
);
899 static inline TCGv_i32
tcg_temp_new_i32(void)
901 return tcg_temp_new_internal_i32(0);
904 static inline TCGv_i32
tcg_temp_local_new_i32(void)
906 return tcg_temp_new_internal_i32(1);
909 static inline TCGv_i64
tcg_global_mem_new_i64(TCGv_ptr reg
, intptr_t offset
,
912 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
913 return temp_tcgv_i64(t
);
916 static inline TCGv_i64
tcg_temp_new_i64(void)
918 return tcg_temp_new_internal_i64(0);
921 static inline TCGv_i64
tcg_temp_local_new_i64(void)
923 return tcg_temp_new_internal_i64(1);
926 #if defined(CONFIG_DEBUG_TCG)
927 /* If you call tcg_clear_temp_count() at the start of a section of
928 * code which is not supposed to leak any TCG temporaries, then
929 * calling tcg_check_temp_count() at the end of the section will
930 * return 1 if the section did in fact leak a temporary.
932 void tcg_clear_temp_count(void);
933 int tcg_check_temp_count(void);
935 #define tcg_clear_temp_count() do { } while (0)
936 #define tcg_check_temp_count() 0
939 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
);
940 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
);
942 #define TCG_CT_ALIAS 0x80
943 #define TCG_CT_IALIAS 0x40
944 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
945 #define TCG_CT_REG 0x01
946 #define TCG_CT_CONST 0x02 /* any constant of register size */
948 typedef struct TCGArgConstraint
{
956 #define TCG_MAX_OP_ARGS 16
958 /* Bits for TCGOpDef->flags, 8 bits available. */
960 /* Instruction defines the end of a basic block. */
961 TCG_OPF_BB_END
= 0x01,
962 /* Instruction clobbers call registers and potentially update globals. */
963 TCG_OPF_CALL_CLOBBER
= 0x02,
964 /* Instruction has side effects: it cannot be removed if its outputs
965 are not used, and might trigger exceptions. */
966 TCG_OPF_SIDE_EFFECTS
= 0x04,
967 /* Instruction operands are 64-bits (otherwise 32-bits). */
968 TCG_OPF_64BIT
= 0x08,
969 /* Instruction is optional and not implemented by the host, or insn
970 is generic and should not be implemened by the host. */
971 TCG_OPF_NOT_PRESENT
= 0x10,
972 /* Instruction operands are vectors. */
973 TCG_OPF_VECTOR
= 0x20,
976 typedef struct TCGOpDef
{
978 uint8_t nb_oargs
, nb_iargs
, nb_cargs
, nb_args
;
980 TCGArgConstraint
*args_ct
;
982 #if defined(CONFIG_DEBUG_TCG)
987 extern TCGOpDef tcg_op_defs
[];
988 extern const size_t tcg_op_defs_max
;
990 typedef struct TCGTargetOpDef
{
992 const char *args_ct_str
[TCG_MAX_OP_ARGS
];
995 #define tcg_abort() \
997 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1001 #if UINTPTR_MAX == UINT32_MAX
1002 static inline TCGv_ptr
TCGV_NAT_TO_PTR(TCGv_i32 n
) { return (TCGv_ptr
)n
; }
1003 static inline TCGv_i32
TCGV_PTR_TO_NAT(TCGv_ptr n
) { return (TCGv_i32
)n
; }
1005 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
1006 #define tcg_global_mem_new_ptr(R, O, N) \
1007 TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
1008 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
1009 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
1011 static inline TCGv_ptr
TCGV_NAT_TO_PTR(TCGv_i64 n
) { return (TCGv_ptr
)n
; }
1012 static inline TCGv_i64
TCGV_PTR_TO_NAT(TCGv_ptr n
) { return (TCGv_i64
)n
; }
1014 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
1015 #define tcg_global_mem_new_ptr(R, O, N) \
1016 TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
1017 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
1018 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
1021 bool tcg_op_supported(TCGOpcode op
);
1023 void tcg_gen_callN(void *func
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
);
1025 TCGOp
*tcg_emit_op(TCGOpcode opc
);
1026 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
);
1027 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
, int narg
);
1028 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
, int narg
);
1030 void tcg_optimize(TCGContext
*s
);
1032 /* only used for debugging purposes */
1033 void tcg_dump_ops(TCGContext
*s
);
1035 TCGv_i32
tcg_const_i32(int32_t val
);
1036 TCGv_i64
tcg_const_i64(int64_t val
);
1037 TCGv_i32
tcg_const_local_i32(int32_t val
);
1038 TCGv_i64
tcg_const_local_i64(int64_t val
);
1039 TCGv_vec
tcg_const_zeros_vec(TCGType
);
1040 TCGv_vec
tcg_const_ones_vec(TCGType
);
1041 TCGv_vec
tcg_const_zeros_vec_matching(TCGv_vec
);
1042 TCGv_vec
tcg_const_ones_vec_matching(TCGv_vec
);
1044 TCGLabel
*gen_new_label(void);
1050 * Encode a label for storage in the TCG opcode stream.
1053 static inline TCGArg
label_arg(TCGLabel
*l
)
1055 return (uintptr_t)l
;
1062 * The opposite of label_arg. Retrieve a label from the
1063 * encoding of the TCG opcode stream.
1066 static inline TCGLabel
*arg_label(TCGArg i
)
1068 return (TCGLabel
*)(uintptr_t)i
;
1073 * @a, @b: addresses to be differenced
1075 * There are many places within the TCG backends where we need a byte
1076 * difference between two pointers. While this can be accomplished
1077 * with local casting, it's easy to get wrong -- especially if one is
1078 * concerned with the signedness of the result.
1080 * This version relies on GCC's void pointer arithmetic to get the
1084 static inline ptrdiff_t tcg_ptr_byte_diff(void *a
, void *b
)
1091 * @s: the tcg context
1092 * @target: address of the target
1094 * Produce a pc-relative difference, from the current code_ptr
1095 * to the destination address.
1098 static inline ptrdiff_t tcg_pcrel_diff(TCGContext
*s
, void *target
)
1100 return tcg_ptr_byte_diff(target
, s
->code_ptr
);
1104 * tcg_current_code_size
1105 * @s: the tcg context
1107 * Compute the current code size within the translation block.
1108 * This is used to fill in qemu's data structures for goto_tb.
1111 static inline size_t tcg_current_code_size(TCGContext
*s
)
1113 return tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
);
1116 /* Combine the TCGMemOp and mmu_idx parameters into a single value. */
1117 typedef uint32_t TCGMemOpIdx
;
1121 * @op: memory operation
1124 * Encode these values into a single parameter.
1126 static inline TCGMemOpIdx
make_memop_idx(TCGMemOp op
, unsigned idx
)
1128 tcg_debug_assert(idx
<= 15);
1129 return (op
<< 4) | idx
;
1134 * @oi: combined op/idx parameter
1136 * Extract the memory operation from the combined value.
1138 static inline TCGMemOp
get_memop(TCGMemOpIdx oi
)
1145 * @oi: combined op/idx parameter
1147 * Extract the mmu index from the combined value.
1149 static inline unsigned get_mmuidx(TCGMemOpIdx oi
)
1156 * @env: pointer to CPUArchState for the CPU
1157 * @tb_ptr: address of generated code for the TB to execute
1159 * Start executing code from a given translation block.
1160 * Where translation blocks have been linked, execution
1161 * may proceed from the given TB into successive ones.
1162 * Control eventually returns only when some action is needed
1163 * from the top-level loop: either control must pass to a TB
1164 * which has not yet been directly linked, or an asynchronous
1165 * event such as an interrupt needs handling.
1167 * Return: The return value is the value passed to the corresponding
1168 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1169 * The value is either zero or a 4-byte aligned pointer to that TB combined
1170 * with additional information in its two least significant bits. The
1171 * additional information is encoded as follows:
1172 * 0, 1: the link between this TB and the next is via the specified
1173 * TB index (0 or 1). That is, we left the TB via (the equivalent
1174 * of) "goto_tb <index>". The main loop uses this to determine
1175 * how to link the TB just executed to the next.
1176 * 2: we are using instruction counting code generation, and we
1177 * did not start executing this TB because the instruction counter
1178 * would hit zero midway through it. In this case the pointer
1179 * returned is the TB we were about to execute, and the caller must
1180 * arrange to execute the remaining count of instructions.
1181 * 3: we stopped because the CPU's exit_request flag was set
1182 * (usually meaning that there is an interrupt that needs to be
1183 * handled). The pointer returned is the TB we were about to execute
1184 * when we noticed the pending exit request.
1186 * If the bottom two bits indicate an exit-via-index then the CPU
1187 * state is correctly synchronised and ready for execution of the next
1188 * TB (and in particular the guest PC is the address to execute next).
1189 * Otherwise, we gave up on execution of this TB before it started, and
1190 * the caller must fix up the CPU state by calling the CPU's
1191 * synchronize_from_tb() method with the TB pointer we return (falling
1192 * back to calling the CPU's set_pc method with tb->pb if no
1193 * synchronize_from_tb() method exists).
1195 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1196 * to this default (which just calls the prologue.code emitted by
1197 * tcg_target_qemu_prologue()).
1199 #define TB_EXIT_MASK 3
1200 #define TB_EXIT_IDX0 0
1201 #define TB_EXIT_IDX1 1
1202 #define TB_EXIT_REQUESTED 3
1204 #ifdef HAVE_TCG_QEMU_TB_EXEC
1205 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
);
1207 # define tcg_qemu_tb_exec(env, tb_ptr) \
1208 ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1211 void tcg_register_jit(void *buf
, size_t buf_size
);
1213 #if TCG_TARGET_MAYBE_vec
1214 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1215 return > 0 if it is directly supportable;
1216 return < 0 if we must call tcg_expand_vec_op. */
1217 int tcg_can_emit_vec_op(TCGOpcode
, TCGType
, unsigned);
1219 static inline int tcg_can_emit_vec_op(TCGOpcode o
, TCGType t
, unsigned ve
)
1225 /* Expand the tuple (opc, type, vece) on the given arguments. */
1226 void tcg_expand_vec_op(TCGOpcode
, TCGType
, unsigned, TCGArg
, ...);
1228 /* Replicate a constant C accoring to the log2 of the element size. */
1229 uint64_t dup_const(unsigned vece
, uint64_t c
);
1231 #define dup_const(VECE, C) \
1232 (__builtin_constant_p(VECE) \
1233 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
1234 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
1235 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
1236 : dup_const(VECE, C)) \
1237 : dup_const(VECE, C))
1241 * Memory helpers that will be used by TCG generated code.
1243 #ifdef CONFIG_SOFTMMU
1244 /* Value zero-extended to tcg register size. */
1245 tcg_target_ulong
helper_ret_ldub_mmu(CPUArchState
*env
, target_ulong addr
,
1246 TCGMemOpIdx oi
, uintptr_t retaddr
);
1247 tcg_target_ulong
helper_le_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1248 TCGMemOpIdx oi
, uintptr_t retaddr
);
1249 tcg_target_ulong
helper_le_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1250 TCGMemOpIdx oi
, uintptr_t retaddr
);
1251 uint64_t helper_le_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1252 TCGMemOpIdx oi
, uintptr_t retaddr
);
1253 tcg_target_ulong
helper_be_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1254 TCGMemOpIdx oi
, uintptr_t retaddr
);
1255 tcg_target_ulong
helper_be_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1256 TCGMemOpIdx oi
, uintptr_t retaddr
);
1257 uint64_t helper_be_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1258 TCGMemOpIdx oi
, uintptr_t retaddr
);
1260 /* Value sign-extended to tcg register size. */
1261 tcg_target_ulong
helper_ret_ldsb_mmu(CPUArchState
*env
, target_ulong addr
,
1262 TCGMemOpIdx oi
, uintptr_t retaddr
);
1263 tcg_target_ulong
helper_le_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1264 TCGMemOpIdx oi
, uintptr_t retaddr
);
1265 tcg_target_ulong
helper_le_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1266 TCGMemOpIdx oi
, uintptr_t retaddr
);
1267 tcg_target_ulong
helper_be_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1268 TCGMemOpIdx oi
, uintptr_t retaddr
);
1269 tcg_target_ulong
helper_be_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1270 TCGMemOpIdx oi
, uintptr_t retaddr
);
1272 void helper_ret_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
1273 TCGMemOpIdx oi
, uintptr_t retaddr
);
1274 void helper_le_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1275 TCGMemOpIdx oi
, uintptr_t retaddr
);
1276 void helper_le_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1277 TCGMemOpIdx oi
, uintptr_t retaddr
);
1278 void helper_le_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1279 TCGMemOpIdx oi
, uintptr_t retaddr
);
1280 void helper_be_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1281 TCGMemOpIdx oi
, uintptr_t retaddr
);
1282 void helper_be_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1283 TCGMemOpIdx oi
, uintptr_t retaddr
);
1284 void helper_be_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1285 TCGMemOpIdx oi
, uintptr_t retaddr
);
1287 uint8_t helper_ret_ldb_cmmu(CPUArchState
*env
, target_ulong addr
,
1288 TCGMemOpIdx oi
, uintptr_t retaddr
);
1289 uint16_t helper_le_ldw_cmmu(CPUArchState
*env
, target_ulong addr
,
1290 TCGMemOpIdx oi
, uintptr_t retaddr
);
1291 uint32_t helper_le_ldl_cmmu(CPUArchState
*env
, target_ulong addr
,
1292 TCGMemOpIdx oi
, uintptr_t retaddr
);
1293 uint64_t helper_le_ldq_cmmu(CPUArchState
*env
, target_ulong addr
,
1294 TCGMemOpIdx oi
, uintptr_t retaddr
);
1295 uint16_t helper_be_ldw_cmmu(CPUArchState
*env
, target_ulong addr
,
1296 TCGMemOpIdx oi
, uintptr_t retaddr
);
1297 uint32_t helper_be_ldl_cmmu(CPUArchState
*env
, target_ulong addr
,
1298 TCGMemOpIdx oi
, uintptr_t retaddr
);
1299 uint64_t helper_be_ldq_cmmu(CPUArchState
*env
, target_ulong addr
,
1300 TCGMemOpIdx oi
, uintptr_t retaddr
);
1302 /* Temporary aliases until backends are converted. */
1303 #ifdef TARGET_WORDS_BIGENDIAN
1304 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1305 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1306 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1307 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1308 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1309 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1310 # define helper_ret_stw_mmu helper_be_stw_mmu
1311 # define helper_ret_stl_mmu helper_be_stl_mmu
1312 # define helper_ret_stq_mmu helper_be_stq_mmu
1313 # define helper_ret_ldw_cmmu helper_be_ldw_cmmu
1314 # define helper_ret_ldl_cmmu helper_be_ldl_cmmu
1315 # define helper_ret_ldq_cmmu helper_be_ldq_cmmu
1317 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1318 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1319 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1320 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1321 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1322 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1323 # define helper_ret_stw_mmu helper_le_stw_mmu
1324 # define helper_ret_stl_mmu helper_le_stl_mmu
1325 # define helper_ret_stq_mmu helper_le_stq_mmu
1326 # define helper_ret_ldw_cmmu helper_le_ldw_cmmu
1327 # define helper_ret_ldl_cmmu helper_le_ldl_cmmu
1328 # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
1331 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState
*env
, target_ulong addr
,
1332 uint32_t cmpv
, uint32_t newv
,
1333 TCGMemOpIdx oi
, uintptr_t retaddr
);
1334 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState
*env
, target_ulong addr
,
1335 uint32_t cmpv
, uint32_t newv
,
1336 TCGMemOpIdx oi
, uintptr_t retaddr
);
1337 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState
*env
, target_ulong addr
,
1338 uint32_t cmpv
, uint32_t newv
,
1339 TCGMemOpIdx oi
, uintptr_t retaddr
);
1340 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState
*env
, target_ulong addr
,
1341 uint64_t cmpv
, uint64_t newv
,
1342 TCGMemOpIdx oi
, uintptr_t retaddr
);
1343 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState
*env
, target_ulong addr
,
1344 uint32_t cmpv
, uint32_t newv
,
1345 TCGMemOpIdx oi
, uintptr_t retaddr
);
1346 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState
*env
, target_ulong addr
,
1347 uint32_t cmpv
, uint32_t newv
,
1348 TCGMemOpIdx oi
, uintptr_t retaddr
);
1349 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState
*env
, target_ulong addr
,
1350 uint64_t cmpv
, uint64_t newv
,
1351 TCGMemOpIdx oi
, uintptr_t retaddr
);
1353 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
1354 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
1355 (CPUArchState *env, target_ulong addr, TYPE val, \
1356 TCGMemOpIdx oi, uintptr_t retaddr);
1358 #ifdef CONFIG_ATOMIC64
1359 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1360 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1361 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1362 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1363 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1364 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
1365 GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
1366 GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1368 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1369 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1370 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1371 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1372 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1373 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1376 GEN_ATOMIC_HELPER_ALL(fetch_add
)
1377 GEN_ATOMIC_HELPER_ALL(fetch_sub
)
1378 GEN_ATOMIC_HELPER_ALL(fetch_and
)
1379 GEN_ATOMIC_HELPER_ALL(fetch_or
)
1380 GEN_ATOMIC_HELPER_ALL(fetch_xor
)
1382 GEN_ATOMIC_HELPER_ALL(add_fetch
)
1383 GEN_ATOMIC_HELPER_ALL(sub_fetch
)
1384 GEN_ATOMIC_HELPER_ALL(and_fetch
)
1385 GEN_ATOMIC_HELPER_ALL(or_fetch
)
1386 GEN_ATOMIC_HELPER_ALL(xor_fetch
)
1388 GEN_ATOMIC_HELPER_ALL(xchg
)
1390 #undef GEN_ATOMIC_HELPER_ALL
1391 #undef GEN_ATOMIC_HELPER
1392 #endif /* CONFIG_SOFTMMU */
1394 #ifdef CONFIG_ATOMIC128
1395 #include "qemu/int128.h"
1397 /* These aren't really a "proper" helpers because TCG cannot manage Int128.
1398 However, use the same format as the others, for use by the backends. */
1399 Int128
helper_atomic_cmpxchgo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1400 Int128 cmpv
, Int128 newv
,
1401 TCGMemOpIdx oi
, uintptr_t retaddr
);
1402 Int128
helper_atomic_cmpxchgo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1403 Int128 cmpv
, Int128 newv
,
1404 TCGMemOpIdx oi
, uintptr_t retaddr
);
1406 Int128
helper_atomic_ldo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1407 TCGMemOpIdx oi
, uintptr_t retaddr
);
1408 Int128
helper_atomic_ldo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1409 TCGMemOpIdx oi
, uintptr_t retaddr
);
1410 void helper_atomic_sto_le_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1411 TCGMemOpIdx oi
, uintptr_t retaddr
);
1412 void helper_atomic_sto_be_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1413 TCGMemOpIdx oi
, uintptr_t retaddr
);
1415 #endif /* CONFIG_ATOMIC128 */