2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "tcg-be-null.h"
29 * - See TODO comments in code.
32 /* Marker for missing code. */
35 fprintf(stderr, "TODO %s:%u: %s()\n", \
36 __FILE__, __LINE__, __func__); \
40 /* Bitfield n...m (in 32 bit value). */
41 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
43 /* Macros used in tcg_target_op_defs. */
46 #if TCG_TARGET_REG_BITS == 32
51 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
59 /* TODO: documentation. */
60 static const TCGTargetOpDef tcg_target_op_defs
[] = {
61 { INDEX_op_exit_tb
, { NULL
} },
62 { INDEX_op_goto_tb
, { NULL
} },
63 { INDEX_op_br
, { NULL
} },
65 { INDEX_op_ld8u_i32
, { R
, R
} },
66 { INDEX_op_ld8s_i32
, { R
, R
} },
67 { INDEX_op_ld16u_i32
, { R
, R
} },
68 { INDEX_op_ld16s_i32
, { R
, R
} },
69 { INDEX_op_ld_i32
, { R
, R
} },
70 { INDEX_op_st8_i32
, { R
, R
} },
71 { INDEX_op_st16_i32
, { R
, R
} },
72 { INDEX_op_st_i32
, { R
, R
} },
74 { INDEX_op_add_i32
, { R
, RI
, RI
} },
75 { INDEX_op_sub_i32
, { R
, RI
, RI
} },
76 { INDEX_op_mul_i32
, { R
, RI
, RI
} },
77 #if TCG_TARGET_HAS_div_i32
78 { INDEX_op_div_i32
, { R
, R
, R
} },
79 { INDEX_op_divu_i32
, { R
, R
, R
} },
80 { INDEX_op_rem_i32
, { R
, R
, R
} },
81 { INDEX_op_remu_i32
, { R
, R
, R
} },
82 #elif TCG_TARGET_HAS_div2_i32
83 { INDEX_op_div2_i32
, { R
, R
, "0", "1", R
} },
84 { INDEX_op_divu2_i32
, { R
, R
, "0", "1", R
} },
86 /* TODO: Does R, RI, RI result in faster code than R, R, RI?
87 If both operands are constants, we can optimize. */
88 { INDEX_op_and_i32
, { R
, RI
, RI
} },
89 #if TCG_TARGET_HAS_andc_i32
90 { INDEX_op_andc_i32
, { R
, RI
, RI
} },
92 #if TCG_TARGET_HAS_eqv_i32
93 { INDEX_op_eqv_i32
, { R
, RI
, RI
} },
95 #if TCG_TARGET_HAS_nand_i32
96 { INDEX_op_nand_i32
, { R
, RI
, RI
} },
98 #if TCG_TARGET_HAS_nor_i32
99 { INDEX_op_nor_i32
, { R
, RI
, RI
} },
101 { INDEX_op_or_i32
, { R
, RI
, RI
} },
102 #if TCG_TARGET_HAS_orc_i32
103 { INDEX_op_orc_i32
, { R
, RI
, RI
} },
105 { INDEX_op_xor_i32
, { R
, RI
, RI
} },
106 { INDEX_op_shl_i32
, { R
, RI
, RI
} },
107 { INDEX_op_shr_i32
, { R
, RI
, RI
} },
108 { INDEX_op_sar_i32
, { R
, RI
, RI
} },
109 #if TCG_TARGET_HAS_rot_i32
110 { INDEX_op_rotl_i32
, { R
, RI
, RI
} },
111 { INDEX_op_rotr_i32
, { R
, RI
, RI
} },
113 #if TCG_TARGET_HAS_deposit_i32
114 { INDEX_op_deposit_i32
, { R
, "0", R
} },
117 { INDEX_op_brcond_i32
, { R
, RI
} },
119 { INDEX_op_setcond_i32
, { R
, R
, RI
} },
120 #if TCG_TARGET_REG_BITS == 64
121 { INDEX_op_setcond_i64
, { R
, R
, RI
} },
122 #endif /* TCG_TARGET_REG_BITS == 64 */
124 #if TCG_TARGET_REG_BITS == 32
125 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
126 { INDEX_op_add2_i32
, { R
, R
, R
, R
, R
, R
} },
127 { INDEX_op_sub2_i32
, { R
, R
, R
, R
, R
, R
} },
128 { INDEX_op_brcond2_i32
, { R
, R
, RI
, RI
} },
129 { INDEX_op_mulu2_i32
, { R
, R
, R
, R
} },
130 { INDEX_op_setcond2_i32
, { R
, R
, R
, RI
, RI
} },
133 #if TCG_TARGET_HAS_not_i32
134 { INDEX_op_not_i32
, { R
, R
} },
136 #if TCG_TARGET_HAS_neg_i32
137 { INDEX_op_neg_i32
, { R
, R
} },
140 #if TCG_TARGET_REG_BITS == 64
141 { INDEX_op_ld8u_i64
, { R
, R
} },
142 { INDEX_op_ld8s_i64
, { R
, R
} },
143 { INDEX_op_ld16u_i64
, { R
, R
} },
144 { INDEX_op_ld16s_i64
, { R
, R
} },
145 { INDEX_op_ld32u_i64
, { R
, R
} },
146 { INDEX_op_ld32s_i64
, { R
, R
} },
147 { INDEX_op_ld_i64
, { R
, R
} },
149 { INDEX_op_st8_i64
, { R
, R
} },
150 { INDEX_op_st16_i64
, { R
, R
} },
151 { INDEX_op_st32_i64
, { R
, R
} },
152 { INDEX_op_st_i64
, { R
, R
} },
154 { INDEX_op_add_i64
, { R
, RI
, RI
} },
155 { INDEX_op_sub_i64
, { R
, RI
, RI
} },
156 { INDEX_op_mul_i64
, { R
, RI
, RI
} },
157 #if TCG_TARGET_HAS_div_i64
158 { INDEX_op_div_i64
, { R
, R
, R
} },
159 { INDEX_op_divu_i64
, { R
, R
, R
} },
160 { INDEX_op_rem_i64
, { R
, R
, R
} },
161 { INDEX_op_remu_i64
, { R
, R
, R
} },
162 #elif TCG_TARGET_HAS_div2_i64
163 { INDEX_op_div2_i64
, { R
, R
, "0", "1", R
} },
164 { INDEX_op_divu2_i64
, { R
, R
, "0", "1", R
} },
166 { INDEX_op_and_i64
, { R
, RI
, RI
} },
167 #if TCG_TARGET_HAS_andc_i64
168 { INDEX_op_andc_i64
, { R
, RI
, RI
} },
170 #if TCG_TARGET_HAS_eqv_i64
171 { INDEX_op_eqv_i64
, { R
, RI
, RI
} },
173 #if TCG_TARGET_HAS_nand_i64
174 { INDEX_op_nand_i64
, { R
, RI
, RI
} },
176 #if TCG_TARGET_HAS_nor_i64
177 { INDEX_op_nor_i64
, { R
, RI
, RI
} },
179 { INDEX_op_or_i64
, { R
, RI
, RI
} },
180 #if TCG_TARGET_HAS_orc_i64
181 { INDEX_op_orc_i64
, { R
, RI
, RI
} },
183 { INDEX_op_xor_i64
, { R
, RI
, RI
} },
184 { INDEX_op_shl_i64
, { R
, RI
, RI
} },
185 { INDEX_op_shr_i64
, { R
, RI
, RI
} },
186 { INDEX_op_sar_i64
, { R
, RI
, RI
} },
187 #if TCG_TARGET_HAS_rot_i64
188 { INDEX_op_rotl_i64
, { R
, RI
, RI
} },
189 { INDEX_op_rotr_i64
, { R
, RI
, RI
} },
191 #if TCG_TARGET_HAS_deposit_i64
192 { INDEX_op_deposit_i64
, { R
, "0", R
} },
194 { INDEX_op_brcond_i64
, { R
, RI
} },
196 #if TCG_TARGET_HAS_ext8s_i64
197 { INDEX_op_ext8s_i64
, { R
, R
} },
199 #if TCG_TARGET_HAS_ext16s_i64
200 { INDEX_op_ext16s_i64
, { R
, R
} },
202 #if TCG_TARGET_HAS_ext32s_i64
203 { INDEX_op_ext32s_i64
, { R
, R
} },
205 #if TCG_TARGET_HAS_ext8u_i64
206 { INDEX_op_ext8u_i64
, { R
, R
} },
208 #if TCG_TARGET_HAS_ext16u_i64
209 { INDEX_op_ext16u_i64
, { R
, R
} },
211 #if TCG_TARGET_HAS_ext32u_i64
212 { INDEX_op_ext32u_i64
, { R
, R
} },
214 { INDEX_op_ext_i32_i64
, { R
, R
} },
215 { INDEX_op_extu_i32_i64
, { R
, R
} },
216 #if TCG_TARGET_HAS_bswap16_i64
217 { INDEX_op_bswap16_i64
, { R
, R
} },
219 #if TCG_TARGET_HAS_bswap32_i64
220 { INDEX_op_bswap32_i64
, { R
, R
} },
222 #if TCG_TARGET_HAS_bswap64_i64
223 { INDEX_op_bswap64_i64
, { R
, R
} },
225 #if TCG_TARGET_HAS_not_i64
226 { INDEX_op_not_i64
, { R
, R
} },
228 #if TCG_TARGET_HAS_neg_i64
229 { INDEX_op_neg_i64
, { R
, R
} },
231 #endif /* TCG_TARGET_REG_BITS == 64 */
233 { INDEX_op_qemu_ld_i32
, { R
, L
} },
234 { INDEX_op_qemu_ld_i64
, { R64
, L
} },
236 { INDEX_op_qemu_st_i32
, { R
, S
} },
237 { INDEX_op_qemu_st_i64
, { R64
, S
} },
239 #if TCG_TARGET_HAS_ext8s_i32
240 { INDEX_op_ext8s_i32
, { R
, R
} },
242 #if TCG_TARGET_HAS_ext16s_i32
243 { INDEX_op_ext16s_i32
, { R
, R
} },
245 #if TCG_TARGET_HAS_ext8u_i32
246 { INDEX_op_ext8u_i32
, { R
, R
} },
248 #if TCG_TARGET_HAS_ext16u_i32
249 { INDEX_op_ext16u_i32
, { R
, R
} },
252 #if TCG_TARGET_HAS_bswap16_i32
253 { INDEX_op_bswap16_i32
, { R
, R
} },
255 #if TCG_TARGET_HAS_bswap32_i32
256 { INDEX_op_bswap32_i32
, { R
, R
} },
262 static const int tcg_target_reg_alloc_order
[] = {
267 #if 0 /* used for TCG_REG_CALL_STACK */
273 #if TCG_TARGET_NB_REGS >= 16
285 #if MAX_OPC_PARAM_IARGS != 5
286 # error Fix needed, number of supported input arguments changed!
289 static const int tcg_target_call_iarg_regs
[] = {
294 #if 0 /* used for TCG_REG_CALL_STACK */
298 #if TCG_TARGET_REG_BITS == 32
299 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
302 #if TCG_TARGET_NB_REGS >= 16
307 # error Too few input registers available
312 static const int tcg_target_call_oarg_regs
[] = {
314 #if TCG_TARGET_REG_BITS == 32
320 static const char *const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
329 #if TCG_TARGET_NB_REGS >= 16
338 #if TCG_TARGET_NB_REGS >= 32
360 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
361 intptr_t value
, intptr_t addend
)
363 /* tcg_out_reloc always uses the same type, addend. */
364 assert(type
== sizeof(tcg_target_long
));
367 if (TCG_TARGET_REG_BITS
== 32) {
368 tcg_patch32(code_ptr
, value
);
370 tcg_patch64(code_ptr
, value
);
374 /* Parse target specific constraints. */
375 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
377 const char *ct_str
= *pct_str
;
380 case 'L': /* qemu_ld constraint */
381 case 'S': /* qemu_st constraint */
382 ct
->ct
|= TCG_CT_REG
;
383 tcg_regset_set32(ct
->u
.regs
, 0, BIT(TCG_TARGET_NB_REGS
) - 1);
393 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
394 /* Show current bytecode. Used by tcg interpreter. */
395 void tci_disas(uint8_t opc
)
397 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
398 fprintf(stderr
, "TCG %s %u, %u, %u\n",
399 def
->name
, def
->nb_oargs
, def
->nb_iargs
, def
->nb_cargs
);
403 /* Write value (native size). */
404 static void tcg_out_i(TCGContext
*s
, tcg_target_ulong v
)
406 if (TCG_TARGET_REG_BITS
== 32) {
414 static void tcg_out_op_t(TCGContext
*s
, TCGOpcode op
)
420 /* Write register. */
421 static void tcg_out_r(TCGContext
*s
, TCGArg t0
)
423 assert(t0
< TCG_TARGET_NB_REGS
);
427 /* Write register or constant (native size). */
428 static void tcg_out_ri(TCGContext
*s
, int const_arg
, TCGArg arg
)
431 assert(const_arg
== 1);
432 tcg_out8(s
, TCG_CONST
);
439 /* Write register or constant (32 bit). */
440 static void tcg_out_ri32(TCGContext
*s
, int const_arg
, TCGArg arg
)
443 assert(const_arg
== 1);
444 tcg_out8(s
, TCG_CONST
);
451 #if TCG_TARGET_REG_BITS == 64
452 /* Write register or constant (64 bit). */
453 static void tcg_out_ri64(TCGContext
*s
, int const_arg
, TCGArg arg
)
456 assert(const_arg
== 1);
457 tcg_out8(s
, TCG_CONST
);
466 static void tci_out_label(TCGContext
*s
, TCGLabel
*label
)
468 if (label
->has_value
) {
469 tcg_out_i(s
, label
->u
.value
);
470 assert(label
->u
.value
);
472 tcg_out_reloc(s
, s
->code_ptr
, sizeof(tcg_target_ulong
), label
, 0);
473 s
->code_ptr
+= sizeof(tcg_target_ulong
);
477 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
480 uint8_t *old_code_ptr
= s
->code_ptr
;
481 if (type
== TCG_TYPE_I32
) {
482 tcg_out_op_t(s
, INDEX_op_ld_i32
);
487 assert(type
== TCG_TYPE_I64
);
488 #if TCG_TARGET_REG_BITS == 64
489 tcg_out_op_t(s
, INDEX_op_ld_i64
);
492 assert(arg2
== (int32_t)arg2
);
498 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
501 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
503 uint8_t *old_code_ptr
= s
->code_ptr
;
505 #if TCG_TARGET_REG_BITS == 32
506 tcg_out_op_t(s
, INDEX_op_mov_i32
);
508 tcg_out_op_t(s
, INDEX_op_mov_i64
);
512 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
515 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
516 TCGReg t0
, tcg_target_long arg
)
518 uint8_t *old_code_ptr
= s
->code_ptr
;
519 uint32_t arg32
= arg
;
520 if (type
== TCG_TYPE_I32
|| arg
== arg32
) {
521 tcg_out_op_t(s
, INDEX_op_movi_i32
);
525 assert(type
== TCG_TYPE_I64
);
526 #if TCG_TARGET_REG_BITS == 64
527 tcg_out_op_t(s
, INDEX_op_movi_i64
);
534 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
537 static inline void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*arg
)
539 uint8_t *old_code_ptr
= s
->code_ptr
;
540 tcg_out_op_t(s
, INDEX_op_call
);
541 tcg_out_ri(s
, 1, (uintptr_t)arg
);
542 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
545 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
546 const int *const_args
)
548 uint8_t *old_code_ptr
= s
->code_ptr
;
550 tcg_out_op_t(s
, opc
);
553 case INDEX_op_exit_tb
:
554 tcg_out64(s
, args
[0]);
556 case INDEX_op_goto_tb
:
557 if (s
->tb_jmp_offset
) {
558 /* Direct jump method. */
559 assert(args
[0] < ARRAY_SIZE(s
->tb_jmp_offset
));
560 s
->tb_jmp_offset
[args
[0]] = tcg_current_code_size(s
);
563 /* Indirect jump method. */
566 assert(args
[0] < ARRAY_SIZE(s
->tb_next_offset
));
567 s
->tb_next_offset
[args
[0]] = tcg_current_code_size(s
);
570 tci_out_label(s
, arg_label(args
[0]));
572 case INDEX_op_setcond_i32
:
573 tcg_out_r(s
, args
[0]);
574 tcg_out_r(s
, args
[1]);
575 tcg_out_ri32(s
, const_args
[2], args
[2]);
576 tcg_out8(s
, args
[3]); /* condition */
578 #if TCG_TARGET_REG_BITS == 32
579 case INDEX_op_setcond2_i32
:
580 /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
581 tcg_out_r(s
, args
[0]);
582 tcg_out_r(s
, args
[1]);
583 tcg_out_r(s
, args
[2]);
584 tcg_out_ri32(s
, const_args
[3], args
[3]);
585 tcg_out_ri32(s
, const_args
[4], args
[4]);
586 tcg_out8(s
, args
[5]); /* condition */
588 #elif TCG_TARGET_REG_BITS == 64
589 case INDEX_op_setcond_i64
:
590 tcg_out_r(s
, args
[0]);
591 tcg_out_r(s
, args
[1]);
592 tcg_out_ri64(s
, const_args
[2], args
[2]);
593 tcg_out8(s
, args
[3]); /* condition */
596 case INDEX_op_ld8u_i32
:
597 case INDEX_op_ld8s_i32
:
598 case INDEX_op_ld16u_i32
:
599 case INDEX_op_ld16s_i32
:
600 case INDEX_op_ld_i32
:
601 case INDEX_op_st8_i32
:
602 case INDEX_op_st16_i32
:
603 case INDEX_op_st_i32
:
604 case INDEX_op_ld8u_i64
:
605 case INDEX_op_ld8s_i64
:
606 case INDEX_op_ld16u_i64
:
607 case INDEX_op_ld16s_i64
:
608 case INDEX_op_ld32u_i64
:
609 case INDEX_op_ld32s_i64
:
610 case INDEX_op_ld_i64
:
611 case INDEX_op_st8_i64
:
612 case INDEX_op_st16_i64
:
613 case INDEX_op_st32_i64
:
614 case INDEX_op_st_i64
:
615 tcg_out_r(s
, args
[0]);
616 tcg_out_r(s
, args
[1]);
617 assert(args
[2] == (int32_t)args
[2]);
618 tcg_out32(s
, args
[2]);
620 case INDEX_op_add_i32
:
621 case INDEX_op_sub_i32
:
622 case INDEX_op_mul_i32
:
623 case INDEX_op_and_i32
:
624 case INDEX_op_andc_i32
: /* Optional (TCG_TARGET_HAS_andc_i32). */
625 case INDEX_op_eqv_i32
: /* Optional (TCG_TARGET_HAS_eqv_i32). */
626 case INDEX_op_nand_i32
: /* Optional (TCG_TARGET_HAS_nand_i32). */
627 case INDEX_op_nor_i32
: /* Optional (TCG_TARGET_HAS_nor_i32). */
628 case INDEX_op_or_i32
:
629 case INDEX_op_orc_i32
: /* Optional (TCG_TARGET_HAS_orc_i32). */
630 case INDEX_op_xor_i32
:
631 case INDEX_op_shl_i32
:
632 case INDEX_op_shr_i32
:
633 case INDEX_op_sar_i32
:
634 case INDEX_op_rotl_i32
: /* Optional (TCG_TARGET_HAS_rot_i32). */
635 case INDEX_op_rotr_i32
: /* Optional (TCG_TARGET_HAS_rot_i32). */
636 tcg_out_r(s
, args
[0]);
637 tcg_out_ri32(s
, const_args
[1], args
[1]);
638 tcg_out_ri32(s
, const_args
[2], args
[2]);
640 case INDEX_op_deposit_i32
: /* Optional (TCG_TARGET_HAS_deposit_i32). */
641 tcg_out_r(s
, args
[0]);
642 tcg_out_r(s
, args
[1]);
643 tcg_out_r(s
, args
[2]);
644 assert(args
[3] <= UINT8_MAX
);
645 tcg_out8(s
, args
[3]);
646 assert(args
[4] <= UINT8_MAX
);
647 tcg_out8(s
, args
[4]);
650 #if TCG_TARGET_REG_BITS == 64
651 case INDEX_op_add_i64
:
652 case INDEX_op_sub_i64
:
653 case INDEX_op_mul_i64
:
654 case INDEX_op_and_i64
:
655 case INDEX_op_andc_i64
: /* Optional (TCG_TARGET_HAS_andc_i64). */
656 case INDEX_op_eqv_i64
: /* Optional (TCG_TARGET_HAS_eqv_i64). */
657 case INDEX_op_nand_i64
: /* Optional (TCG_TARGET_HAS_nand_i64). */
658 case INDEX_op_nor_i64
: /* Optional (TCG_TARGET_HAS_nor_i64). */
659 case INDEX_op_or_i64
:
660 case INDEX_op_orc_i64
: /* Optional (TCG_TARGET_HAS_orc_i64). */
661 case INDEX_op_xor_i64
:
662 case INDEX_op_shl_i64
:
663 case INDEX_op_shr_i64
:
664 case INDEX_op_sar_i64
:
665 case INDEX_op_rotl_i64
: /* Optional (TCG_TARGET_HAS_rot_i64). */
666 case INDEX_op_rotr_i64
: /* Optional (TCG_TARGET_HAS_rot_i64). */
667 tcg_out_r(s
, args
[0]);
668 tcg_out_ri64(s
, const_args
[1], args
[1]);
669 tcg_out_ri64(s
, const_args
[2], args
[2]);
671 case INDEX_op_deposit_i64
: /* Optional (TCG_TARGET_HAS_deposit_i64). */
672 tcg_out_r(s
, args
[0]);
673 tcg_out_r(s
, args
[1]);
674 tcg_out_r(s
, args
[2]);
675 assert(args
[3] <= UINT8_MAX
);
676 tcg_out8(s
, args
[3]);
677 assert(args
[4] <= UINT8_MAX
);
678 tcg_out8(s
, args
[4]);
680 case INDEX_op_div_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
681 case INDEX_op_divu_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
682 case INDEX_op_rem_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
683 case INDEX_op_remu_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
686 case INDEX_op_div2_i64
: /* Optional (TCG_TARGET_HAS_div2_i64). */
687 case INDEX_op_divu2_i64
: /* Optional (TCG_TARGET_HAS_div2_i64). */
690 case INDEX_op_brcond_i64
:
691 tcg_out_r(s
, args
[0]);
692 tcg_out_ri64(s
, const_args
[1], args
[1]);
693 tcg_out8(s
, args
[2]); /* condition */
694 tci_out_label(s
, arg_label(args
[3]));
696 case INDEX_op_bswap16_i64
: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
697 case INDEX_op_bswap32_i64
: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
698 case INDEX_op_bswap64_i64
: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
699 case INDEX_op_not_i64
: /* Optional (TCG_TARGET_HAS_not_i64). */
700 case INDEX_op_neg_i64
: /* Optional (TCG_TARGET_HAS_neg_i64). */
701 case INDEX_op_ext8s_i64
: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
702 case INDEX_op_ext8u_i64
: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
703 case INDEX_op_ext16s_i64
: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
704 case INDEX_op_ext16u_i64
: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
705 case INDEX_op_ext32s_i64
: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
706 case INDEX_op_ext32u_i64
: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
707 case INDEX_op_ext_i32_i64
:
708 case INDEX_op_extu_i32_i64
:
709 #endif /* TCG_TARGET_REG_BITS == 64 */
710 case INDEX_op_neg_i32
: /* Optional (TCG_TARGET_HAS_neg_i32). */
711 case INDEX_op_not_i32
: /* Optional (TCG_TARGET_HAS_not_i32). */
712 case INDEX_op_ext8s_i32
: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
713 case INDEX_op_ext16s_i32
: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
714 case INDEX_op_ext8u_i32
: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
715 case INDEX_op_ext16u_i32
: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
716 case INDEX_op_bswap16_i32
: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
717 case INDEX_op_bswap32_i32
: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
718 tcg_out_r(s
, args
[0]);
719 tcg_out_r(s
, args
[1]);
721 case INDEX_op_div_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
722 case INDEX_op_divu_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
723 case INDEX_op_rem_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
724 case INDEX_op_remu_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
725 tcg_out_r(s
, args
[0]);
726 tcg_out_ri32(s
, const_args
[1], args
[1]);
727 tcg_out_ri32(s
, const_args
[2], args
[2]);
729 case INDEX_op_div2_i32
: /* Optional (TCG_TARGET_HAS_div2_i32). */
730 case INDEX_op_divu2_i32
: /* Optional (TCG_TARGET_HAS_div2_i32). */
733 #if TCG_TARGET_REG_BITS == 32
734 case INDEX_op_add2_i32
:
735 case INDEX_op_sub2_i32
:
736 tcg_out_r(s
, args
[0]);
737 tcg_out_r(s
, args
[1]);
738 tcg_out_r(s
, args
[2]);
739 tcg_out_r(s
, args
[3]);
740 tcg_out_r(s
, args
[4]);
741 tcg_out_r(s
, args
[5]);
743 case INDEX_op_brcond2_i32
:
744 tcg_out_r(s
, args
[0]);
745 tcg_out_r(s
, args
[1]);
746 tcg_out_ri32(s
, const_args
[2], args
[2]);
747 tcg_out_ri32(s
, const_args
[3], args
[3]);
748 tcg_out8(s
, args
[4]); /* condition */
749 tci_out_label(s
, arg_label(args
[5]));
751 case INDEX_op_mulu2_i32
:
752 tcg_out_r(s
, args
[0]);
753 tcg_out_r(s
, args
[1]);
754 tcg_out_r(s
, args
[2]);
755 tcg_out_r(s
, args
[3]);
758 case INDEX_op_brcond_i32
:
759 tcg_out_r(s
, args
[0]);
760 tcg_out_ri32(s
, const_args
[1], args
[1]);
761 tcg_out8(s
, args
[2]); /* condition */
762 tci_out_label(s
, arg_label(args
[3]));
764 case INDEX_op_qemu_ld_i32
:
765 tcg_out_r(s
, *args
++);
766 tcg_out_r(s
, *args
++);
767 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
768 tcg_out_r(s
, *args
++);
770 tcg_out_i(s
, *args
++);
772 case INDEX_op_qemu_ld_i64
:
773 tcg_out_r(s
, *args
++);
774 if (TCG_TARGET_REG_BITS
== 32) {
775 tcg_out_r(s
, *args
++);
777 tcg_out_r(s
, *args
++);
778 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
779 tcg_out_r(s
, *args
++);
781 tcg_out_i(s
, *args
++);
783 case INDEX_op_qemu_st_i32
:
784 tcg_out_r(s
, *args
++);
785 tcg_out_r(s
, *args
++);
786 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
787 tcg_out_r(s
, *args
++);
789 tcg_out_i(s
, *args
++);
791 case INDEX_op_qemu_st_i64
:
792 tcg_out_r(s
, *args
++);
793 if (TCG_TARGET_REG_BITS
== 32) {
794 tcg_out_r(s
, *args
++);
796 tcg_out_r(s
, *args
++);
797 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
798 tcg_out_r(s
, *args
++);
800 tcg_out_i(s
, *args
++);
802 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
803 case INDEX_op_mov_i64
:
804 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
805 case INDEX_op_movi_i64
:
806 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
810 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
813 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
816 uint8_t *old_code_ptr
= s
->code_ptr
;
817 if (type
== TCG_TYPE_I32
) {
818 tcg_out_op_t(s
, INDEX_op_st_i32
);
823 assert(type
== TCG_TYPE_I64
);
824 #if TCG_TARGET_REG_BITS == 64
825 tcg_out_op_t(s
, INDEX_op_st_i64
);
833 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
836 /* Test if a constant matches the constraint. */
837 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
838 const TCGArgConstraint
*arg_ct
)
840 /* No need to return 0 or 1, 0 or != 0 is good enough. */
841 return arg_ct
->ct
& TCG_CT_CONST
;
844 static void tcg_target_init(TCGContext
*s
)
846 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
847 const char *envval
= getenv("DEBUG_TCG");
849 qemu_set_log(strtol(envval
, NULL
, 0));
853 /* The current code uses uint8_t for tcg operations. */
854 assert(tcg_op_defs_max
<= UINT8_MAX
);
856 /* Registers available for 32 bit operations. */
857 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0,
858 BIT(TCG_TARGET_NB_REGS
) - 1);
859 /* Registers available for 64 bit operations. */
860 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0,
861 BIT(TCG_TARGET_NB_REGS
) - 1);
862 /* TODO: Which registers should be set here? */
863 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
864 BIT(TCG_TARGET_NB_REGS
) - 1);
866 tcg_regset_clear(s
->reserved_regs
);
867 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
868 tcg_add_target_add_op_defs(tcg_target_op_defs
);
870 /* We use negative offsets from "sp" so that we can distinguish
871 stores that might pretend to be call arguments. */
872 tcg_set_frame(s
, TCG_REG_CALL_STACK
,
873 -CPU_TEMP_BUF_NLONGS
* sizeof(long),
874 CPU_TEMP_BUF_NLONGS
* sizeof(long));
877 /* Generate global QEMU prologue and epilogue code. */
878 static inline void tcg_target_qemu_prologue(TCGContext
*s
)