tcg/tci/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /*
  26  * This code implements a TCG which does not generate machine code for some
  27  * real target machine but which generates virtual machine code for an
  28  * interpreter. Interpreted pseudo code is slow, but it works on any host.
  29  *
  30  * Some remarks might help in understanding the code:
  31  *
  32  * "target" or "TCG target" is the machine which runs the generated code.
  33  * This is different to the usual meaning in QEMU where "target" is the
  34  * emulated machine. So normally QEMU host is identical to TCG target.
  35  * Here the TCG target is a virtual machine, but this virtual machine must
  36  * use the same word size like the real machine.
  37  * Therefore, we need both 32 and 64 bit virtual machines (interpreter).
  38  */
  39
  40 #ifndef TCG_TARGET_H
  41 #define TCG_TARGET_H
  42
  43 #define TCG_TARGET_INTERPRETER 1
  44 #define TCG_TARGET_INSN_UNIT_SIZE 4
  45 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
  46
  47 /* Optional instructions. */
  48
  49 #define TCG_TARGET_HAS_bswap16_i32      1
  50 #define TCG_TARGET_HAS_bswap32_i32      1
  51 #define TCG_TARGET_HAS_div_i32          1
  52 #define TCG_TARGET_HAS_rem_i32          1
  53 #define TCG_TARGET_HAS_ext8s_i32        1
  54 #define TCG_TARGET_HAS_ext16s_i32       1
  55 #define TCG_TARGET_HAS_ext8u_i32        1
  56 #define TCG_TARGET_HAS_ext16u_i32       1
  57 #define TCG_TARGET_HAS_andc_i32         1
  58 #define TCG_TARGET_HAS_deposit_i32      1
  59 #define TCG_TARGET_HAS_extract_i32      1
  60 #define TCG_TARGET_HAS_sextract_i32     1
  61 #define TCG_TARGET_HAS_extract2_i32     0
  62 #define TCG_TARGET_HAS_eqv_i32          1
  63 #define TCG_TARGET_HAS_nand_i32         1
  64 #define TCG_TARGET_HAS_nor_i32          1
  65 #define TCG_TARGET_HAS_clz_i32          1
  66 #define TCG_TARGET_HAS_ctz_i32          1
  67 #define TCG_TARGET_HAS_ctpop_i32        1
  68 #define TCG_TARGET_HAS_neg_i32          1
  69 #define TCG_TARGET_HAS_not_i32          1
  70 #define TCG_TARGET_HAS_orc_i32          1
  71 #define TCG_TARGET_HAS_rot_i32          1
  72 #define TCG_TARGET_HAS_movcond_i32      1
  73 #define TCG_TARGET_HAS_negsetcond_i32   0
  74 #define TCG_TARGET_HAS_muls2_i32        1
  75 #define TCG_TARGET_HAS_muluh_i32        0
  76 #define TCG_TARGET_HAS_mulsh_i32        0
  77 #define TCG_TARGET_HAS_qemu_st8_i32     0
  78
  79 #if TCG_TARGET_REG_BITS == 64
  80 #define TCG_TARGET_HAS_extr_i64_i32     0
  81 #define TCG_TARGET_HAS_bswap16_i64      1
  82 #define TCG_TARGET_HAS_bswap32_i64      1
  83 #define TCG_TARGET_HAS_bswap64_i64      1
  84 #define TCG_TARGET_HAS_deposit_i64      1
  85 #define TCG_TARGET_HAS_extract_i64      1
  86 #define TCG_TARGET_HAS_sextract_i64     1
  87 #define TCG_TARGET_HAS_extract2_i64     0
  88 #define TCG_TARGET_HAS_div_i64          1
  89 #define TCG_TARGET_HAS_rem_i64          1
  90 #define TCG_TARGET_HAS_ext8s_i64        1
  91 #define TCG_TARGET_HAS_ext16s_i64       1
  92 #define TCG_TARGET_HAS_ext32s_i64       1
  93 #define TCG_TARGET_HAS_ext8u_i64        1
  94 #define TCG_TARGET_HAS_ext16u_i64       1
  95 #define TCG_TARGET_HAS_ext32u_i64       1
  96 #define TCG_TARGET_HAS_andc_i64         1
  97 #define TCG_TARGET_HAS_eqv_i64          1
  98 #define TCG_TARGET_HAS_nand_i64         1
  99 #define TCG_TARGET_HAS_nor_i64          1
 100 #define TCG_TARGET_HAS_clz_i64          1
 101 #define TCG_TARGET_HAS_ctz_i64          1
 102 #define TCG_TARGET_HAS_ctpop_i64        1
 103 #define TCG_TARGET_HAS_neg_i64          1
 104 #define TCG_TARGET_HAS_not_i64          1
 105 #define TCG_TARGET_HAS_orc_i64          1
 106 #define TCG_TARGET_HAS_rot_i64          1
 107 #define TCG_TARGET_HAS_movcond_i64      1
 108 #define TCG_TARGET_HAS_negsetcond_i64   0
 109 #define TCG_TARGET_HAS_muls2_i64        1
 110 #define TCG_TARGET_HAS_add2_i32         1
 111 #define TCG_TARGET_HAS_sub2_i32         1
 112 #define TCG_TARGET_HAS_mulu2_i32        1
 113 #define TCG_TARGET_HAS_add2_i64         1
 114 #define TCG_TARGET_HAS_sub2_i64         1
 115 #define TCG_TARGET_HAS_mulu2_i64        1
 116 #define TCG_TARGET_HAS_muluh_i64        0
 117 #define TCG_TARGET_HAS_mulsh_i64        0
 118 #else
 119 #define TCG_TARGET_HAS_mulu2_i32        1
 120 #endif /* TCG_TARGET_REG_BITS == 64 */
 121
 122 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 123
 124 /* Number of registers available. */
 125 #define TCG_TARGET_NB_REGS 16
 126
 127 /* List of registers which are used by TCG. */
 128 typedef enum {
 129     TCG_REG_R0 = 0,
 130     TCG_REG_R1,
 131     TCG_REG_R2,
 132     TCG_REG_R3,
 133     TCG_REG_R4,
 134     TCG_REG_R5,
 135     TCG_REG_R6,
 136     TCG_REG_R7,
 137     TCG_REG_R8,
 138     TCG_REG_R9,
 139     TCG_REG_R10,
 140     TCG_REG_R11,
 141     TCG_REG_R12,
 142     TCG_REG_R13,
 143     TCG_REG_R14,
 144     TCG_REG_R15,
 145
 146     TCG_REG_TMP = TCG_REG_R13,
 147     TCG_AREG0 = TCG_REG_R14,
 148     TCG_REG_CALL_STACK = TCG_REG_R15,
 149 } TCGReg;
 150
 151 /* Used for function call generation. */
 152 #define TCG_TARGET_CALL_STACK_OFFSET    0
 153 #define TCG_TARGET_STACK_ALIGN          8
 154 #if TCG_TARGET_REG_BITS == 32
 155 # define TCG_TARGET_CALL_ARG_I32        TCG_CALL_ARG_EVEN
 156 # define TCG_TARGET_CALL_ARG_I64        TCG_CALL_ARG_EVEN
 157 # define TCG_TARGET_CALL_ARG_I128       TCG_CALL_ARG_EVEN
 158 #else
 159 # define TCG_TARGET_CALL_ARG_I32        TCG_CALL_ARG_NORMAL
 160 # define TCG_TARGET_CALL_ARG_I64        TCG_CALL_ARG_NORMAL
 161 # define TCG_TARGET_CALL_ARG_I128       TCG_CALL_ARG_NORMAL
 162 #endif
 163 #define TCG_TARGET_CALL_RET_I128        TCG_CALL_RET_NORMAL
 164
 165 #define HAVE_TCG_QEMU_TB_EXEC
 166 #define TCG_TARGET_NEED_POOL_LABELS
 167
 168 /* We could notice __i386__ or __s390x__ and reduce the barriers depending
 169    on the host.  But if you want performance, you use the normal backend.
 170    We prefer consistency across hosts on this.  */
 171 #define TCG_TARGET_DEFAULT_MO  (0)
 172
 173 #endif /* TCG_TARGET_H */