2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011, 2016 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
23 #include "exec/cpu_ldst.h"
24 #include "tcg/tcg-op.h"
25 #include "qemu/compiler.h"
30 * Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
31 * Without assertions, the interpreter runs much faster.
33 #if defined(CONFIG_DEBUG_TCG)
34 # define tci_assert(cond) assert(cond)
36 # define tci_assert(cond) ((void)(cond))
39 __thread
uintptr_t tci_tb_ptr
;
42 tci_write_reg(tcg_target_ulong
*regs
, TCGReg index
, tcg_target_ulong value
)
44 tci_assert(index
< TCG_TARGET_NB_REGS
);
45 tci_assert(index
!= TCG_AREG0
);
46 tci_assert(index
!= TCG_REG_CALL_STACK
);
50 static void tci_write_reg64(tcg_target_ulong
*regs
, uint32_t high_index
,
51 uint32_t low_index
, uint64_t value
)
53 tci_write_reg(regs
, low_index
, value
);
54 tci_write_reg(regs
, high_index
, value
>> 32);
57 /* Create a 64 bit value from two 32 bit values. */
58 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
60 return ((uint64_t)high
<< 32) + low
;
63 /* Read constant byte from bytecode. */
64 static uint8_t tci_read_b(const uint8_t **tb_ptr
)
66 return *(tb_ptr
[0]++);
69 /* Read register number from bytecode. */
70 static TCGReg
tci_read_r(const uint8_t **tb_ptr
)
72 uint8_t regno
= tci_read_b(tb_ptr
);
73 tci_assert(regno
< TCG_TARGET_NB_REGS
);
77 /* Read constant (native size) from bytecode. */
78 static tcg_target_ulong
tci_read_i(const uint8_t **tb_ptr
)
80 tcg_target_ulong value
= *(const tcg_target_ulong
*)(*tb_ptr
);
81 *tb_ptr
+= sizeof(value
);
85 /* Read unsigned constant (32 bit) from bytecode. */
86 static uint32_t tci_read_i32(const uint8_t **tb_ptr
)
88 uint32_t value
= *(const uint32_t *)(*tb_ptr
);
89 *tb_ptr
+= sizeof(value
);
93 /* Read signed constant (32 bit) from bytecode. */
94 static int32_t tci_read_s32(const uint8_t **tb_ptr
)
96 int32_t value
= *(const int32_t *)(*tb_ptr
);
97 *tb_ptr
+= sizeof(value
);
101 static tcg_target_ulong
tci_read_label(const uint8_t **tb_ptr
)
103 return tci_read_i(tb_ptr
);
107 * Load sets of arguments all at once. The naming convention is:
108 * tci_args_<arguments>
109 * where arguments is a sequence of
111 * b = immediate (bit position)
112 * c = condition (TCGCond)
113 * i = immediate (uint32_t)
114 * I = immediate (tcg_target_ulong)
115 * l = label or pointer
116 * m = immediate (TCGMemOpIdx)
117 * n = immediate (call return length)
119 * s = signed ldst offset
122 static void check_size(const uint8_t *start
, const uint8_t **tb_ptr
)
124 const uint8_t *old_code_ptr
= start
- 2;
125 uint8_t op_size
= old_code_ptr
[1];
126 tci_assert(*tb_ptr
== old_code_ptr
+ op_size
);
129 static void tci_args_l(const uint8_t **tb_ptr
, void **l0
)
131 const uint8_t *start
= *tb_ptr
;
133 *l0
= (void *)tci_read_label(tb_ptr
);
135 check_size(start
, tb_ptr
);
138 static void tci_args_nll(const uint8_t **tb_ptr
, uint8_t *n0
,
139 void **l1
, void **l2
)
141 const uint8_t *start
= *tb_ptr
;
143 *n0
= tci_read_b(tb_ptr
);
144 *l1
= (void *)tci_read_label(tb_ptr
);
145 *l2
= (void *)tci_read_label(tb_ptr
);
147 check_size(start
, tb_ptr
);
150 static void tci_args_rr(const uint8_t **tb_ptr
,
151 TCGReg
*r0
, TCGReg
*r1
)
153 const uint8_t *start
= *tb_ptr
;
155 *r0
= tci_read_r(tb_ptr
);
156 *r1
= tci_read_r(tb_ptr
);
158 check_size(start
, tb_ptr
);
161 static void tci_args_ri(const uint8_t **tb_ptr
,
162 TCGReg
*r0
, tcg_target_ulong
*i1
)
164 const uint8_t *start
= *tb_ptr
;
166 *r0
= tci_read_r(tb_ptr
);
167 *i1
= tci_read_i32(tb_ptr
);
169 check_size(start
, tb_ptr
);
172 #if TCG_TARGET_REG_BITS == 64
173 static void tci_args_rI(const uint8_t **tb_ptr
,
174 TCGReg
*r0
, tcg_target_ulong
*i1
)
176 const uint8_t *start
= *tb_ptr
;
178 *r0
= tci_read_r(tb_ptr
);
179 *i1
= tci_read_i(tb_ptr
);
181 check_size(start
, tb_ptr
);
185 static void tci_args_rrm(const uint8_t **tb_ptr
,
186 TCGReg
*r0
, TCGReg
*r1
, TCGMemOpIdx
*m2
)
188 const uint8_t *start
= *tb_ptr
;
190 *r0
= tci_read_r(tb_ptr
);
191 *r1
= tci_read_r(tb_ptr
);
192 *m2
= tci_read_i32(tb_ptr
);
194 check_size(start
, tb_ptr
);
197 static void tci_args_rrr(const uint8_t **tb_ptr
,
198 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
)
200 const uint8_t *start
= *tb_ptr
;
202 *r0
= tci_read_r(tb_ptr
);
203 *r1
= tci_read_r(tb_ptr
);
204 *r2
= tci_read_r(tb_ptr
);
206 check_size(start
, tb_ptr
);
209 static void tci_args_rrs(const uint8_t **tb_ptr
,
210 TCGReg
*r0
, TCGReg
*r1
, int32_t *i2
)
212 const uint8_t *start
= *tb_ptr
;
214 *r0
= tci_read_r(tb_ptr
);
215 *r1
= tci_read_r(tb_ptr
);
216 *i2
= tci_read_s32(tb_ptr
);
218 check_size(start
, tb_ptr
);
221 static void tci_args_rrcl(const uint8_t **tb_ptr
,
222 TCGReg
*r0
, TCGReg
*r1
, TCGCond
*c2
, void **l3
)
224 const uint8_t *start
= *tb_ptr
;
226 *r0
= tci_read_r(tb_ptr
);
227 *r1
= tci_read_r(tb_ptr
);
228 *c2
= tci_read_b(tb_ptr
);
229 *l3
= (void *)tci_read_label(tb_ptr
);
231 check_size(start
, tb_ptr
);
234 static void tci_args_rrrc(const uint8_t **tb_ptr
,
235 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGCond
*c3
)
237 const uint8_t *start
= *tb_ptr
;
239 *r0
= tci_read_r(tb_ptr
);
240 *r1
= tci_read_r(tb_ptr
);
241 *r2
= tci_read_r(tb_ptr
);
242 *c3
= tci_read_b(tb_ptr
);
244 check_size(start
, tb_ptr
);
247 static void tci_args_rrrm(const uint8_t **tb_ptr
,
248 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGMemOpIdx
*m3
)
250 const uint8_t *start
= *tb_ptr
;
252 *r0
= tci_read_r(tb_ptr
);
253 *r1
= tci_read_r(tb_ptr
);
254 *r2
= tci_read_r(tb_ptr
);
255 *m3
= tci_read_i32(tb_ptr
);
257 check_size(start
, tb_ptr
);
260 static void tci_args_rrrbb(const uint8_t **tb_ptr
, TCGReg
*r0
, TCGReg
*r1
,
261 TCGReg
*r2
, uint8_t *i3
, uint8_t *i4
)
263 const uint8_t *start
= *tb_ptr
;
265 *r0
= tci_read_r(tb_ptr
);
266 *r1
= tci_read_r(tb_ptr
);
267 *r2
= tci_read_r(tb_ptr
);
268 *i3
= tci_read_b(tb_ptr
);
269 *i4
= tci_read_b(tb_ptr
);
271 check_size(start
, tb_ptr
);
274 static void tci_args_rrrrm(const uint8_t **tb_ptr
, TCGReg
*r0
, TCGReg
*r1
,
275 TCGReg
*r2
, TCGReg
*r3
, TCGMemOpIdx
*m4
)
277 const uint8_t *start
= *tb_ptr
;
279 *r0
= tci_read_r(tb_ptr
);
280 *r1
= tci_read_r(tb_ptr
);
281 *r2
= tci_read_r(tb_ptr
);
282 *r3
= tci_read_r(tb_ptr
);
283 *m4
= tci_read_i32(tb_ptr
);
285 check_size(start
, tb_ptr
);
288 #if TCG_TARGET_REG_BITS == 32
289 static void tci_args_rrrr(const uint8_t **tb_ptr
,
290 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGReg
*r3
)
292 const uint8_t *start
= *tb_ptr
;
294 *r0
= tci_read_r(tb_ptr
);
295 *r1
= tci_read_r(tb_ptr
);
296 *r2
= tci_read_r(tb_ptr
);
297 *r3
= tci_read_r(tb_ptr
);
299 check_size(start
, tb_ptr
);
302 static void tci_args_rrrrcl(const uint8_t **tb_ptr
, TCGReg
*r0
, TCGReg
*r1
,
303 TCGReg
*r2
, TCGReg
*r3
, TCGCond
*c4
, void **l5
)
305 const uint8_t *start
= *tb_ptr
;
307 *r0
= tci_read_r(tb_ptr
);
308 *r1
= tci_read_r(tb_ptr
);
309 *r2
= tci_read_r(tb_ptr
);
310 *r3
= tci_read_r(tb_ptr
);
311 *c4
= tci_read_b(tb_ptr
);
312 *l5
= (void *)tci_read_label(tb_ptr
);
314 check_size(start
, tb_ptr
);
317 static void tci_args_rrrrrc(const uint8_t **tb_ptr
, TCGReg
*r0
, TCGReg
*r1
,
318 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
, TCGCond
*c5
)
320 const uint8_t *start
= *tb_ptr
;
322 *r0
= tci_read_r(tb_ptr
);
323 *r1
= tci_read_r(tb_ptr
);
324 *r2
= tci_read_r(tb_ptr
);
325 *r3
= tci_read_r(tb_ptr
);
326 *r4
= tci_read_r(tb_ptr
);
327 *c5
= tci_read_b(tb_ptr
);
329 check_size(start
, tb_ptr
);
332 static void tci_args_rrrrrr(const uint8_t **tb_ptr
, TCGReg
*r0
, TCGReg
*r1
,
333 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
, TCGReg
*r5
)
335 const uint8_t *start
= *tb_ptr
;
337 *r0
= tci_read_r(tb_ptr
);
338 *r1
= tci_read_r(tb_ptr
);
339 *r2
= tci_read_r(tb_ptr
);
340 *r3
= tci_read_r(tb_ptr
);
341 *r4
= tci_read_r(tb_ptr
);
342 *r5
= tci_read_r(tb_ptr
);
344 check_size(start
, tb_ptr
);
348 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
385 g_assert_not_reached();
390 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
427 g_assert_not_reached();
433 cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
434 #define qemu_ld_leuw \
435 cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
436 #define qemu_ld_leul \
437 cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
438 #define qemu_ld_leq \
439 cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
440 #define qemu_ld_beuw \
441 cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
442 #define qemu_ld_beul \
443 cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
444 #define qemu_ld_beq \
445 cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
446 #define qemu_st_b(X) \
447 cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
448 #define qemu_st_lew(X) \
449 cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
450 #define qemu_st_lel(X) \
451 cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
452 #define qemu_st_leq(X) \
453 cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
454 #define qemu_st_bew(X) \
455 cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
456 #define qemu_st_bel(X) \
457 cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
458 #define qemu_st_beq(X) \
459 cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
461 #if TCG_TARGET_REG_BITS == 64
462 # define CASE_32_64(x) \
463 case glue(glue(INDEX_op_, x), _i64): \
464 case glue(glue(INDEX_op_, x), _i32):
465 # define CASE_64(x) \
466 case glue(glue(INDEX_op_, x), _i64):
468 # define CASE_32_64(x) \
469 case glue(glue(INDEX_op_, x), _i32):
473 /* Interpret pseudo code in tb. */
475 * Disable CFI checks.
476 * One possible operation in the pseudo code is a call to binary code.
477 * Therefore, disable CFI checks in the interpreter function
479 uintptr_t QEMU_DISABLE_CFI
tcg_qemu_tb_exec(CPUArchState
*env
,
480 const void *v_tb_ptr
)
482 const uint8_t *tb_ptr
= v_tb_ptr
;
483 tcg_target_ulong regs
[TCG_TARGET_NB_REGS
];
484 uint64_t stack
[(TCG_STATIC_CALL_ARGS_SIZE
+ TCG_STATIC_FRAME_SIZE
)
486 void *call_slots
[TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(uint64_t)];
488 regs
[TCG_AREG0
] = (tcg_target_ulong
)env
;
489 regs
[TCG_REG_CALL_STACK
] = (uintptr_t)stack
;
490 /* Other call_slots entries initialized at first use (see below). */
491 call_slots
[0] = NULL
;
495 TCGOpcode opc
= tb_ptr
[0];
496 TCGReg r0
, r1
, r2
, r3
;
503 #if TCG_TARGET_REG_BITS == 32
511 /* Skip opcode and size entry. */
517 * Set up the ffi_avalue array once, delayed until now
518 * because many TB's do not make any calls. In tcg_gen_callN,
519 * we arranged for every real argument to be "left-aligned"
520 * in each 64-bit slot.
522 if (unlikely(call_slots
[0] == NULL
)) {
523 for (int i
= 0; i
< ARRAY_SIZE(call_slots
); ++i
) {
524 call_slots
[i
] = &stack
[i
];
528 tci_args_nll(&tb_ptr
, &len
, &ptr
, &cif
);
530 /* Helper functions may need to access the "return address" */
531 tci_tb_ptr
= (uintptr_t)tb_ptr
;
533 ffi_call(cif
, ptr
, stack
, call_slots
);
535 /* Any result winds up "left-aligned" in the stack[0] slot. */
539 case 1: /* uint32_t */
541 * Note that libffi has an odd special case in that it will
542 * always widen an integral result to ffi_arg.
544 if (sizeof(ffi_arg
) == 4) {
545 regs
[TCG_REG_R0
] = *(uint32_t *)stack
;
549 case 2: /* uint64_t */
550 if (TCG_TARGET_REG_BITS
== 32) {
551 tci_write_reg64(regs
, TCG_REG_R1
, TCG_REG_R0
, stack
[0]);
553 regs
[TCG_REG_R0
] = stack
[0];
557 g_assert_not_reached();
562 tci_args_l(&tb_ptr
, &ptr
);
565 case INDEX_op_setcond_i32
:
566 tci_args_rrrc(&tb_ptr
, &r0
, &r1
, &r2
, &condition
);
567 regs
[r0
] = tci_compare32(regs
[r1
], regs
[r2
], condition
);
569 #if TCG_TARGET_REG_BITS == 32
570 case INDEX_op_setcond2_i32
:
571 tci_args_rrrrrc(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
572 T1
= tci_uint64(regs
[r2
], regs
[r1
]);
573 T2
= tci_uint64(regs
[r4
], regs
[r3
]);
574 regs
[r0
] = tci_compare64(T1
, T2
, condition
);
576 #elif TCG_TARGET_REG_BITS == 64
577 case INDEX_op_setcond_i64
:
578 tci_args_rrrc(&tb_ptr
, &r0
, &r1
, &r2
, &condition
);
579 regs
[r0
] = tci_compare64(regs
[r1
], regs
[r2
], condition
);
583 tci_args_rr(&tb_ptr
, &r0
, &r1
);
586 case INDEX_op_tci_movi_i32
:
587 tci_args_ri(&tb_ptr
, &r0
, &t1
);
591 /* Load/store operations (32 bit). */
594 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
595 ptr
= (void *)(regs
[r1
] + ofs
);
596 regs
[r0
] = *(uint8_t *)ptr
;
599 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
600 ptr
= (void *)(regs
[r1
] + ofs
);
601 regs
[r0
] = *(int8_t *)ptr
;
604 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
605 ptr
= (void *)(regs
[r1
] + ofs
);
606 regs
[r0
] = *(uint16_t *)ptr
;
609 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
610 ptr
= (void *)(regs
[r1
] + ofs
);
611 regs
[r0
] = *(int16_t *)ptr
;
613 case INDEX_op_ld_i32
:
615 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
616 ptr
= (void *)(regs
[r1
] + ofs
);
617 regs
[r0
] = *(uint32_t *)ptr
;
620 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
621 ptr
= (void *)(regs
[r1
] + ofs
);
622 *(uint8_t *)ptr
= regs
[r0
];
625 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
626 ptr
= (void *)(regs
[r1
] + ofs
);
627 *(uint16_t *)ptr
= regs
[r0
];
629 case INDEX_op_st_i32
:
631 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
632 ptr
= (void *)(regs
[r1
] + ofs
);
633 *(uint32_t *)ptr
= regs
[r0
];
636 /* Arithmetic operations (mixed 32/64 bit). */
639 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
640 regs
[r0
] = regs
[r1
] + regs
[r2
];
643 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
644 regs
[r0
] = regs
[r1
] - regs
[r2
];
647 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
648 regs
[r0
] = regs
[r1
] * regs
[r2
];
651 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
652 regs
[r0
] = regs
[r1
] & regs
[r2
];
655 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
656 regs
[r0
] = regs
[r1
] | regs
[r2
];
659 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
660 regs
[r0
] = regs
[r1
] ^ regs
[r2
];
663 /* Arithmetic operations (32 bit). */
665 case INDEX_op_div_i32
:
666 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
667 regs
[r0
] = (int32_t)regs
[r1
] / (int32_t)regs
[r2
];
669 case INDEX_op_divu_i32
:
670 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
671 regs
[r0
] = (uint32_t)regs
[r1
] / (uint32_t)regs
[r2
];
673 case INDEX_op_rem_i32
:
674 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
675 regs
[r0
] = (int32_t)regs
[r1
] % (int32_t)regs
[r2
];
677 case INDEX_op_remu_i32
:
678 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
679 regs
[r0
] = (uint32_t)regs
[r1
] % (uint32_t)regs
[r2
];
682 /* Shift/rotate operations (32 bit). */
684 case INDEX_op_shl_i32
:
685 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
686 regs
[r0
] = (uint32_t)regs
[r1
] << (regs
[r2
] & 31);
688 case INDEX_op_shr_i32
:
689 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
690 regs
[r0
] = (uint32_t)regs
[r1
] >> (regs
[r2
] & 31);
692 case INDEX_op_sar_i32
:
693 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
694 regs
[r0
] = (int32_t)regs
[r1
] >> (regs
[r2
] & 31);
696 #if TCG_TARGET_HAS_rot_i32
697 case INDEX_op_rotl_i32
:
698 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
699 regs
[r0
] = rol32(regs
[r1
], regs
[r2
] & 31);
701 case INDEX_op_rotr_i32
:
702 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
703 regs
[r0
] = ror32(regs
[r1
], regs
[r2
] & 31);
706 #if TCG_TARGET_HAS_deposit_i32
707 case INDEX_op_deposit_i32
:
708 tci_args_rrrbb(&tb_ptr
, &r0
, &r1
, &r2
, &pos
, &len
);
709 regs
[r0
] = deposit32(regs
[r1
], pos
, len
, regs
[r2
]);
712 case INDEX_op_brcond_i32
:
713 tci_args_rrcl(&tb_ptr
, &r0
, &r1
, &condition
, &ptr
);
714 if (tci_compare32(regs
[r0
], regs
[r1
], condition
)) {
718 #if TCG_TARGET_REG_BITS == 32
719 case INDEX_op_add2_i32
:
720 tci_args_rrrrrr(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
721 T1
= tci_uint64(regs
[r3
], regs
[r2
]);
722 T2
= tci_uint64(regs
[r5
], regs
[r4
]);
723 tci_write_reg64(regs
, r1
, r0
, T1
+ T2
);
725 case INDEX_op_sub2_i32
:
726 tci_args_rrrrrr(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
727 T1
= tci_uint64(regs
[r3
], regs
[r2
]);
728 T2
= tci_uint64(regs
[r5
], regs
[r4
]);
729 tci_write_reg64(regs
, r1
, r0
, T1
- T2
);
731 case INDEX_op_brcond2_i32
:
732 tci_args_rrrrcl(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &condition
, &ptr
);
733 T1
= tci_uint64(regs
[r1
], regs
[r0
]);
734 T2
= tci_uint64(regs
[r3
], regs
[r2
]);
735 if (tci_compare64(T1
, T2
, condition
)) {
740 case INDEX_op_mulu2_i32
:
741 tci_args_rrrr(&tb_ptr
, &r0
, &r1
, &r2
, &r3
);
742 tci_write_reg64(regs
, r1
, r0
, (uint64_t)regs
[r2
] * regs
[r3
]);
744 #endif /* TCG_TARGET_REG_BITS == 32 */
745 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
747 tci_args_rr(&tb_ptr
, &r0
, &r1
);
748 regs
[r0
] = (int8_t)regs
[r1
];
751 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
753 tci_args_rr(&tb_ptr
, &r0
, &r1
);
754 regs
[r0
] = (int16_t)regs
[r1
];
757 #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
759 tci_args_rr(&tb_ptr
, &r0
, &r1
);
760 regs
[r0
] = (uint8_t)regs
[r1
];
763 #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
765 tci_args_rr(&tb_ptr
, &r0
, &r1
);
766 regs
[r0
] = (uint16_t)regs
[r1
];
769 #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
771 tci_args_rr(&tb_ptr
, &r0
, &r1
);
772 regs
[r0
] = bswap16(regs
[r1
]);
775 #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
777 tci_args_rr(&tb_ptr
, &r0
, &r1
);
778 regs
[r0
] = bswap32(regs
[r1
]);
781 #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
783 tci_args_rr(&tb_ptr
, &r0
, &r1
);
784 regs
[r0
] = ~regs
[r1
];
787 #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
789 tci_args_rr(&tb_ptr
, &r0
, &r1
);
790 regs
[r0
] = -regs
[r1
];
793 #if TCG_TARGET_REG_BITS == 64
794 case INDEX_op_tci_movi_i64
:
795 tci_args_rI(&tb_ptr
, &r0
, &t1
);
799 /* Load/store operations (64 bit). */
801 case INDEX_op_ld32s_i64
:
802 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
803 ptr
= (void *)(regs
[r1
] + ofs
);
804 regs
[r0
] = *(int32_t *)ptr
;
806 case INDEX_op_ld_i64
:
807 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
808 ptr
= (void *)(regs
[r1
] + ofs
);
809 regs
[r0
] = *(uint64_t *)ptr
;
811 case INDEX_op_st_i64
:
812 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &ofs
);
813 ptr
= (void *)(regs
[r1
] + ofs
);
814 *(uint64_t *)ptr
= regs
[r0
];
817 /* Arithmetic operations (64 bit). */
819 case INDEX_op_div_i64
:
820 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
821 regs
[r0
] = (int64_t)regs
[r1
] / (int64_t)regs
[r2
];
823 case INDEX_op_divu_i64
:
824 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
825 regs
[r0
] = (uint64_t)regs
[r1
] / (uint64_t)regs
[r2
];
827 case INDEX_op_rem_i64
:
828 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
829 regs
[r0
] = (int64_t)regs
[r1
] % (int64_t)regs
[r2
];
831 case INDEX_op_remu_i64
:
832 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
833 regs
[r0
] = (uint64_t)regs
[r1
] % (uint64_t)regs
[r2
];
836 /* Shift/rotate operations (64 bit). */
838 case INDEX_op_shl_i64
:
839 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
840 regs
[r0
] = regs
[r1
] << (regs
[r2
] & 63);
842 case INDEX_op_shr_i64
:
843 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
844 regs
[r0
] = regs
[r1
] >> (regs
[r2
] & 63);
846 case INDEX_op_sar_i64
:
847 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
848 regs
[r0
] = (int64_t)regs
[r1
] >> (regs
[r2
] & 63);
850 #if TCG_TARGET_HAS_rot_i64
851 case INDEX_op_rotl_i64
:
852 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
853 regs
[r0
] = rol64(regs
[r1
], regs
[r2
] & 63);
855 case INDEX_op_rotr_i64
:
856 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
857 regs
[r0
] = ror64(regs
[r1
], regs
[r2
] & 63);
860 #if TCG_TARGET_HAS_deposit_i64
861 case INDEX_op_deposit_i64
:
862 tci_args_rrrbb(&tb_ptr
, &r0
, &r1
, &r2
, &pos
, &len
);
863 regs
[r0
] = deposit64(regs
[r1
], pos
, len
, regs
[r2
]);
866 case INDEX_op_brcond_i64
:
867 tci_args_rrcl(&tb_ptr
, &r0
, &r1
, &condition
, &ptr
);
868 if (tci_compare64(regs
[r0
], regs
[r1
], condition
)) {
872 case INDEX_op_ext32s_i64
:
873 case INDEX_op_ext_i32_i64
:
874 tci_args_rr(&tb_ptr
, &r0
, &r1
);
875 regs
[r0
] = (int32_t)regs
[r1
];
877 case INDEX_op_ext32u_i64
:
878 case INDEX_op_extu_i32_i64
:
879 tci_args_rr(&tb_ptr
, &r0
, &r1
);
880 regs
[r0
] = (uint32_t)regs
[r1
];
882 #if TCG_TARGET_HAS_bswap64_i64
883 case INDEX_op_bswap64_i64
:
884 tci_args_rr(&tb_ptr
, &r0
, &r1
);
885 regs
[r0
] = bswap64(regs
[r1
]);
888 #endif /* TCG_TARGET_REG_BITS == 64 */
890 /* QEMU specific operations. */
892 case INDEX_op_exit_tb
:
893 tci_args_l(&tb_ptr
, &ptr
);
894 return (uintptr_t)ptr
;
896 case INDEX_op_goto_tb
:
897 tci_args_l(&tb_ptr
, &ptr
);
898 tb_ptr
= *(void **)ptr
;
901 case INDEX_op_qemu_ld_i32
:
902 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
903 tci_args_rrm(&tb_ptr
, &r0
, &r1
, &oi
);
906 tci_args_rrrm(&tb_ptr
, &r0
, &r1
, &r2
, &oi
);
907 taddr
= tci_uint64(regs
[r2
], regs
[r1
]);
909 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
914 tmp32
= (int8_t)qemu_ld_ub
;
917 tmp32
= qemu_ld_leuw
;
920 tmp32
= (int16_t)qemu_ld_leuw
;
923 tmp32
= qemu_ld_leul
;
926 tmp32
= qemu_ld_beuw
;
929 tmp32
= (int16_t)qemu_ld_beuw
;
932 tmp32
= qemu_ld_beul
;
935 g_assert_not_reached();
940 case INDEX_op_qemu_ld_i64
:
941 if (TCG_TARGET_REG_BITS
== 64) {
942 tci_args_rrm(&tb_ptr
, &r0
, &r1
, &oi
);
944 } else if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
945 tci_args_rrrm(&tb_ptr
, &r0
, &r1
, &r2
, &oi
);
948 tci_args_rrrrm(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &oi
);
949 taddr
= tci_uint64(regs
[r3
], regs
[r2
]);
951 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
956 tmp64
= (int8_t)qemu_ld_ub
;
959 tmp64
= qemu_ld_leuw
;
962 tmp64
= (int16_t)qemu_ld_leuw
;
965 tmp64
= qemu_ld_leul
;
968 tmp64
= (int32_t)qemu_ld_leul
;
974 tmp64
= qemu_ld_beuw
;
977 tmp64
= (int16_t)qemu_ld_beuw
;
980 tmp64
= qemu_ld_beul
;
983 tmp64
= (int32_t)qemu_ld_beul
;
989 g_assert_not_reached();
991 if (TCG_TARGET_REG_BITS
== 32) {
992 tci_write_reg64(regs
, r1
, r0
, tmp64
);
998 case INDEX_op_qemu_st_i32
:
999 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
1000 tci_args_rrm(&tb_ptr
, &r0
, &r1
, &oi
);
1003 tci_args_rrrm(&tb_ptr
, &r0
, &r1
, &r2
, &oi
);
1004 taddr
= tci_uint64(regs
[r2
], regs
[r1
]);
1007 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
1024 g_assert_not_reached();
1028 case INDEX_op_qemu_st_i64
:
1029 if (TCG_TARGET_REG_BITS
== 64) {
1030 tci_args_rrm(&tb_ptr
, &r0
, &r1
, &oi
);
1034 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
1035 tci_args_rrrm(&tb_ptr
, &r0
, &r1
, &r2
, &oi
);
1038 tci_args_rrrrm(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &oi
);
1039 taddr
= tci_uint64(regs
[r3
], regs
[r2
]);
1041 tmp64
= tci_uint64(regs
[r1
], regs
[r0
]);
1043 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
1066 g_assert_not_reached();
1071 /* Ensure ordering for all kinds */
1075 g_assert_not_reached();
1081 * Disassembler that matches the interpreter
1084 static const char *str_r(TCGReg r
)
1086 static const char regs
[TCG_TARGET_NB_REGS
][4] = {
1087 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1088 "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
1091 QEMU_BUILD_BUG_ON(TCG_AREG0
!= TCG_REG_R14
);
1092 QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK
!= TCG_REG_R15
);
1094 assert((unsigned)r
< TCG_TARGET_NB_REGS
);
1098 static const char *str_c(TCGCond c
)
1100 static const char cond
[16][8] = {
1101 [TCG_COND_NEVER
] = "never",
1102 [TCG_COND_ALWAYS
] = "always",
1103 [TCG_COND_EQ
] = "eq",
1104 [TCG_COND_NE
] = "ne",
1105 [TCG_COND_LT
] = "lt",
1106 [TCG_COND_GE
] = "ge",
1107 [TCG_COND_LE
] = "le",
1108 [TCG_COND_GT
] = "gt",
1109 [TCG_COND_LTU
] = "ltu",
1110 [TCG_COND_GEU
] = "geu",
1111 [TCG_COND_LEU
] = "leu",
1112 [TCG_COND_GTU
] = "gtu",
1115 assert((unsigned)c
< ARRAY_SIZE(cond
));
1116 assert(cond
[c
][0] != 0);
1120 /* Disassemble TCI bytecode. */
1121 int print_insn_tci(bfd_vma addr
, disassemble_info
*info
)
1125 const TCGOpDef
*def
;
1126 const char *op_name
;
1128 TCGReg r0
, r1
, r2
, r3
;
1129 #if TCG_TARGET_REG_BITS == 32
1132 tcg_target_ulong i1
;
1138 const uint8_t *tb_ptr
;
1140 status
= info
->read_memory_func(addr
, buf
, 2, info
);
1142 info
->memory_error_func(status
, addr
, info
);
1149 info
->fprintf_func(info
->stream
, "invalid length %d", length
);
1153 status
= info
->read_memory_func(addr
+ 2, buf
+ 2, length
- 2, info
);
1155 info
->memory_error_func(status
, addr
+ 2, info
);
1159 def
= &tcg_op_defs
[op
];
1160 op_name
= def
->name
;
1165 case INDEX_op_exit_tb
:
1166 case INDEX_op_goto_tb
:
1167 tci_args_l(&tb_ptr
, &ptr
);
1168 info
->fprintf_func(info
->stream
, "%-12s %p", op_name
, ptr
);
1172 tci_args_nll(&tb_ptr
, &len
, &ptr
, &cif
);
1173 info
->fprintf_func(info
->stream
, "%-12s %d, %p, %p",
1174 op_name
, len
, ptr
, cif
);
1177 case INDEX_op_brcond_i32
:
1178 case INDEX_op_brcond_i64
:
1179 tci_args_rrcl(&tb_ptr
, &r0
, &r1
, &c
, &ptr
);
1180 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %p",
1181 op_name
, str_r(r0
), str_r(r1
), str_c(c
), ptr
);
1184 case INDEX_op_setcond_i32
:
1185 case INDEX_op_setcond_i64
:
1186 tci_args_rrrc(&tb_ptr
, &r0
, &r1
, &r2
, &c
);
1187 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s",
1188 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), str_c(c
));
1191 case INDEX_op_tci_movi_i32
:
1192 tci_args_ri(&tb_ptr
, &r0
, &i1
);
1193 info
->fprintf_func(info
->stream
, "%-12s %s, 0x%" TCG_PRIlx
,
1194 op_name
, str_r(r0
), i1
);
1197 #if TCG_TARGET_REG_BITS == 64
1198 case INDEX_op_tci_movi_i64
:
1199 tci_args_rI(&tb_ptr
, &r0
, &i1
);
1200 info
->fprintf_func(info
->stream
, "%-12s %s, 0x%" TCG_PRIlx
,
1201 op_name
, str_r(r0
), i1
);
1205 case INDEX_op_ld8u_i32
:
1206 case INDEX_op_ld8u_i64
:
1207 case INDEX_op_ld8s_i32
:
1208 case INDEX_op_ld8s_i64
:
1209 case INDEX_op_ld16u_i32
:
1210 case INDEX_op_ld16u_i64
:
1211 case INDEX_op_ld16s_i32
:
1212 case INDEX_op_ld16s_i64
:
1213 case INDEX_op_ld32u_i64
:
1214 case INDEX_op_ld32s_i64
:
1215 case INDEX_op_ld_i32
:
1216 case INDEX_op_ld_i64
:
1217 case INDEX_op_st8_i32
:
1218 case INDEX_op_st8_i64
:
1219 case INDEX_op_st16_i32
:
1220 case INDEX_op_st16_i64
:
1221 case INDEX_op_st32_i64
:
1222 case INDEX_op_st_i32
:
1223 case INDEX_op_st_i64
:
1224 tci_args_rrs(&tb_ptr
, &r0
, &r1
, &s2
);
1225 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %d",
1226 op_name
, str_r(r0
), str_r(r1
), s2
);
1229 case INDEX_op_mov_i32
:
1230 case INDEX_op_mov_i64
:
1231 case INDEX_op_ext8s_i32
:
1232 case INDEX_op_ext8s_i64
:
1233 case INDEX_op_ext8u_i32
:
1234 case INDEX_op_ext8u_i64
:
1235 case INDEX_op_ext16s_i32
:
1236 case INDEX_op_ext16s_i64
:
1237 case INDEX_op_ext16u_i32
:
1238 case INDEX_op_ext32s_i64
:
1239 case INDEX_op_ext32u_i64
:
1240 case INDEX_op_ext_i32_i64
:
1241 case INDEX_op_extu_i32_i64
:
1242 case INDEX_op_bswap16_i32
:
1243 case INDEX_op_bswap16_i64
:
1244 case INDEX_op_bswap32_i32
:
1245 case INDEX_op_bswap32_i64
:
1246 case INDEX_op_bswap64_i64
:
1247 case INDEX_op_not_i32
:
1248 case INDEX_op_not_i64
:
1249 case INDEX_op_neg_i32
:
1250 case INDEX_op_neg_i64
:
1251 tci_args_rr(&tb_ptr
, &r0
, &r1
);
1252 info
->fprintf_func(info
->stream
, "%-12s %s, %s",
1253 op_name
, str_r(r0
), str_r(r1
));
1256 case INDEX_op_add_i32
:
1257 case INDEX_op_add_i64
:
1258 case INDEX_op_sub_i32
:
1259 case INDEX_op_sub_i64
:
1260 case INDEX_op_mul_i32
:
1261 case INDEX_op_mul_i64
:
1262 case INDEX_op_and_i32
:
1263 case INDEX_op_and_i64
:
1264 case INDEX_op_or_i32
:
1265 case INDEX_op_or_i64
:
1266 case INDEX_op_xor_i32
:
1267 case INDEX_op_xor_i64
:
1268 case INDEX_op_div_i32
:
1269 case INDEX_op_div_i64
:
1270 case INDEX_op_rem_i32
:
1271 case INDEX_op_rem_i64
:
1272 case INDEX_op_divu_i32
:
1273 case INDEX_op_divu_i64
:
1274 case INDEX_op_remu_i32
:
1275 case INDEX_op_remu_i64
:
1276 case INDEX_op_shl_i32
:
1277 case INDEX_op_shl_i64
:
1278 case INDEX_op_shr_i32
:
1279 case INDEX_op_shr_i64
:
1280 case INDEX_op_sar_i32
:
1281 case INDEX_op_sar_i64
:
1282 case INDEX_op_rotl_i32
:
1283 case INDEX_op_rotl_i64
:
1284 case INDEX_op_rotr_i32
:
1285 case INDEX_op_rotr_i64
:
1286 tci_args_rrr(&tb_ptr
, &r0
, &r1
, &r2
);
1287 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s",
1288 op_name
, str_r(r0
), str_r(r1
), str_r(r2
));
1291 case INDEX_op_deposit_i32
:
1292 case INDEX_op_deposit_i64
:
1293 tci_args_rrrbb(&tb_ptr
, &r0
, &r1
, &r2
, &pos
, &len
);
1294 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %d, %d",
1295 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), pos
, len
);
1298 #if TCG_TARGET_REG_BITS == 32
1299 case INDEX_op_setcond2_i32
:
1300 tci_args_rrrrrc(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &r4
, &c
);
1301 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %s",
1302 op_name
, str_r(r0
), str_r(r1
), str_r(r2
),
1303 str_r(r3
), str_r(r4
), str_c(c
));
1306 case INDEX_op_brcond2_i32
:
1307 tci_args_rrrrcl(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &c
, &ptr
);
1308 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %p",
1309 op_name
, str_r(r0
), str_r(r1
),
1310 str_r(r2
), str_r(r3
), str_c(c
), ptr
);
1313 case INDEX_op_mulu2_i32
:
1314 tci_args_rrrr(&tb_ptr
, &r0
, &r1
, &r2
, &r3
);
1315 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s",
1316 op_name
, str_r(r0
), str_r(r1
),
1317 str_r(r2
), str_r(r3
));
1320 case INDEX_op_add2_i32
:
1321 case INDEX_op_sub2_i32
:
1322 tci_args_rrrrrr(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
1323 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %s",
1324 op_name
, str_r(r0
), str_r(r1
), str_r(r2
),
1325 str_r(r3
), str_r(r4
), str_r(r5
));
1329 case INDEX_op_qemu_ld_i64
:
1330 case INDEX_op_qemu_st_i64
:
1331 len
= DIV_ROUND_UP(64, TCG_TARGET_REG_BITS
);
1333 case INDEX_op_qemu_ld_i32
:
1334 case INDEX_op_qemu_st_i32
:
1337 len
+= DIV_ROUND_UP(TARGET_LONG_BITS
, TCG_TARGET_REG_BITS
);
1340 tci_args_rrm(&tb_ptr
, &r0
, &r1
, &oi
);
1341 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %x",
1342 op_name
, str_r(r0
), str_r(r1
), oi
);
1345 tci_args_rrrm(&tb_ptr
, &r0
, &r1
, &r2
, &oi
);
1346 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %x",
1347 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), oi
);
1350 tci_args_rrrrm(&tb_ptr
, &r0
, &r1
, &r2
, &r3
, &oi
);
1351 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %x",
1352 op_name
, str_r(r0
), str_r(r1
),
1353 str_r(r2
), str_r(r3
), oi
);
1356 g_assert_not_reached();
1361 info
->fprintf_func(info
->stream
, "illegal opcode %d", op
);