2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
31 /* Marker for missing code. */
34 fprintf(stderr, "TODO %s:%u: %s()\n", \
35 __FILE__, __LINE__, __func__); \
39 #if MAX_OPC_PARAM_IARGS != 5
40 # error Fix needed, number of supported input arguments changed!
42 #if TCG_TARGET_REG_BITS == 32
43 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
44 tcg_target_ulong
, tcg_target_ulong
,
45 tcg_target_ulong
, tcg_target_ulong
,
46 tcg_target_ulong
, tcg_target_ulong
,
47 tcg_target_ulong
, tcg_target_ulong
);
49 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
50 tcg_target_ulong
, tcg_target_ulong
,
54 /* Targets which don't use GETPC also don't need tci_tb_ptr
55 which makes them a little faster. */
60 static tcg_target_ulong tci_reg
[TCG_TARGET_NB_REGS
];
62 static tcg_target_ulong
tci_read_reg(TCGReg index
)
64 assert(index
< ARRAY_SIZE(tci_reg
));
65 return tci_reg
[index
];
68 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
69 static int8_t tci_read_reg8s(TCGReg index
)
71 return (int8_t)tci_read_reg(index
);
75 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
76 static int16_t tci_read_reg16s(TCGReg index
)
78 return (int16_t)tci_read_reg(index
);
82 #if TCG_TARGET_REG_BITS == 64
83 static int32_t tci_read_reg32s(TCGReg index
)
85 return (int32_t)tci_read_reg(index
);
89 static uint8_t tci_read_reg8(TCGReg index
)
91 return (uint8_t)tci_read_reg(index
);
94 static uint16_t tci_read_reg16(TCGReg index
)
96 return (uint16_t)tci_read_reg(index
);
99 static uint32_t tci_read_reg32(TCGReg index
)
101 return (uint32_t)tci_read_reg(index
);
104 #if TCG_TARGET_REG_BITS == 64
105 static uint64_t tci_read_reg64(TCGReg index
)
107 return tci_read_reg(index
);
111 static void tci_write_reg(TCGReg index
, tcg_target_ulong value
)
113 assert(index
< ARRAY_SIZE(tci_reg
));
114 assert(index
!= TCG_AREG0
);
115 tci_reg
[index
] = value
;
118 static void tci_write_reg8s(TCGReg index
, int8_t value
)
120 tci_write_reg(index
, value
);
123 static void tci_write_reg16s(TCGReg index
, int16_t value
)
125 tci_write_reg(index
, value
);
128 #if TCG_TARGET_REG_BITS == 64
129 static void tci_write_reg32s(TCGReg index
, int32_t value
)
131 tci_write_reg(index
, value
);
135 static void tci_write_reg8(TCGReg index
, uint8_t value
)
137 tci_write_reg(index
, value
);
140 static void tci_write_reg16(TCGReg index
, uint16_t value
)
142 tci_write_reg(index
, value
);
145 static void tci_write_reg32(TCGReg index
, uint32_t value
)
147 tci_write_reg(index
, value
);
150 #if TCG_TARGET_REG_BITS == 32
151 static void tci_write_reg64(uint32_t high_index
, uint32_t low_index
,
154 tci_write_reg(low_index
, value
);
155 tci_write_reg(high_index
, value
>> 32);
157 #elif TCG_TARGET_REG_BITS == 64
158 static void tci_write_reg64(TCGReg index
, uint64_t value
)
160 tci_write_reg(index
, value
);
164 #if TCG_TARGET_REG_BITS == 32
165 /* Create a 64 bit value from two 32 bit values. */
166 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
168 return ((uint64_t)high
<< 32) + low
;
172 /* Read constant (native size) from bytecode. */
173 static tcg_target_ulong
tci_read_i(uint8_t **tb_ptr
)
175 tcg_target_ulong value
= *(tcg_target_ulong
*)(*tb_ptr
);
176 *tb_ptr
+= sizeof(value
);
180 /* Read unsigned constant (32 bit) from bytecode. */
181 static uint32_t tci_read_i32(uint8_t **tb_ptr
)
183 uint32_t value
= *(uint32_t *)(*tb_ptr
);
184 *tb_ptr
+= sizeof(value
);
188 /* Read signed constant (32 bit) from bytecode. */
189 static int32_t tci_read_s32(uint8_t **tb_ptr
)
191 int32_t value
= *(int32_t *)(*tb_ptr
);
192 *tb_ptr
+= sizeof(value
);
196 #if TCG_TARGET_REG_BITS == 64
197 /* Read constant (64 bit) from bytecode. */
198 static uint64_t tci_read_i64(uint8_t **tb_ptr
)
200 uint64_t value
= *(uint64_t *)(*tb_ptr
);
201 *tb_ptr
+= sizeof(value
);
206 /* Read indexed register (native size) from bytecode. */
207 static tcg_target_ulong
tci_read_r(uint8_t **tb_ptr
)
209 tcg_target_ulong value
= tci_read_reg(**tb_ptr
);
214 /* Read indexed register (8 bit) from bytecode. */
215 static uint8_t tci_read_r8(uint8_t **tb_ptr
)
217 uint8_t value
= tci_read_reg8(**tb_ptr
);
222 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
223 /* Read indexed register (8 bit signed) from bytecode. */
224 static int8_t tci_read_r8s(uint8_t **tb_ptr
)
226 int8_t value
= tci_read_reg8s(**tb_ptr
);
232 /* Read indexed register (16 bit) from bytecode. */
233 static uint16_t tci_read_r16(uint8_t **tb_ptr
)
235 uint16_t value
= tci_read_reg16(**tb_ptr
);
240 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
241 /* Read indexed register (16 bit signed) from bytecode. */
242 static int16_t tci_read_r16s(uint8_t **tb_ptr
)
244 int16_t value
= tci_read_reg16s(**tb_ptr
);
250 /* Read indexed register (32 bit) from bytecode. */
251 static uint32_t tci_read_r32(uint8_t **tb_ptr
)
253 uint32_t value
= tci_read_reg32(**tb_ptr
);
258 #if TCG_TARGET_REG_BITS == 32
259 /* Read two indexed registers (2 * 32 bit) from bytecode. */
260 static uint64_t tci_read_r64(uint8_t **tb_ptr
)
262 uint32_t low
= tci_read_r32(tb_ptr
);
263 return tci_uint64(tci_read_r32(tb_ptr
), low
);
265 #elif TCG_TARGET_REG_BITS == 64
266 /* Read indexed register (32 bit signed) from bytecode. */
267 static int32_t tci_read_r32s(uint8_t **tb_ptr
)
269 int32_t value
= tci_read_reg32s(**tb_ptr
);
274 /* Read indexed register (64 bit) from bytecode. */
275 static uint64_t tci_read_r64(uint8_t **tb_ptr
)
277 uint64_t value
= tci_read_reg64(**tb_ptr
);
283 /* Read indexed register(s) with target address from bytecode. */
284 static target_ulong
tci_read_ulong(uint8_t **tb_ptr
)
286 target_ulong taddr
= tci_read_r(tb_ptr
);
287 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
288 taddr
+= (uint64_t)tci_read_r(tb_ptr
) << 32;
293 /* Read indexed register or constant (native size) from bytecode. */
294 static tcg_target_ulong
tci_read_ri(uint8_t **tb_ptr
)
296 tcg_target_ulong value
;
299 if (r
== TCG_CONST
) {
300 value
= tci_read_i(tb_ptr
);
302 value
= tci_read_reg(r
);
307 /* Read indexed register or constant (32 bit) from bytecode. */
308 static uint32_t tci_read_ri32(uint8_t **tb_ptr
)
313 if (r
== TCG_CONST
) {
314 value
= tci_read_i32(tb_ptr
);
316 value
= tci_read_reg32(r
);
321 #if TCG_TARGET_REG_BITS == 32
322 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
323 static uint64_t tci_read_ri64(uint8_t **tb_ptr
)
325 uint32_t low
= tci_read_ri32(tb_ptr
);
326 return tci_uint64(tci_read_ri32(tb_ptr
), low
);
328 #elif TCG_TARGET_REG_BITS == 64
329 /* Read indexed register or constant (64 bit) from bytecode. */
330 static uint64_t tci_read_ri64(uint8_t **tb_ptr
)
335 if (r
== TCG_CONST
) {
336 value
= tci_read_i64(tb_ptr
);
338 value
= tci_read_reg64(r
);
344 static tcg_target_ulong
tci_read_label(uint8_t **tb_ptr
)
346 tcg_target_ulong label
= tci_read_i(tb_ptr
);
351 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
393 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
435 /* Interpret pseudo code in tb. */
436 tcg_target_ulong
tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
)
438 tcg_target_ulong next_tb
= 0;
440 tci_reg
[TCG_AREG0
] = (tcg_target_ulong
)env
;
444 TCGOpcode opc
= tb_ptr
[0];
446 uint8_t op_size
= tb_ptr
[1];
447 uint8_t *old_code_ptr
= tb_ptr
;
452 tcg_target_ulong label
;
455 #ifndef CONFIG_SOFTMMU
456 tcg_target_ulong host_addr
;
462 #if TCG_TARGET_REG_BITS == 32
467 tci_tb_ptr
= (uintptr_t)tb_ptr
;
470 /* Skip opcode and size entry. */
481 case INDEX_op_discard
:
484 case INDEX_op_set_label
:
488 t0
= tci_read_ri(&tb_ptr
);
489 #if TCG_TARGET_REG_BITS == 32
490 tmp64
= ((helper_function
)t0
)(tci_read_reg(TCG_REG_R0
),
491 tci_read_reg(TCG_REG_R1
),
492 tci_read_reg(TCG_REG_R2
),
493 tci_read_reg(TCG_REG_R3
),
494 tci_read_reg(TCG_REG_R5
),
495 tci_read_reg(TCG_REG_R6
),
496 tci_read_reg(TCG_REG_R7
),
497 tci_read_reg(TCG_REG_R8
),
498 tci_read_reg(TCG_REG_R9
),
499 tci_read_reg(TCG_REG_R10
));
500 tci_write_reg(TCG_REG_R0
, tmp64
);
501 tci_write_reg(TCG_REG_R1
, tmp64
>> 32);
503 tmp64
= ((helper_function
)t0
)(tci_read_reg(TCG_REG_R0
),
504 tci_read_reg(TCG_REG_R1
),
505 tci_read_reg(TCG_REG_R2
),
506 tci_read_reg(TCG_REG_R3
),
507 tci_read_reg(TCG_REG_R5
));
508 tci_write_reg(TCG_REG_R0
, tmp64
);
512 label
= tci_read_label(&tb_ptr
);
513 assert(tb_ptr
== old_code_ptr
+ op_size
);
514 tb_ptr
= (uint8_t *)label
;
516 case INDEX_op_setcond_i32
:
518 t1
= tci_read_r32(&tb_ptr
);
519 t2
= tci_read_ri32(&tb_ptr
);
520 condition
= *tb_ptr
++;
521 tci_write_reg32(t0
, tci_compare32(t1
, t2
, condition
));
523 #if TCG_TARGET_REG_BITS == 32
524 case INDEX_op_setcond2_i32
:
526 tmp64
= tci_read_r64(&tb_ptr
);
527 v64
= tci_read_ri64(&tb_ptr
);
528 condition
= *tb_ptr
++;
529 tci_write_reg32(t0
, tci_compare64(tmp64
, v64
, condition
));
531 #elif TCG_TARGET_REG_BITS == 64
532 case INDEX_op_setcond_i64
:
534 t1
= tci_read_r64(&tb_ptr
);
535 t2
= tci_read_ri64(&tb_ptr
);
536 condition
= *tb_ptr
++;
537 tci_write_reg64(t0
, tci_compare64(t1
, t2
, condition
));
540 case INDEX_op_mov_i32
:
542 t1
= tci_read_r32(&tb_ptr
);
543 tci_write_reg32(t0
, t1
);
545 case INDEX_op_movi_i32
:
547 t1
= tci_read_i32(&tb_ptr
);
548 tci_write_reg32(t0
, t1
);
551 /* Load/store operations (32 bit). */
553 case INDEX_op_ld8u_i32
:
555 t1
= tci_read_r(&tb_ptr
);
556 t2
= tci_read_s32(&tb_ptr
);
557 tci_write_reg8(t0
, *(uint8_t *)(t1
+ t2
));
559 case INDEX_op_ld8s_i32
:
560 case INDEX_op_ld16u_i32
:
563 case INDEX_op_ld16s_i32
:
566 case INDEX_op_ld_i32
:
568 t1
= tci_read_r(&tb_ptr
);
569 t2
= tci_read_s32(&tb_ptr
);
570 tci_write_reg32(t0
, *(uint32_t *)(t1
+ t2
));
572 case INDEX_op_st8_i32
:
573 t0
= tci_read_r8(&tb_ptr
);
574 t1
= tci_read_r(&tb_ptr
);
575 t2
= tci_read_s32(&tb_ptr
);
576 *(uint8_t *)(t1
+ t2
) = t0
;
578 case INDEX_op_st16_i32
:
579 t0
= tci_read_r16(&tb_ptr
);
580 t1
= tci_read_r(&tb_ptr
);
581 t2
= tci_read_s32(&tb_ptr
);
582 *(uint16_t *)(t1
+ t2
) = t0
;
584 case INDEX_op_st_i32
:
585 t0
= tci_read_r32(&tb_ptr
);
586 t1
= tci_read_r(&tb_ptr
);
587 t2
= tci_read_s32(&tb_ptr
);
588 *(uint32_t *)(t1
+ t2
) = t0
;
591 /* Arithmetic operations (32 bit). */
593 case INDEX_op_add_i32
:
595 t1
= tci_read_ri32(&tb_ptr
);
596 t2
= tci_read_ri32(&tb_ptr
);
597 tci_write_reg32(t0
, t1
+ t2
);
599 case INDEX_op_sub_i32
:
601 t1
= tci_read_ri32(&tb_ptr
);
602 t2
= tci_read_ri32(&tb_ptr
);
603 tci_write_reg32(t0
, t1
- t2
);
605 case INDEX_op_mul_i32
:
607 t1
= tci_read_ri32(&tb_ptr
);
608 t2
= tci_read_ri32(&tb_ptr
);
609 tci_write_reg32(t0
, t1
* t2
);
611 #if TCG_TARGET_HAS_div_i32
612 case INDEX_op_div_i32
:
614 t1
= tci_read_ri32(&tb_ptr
);
615 t2
= tci_read_ri32(&tb_ptr
);
616 tci_write_reg32(t0
, (int32_t)t1
/ (int32_t)t2
);
618 case INDEX_op_divu_i32
:
620 t1
= tci_read_ri32(&tb_ptr
);
621 t2
= tci_read_ri32(&tb_ptr
);
622 tci_write_reg32(t0
, t1
/ t2
);
624 case INDEX_op_rem_i32
:
626 t1
= tci_read_ri32(&tb_ptr
);
627 t2
= tci_read_ri32(&tb_ptr
);
628 tci_write_reg32(t0
, (int32_t)t1
% (int32_t)t2
);
630 case INDEX_op_remu_i32
:
632 t1
= tci_read_ri32(&tb_ptr
);
633 t2
= tci_read_ri32(&tb_ptr
);
634 tci_write_reg32(t0
, t1
% t2
);
636 #elif TCG_TARGET_HAS_div2_i32
637 case INDEX_op_div2_i32
:
638 case INDEX_op_divu2_i32
:
642 case INDEX_op_and_i32
:
644 t1
= tci_read_ri32(&tb_ptr
);
645 t2
= tci_read_ri32(&tb_ptr
);
646 tci_write_reg32(t0
, t1
& t2
);
648 case INDEX_op_or_i32
:
650 t1
= tci_read_ri32(&tb_ptr
);
651 t2
= tci_read_ri32(&tb_ptr
);
652 tci_write_reg32(t0
, t1
| t2
);
654 case INDEX_op_xor_i32
:
656 t1
= tci_read_ri32(&tb_ptr
);
657 t2
= tci_read_ri32(&tb_ptr
);
658 tci_write_reg32(t0
, t1
^ t2
);
661 /* Shift/rotate operations (32 bit). */
663 case INDEX_op_shl_i32
:
665 t1
= tci_read_ri32(&tb_ptr
);
666 t2
= tci_read_ri32(&tb_ptr
);
667 tci_write_reg32(t0
, t1
<< t2
);
669 case INDEX_op_shr_i32
:
671 t1
= tci_read_ri32(&tb_ptr
);
672 t2
= tci_read_ri32(&tb_ptr
);
673 tci_write_reg32(t0
, t1
>> t2
);
675 case INDEX_op_sar_i32
:
677 t1
= tci_read_ri32(&tb_ptr
);
678 t2
= tci_read_ri32(&tb_ptr
);
679 tci_write_reg32(t0
, ((int32_t)t1
>> t2
));
681 #if TCG_TARGET_HAS_rot_i32
682 case INDEX_op_rotl_i32
:
684 t1
= tci_read_ri32(&tb_ptr
);
685 t2
= tci_read_ri32(&tb_ptr
);
686 tci_write_reg32(t0
, (t1
<< t2
) | (t1
>> (32 - t2
)));
688 case INDEX_op_rotr_i32
:
690 t1
= tci_read_ri32(&tb_ptr
);
691 t2
= tci_read_ri32(&tb_ptr
);
692 tci_write_reg32(t0
, (t1
>> t2
) | (t1
<< (32 - t2
)));
695 #if TCG_TARGET_HAS_deposit_i32
696 case INDEX_op_deposit_i32
:
698 t1
= tci_read_r32(&tb_ptr
);
699 t2
= tci_read_r32(&tb_ptr
);
702 tmp32
= (((1 << tmp8
) - 1) << tmp16
);
703 tci_write_reg32(t0
, (t1
& ~tmp32
) | ((t2
<< tmp16
) & tmp32
));
706 case INDEX_op_brcond_i32
:
707 t0
= tci_read_r32(&tb_ptr
);
708 t1
= tci_read_ri32(&tb_ptr
);
709 condition
= *tb_ptr
++;
710 label
= tci_read_label(&tb_ptr
);
711 if (tci_compare32(t0
, t1
, condition
)) {
712 assert(tb_ptr
== old_code_ptr
+ op_size
);
713 tb_ptr
= (uint8_t *)label
;
717 #if TCG_TARGET_REG_BITS == 32
718 case INDEX_op_add2_i32
:
721 tmp64
= tci_read_r64(&tb_ptr
);
722 tmp64
+= tci_read_r64(&tb_ptr
);
723 tci_write_reg64(t1
, t0
, tmp64
);
725 case INDEX_op_sub2_i32
:
728 tmp64
= tci_read_r64(&tb_ptr
);
729 tmp64
-= tci_read_r64(&tb_ptr
);
730 tci_write_reg64(t1
, t0
, tmp64
);
732 case INDEX_op_brcond2_i32
:
733 tmp64
= tci_read_r64(&tb_ptr
);
734 v64
= tci_read_ri64(&tb_ptr
);
735 condition
= *tb_ptr
++;
736 label
= tci_read_label(&tb_ptr
);
737 if (tci_compare64(tmp64
, v64
, condition
)) {
738 assert(tb_ptr
== old_code_ptr
+ op_size
);
739 tb_ptr
= (uint8_t *)label
;
743 case INDEX_op_mulu2_i32
:
746 t2
= tci_read_r32(&tb_ptr
);
747 tmp64
= tci_read_r32(&tb_ptr
);
748 tci_write_reg64(t1
, t0
, t2
* tmp64
);
750 #endif /* TCG_TARGET_REG_BITS == 32 */
751 #if TCG_TARGET_HAS_ext8s_i32
752 case INDEX_op_ext8s_i32
:
754 t1
= tci_read_r8s(&tb_ptr
);
755 tci_write_reg32(t0
, t1
);
758 #if TCG_TARGET_HAS_ext16s_i32
759 case INDEX_op_ext16s_i32
:
761 t1
= tci_read_r16s(&tb_ptr
);
762 tci_write_reg32(t0
, t1
);
765 #if TCG_TARGET_HAS_ext8u_i32
766 case INDEX_op_ext8u_i32
:
768 t1
= tci_read_r8(&tb_ptr
);
769 tci_write_reg32(t0
, t1
);
772 #if TCG_TARGET_HAS_ext16u_i32
773 case INDEX_op_ext16u_i32
:
775 t1
= tci_read_r16(&tb_ptr
);
776 tci_write_reg32(t0
, t1
);
779 #if TCG_TARGET_HAS_bswap16_i32
780 case INDEX_op_bswap16_i32
:
782 t1
= tci_read_r16(&tb_ptr
);
783 tci_write_reg32(t0
, bswap16(t1
));
786 #if TCG_TARGET_HAS_bswap32_i32
787 case INDEX_op_bswap32_i32
:
789 t1
= tci_read_r32(&tb_ptr
);
790 tci_write_reg32(t0
, bswap32(t1
));
793 #if TCG_TARGET_HAS_not_i32
794 case INDEX_op_not_i32
:
796 t1
= tci_read_r32(&tb_ptr
);
797 tci_write_reg32(t0
, ~t1
);
800 #if TCG_TARGET_HAS_neg_i32
801 case INDEX_op_neg_i32
:
803 t1
= tci_read_r32(&tb_ptr
);
804 tci_write_reg32(t0
, -t1
);
807 #if TCG_TARGET_REG_BITS == 64
808 case INDEX_op_mov_i64
:
810 t1
= tci_read_r64(&tb_ptr
);
811 tci_write_reg64(t0
, t1
);
813 case INDEX_op_movi_i64
:
815 t1
= tci_read_i64(&tb_ptr
);
816 tci_write_reg64(t0
, t1
);
819 /* Load/store operations (64 bit). */
821 case INDEX_op_ld8u_i64
:
823 t1
= tci_read_r(&tb_ptr
);
824 t2
= tci_read_s32(&tb_ptr
);
825 tci_write_reg8(t0
, *(uint8_t *)(t1
+ t2
));
827 case INDEX_op_ld8s_i64
:
828 case INDEX_op_ld16u_i64
:
829 case INDEX_op_ld16s_i64
:
832 case INDEX_op_ld32u_i64
:
834 t1
= tci_read_r(&tb_ptr
);
835 t2
= tci_read_s32(&tb_ptr
);
836 tci_write_reg32(t0
, *(uint32_t *)(t1
+ t2
));
838 case INDEX_op_ld32s_i64
:
840 t1
= tci_read_r(&tb_ptr
);
841 t2
= tci_read_s32(&tb_ptr
);
842 tci_write_reg32s(t0
, *(int32_t *)(t1
+ t2
));
844 case INDEX_op_ld_i64
:
846 t1
= tci_read_r(&tb_ptr
);
847 t2
= tci_read_s32(&tb_ptr
);
848 tci_write_reg64(t0
, *(uint64_t *)(t1
+ t2
));
850 case INDEX_op_st8_i64
:
851 t0
= tci_read_r8(&tb_ptr
);
852 t1
= tci_read_r(&tb_ptr
);
853 t2
= tci_read_s32(&tb_ptr
);
854 *(uint8_t *)(t1
+ t2
) = t0
;
856 case INDEX_op_st16_i64
:
857 t0
= tci_read_r16(&tb_ptr
);
858 t1
= tci_read_r(&tb_ptr
);
859 t2
= tci_read_s32(&tb_ptr
);
860 *(uint16_t *)(t1
+ t2
) = t0
;
862 case INDEX_op_st32_i64
:
863 t0
= tci_read_r32(&tb_ptr
);
864 t1
= tci_read_r(&tb_ptr
);
865 t2
= tci_read_s32(&tb_ptr
);
866 *(uint32_t *)(t1
+ t2
) = t0
;
868 case INDEX_op_st_i64
:
869 t0
= tci_read_r64(&tb_ptr
);
870 t1
= tci_read_r(&tb_ptr
);
871 t2
= tci_read_s32(&tb_ptr
);
872 *(uint64_t *)(t1
+ t2
) = t0
;
875 /* Arithmetic operations (64 bit). */
877 case INDEX_op_add_i64
:
879 t1
= tci_read_ri64(&tb_ptr
);
880 t2
= tci_read_ri64(&tb_ptr
);
881 tci_write_reg64(t0
, t1
+ t2
);
883 case INDEX_op_sub_i64
:
885 t1
= tci_read_ri64(&tb_ptr
);
886 t2
= tci_read_ri64(&tb_ptr
);
887 tci_write_reg64(t0
, t1
- t2
);
889 case INDEX_op_mul_i64
:
891 t1
= tci_read_ri64(&tb_ptr
);
892 t2
= tci_read_ri64(&tb_ptr
);
893 tci_write_reg64(t0
, t1
* t2
);
895 #if TCG_TARGET_HAS_div_i64
896 case INDEX_op_div_i64
:
897 case INDEX_op_divu_i64
:
898 case INDEX_op_rem_i64
:
899 case INDEX_op_remu_i64
:
902 #elif TCG_TARGET_HAS_div2_i64
903 case INDEX_op_div2_i64
:
904 case INDEX_op_divu2_i64
:
908 case INDEX_op_and_i64
:
910 t1
= tci_read_ri64(&tb_ptr
);
911 t2
= tci_read_ri64(&tb_ptr
);
912 tci_write_reg64(t0
, t1
& t2
);
914 case INDEX_op_or_i64
:
916 t1
= tci_read_ri64(&tb_ptr
);
917 t2
= tci_read_ri64(&tb_ptr
);
918 tci_write_reg64(t0
, t1
| t2
);
920 case INDEX_op_xor_i64
:
922 t1
= tci_read_ri64(&tb_ptr
);
923 t2
= tci_read_ri64(&tb_ptr
);
924 tci_write_reg64(t0
, t1
^ t2
);
927 /* Shift/rotate operations (64 bit). */
929 case INDEX_op_shl_i64
:
931 t1
= tci_read_ri64(&tb_ptr
);
932 t2
= tci_read_ri64(&tb_ptr
);
933 tci_write_reg64(t0
, t1
<< t2
);
935 case INDEX_op_shr_i64
:
937 t1
= tci_read_ri64(&tb_ptr
);
938 t2
= tci_read_ri64(&tb_ptr
);
939 tci_write_reg64(t0
, t1
>> t2
);
941 case INDEX_op_sar_i64
:
943 t1
= tci_read_ri64(&tb_ptr
);
944 t2
= tci_read_ri64(&tb_ptr
);
945 tci_write_reg64(t0
, ((int64_t)t1
>> t2
));
947 #if TCG_TARGET_HAS_rot_i64
948 case INDEX_op_rotl_i64
:
949 case INDEX_op_rotr_i64
:
953 #if TCG_TARGET_HAS_deposit_i64
954 case INDEX_op_deposit_i64
:
956 t1
= tci_read_r64(&tb_ptr
);
957 t2
= tci_read_r64(&tb_ptr
);
960 tmp64
= (((1ULL << tmp8
) - 1) << tmp16
);
961 tci_write_reg64(t0
, (t1
& ~tmp64
) | ((t2
<< tmp16
) & tmp64
));
964 case INDEX_op_brcond_i64
:
965 t0
= tci_read_r64(&tb_ptr
);
966 t1
= tci_read_ri64(&tb_ptr
);
967 condition
= *tb_ptr
++;
968 label
= tci_read_label(&tb_ptr
);
969 if (tci_compare64(t0
, t1
, condition
)) {
970 assert(tb_ptr
== old_code_ptr
+ op_size
);
971 tb_ptr
= (uint8_t *)label
;
975 #if TCG_TARGET_HAS_ext8u_i64
976 case INDEX_op_ext8u_i64
:
978 t1
= tci_read_r8(&tb_ptr
);
979 tci_write_reg64(t0
, t1
);
982 #if TCG_TARGET_HAS_ext8s_i64
983 case INDEX_op_ext8s_i64
:
985 t1
= tci_read_r8s(&tb_ptr
);
986 tci_write_reg64(t0
, t1
);
989 #if TCG_TARGET_HAS_ext16s_i64
990 case INDEX_op_ext16s_i64
:
992 t1
= tci_read_r16s(&tb_ptr
);
993 tci_write_reg64(t0
, t1
);
996 #if TCG_TARGET_HAS_ext16u_i64
997 case INDEX_op_ext16u_i64
:
999 t1
= tci_read_r16(&tb_ptr
);
1000 tci_write_reg64(t0
, t1
);
1003 #if TCG_TARGET_HAS_ext32s_i64
1004 case INDEX_op_ext32s_i64
:
1006 t1
= tci_read_r32s(&tb_ptr
);
1007 tci_write_reg64(t0
, t1
);
1010 #if TCG_TARGET_HAS_ext32u_i64
1011 case INDEX_op_ext32u_i64
:
1013 t1
= tci_read_r32(&tb_ptr
);
1014 tci_write_reg64(t0
, t1
);
1017 #if TCG_TARGET_HAS_bswap16_i64
1018 case INDEX_op_bswap16_i64
:
1021 t1
= tci_read_r16(&tb_ptr
);
1022 tci_write_reg64(t0
, bswap16(t1
));
1025 #if TCG_TARGET_HAS_bswap32_i64
1026 case INDEX_op_bswap32_i64
:
1028 t1
= tci_read_r32(&tb_ptr
);
1029 tci_write_reg64(t0
, bswap32(t1
));
1032 #if TCG_TARGET_HAS_bswap64_i64
1033 case INDEX_op_bswap64_i64
:
1035 t1
= tci_read_r64(&tb_ptr
);
1036 tci_write_reg64(t0
, bswap64(t1
));
1039 #if TCG_TARGET_HAS_not_i64
1040 case INDEX_op_not_i64
:
1042 t1
= tci_read_r64(&tb_ptr
);
1043 tci_write_reg64(t0
, ~t1
);
1046 #if TCG_TARGET_HAS_neg_i64
1047 case INDEX_op_neg_i64
:
1049 t1
= tci_read_r64(&tb_ptr
);
1050 tci_write_reg64(t0
, -t1
);
1053 #endif /* TCG_TARGET_REG_BITS == 64 */
1055 /* QEMU specific operations. */
1057 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1058 case INDEX_op_debug_insn_start
:
1062 case INDEX_op_debug_insn_start
:
1066 case INDEX_op_exit_tb
:
1067 next_tb
= *(uint64_t *)tb_ptr
;
1070 case INDEX_op_goto_tb
:
1071 t0
= tci_read_i32(&tb_ptr
);
1072 assert(tb_ptr
== old_code_ptr
+ op_size
);
1073 tb_ptr
+= (int32_t)t0
;
1075 case INDEX_op_qemu_ld8u
:
1077 taddr
= tci_read_ulong(&tb_ptr
);
1078 #ifdef CONFIG_SOFTMMU
1079 tmp8
= helper_ldb_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1081 host_addr
= (tcg_target_ulong
)taddr
;
1082 assert(taddr
== host_addr
);
1083 tmp8
= *(uint8_t *)(host_addr
+ GUEST_BASE
);
1085 tci_write_reg8(t0
, tmp8
);
1087 case INDEX_op_qemu_ld8s
:
1089 taddr
= tci_read_ulong(&tb_ptr
);
1090 #ifdef CONFIG_SOFTMMU
1091 tmp8
= helper_ldb_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1093 host_addr
= (tcg_target_ulong
)taddr
;
1094 assert(taddr
== host_addr
);
1095 tmp8
= *(uint8_t *)(host_addr
+ GUEST_BASE
);
1097 tci_write_reg8s(t0
, tmp8
);
1099 case INDEX_op_qemu_ld16u
:
1101 taddr
= tci_read_ulong(&tb_ptr
);
1102 #ifdef CONFIG_SOFTMMU
1103 tmp16
= helper_ldw_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1105 host_addr
= (tcg_target_ulong
)taddr
;
1106 assert(taddr
== host_addr
);
1107 tmp16
= tswap16(*(uint16_t *)(host_addr
+ GUEST_BASE
));
1109 tci_write_reg16(t0
, tmp16
);
1111 case INDEX_op_qemu_ld16s
:
1113 taddr
= tci_read_ulong(&tb_ptr
);
1114 #ifdef CONFIG_SOFTMMU
1115 tmp16
= helper_ldw_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1117 host_addr
= (tcg_target_ulong
)taddr
;
1118 assert(taddr
== host_addr
);
1119 tmp16
= tswap16(*(uint16_t *)(host_addr
+ GUEST_BASE
));
1121 tci_write_reg16s(t0
, tmp16
);
1123 #if TCG_TARGET_REG_BITS == 64
1124 case INDEX_op_qemu_ld32u
:
1126 taddr
= tci_read_ulong(&tb_ptr
);
1127 #ifdef CONFIG_SOFTMMU
1128 tmp32
= helper_ldl_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1130 host_addr
= (tcg_target_ulong
)taddr
;
1131 assert(taddr
== host_addr
);
1132 tmp32
= tswap32(*(uint32_t *)(host_addr
+ GUEST_BASE
));
1134 tci_write_reg32(t0
, tmp32
);
1136 case INDEX_op_qemu_ld32s
:
1138 taddr
= tci_read_ulong(&tb_ptr
);
1139 #ifdef CONFIG_SOFTMMU
1140 tmp32
= helper_ldl_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1142 host_addr
= (tcg_target_ulong
)taddr
;
1143 assert(taddr
== host_addr
);
1144 tmp32
= tswap32(*(uint32_t *)(host_addr
+ GUEST_BASE
));
1146 tci_write_reg32s(t0
, tmp32
);
1148 #endif /* TCG_TARGET_REG_BITS == 64 */
1149 case INDEX_op_qemu_ld32
:
1151 taddr
= tci_read_ulong(&tb_ptr
);
1152 #ifdef CONFIG_SOFTMMU
1153 tmp32
= helper_ldl_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1155 host_addr
= (tcg_target_ulong
)taddr
;
1156 assert(taddr
== host_addr
);
1157 tmp32
= tswap32(*(uint32_t *)(host_addr
+ GUEST_BASE
));
1159 tci_write_reg32(t0
, tmp32
);
1161 case INDEX_op_qemu_ld64
:
1163 #if TCG_TARGET_REG_BITS == 32
1166 taddr
= tci_read_ulong(&tb_ptr
);
1167 #ifdef CONFIG_SOFTMMU
1168 tmp64
= helper_ldq_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1170 host_addr
= (tcg_target_ulong
)taddr
;
1171 assert(taddr
== host_addr
);
1172 tmp64
= tswap64(*(uint64_t *)(host_addr
+ GUEST_BASE
));
1174 tci_write_reg(t0
, tmp64
);
1175 #if TCG_TARGET_REG_BITS == 32
1176 tci_write_reg(t1
, tmp64
>> 32);
1179 case INDEX_op_qemu_st8
:
1180 t0
= tci_read_r8(&tb_ptr
);
1181 taddr
= tci_read_ulong(&tb_ptr
);
1182 #ifdef CONFIG_SOFTMMU
1183 t2
= tci_read_i(&tb_ptr
);
1184 helper_stb_mmu(env
, taddr
, t0
, t2
);
1186 host_addr
= (tcg_target_ulong
)taddr
;
1187 assert(taddr
== host_addr
);
1188 *(uint8_t *)(host_addr
+ GUEST_BASE
) = t0
;
1191 case INDEX_op_qemu_st16
:
1192 t0
= tci_read_r16(&tb_ptr
);
1193 taddr
= tci_read_ulong(&tb_ptr
);
1194 #ifdef CONFIG_SOFTMMU
1195 t2
= tci_read_i(&tb_ptr
);
1196 helper_stw_mmu(env
, taddr
, t0
, t2
);
1198 host_addr
= (tcg_target_ulong
)taddr
;
1199 assert(taddr
== host_addr
);
1200 *(uint16_t *)(host_addr
+ GUEST_BASE
) = tswap16(t0
);
1203 case INDEX_op_qemu_st32
:
1204 t0
= tci_read_r32(&tb_ptr
);
1205 taddr
= tci_read_ulong(&tb_ptr
);
1206 #ifdef CONFIG_SOFTMMU
1207 t2
= tci_read_i(&tb_ptr
);
1208 helper_stl_mmu(env
, taddr
, t0
, t2
);
1210 host_addr
= (tcg_target_ulong
)taddr
;
1211 assert(taddr
== host_addr
);
1212 *(uint32_t *)(host_addr
+ GUEST_BASE
) = tswap32(t0
);
1215 case INDEX_op_qemu_st64
:
1216 tmp64
= tci_read_r64(&tb_ptr
);
1217 taddr
= tci_read_ulong(&tb_ptr
);
1218 #ifdef CONFIG_SOFTMMU
1219 t2
= tci_read_i(&tb_ptr
);
1220 helper_stq_mmu(env
, taddr
, tmp64
, t2
);
1222 host_addr
= (tcg_target_ulong
)taddr
;
1223 assert(taddr
== host_addr
);
1224 *(uint64_t *)(host_addr
+ GUEST_BASE
) = tswap64(tmp64
);
1231 assert(tb_ptr
== old_code_ptr
+ op_size
);