4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
36 #include "qemu-common.h"
37 #include "qemu/host-utils.h"
39 #include "hw/pci/pci_ids.h"
40 #include "hw/pci/pci_regs.h"
42 /* Test-specific defines -- in MiB */
43 #define TEST_IMAGE_SIZE_MB (200 * 1024)
44 #define TEST_IMAGE_SECTORS ((TEST_IMAGE_SIZE_MB / AHCI_SECTOR_SIZE) \
48 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
49 static char debug_path
[] = "/tmp/qtest-blkdebug.XXXXXX";
50 static char mig_socket
[] = "/tmp/qtest-migration.XXXXXX";
51 static bool ahci_pedantic
;
53 /*** Function Declarations ***/
54 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
55 static void ahci_test_pci_spec(AHCIQState
*ahci
);
56 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
58 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
59 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
60 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
64 static void string_bswap16(uint16_t *s
, size_t bytes
)
66 g_assert_cmphex((bytes
& 1), ==, 0);
76 * Verify that the transfer did not corrupt our state at all.
78 static void verify_state(AHCIQState
*ahci
)
81 uint32_t ahci_fingerprint
;
84 AHCICommandHeader cmd
;
86 ahci_fingerprint
= qpci_config_readl(ahci
->dev
, PCI_VENDOR_ID
);
87 g_assert_cmphex(ahci_fingerprint
, ==, ahci
->fingerprint
);
89 /* If we haven't initialized, this is as much as can be validated. */
90 if (!ahci
->hba_base
) {
94 hba_base
= (uint64_t)qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
95 hba_stored
= (uint64_t)(uintptr_t)ahci
->hba_base
;
96 g_assert_cmphex(hba_base
, ==, hba_stored
);
98 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP
), ==, ahci
->cap
);
99 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP2
), ==, ahci
->cap2
);
101 for (i
= 0; i
< 32; i
++) {
102 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_FB
), ==,
104 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_CLB
), ==,
106 for (j
= 0; j
< 32; j
++) {
107 ahci_get_command_header(ahci
, i
, j
, &cmd
);
108 g_assert_cmphex(cmd
.prdtl
, ==, ahci
->port
[i
].prdtl
[j
]);
109 g_assert_cmphex(cmd
.ctba
, ==, ahci
->port
[i
].ctba
[j
]);
114 static void ahci_migrate(AHCIQState
*from
, AHCIQState
*to
, const char *uri
)
116 QOSState
*tmp
= to
->parent
;
117 QPCIDevice
*dev
= to
->dev
;
118 char *uri_local
= NULL
;
121 uri_local
= g_strdup_printf("%s%s", "unix:", mig_socket
);
125 /* context will be 'to' after completion. */
126 migrate(from
->parent
, to
->parent
, uri
);
128 /* We'd like for the AHCIState objects to still point
129 * to information specific to its specific parent
130 * instance, but otherwise just inherit the new data. */
131 memcpy(to
, from
, sizeof(AHCIQState
));
137 memset(from
, 0x00, sizeof(AHCIQState
));
145 /*** Test Setup & Teardown ***/
148 * Start a Q35 machine and bookmark a handle to the AHCI device.
150 static AHCIQState
*ahci_vboot(const char *cli
, va_list ap
)
154 s
= g_malloc0(sizeof(AHCIQState
));
155 s
->parent
= qtest_pc_vboot(cli
, ap
);
156 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
158 /* Verify that we have an AHCI device present. */
159 s
->dev
= get_ahci_device(&s
->fingerprint
);
165 * Start a Q35 machine and bookmark a handle to the AHCI device.
167 static AHCIQState
*ahci_boot(const char *cli
, ...)
174 s
= ahci_vboot(cli
, ap
);
177 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
180 "-device ide-hd,drive=drive0 "
181 "-global ide-hd.ver=%s";
182 s
= ahci_boot(cli
, tmp_path
, "testdisk", "version");
189 * Clean up the PCI device, then terminate the QEMU instance.
191 static void ahci_shutdown(AHCIQState
*ahci
)
193 QOSState
*qs
= ahci
->parent
;
196 ahci_clean_mem(ahci
);
197 free_ahci_device(ahci
->dev
);
203 * Boot and fully enable the HBA device.
204 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
206 static AHCIQState
*ahci_boot_and_enable(const char *cli
, ...)
215 ahci
= ahci_vboot(cli
, ap
);
218 ahci
= ahci_boot(NULL
);
221 ahci_pci_enable(ahci
);
222 ahci_hba_enable(ahci
);
223 /* Initialize test device */
224 port
= ahci_port_select(ahci
);
225 ahci_port_clear(ahci
, port
);
226 ahci_io(ahci
, port
, CMD_IDENTIFY
, &buff
, sizeof(buff
), 0);
231 /*** Specification Adherence Tests ***/
234 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
236 static void ahci_test_pci_spec(AHCIQState
*ahci
)
242 /* Most of these bits should start cleared until we turn them on. */
243 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
244 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
245 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
246 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
247 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
248 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
249 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
250 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
251 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
252 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
253 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
255 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
256 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
257 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
258 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
259 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
260 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
261 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
262 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
263 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
264 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
265 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
267 /* RID occupies the low byte, CCs occupy the high three. */
268 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
270 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
271 * Though in practice this is likely seldom true. */
272 ASSERT_BIT_CLEAR(datal
, 0xFF);
275 /* BCC *must* equal 0x01. */
276 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
277 if (PCI_SCC(datal
) == 0x01) {
279 ASSERT_BIT_SET(0x80000000, datal
);
280 ASSERT_BIT_CLEAR(0x60000000, datal
);
281 } else if (PCI_SCC(datal
) == 0x04) {
283 g_assert_cmphex(PCI_PI(datal
), ==, 0);
284 } else if (PCI_SCC(datal
) == 0x06) {
286 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
288 g_assert_not_reached();
291 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
292 g_assert_cmphex(datab
, ==, 0);
294 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
295 g_assert_cmphex(datab
, ==, 0);
297 /* Only the bottom 7 bits must be off. */
298 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
299 ASSERT_BIT_CLEAR(datab
, 0x7F);
301 /* BIST is optional, but the low 7 bits must always start off regardless. */
302 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
303 ASSERT_BIT_CLEAR(datab
, 0x7F);
305 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
306 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
307 g_assert_cmphex(datal
, ==, 0);
309 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
310 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
311 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
312 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
313 ASSERT_BIT_CLEAR(datal
, 0xFF);
315 /* Capability list MUST be present, */
316 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
317 /* But these bits are reserved. */
318 ASSERT_BIT_CLEAR(datal
, ~0xFF);
319 g_assert_cmphex(datal
, !=, 0);
321 /* Check specification adherence for capability extenstions. */
322 data
= qpci_config_readw(ahci
->dev
, datal
);
324 switch (ahci
->fingerprint
) {
325 case AHCI_INTEL_ICH9
:
326 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
327 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
330 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
331 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
334 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
337 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
338 g_assert_cmphex(datal
, ==, 0);
340 /* IPIN might vary, but ILINE must be off. */
341 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
342 g_assert_cmphex(datab
, ==, 0);
346 * Test PCI capabilities for AHCI specification adherence.
348 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
351 uint8_t cid
= header
& 0xFF;
352 uint8_t next
= header
>> 8;
354 g_test_message("CID: %02x; next: %02x", cid
, next
);
358 ahci_test_pmcap(ahci
, offset
);
361 ahci_test_msicap(ahci
, offset
);
363 case PCI_CAP_ID_SATA
:
364 ahci_test_satacap(ahci
, offset
);
368 g_test_message("Unknown CAP 0x%02x", cid
);
372 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
377 * Test SATA PCI capabilitity for AHCI specification adherence.
379 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
384 g_test_message("Verifying SATACAP");
386 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
387 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
388 g_assert_cmphex(dataw
, ==, 0x10);
390 /* Grab the SATACR1 register. */
391 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
393 switch (datal
& 0x0F) {
394 case 0x04: /* BAR0 */
395 case 0x05: /* BAR1 */
399 case 0x09: /* BAR5 */
400 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
403 /* Invalid BARLOC for the Index Data Pair. */
404 g_assert_not_reached();
408 g_assert_cmphex((datal
>> 24), ==, 0x00);
412 * Test MSI PCI capability for AHCI specification adherence.
414 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
419 g_test_message("Verifying MSICAP");
421 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
422 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
423 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
424 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
426 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
427 g_assert_cmphex(datal
, ==, 0);
429 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
430 g_test_message("MSICAP is 64bit");
431 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
432 g_assert_cmphex(datal
, ==, 0);
433 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
434 g_assert_cmphex(dataw
, ==, 0);
436 g_test_message("MSICAP is 32bit");
437 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
438 g_assert_cmphex(dataw
, ==, 0);
443 * Test Power Management PCI capability for AHCI specification adherence.
445 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
449 g_test_message("Verifying PMCAP");
451 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
452 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
453 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
454 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
455 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
457 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
458 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
459 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
460 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
461 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
464 static void ahci_test_hba_spec(AHCIQState
*ahci
)
472 g_assert(ahci
!= NULL
);
475 * Note that the AHCI spec does expect the BIOS to set up a few things:
476 * CAP.SSS - Support for staggered spin-up (t/f)
477 * CAP.SMPS - Support for mechanical presence switches (t/f)
478 * PI - Ports Implemented (1-32)
479 * PxCMD.HPCP - Hot Plug Capable Port
480 * PxCMD.MPSP - Mechanical Presence Switch Present
481 * PxCMD.CPD - Cold Presence Detection support
483 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
484 * Foreach Port Implemented:
485 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
486 * -PxCLB/U and PxFB/U are set to valid regions in memory
487 * -PxSUD is set to 1.
488 * -PxSSTS.DET is polled for presence; if detected, we continue:
489 * -PxSERR is cleared with 1's.
490 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
491 * the device is ready.
494 /* 1 CAP - Capabilities Register */
495 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
496 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
498 /* 2 GHC - Global Host Control */
499 reg
= ahci_rreg(ahci
, AHCI_GHC
);
500 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
501 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
502 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
503 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
504 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
505 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
507 g_test_message("Supports AHCI/Legacy mix.");
508 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
511 /* 3 IS - Interrupt Status */
512 reg
= ahci_rreg(ahci
, AHCI_IS
);
513 g_assert_cmphex(reg
, ==, 0);
515 /* 4 PI - Ports Implemented */
516 ports
= ahci_rreg(ahci
, AHCI_PI
);
517 /* Ports Implemented must be non-zero. */
518 g_assert_cmphex(ports
, !=, 0);
519 /* Ports Implemented must be <= Number of Ports. */
520 nports_impl
= ctpopl(ports
);
521 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
523 /* Ports must be within the proper range. Given a mapping of SIZE,
524 * 256 bytes are used for global HBA control, and the rest is used
525 * for ports data, at 0x80 bytes each. */
526 g_assert_cmphex(ahci
->barsize
, >, 0);
527 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
528 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
529 g_assert_cmphex((reg
>> maxports
), ==, 0);
532 reg
= ahci_rreg(ahci
, AHCI_VS
);
534 case AHCI_VERSION_0_95
:
535 case AHCI_VERSION_1_0
:
536 case AHCI_VERSION_1_1
:
537 case AHCI_VERSION_1_2
:
538 case AHCI_VERSION_1_3
:
541 g_assert_not_reached();
544 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
545 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
546 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
547 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
548 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
549 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
550 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
552 g_assert_cmphex(reg
, ==, 0);
556 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
557 /* Must be zeroes initially regardless of CAP.CCCS */
558 g_assert_cmphex(reg
, ==, 0);
561 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
562 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
563 g_assert_cmphex(reg
, ==, 0);
567 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
568 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
569 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
570 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
571 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
572 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
574 g_assert_cmphex(reg
, ==, 0);
577 /* 10 CAP2 -- Capabilities Extended */
578 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
579 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
581 /* 11 BOHC -- Bios/OS Handoff Control */
582 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
583 g_assert_cmphex(reg
, ==, 0);
585 /* 12 -- 23: Reserved */
586 g_test_message("Verifying HBA reserved area is empty.");
587 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
588 reg
= ahci_rreg(ahci
, i
);
589 g_assert_cmphex(reg
, ==, 0);
592 /* 24 -- 39: NVMHCI */
593 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
594 g_test_message("Verifying HBA/NVMHCI area is empty.");
595 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
596 reg
= ahci_rreg(ahci
, i
);
597 g_assert_cmphex(reg
, ==, 0);
601 /* 40 -- 63: Vendor */
602 g_test_message("Verifying HBA/Vendor area is empty.");
603 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
604 reg
= ahci_rreg(ahci
, i
);
605 g_assert_cmphex(reg
, ==, 0);
608 /* 64 -- XX: Port Space */
609 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
610 if (BITSET(ports
, 0x1)) {
611 g_test_message("Testing port %u for spec", i
);
612 ahci_test_port_spec(ahci
, i
);
615 uint16_t low
= AHCI_PORTS
+ (32 * i
);
616 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
617 g_test_message("Asserting unimplemented port %u "
618 "(reg [%u-%u]) is empty.",
620 for (j
= low
; j
< high
; ++j
) {
621 reg
= ahci_rreg(ahci
, j
);
622 g_assert_cmphex(reg
, ==, 0);
629 * Test the memory space for one port for specification adherence.
631 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
637 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
638 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
641 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
642 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
643 g_assert_cmphex(reg
, ==, 0);
647 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
648 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
651 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
652 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
653 g_assert_cmphex(reg
, ==, 0);
657 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
658 g_assert_cmphex(reg
, ==, 0);
661 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
662 g_assert_cmphex(reg
, ==, 0);
665 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
666 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
667 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
668 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
669 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
670 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
671 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
672 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
673 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
674 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
675 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
676 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
677 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
678 /* If CPDetect support does not exist, CPState must be off. */
679 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
680 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
682 /* If MPSPresence is not set, MPSState must be off. */
683 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
684 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
686 /* If we do not support MPS, MPSS and MPSP must be off. */
687 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
688 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
689 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
691 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
692 if (BITANY(reg
, AHCI_PX_CMD_CPD
| AHCI_PX_CMD_MPSP
)) {
693 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
695 /* HPCP and ESP cannot both be active. */
696 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
697 /* If CAP.FBSS is not set, FBSCP must not be set. */
698 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
699 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
703 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
704 g_assert_cmphex(reg
, ==, 0);
707 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
708 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
709 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
710 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
711 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
712 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
713 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
714 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
715 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
716 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
719 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
720 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
721 * D2H register FIS and update the signature asynchronously,
722 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
724 /* (10) SSTS / SCR0: SStatus */
725 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
726 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
727 /* Even though the register should be 0 at boot, it is asynchronous and
728 * prone to change, so we cannot test any well known value. */
730 /* (11) SCTL / SCR2: SControl */
731 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
732 g_assert_cmphex(reg
, ==, 0);
734 /* (12) SERR / SCR1: SError */
735 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
736 g_assert_cmphex(reg
, ==, 0);
738 /* (13) SACT / SCR3: SActive */
739 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
740 g_assert_cmphex(reg
, ==, 0);
743 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
744 g_assert_cmphex(reg
, ==, 0);
747 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
748 g_assert_cmphex(reg
, ==, 0);
751 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
752 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
753 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
754 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
755 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
756 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
757 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
758 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
759 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
760 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
763 /* [17 -- 27] RESERVED */
764 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
765 reg
= ahci_px_rreg(ahci
, port
, i
);
766 g_assert_cmphex(reg
, ==, 0);
769 /* [28 -- 31] Vendor-Specific */
770 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
771 reg
= ahci_px_rreg(ahci
, port
, i
);
773 g_test_message("INFO: Vendor register %u non-empty", i
);
779 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
780 * device we see, then read and check the response.
782 static void ahci_test_identify(AHCIQState
*ahci
)
788 const size_t buffsize
= 512;
790 g_assert(ahci
!= NULL
);
793 * This serves as a bit of a tutorial on AHCI device programming:
795 * (1) Create a data buffer for the IDENTIFY response to be sent to
796 * (2) Create a Command Table buffer, where we will store the
797 * command and PRDT (Physical Region Descriptor Table)
798 * (3) Construct an FIS host-to-device command structure, and write it to
799 * the top of the Command Table buffer.
800 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
801 * a location in memory where data may be stored/retrieved.
802 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
803 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
804 * header that points to a Command Table buffer. Pick an unused slot
805 * and update it to point to the Command Table we have built.
806 * (7) Now: Command #n points to our Command Table, and our Command Table
807 * contains the FIS (that describes our command) and the PRDTL, which
808 * describes our buffer.
809 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
810 * #n is ready for processing.
813 /* Pick the first implemented and running port */
814 px
= ahci_port_select(ahci
);
815 g_test_message("Selected port %u for test", px
);
817 /* Clear out the FIS Receive area and any pending interrupts. */
818 ahci_port_clear(ahci
, px
);
820 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
821 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
, 0);
823 /* Check serial number/version in the buffer */
824 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
825 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
826 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
827 * as a consequence, only needs to unchunk the data on LE machines. */
828 string_bswap16(&buff
[10], 20);
829 rc
= memcmp(&buff
[10], "testdisk ", 20);
830 g_assert_cmphex(rc
, ==, 0);
832 string_bswap16(&buff
[23], 8);
833 rc
= memcmp(&buff
[23], "version ", 8);
834 g_assert_cmphex(rc
, ==, 0);
836 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
837 g_assert_cmphex(sect_size
, ==, AHCI_SECTOR_SIZE
);
840 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
841 uint64_t sector
, uint8_t read_cmd
,
846 unsigned char *tx
= g_malloc(bufsize
);
847 unsigned char *rx
= g_malloc0(bufsize
);
849 g_assert(ahci
!= NULL
);
851 /* Pick the first running port and clear it. */
852 port
= ahci_port_select(ahci
);
853 ahci_port_clear(ahci
, port
);
855 /*** Create pattern and transfer to guest ***/
856 /* Data buffer in the guest */
857 ptr
= ahci_alloc(ahci
, bufsize
);
860 /* Write some indicative pattern to our buffer. */
861 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
862 bufwrite(ptr
, tx
, bufsize
);
864 /* Write this buffer to disk, then read it back to the DMA buffer. */
865 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
, sector
);
866 qmemset(ptr
, 0x00, bufsize
);
867 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
, sector
);
869 /*** Read back the Data ***/
870 bufread(ptr
, rx
, bufsize
);
871 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
873 ahci_free(ahci
, ptr
);
878 static uint8_t ahci_test_nondata(AHCIQState
*ahci
, uint8_t ide_cmd
)
884 port
= ahci_port_select(ahci
);
885 ahci_port_clear(ahci
, port
);
888 cmd
= ahci_command_create(ide_cmd
);
889 ahci_command_commit(ahci
, cmd
, port
);
890 ahci_command_issue(ahci
, cmd
);
891 ahci_command_verify(ahci
, cmd
);
892 ahci_command_free(cmd
);
897 static void ahci_test_flush(AHCIQState
*ahci
)
899 ahci_test_nondata(ahci
, CMD_FLUSH_CACHE
);
902 static void ahci_test_max(AHCIQState
*ahci
)
904 RegD2HFIS
*d2h
= g_malloc0(0x20);
908 uint64_t config_sect
= TEST_IMAGE_SECTORS
- 1;
910 if (config_sect
> 0xFFFFFF) {
911 cmd
= CMD_READ_MAX_EXT
;
916 port
= ahci_test_nondata(ahci
, cmd
);
917 memread(ahci
->port
[port
].fb
+ 0x40, d2h
, 0x20);
918 nsect
= (uint64_t)d2h
->lba_hi
[2] << 40 |
919 (uint64_t)d2h
->lba_hi
[1] << 32 |
920 (uint64_t)d2h
->lba_hi
[0] << 24 |
921 (uint64_t)d2h
->lba_lo
[2] << 16 |
922 (uint64_t)d2h
->lba_lo
[1] << 8 |
923 (uint64_t)d2h
->lba_lo
[0];
925 g_assert_cmphex(nsect
, ==, config_sect
);
930 /******************************************************************************/
931 /* Test Interfaces */
932 /******************************************************************************/
935 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
937 static void test_sanity(void)
940 ahci
= ahci_boot(NULL
);
945 * Ensure that the PCI configuration space for the AHCI device is in-line with
946 * the AHCI 1.3 specification for initial values.
948 static void test_pci_spec(void)
951 ahci
= ahci_boot(NULL
);
952 ahci_test_pci_spec(ahci
);
957 * Engage the PCI AHCI device and sanity check the response.
958 * Perform additional PCI config space bringup for the HBA.
960 static void test_pci_enable(void)
963 ahci
= ahci_boot(NULL
);
964 ahci_pci_enable(ahci
);
969 * Investigate the memory mapped regions of the HBA,
970 * and test them for AHCI specification adherence.
972 static void test_hba_spec(void)
976 ahci
= ahci_boot(NULL
);
977 ahci_pci_enable(ahci
);
978 ahci_test_hba_spec(ahci
);
983 * Engage the HBA functionality of the AHCI PCI device,
984 * and bring it into a functional idle state.
986 static void test_hba_enable(void)
990 ahci
= ahci_boot(NULL
);
991 ahci_pci_enable(ahci
);
992 ahci_hba_enable(ahci
);
997 * Bring up the device and issue an IDENTIFY command.
998 * Inspect the state of the HBA device and the data returned.
1000 static void test_identify(void)
1004 ahci
= ahci_boot_and_enable(NULL
);
1005 ahci_test_identify(ahci
);
1006 ahci_shutdown(ahci
);
1010 * Fragmented DMA test: Perform a standard 4K DMA read/write
1011 * test, but make sure the physical regions are fragmented to
1012 * be very small, each just 32 bytes, to see how AHCI performs
1013 * with chunks defined to be much less than a sector.
1015 static void test_dma_fragmented(void)
1020 size_t bufsize
= 4096;
1021 unsigned char *tx
= g_malloc(bufsize
);
1022 unsigned char *rx
= g_malloc0(bufsize
);
1025 ahci
= ahci_boot_and_enable(NULL
);
1026 px
= ahci_port_select(ahci
);
1027 ahci_port_clear(ahci
, px
);
1029 /* create pattern */
1030 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1032 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1033 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
1035 bufwrite(ptr
, tx
, bufsize
);
1037 cmd
= ahci_command_create(CMD_WRITE_DMA
);
1038 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1039 ahci_command_commit(ahci
, cmd
, px
);
1040 ahci_command_issue(ahci
, cmd
);
1041 ahci_command_verify(ahci
, cmd
);
1044 cmd
= ahci_command_create(CMD_READ_DMA
);
1045 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1046 ahci_command_commit(ahci
, cmd
, px
);
1047 ahci_command_issue(ahci
, cmd
);
1048 ahci_command_verify(ahci
, cmd
);
1051 /* Read back the guest's receive buffer into local memory */
1052 bufread(ptr
, rx
, bufsize
);
1053 guest_free(ahci
->parent
->alloc
, ptr
);
1055 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1057 ahci_shutdown(ahci
);
1063 static void test_flush(void)
1067 ahci
= ahci_boot_and_enable(NULL
);
1068 ahci_test_flush(ahci
);
1069 ahci_shutdown(ahci
);
1072 static void test_flush_retry(void)
1079 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1080 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1081 "format=qcow2,cache=writeback,"
1082 "rerror=stop,werror=stop "
1084 "-device ide-hd,drive=drive0 ",
1088 /* Issue Flush Command and wait for error */
1089 port
= ahci_port_select(ahci
);
1090 ahci_port_clear(ahci
, port
);
1091 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1092 ahci_command_commit(ahci
, cmd
, port
);
1093 ahci_command_issue_async(ahci
, cmd
);
1094 qmp_eventwait("STOP");
1096 /* Complete the command */
1097 s
= "{'execute':'cont' }";
1099 qmp_eventwait("RESUME");
1100 ahci_command_wait(ahci
, cmd
);
1101 ahci_command_verify(ahci
, cmd
);
1103 ahci_command_free(cmd
);
1104 ahci_shutdown(ahci
);
1108 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1110 static void test_migrate_sanity(void)
1112 AHCIQState
*src
, *dst
;
1113 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1115 src
= ahci_boot("-m 1024 -M q35 "
1116 "-hda %s ", tmp_path
);
1117 dst
= ahci_boot("-m 1024 -M q35 "
1119 "-incoming %s", tmp_path
, uri
);
1121 ahci_migrate(src
, dst
, uri
);
1129 * Simple migration test: Write a pattern, migrate, then read.
1131 static void ahci_migrate_simple(uint8_t cmd_read
, uint8_t cmd_write
)
1133 AHCIQState
*src
, *dst
;
1135 size_t bufsize
= 4096;
1136 unsigned char *tx
= g_malloc(bufsize
);
1137 unsigned char *rx
= g_malloc0(bufsize
);
1138 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1140 src
= ahci_boot_and_enable("-m 1024 -M q35 "
1141 "-hda %s ", tmp_path
);
1142 dst
= ahci_boot("-m 1024 -M q35 "
1144 "-incoming %s", tmp_path
, uri
);
1146 set_context(src
->parent
);
1149 px
= ahci_port_select(src
);
1150 ahci_port_clear(src
, px
);
1152 /* create pattern */
1153 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1155 /* Write, migrate, then read. */
1156 ahci_io(src
, px
, cmd_write
, tx
, bufsize
, 0);
1157 ahci_migrate(src
, dst
, uri
);
1158 ahci_io(dst
, px
, cmd_read
, rx
, bufsize
, 0);
1160 /* Verify pattern */
1161 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1170 static void test_migrate_dma(void)
1172 ahci_migrate_simple(CMD_READ_DMA
, CMD_WRITE_DMA
);
1175 static void test_migrate_ncq(void)
1177 ahci_migrate_simple(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1181 * Halted IO Error Test
1183 * Simulate an error on first write, Try to write a pattern,
1184 * Confirm the VM has stopped, resume the VM, verify command
1185 * has completed, then read back the data and verify.
1187 static void ahci_halted_io_test(uint8_t cmd_read
, uint8_t cmd_write
)
1191 size_t bufsize
= 4096;
1192 unsigned char *tx
= g_malloc(bufsize
);
1193 unsigned char *rx
= g_malloc0(bufsize
);
1197 prepare_blkdebug_script(debug_path
, "write_aio");
1199 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1200 "format=qcow2,cache=writeback,"
1201 "rerror=stop,werror=stop "
1203 "-device ide-hd,drive=drive0 ",
1207 /* Initialize and prepare */
1208 port
= ahci_port_select(ahci
);
1209 ahci_port_clear(ahci
, port
);
1211 /* create DMA source buffer and write pattern */
1212 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1213 ptr
= ahci_alloc(ahci
, bufsize
);
1215 memwrite(ptr
, tx
, bufsize
);
1217 /* Attempt to write (and fail) */
1218 cmd
= ahci_guest_io_halt(ahci
, port
, cmd_write
,
1221 /* Attempt to resume the command */
1222 ahci_guest_io_resume(ahci
, cmd
);
1223 ahci_free(ahci
, ptr
);
1225 /* Read back and verify */
1226 ahci_io(ahci
, port
, cmd_read
, rx
, bufsize
, 0);
1227 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1229 /* Cleanup and go home */
1230 ahci_shutdown(ahci
);
1235 static void test_halted_dma(void)
1237 ahci_halted_io_test(CMD_READ_DMA
, CMD_WRITE_DMA
);
1240 static void test_halted_ncq(void)
1242 ahci_halted_io_test(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1246 * IO Error Migration Test
1248 * Simulate an error on first write, Try to write a pattern,
1249 * Confirm the VM has stopped, migrate, resume the VM,
1250 * verify command has completed, then read back the data and verify.
1252 static void ahci_migrate_halted_io(uint8_t cmd_read
, uint8_t cmd_write
)
1254 AHCIQState
*src
, *dst
;
1256 size_t bufsize
= 4096;
1257 unsigned char *tx
= g_malloc(bufsize
);
1258 unsigned char *rx
= g_malloc0(bufsize
);
1261 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1263 prepare_blkdebug_script(debug_path
, "write_aio");
1265 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1266 "format=qcow2,cache=writeback,"
1267 "rerror=stop,werror=stop "
1269 "-device ide-hd,drive=drive0 ",
1273 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1274 "format=qcow2,cache=writeback,"
1275 "rerror=stop,werror=stop "
1277 "-device ide-hd,drive=drive0 "
1281 set_context(src
->parent
);
1283 /* Initialize and prepare */
1284 port
= ahci_port_select(src
);
1285 ahci_port_clear(src
, port
);
1286 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1288 /* create DMA source buffer and write pattern */
1289 ptr
= ahci_alloc(src
, bufsize
);
1291 memwrite(ptr
, tx
, bufsize
);
1293 /* Write, trigger the VM to stop, migrate, then resume. */
1294 cmd
= ahci_guest_io_halt(src
, port
, cmd_write
,
1296 ahci_migrate(src
, dst
, uri
);
1297 ahci_guest_io_resume(dst
, cmd
);
1298 ahci_free(dst
, ptr
);
1301 ahci_io(dst
, port
, cmd_read
, rx
, bufsize
, 0);
1303 /* Verify TX and RX are identical */
1304 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1306 /* Cleanup and go home. */
1314 static void test_migrate_halted_dma(void)
1316 ahci_migrate_halted_io(CMD_READ_DMA
, CMD_WRITE_DMA
);
1319 static void test_migrate_halted_ncq(void)
1321 ahci_migrate_halted_io(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1325 * Migration test: Try to flush, migrate, then resume.
1327 static void test_flush_migrate(void)
1329 AHCIQState
*src
, *dst
;
1333 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1335 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1337 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1338 "cache=writeback,rerror=stop,werror=stop "
1340 "-device ide-hd,drive=drive0 ",
1341 debug_path
, tmp_path
);
1342 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1343 "cache=writeback,rerror=stop,werror=stop "
1345 "-device ide-hd,drive=drive0 "
1346 "-incoming %s", tmp_path
, uri
);
1348 set_context(src
->parent
);
1350 /* Issue Flush Command */
1351 px
= ahci_port_select(src
);
1352 ahci_port_clear(src
, px
);
1353 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1354 ahci_command_commit(src
, cmd
, px
);
1355 ahci_command_issue_async(src
, cmd
);
1356 qmp_eventwait("STOP");
1359 ahci_migrate(src
, dst
, uri
);
1361 /* Complete the command */
1362 s
= "{'execute':'cont' }";
1364 qmp_eventwait("RESUME");
1365 ahci_command_wait(dst
, cmd
);
1366 ahci_command_verify(dst
, cmd
);
1368 ahci_command_free(cmd
);
1374 static void test_max(void)
1378 ahci
= ahci_boot_and_enable(NULL
);
1379 ahci_test_max(ahci
);
1380 ahci_shutdown(ahci
);
1383 static void test_reset(void)
1388 ahci
= ahci_boot(NULL
);
1389 ahci_test_pci_spec(ahci
);
1390 ahci_pci_enable(ahci
);
1392 for (i
= 0; i
< 2; i
++) {
1393 ahci_test_hba_spec(ahci
);
1394 ahci_hba_enable(ahci
);
1395 ahci_test_identify(ahci
);
1396 ahci_test_io_rw_simple(ahci
, 4096, 0,
1399 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_HR
);
1400 ahci_clean_mem(ahci
);
1403 ahci_shutdown(ahci
);
1406 static void test_ncq_simple(void)
1410 ahci
= ahci_boot_and_enable(NULL
);
1411 ahci_test_io_rw_simple(ahci
, 4096, 0,
1413 WRITE_FPDMA_QUEUED
);
1414 ahci_shutdown(ahci
);
1417 /******************************************************************************/
1418 /* AHCI I/O Test Matrix Definitions */
1422 LEN_SIMPLE
= LEN_BEGIN
,
1429 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
1433 ADDR_MODE_BEGIN
= 0,
1434 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
1439 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
1443 MODE_PIO
= MODE_BEGIN
,
1448 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
1459 OFFSET_ZERO
= OFFSET_BEGIN
,
1465 static const char *offset_str
[NUM_OFFSETS
] = { "zero", "low", "high" };
1467 typedef struct AHCIIOTestOptions
{
1468 enum BuffLen length
;
1469 enum AddrMode address_type
;
1470 enum IOMode io_type
;
1471 enum OffsetType offset
;
1472 } AHCIIOTestOptions
;
1474 static uint64_t offset_sector(enum OffsetType ofst
,
1475 enum AddrMode addr_type
,
1487 ceil
= (addr_type
== ADDR_MODE_LBA28
) ? 0xfffffff : 0xffffffffffff;
1488 ceil
= MIN(ceil
, TEST_IMAGE_SECTORS
- 1);
1489 nsectors
= buffsize
/ AHCI_SECTOR_SIZE
;
1490 return ceil
- nsectors
+ 1;
1492 g_assert_not_reached();
1497 * Table of possible I/O ATA commands given a set of enumerations.
1499 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
1501 [ADDR_MODE_LBA28
] = {
1502 [IO_READ
] = CMD_READ_PIO
,
1503 [IO_WRITE
] = CMD_WRITE_PIO
},
1504 [ADDR_MODE_LBA48
] = {
1505 [IO_READ
] = CMD_READ_PIO_EXT
,
1506 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
1509 [ADDR_MODE_LBA28
] = {
1510 [IO_READ
] = CMD_READ_DMA
,
1511 [IO_WRITE
] = CMD_WRITE_DMA
},
1512 [ADDR_MODE_LBA48
] = {
1513 [IO_READ
] = CMD_READ_DMA_EXT
,
1514 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
1519 * Test a Read/Write pattern using various commands, addressing modes,
1520 * transfer modes, and buffer sizes.
1522 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
1523 unsigned bufsize
, uint64_t sector
)
1527 ahci
= ahci_boot_and_enable(NULL
);
1528 ahci_test_io_rw_simple(ahci
, bufsize
, sector
,
1529 io_cmds
[dma
][lba48
][IO_READ
],
1530 io_cmds
[dma
][lba48
][IO_WRITE
]);
1531 ahci_shutdown(ahci
);
1535 * Demultiplex the test data and invoke the actual test routine.
1537 static void test_io_interface(gconstpointer opaque
)
1539 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1543 switch (opts
->length
) {
1551 bufsize
= 4096 * 64;
1557 g_assert_not_reached();
1560 sector
= offset_sector(opts
->offset
, opts
->address_type
, bufsize
);
1561 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
, sector
);
1566 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1567 enum BuffLen len
, enum OffsetType offset
)
1570 AHCIIOTestOptions
*opts
= g_malloc(sizeof(AHCIIOTestOptions
));
1573 opts
->address_type
= addr
;
1574 opts
->io_type
= type
;
1575 opts
->offset
= offset
;
1577 name
= g_strdup_printf("ahci/io/%s/%s/%s/%s",
1579 addr_mode_str
[addr
],
1581 offset_str
[offset
]);
1583 qtest_add_data_func(name
, opts
, test_io_interface
);
1587 /******************************************************************************/
1589 int main(int argc
, char **argv
)
1597 static struct option long_options
[] = {
1598 {"pedantic", no_argument
, 0, 'p' },
1602 /* Should be first to utilize g_test functionality, So we can see errors. */
1603 g_test_init(&argc
, &argv
, NULL
);
1606 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1617 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1618 g_assert_not_reached();
1622 /* Check architecture */
1623 arch
= qtest_get_arch();
1624 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1625 g_test_message("Skipping test for non-x86");
1629 /* Create a temporary qcow2 image */
1630 close(mkstemp(tmp_path
));
1631 mkqcow2(tmp_path
, TEST_IMAGE_SIZE_MB
);
1633 /* Create temporary blkdebug instructions */
1634 fd
= mkstemp(debug_path
);
1638 /* Reserve a hollow file to use as a socket for migration tests */
1639 fd
= mkstemp(mig_socket
);
1644 qtest_add_func("/ahci/sanity", test_sanity
);
1645 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1646 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1647 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1648 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1649 qtest_add_func("/ahci/identify", test_identify
);
1651 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1652 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1653 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1654 for (m
= OFFSET_BEGIN
; m
< NUM_OFFSETS
; m
++) {
1655 create_ahci_io_test(i
, j
, k
, m
);
1661 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);
1663 qtest_add_func("/ahci/flush/simple", test_flush
);
1664 qtest_add_func("/ahci/flush/retry", test_flush_retry
);
1665 qtest_add_func("/ahci/flush/migrate", test_flush_migrate
);
1667 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity
);
1668 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma
);
1669 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma
);
1670 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma
);
1672 qtest_add_func("/ahci/max", test_max
);
1673 qtest_add_func("/ahci/reset", test_reset
);
1675 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple
);
1676 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq
);
1677 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq
);
1678 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq
);