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1 /*
2 * AHCI test cases
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include <stdint.h>
26 #include <string.h>
27 #include <stdio.h>
28 #include <getopt.h>
29 #include <glib.h>
30
31 #include "libqtest.h"
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
35
36 #include "qemu-common.h"
37 #include "qemu/host-utils.h"
38
39 #include "hw/pci/pci_ids.h"
40 #include "hw/pci/pci_regs.h"
41
42 /* Test-specific defines -- in MiB */
43 #define TEST_IMAGE_SIZE_MB (200 * 1024)
44 #define TEST_IMAGE_SECTORS ((TEST_IMAGE_SIZE_MB / AHCI_SECTOR_SIZE) \
45 * 1024 * 1024)
46
47 /*** Globals ***/
48 static char tmp_path[] = "/tmp/qtest.XXXXXX";
49 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
50 static bool ahci_pedantic;
51
52 /*** Function Declarations ***/
53 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
54 static void ahci_test_pci_spec(AHCIQState *ahci);
55 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
56 uint8_t offset);
57 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
58 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
59 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
60
61 /*** Utilities ***/
62
63 static void string_bswap16(uint16_t *s, size_t bytes)
64 {
65 g_assert_cmphex((bytes & 1), ==, 0);
66 bytes /= 2;
67
68 while (bytes--) {
69 *s = bswap16(*s);
70 s++;
71 }
72 }
73
74 static void generate_pattern(void *buffer, size_t len, size_t cycle_len)
75 {
76 int i, j;
77 unsigned char *tx = (unsigned char *)buffer;
78 unsigned char p;
79 size_t *sx;
80
81 /* Write an indicative pattern that varies and is unique per-cycle */
82 p = rand() % 256;
83 for (i = j = 0; i < len; i++, j++) {
84 tx[i] = p;
85 if (j % cycle_len == 0) {
86 p = rand() % 256;
87 }
88 }
89
90 /* force uniqueness by writing an id per-cycle */
91 for (i = 0; i < len / cycle_len; i++) {
92 j = i * cycle_len;
93 if (j + sizeof(*sx) <= len) {
94 sx = (size_t *)&tx[j];
95 *sx = i;
96 }
97 }
98 }
99
100 /**
101 * Verify that the transfer did not corrupt our state at all.
102 */
103 static void verify_state(AHCIQState *ahci)
104 {
105 int i, j;
106 uint32_t ahci_fingerprint;
107 uint64_t hba_base;
108 uint64_t hba_stored;
109 AHCICommandHeader cmd;
110
111 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
112 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
113
114 /* If we haven't initialized, this is as much as can be validated. */
115 if (!ahci->hba_base) {
116 return;
117 }
118
119 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
120 hba_stored = (uint64_t)(uintptr_t)ahci->hba_base;
121 g_assert_cmphex(hba_base, ==, hba_stored);
122
123 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
124 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
125
126 for (i = 0; i < 32; i++) {
127 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
128 ahci->port[i].fb);
129 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
130 ahci->port[i].clb);
131 for (j = 0; j < 32; j++) {
132 ahci_get_command_header(ahci, i, j, &cmd);
133 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
134 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
135 }
136 }
137 }
138
139 static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
140 {
141 QOSState *tmp = to->parent;
142 QPCIDevice *dev = to->dev;
143 if (uri == NULL) {
144 uri = "tcp:127.0.0.1:1234";
145 }
146
147 /* context will be 'to' after completion. */
148 migrate(from->parent, to->parent, uri);
149
150 /* We'd like for the AHCIState objects to still point
151 * to information specific to its specific parent
152 * instance, but otherwise just inherit the new data. */
153 memcpy(to, from, sizeof(AHCIQState));
154 to->parent = tmp;
155 to->dev = dev;
156
157 tmp = from->parent;
158 dev = from->dev;
159 memset(from, 0x00, sizeof(AHCIQState));
160 from->parent = tmp;
161 from->dev = dev;
162
163 verify_state(to);
164 }
165
166 /*** Test Setup & Teardown ***/
167
168 /**
169 * Start a Q35 machine and bookmark a handle to the AHCI device.
170 */
171 static AHCIQState *ahci_vboot(const char *cli, va_list ap)
172 {
173 AHCIQState *s;
174
175 s = g_malloc0(sizeof(AHCIQState));
176 s->parent = qtest_pc_vboot(cli, ap);
177 alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
178
179 /* Verify that we have an AHCI device present. */
180 s->dev = get_ahci_device(&s->fingerprint);
181
182 return s;
183 }
184
185 /**
186 * Start a Q35 machine and bookmark a handle to the AHCI device.
187 */
188 static AHCIQState *ahci_boot(const char *cli, ...)
189 {
190 AHCIQState *s;
191 va_list ap;
192
193 if (cli) {
194 va_start(ap, cli);
195 s = ahci_vboot(cli, ap);
196 va_end(ap);
197 } else {
198 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
199 ",format=qcow2"
200 " -M q35 "
201 "-device ide-hd,drive=drive0 "
202 "-global ide-hd.ver=%s";
203 s = ahci_boot(cli, tmp_path, "testdisk", "version");
204 }
205
206 return s;
207 }
208
209 /**
210 * Clean up the PCI device, then terminate the QEMU instance.
211 */
212 static void ahci_shutdown(AHCIQState *ahci)
213 {
214 QOSState *qs = ahci->parent;
215
216 set_context(qs);
217 ahci_clean_mem(ahci);
218 free_ahci_device(ahci->dev);
219 g_free(ahci);
220 qtest_shutdown(qs);
221 }
222
223 /**
224 * Boot and fully enable the HBA device.
225 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
226 */
227 static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
228 {
229 AHCIQState *ahci;
230 va_list ap;
231 uint16_t buff[256];
232 uint8_t port;
233
234 if (cli) {
235 va_start(ap, cli);
236 ahci = ahci_vboot(cli, ap);
237 va_end(ap);
238 } else {
239 ahci = ahci_boot(NULL);
240 }
241
242 ahci_pci_enable(ahci);
243 ahci_hba_enable(ahci);
244 /* Initialize test device */
245 port = ahci_port_select(ahci);
246 ahci_port_clear(ahci, port);
247 ahci_io(ahci, port, CMD_IDENTIFY, &buff, sizeof(buff), 0);
248
249 return ahci;
250 }
251
252 /*** Specification Adherence Tests ***/
253
254 /**
255 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
256 */
257 static void ahci_test_pci_spec(AHCIQState *ahci)
258 {
259 uint8_t datab;
260 uint16_t data;
261 uint32_t datal;
262
263 /* Most of these bits should start cleared until we turn them on. */
264 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
265 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
266 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
267 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
268 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
269 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
270 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
271 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
272 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
273 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
274 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
275
276 data = qpci_config_readw(ahci->dev, PCI_STATUS);
277 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
278 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
279 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
280 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
281 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
282 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
283 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
284 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
285 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
286 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
287
288 /* RID occupies the low byte, CCs occupy the high three. */
289 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
290 if (ahci_pedantic) {
291 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
292 * Though in practice this is likely seldom true. */
293 ASSERT_BIT_CLEAR(datal, 0xFF);
294 }
295
296 /* BCC *must* equal 0x01. */
297 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
298 if (PCI_SCC(datal) == 0x01) {
299 /* IDE */
300 ASSERT_BIT_SET(0x80000000, datal);
301 ASSERT_BIT_CLEAR(0x60000000, datal);
302 } else if (PCI_SCC(datal) == 0x04) {
303 /* RAID */
304 g_assert_cmphex(PCI_PI(datal), ==, 0);
305 } else if (PCI_SCC(datal) == 0x06) {
306 /* AHCI */
307 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
308 } else {
309 g_assert_not_reached();
310 }
311
312 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
313 g_assert_cmphex(datab, ==, 0);
314
315 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
316 g_assert_cmphex(datab, ==, 0);
317
318 /* Only the bottom 7 bits must be off. */
319 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
320 ASSERT_BIT_CLEAR(datab, 0x7F);
321
322 /* BIST is optional, but the low 7 bits must always start off regardless. */
323 datab = qpci_config_readb(ahci->dev, PCI_BIST);
324 ASSERT_BIT_CLEAR(datab, 0x7F);
325
326 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
327 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
328 g_assert_cmphex(datal, ==, 0);
329
330 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
331 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
332 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
333 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
334 ASSERT_BIT_CLEAR(datal, 0xFF);
335
336 /* Capability list MUST be present, */
337 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
338 /* But these bits are reserved. */
339 ASSERT_BIT_CLEAR(datal, ~0xFF);
340 g_assert_cmphex(datal, !=, 0);
341
342 /* Check specification adherence for capability extenstions. */
343 data = qpci_config_readw(ahci->dev, datal);
344
345 switch (ahci->fingerprint) {
346 case AHCI_INTEL_ICH9:
347 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
348 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
349 break;
350 default:
351 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
352 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
353 }
354
355 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
356
357 /* Reserved. */
358 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
359 g_assert_cmphex(datal, ==, 0);
360
361 /* IPIN might vary, but ILINE must be off. */
362 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
363 g_assert_cmphex(datab, ==, 0);
364 }
365
366 /**
367 * Test PCI capabilities for AHCI specification adherence.
368 */
369 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
370 uint8_t offset)
371 {
372 uint8_t cid = header & 0xFF;
373 uint8_t next = header >> 8;
374
375 g_test_message("CID: %02x; next: %02x", cid, next);
376
377 switch (cid) {
378 case PCI_CAP_ID_PM:
379 ahci_test_pmcap(ahci, offset);
380 break;
381 case PCI_CAP_ID_MSI:
382 ahci_test_msicap(ahci, offset);
383 break;
384 case PCI_CAP_ID_SATA:
385 ahci_test_satacap(ahci, offset);
386 break;
387
388 default:
389 g_test_message("Unknown CAP 0x%02x", cid);
390 }
391
392 if (next) {
393 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
394 }
395 }
396
397 /**
398 * Test SATA PCI capabilitity for AHCI specification adherence.
399 */
400 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
401 {
402 uint16_t dataw;
403 uint32_t datal;
404
405 g_test_message("Verifying SATACAP");
406
407 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
408 dataw = qpci_config_readw(ahci->dev, offset + 2);
409 g_assert_cmphex(dataw, ==, 0x10);
410
411 /* Grab the SATACR1 register. */
412 datal = qpci_config_readw(ahci->dev, offset + 4);
413
414 switch (datal & 0x0F) {
415 case 0x04: /* BAR0 */
416 case 0x05: /* BAR1 */
417 case 0x06:
418 case 0x07:
419 case 0x08:
420 case 0x09: /* BAR5 */
421 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
422 break;
423 default:
424 /* Invalid BARLOC for the Index Data Pair. */
425 g_assert_not_reached();
426 }
427
428 /* Reserved. */
429 g_assert_cmphex((datal >> 24), ==, 0x00);
430 }
431
432 /**
433 * Test MSI PCI capability for AHCI specification adherence.
434 */
435 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
436 {
437 uint16_t dataw;
438 uint32_t datal;
439
440 g_test_message("Verifying MSICAP");
441
442 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
443 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
444 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
445 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
446
447 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
448 g_assert_cmphex(datal, ==, 0);
449
450 if (dataw & PCI_MSI_FLAGS_64BIT) {
451 g_test_message("MSICAP is 64bit");
452 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
453 g_assert_cmphex(datal, ==, 0);
454 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
455 g_assert_cmphex(dataw, ==, 0);
456 } else {
457 g_test_message("MSICAP is 32bit");
458 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
459 g_assert_cmphex(dataw, ==, 0);
460 }
461 }
462
463 /**
464 * Test Power Management PCI capability for AHCI specification adherence.
465 */
466 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
467 {
468 uint16_t dataw;
469
470 g_test_message("Verifying PMCAP");
471
472 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
474 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
475 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
476 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
477
478 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
479 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
480 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
481 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
482 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
483 }
484
485 static void ahci_test_hba_spec(AHCIQState *ahci)
486 {
487 unsigned i;
488 uint32_t reg;
489 uint32_t ports;
490 uint8_t nports_impl;
491 uint8_t maxports;
492
493 g_assert(ahci != NULL);
494
495 /*
496 * Note that the AHCI spec does expect the BIOS to set up a few things:
497 * CAP.SSS - Support for staggered spin-up (t/f)
498 * CAP.SMPS - Support for mechanical presence switches (t/f)
499 * PI - Ports Implemented (1-32)
500 * PxCMD.HPCP - Hot Plug Capable Port
501 * PxCMD.MPSP - Mechanical Presence Switch Present
502 * PxCMD.CPD - Cold Presence Detection support
503 *
504 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
505 * Foreach Port Implemented:
506 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
507 * -PxCLB/U and PxFB/U are set to valid regions in memory
508 * -PxSUD is set to 1.
509 * -PxSSTS.DET is polled for presence; if detected, we continue:
510 * -PxSERR is cleared with 1's.
511 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
512 * the device is ready.
513 */
514
515 /* 1 CAP - Capabilities Register */
516 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
517 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
518
519 /* 2 GHC - Global Host Control */
520 reg = ahci_rreg(ahci, AHCI_GHC);
521 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
522 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
523 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
524 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
525 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
526 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
527 } else {
528 g_test_message("Supports AHCI/Legacy mix.");
529 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
530 }
531
532 /* 3 IS - Interrupt Status */
533 reg = ahci_rreg(ahci, AHCI_IS);
534 g_assert_cmphex(reg, ==, 0);
535
536 /* 4 PI - Ports Implemented */
537 ports = ahci_rreg(ahci, AHCI_PI);
538 /* Ports Implemented must be non-zero. */
539 g_assert_cmphex(ports, !=, 0);
540 /* Ports Implemented must be <= Number of Ports. */
541 nports_impl = ctpopl(ports);
542 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
543
544 /* Ports must be within the proper range. Given a mapping of SIZE,
545 * 256 bytes are used for global HBA control, and the rest is used
546 * for ports data, at 0x80 bytes each. */
547 g_assert_cmphex(ahci->barsize, >, 0);
548 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
549 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
550 g_assert_cmphex((reg >> maxports), ==, 0);
551
552 /* 5 AHCI Version */
553 reg = ahci_rreg(ahci, AHCI_VS);
554 switch (reg) {
555 case AHCI_VERSION_0_95:
556 case AHCI_VERSION_1_0:
557 case AHCI_VERSION_1_1:
558 case AHCI_VERSION_1_2:
559 case AHCI_VERSION_1_3:
560 break;
561 default:
562 g_assert_not_reached();
563 }
564
565 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
566 reg = ahci_rreg(ahci, AHCI_CCCCTL);
567 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
568 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
569 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
570 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
571 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
572 } else {
573 g_assert_cmphex(reg, ==, 0);
574 }
575
576 /* 7 CCC_PORTS */
577 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
578 /* Must be zeroes initially regardless of CAP.CCCS */
579 g_assert_cmphex(reg, ==, 0);
580
581 /* 8 EM_LOC */
582 reg = ahci_rreg(ahci, AHCI_EMLOC);
583 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
584 g_assert_cmphex(reg, ==, 0);
585 }
586
587 /* 9 EM_CTL */
588 reg = ahci_rreg(ahci, AHCI_EMCTL);
589 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
590 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
591 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
592 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
593 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
594 } else {
595 g_assert_cmphex(reg, ==, 0);
596 }
597
598 /* 10 CAP2 -- Capabilities Extended */
599 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
600 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
601
602 /* 11 BOHC -- Bios/OS Handoff Control */
603 reg = ahci_rreg(ahci, AHCI_BOHC);
604 g_assert_cmphex(reg, ==, 0);
605
606 /* 12 -- 23: Reserved */
607 g_test_message("Verifying HBA reserved area is empty.");
608 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
609 reg = ahci_rreg(ahci, i);
610 g_assert_cmphex(reg, ==, 0);
611 }
612
613 /* 24 -- 39: NVMHCI */
614 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
615 g_test_message("Verifying HBA/NVMHCI area is empty.");
616 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
617 reg = ahci_rreg(ahci, i);
618 g_assert_cmphex(reg, ==, 0);
619 }
620 }
621
622 /* 40 -- 63: Vendor */
623 g_test_message("Verifying HBA/Vendor area is empty.");
624 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
625 reg = ahci_rreg(ahci, i);
626 g_assert_cmphex(reg, ==, 0);
627 }
628
629 /* 64 -- XX: Port Space */
630 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
631 if (BITSET(ports, 0x1)) {
632 g_test_message("Testing port %u for spec", i);
633 ahci_test_port_spec(ahci, i);
634 } else {
635 uint16_t j;
636 uint16_t low = AHCI_PORTS + (32 * i);
637 uint16_t high = AHCI_PORTS + (32 * (i + 1));
638 g_test_message("Asserting unimplemented port %u "
639 "(reg [%u-%u]) is empty.",
640 i, low, high - 1);
641 for (j = low; j < high; ++j) {
642 reg = ahci_rreg(ahci, j);
643 g_assert_cmphex(reg, ==, 0);
644 }
645 }
646 }
647 }
648
649 /**
650 * Test the memory space for one port for specification adherence.
651 */
652 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
653 {
654 uint32_t reg;
655 unsigned i;
656
657 /* (0) CLB */
658 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
659 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
660
661 /* (1) CLBU */
662 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
663 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
664 g_assert_cmphex(reg, ==, 0);
665 }
666
667 /* (2) FB */
668 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
669 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
670
671 /* (3) FBU */
672 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
673 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
674 g_assert_cmphex(reg, ==, 0);
675 }
676
677 /* (4) IS */
678 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
679 g_assert_cmphex(reg, ==, 0);
680
681 /* (5) IE */
682 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
683 g_assert_cmphex(reg, ==, 0);
684
685 /* (6) CMD */
686 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
690 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
691 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
693 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
694 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
695 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */
697 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */
698 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
699 /* If CPDetect support does not exist, CPState must be off. */
700 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
702 }
703 /* If MPSPresence is not set, MPSState must be off. */
704 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
705 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
706 }
707 /* If we do not support MPS, MPSS and MPSP must be off. */
708 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
709 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
710 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
711 }
712 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
713 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
714 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
715 }
716 /* HPCP and ESP cannot both be active. */
717 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
718 /* If CAP.FBSS is not set, FBSCP must not be set. */
719 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
720 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
721 }
722
723 /* (7) RESERVED */
724 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
725 g_assert_cmphex(reg, ==, 0);
726
727 /* (8) TFD */
728 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
729 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
730 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
731 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
732 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
733 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
734 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
735 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
736 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
737 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
738
739 /* (9) SIG */
740 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
741 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
742 * D2H register FIS and update the signature asynchronously,
743 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
744
745 /* (10) SSTS / SCR0: SStatus */
746 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
747 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
748 /* Even though the register should be 0 at boot, it is asynchronous and
749 * prone to change, so we cannot test any well known value. */
750
751 /* (11) SCTL / SCR2: SControl */
752 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
753 g_assert_cmphex(reg, ==, 0);
754
755 /* (12) SERR / SCR1: SError */
756 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
757 g_assert_cmphex(reg, ==, 0);
758
759 /* (13) SACT / SCR3: SActive */
760 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
761 g_assert_cmphex(reg, ==, 0);
762
763 /* (14) CI */
764 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
765 g_assert_cmphex(reg, ==, 0);
766
767 /* (15) SNTF */
768 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
769 g_assert_cmphex(reg, ==, 0);
770
771 /* (16) FBS */
772 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
773 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
774 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
775 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
776 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
777 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
778 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
779 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
780 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
781 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
782 }
783
784 /* [17 -- 27] RESERVED */
785 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
786 reg = ahci_px_rreg(ahci, port, i);
787 g_assert_cmphex(reg, ==, 0);
788 }
789
790 /* [28 -- 31] Vendor-Specific */
791 for (i = AHCI_PX_VS; i < 32; ++i) {
792 reg = ahci_px_rreg(ahci, port, i);
793 if (reg) {
794 g_test_message("INFO: Vendor register %u non-empty", i);
795 }
796 }
797 }
798
799 /**
800 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
801 * device we see, then read and check the response.
802 */
803 static void ahci_test_identify(AHCIQState *ahci)
804 {
805 uint16_t buff[256];
806 unsigned px;
807 int rc;
808 uint16_t sect_size;
809 const size_t buffsize = 512;
810
811 g_assert(ahci != NULL);
812
813 /**
814 * This serves as a bit of a tutorial on AHCI device programming:
815 *
816 * (1) Create a data buffer for the IDENTIFY response to be sent to
817 * (2) Create a Command Table buffer, where we will store the
818 * command and PRDT (Physical Region Descriptor Table)
819 * (3) Construct an FIS host-to-device command structure, and write it to
820 * the top of the Command Table buffer.
821 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
822 * a location in memory where data may be stored/retrieved.
823 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
824 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
825 * header that points to a Command Table buffer. Pick an unused slot
826 * and update it to point to the Command Table we have built.
827 * (7) Now: Command #n points to our Command Table, and our Command Table
828 * contains the FIS (that describes our command) and the PRDTL, which
829 * describes our buffer.
830 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
831 * #n is ready for processing.
832 */
833
834 /* Pick the first implemented and running port */
835 px = ahci_port_select(ahci);
836 g_test_message("Selected port %u for test", px);
837
838 /* Clear out the FIS Receive area and any pending interrupts. */
839 ahci_port_clear(ahci, px);
840
841 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
842 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
843
844 /* Check serial number/version in the buffer */
845 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
846 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
847 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
848 * as a consequence, only needs to unchunk the data on LE machines. */
849 string_bswap16(&buff[10], 20);
850 rc = memcmp(&buff[10], "testdisk ", 20);
851 g_assert_cmphex(rc, ==, 0);
852
853 string_bswap16(&buff[23], 8);
854 rc = memcmp(&buff[23], "version ", 8);
855 g_assert_cmphex(rc, ==, 0);
856
857 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
858 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
859 }
860
861 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
862 uint64_t sector, uint8_t read_cmd,
863 uint8_t write_cmd)
864 {
865 uint64_t ptr;
866 uint8_t port;
867 unsigned char *tx = g_malloc(bufsize);
868 unsigned char *rx = g_malloc0(bufsize);
869
870 g_assert(ahci != NULL);
871
872 /* Pick the first running port and clear it. */
873 port = ahci_port_select(ahci);
874 ahci_port_clear(ahci, port);
875
876 /*** Create pattern and transfer to guest ***/
877 /* Data buffer in the guest */
878 ptr = ahci_alloc(ahci, bufsize);
879 g_assert(ptr);
880
881 /* Write some indicative pattern to our buffer. */
882 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
883 bufwrite(ptr, tx, bufsize);
884
885 /* Write this buffer to disk, then read it back to the DMA buffer. */
886 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
887 qmemset(ptr, 0x00, bufsize);
888 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
889
890 /*** Read back the Data ***/
891 bufread(ptr, rx, bufsize);
892 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
893
894 ahci_free(ahci, ptr);
895 g_free(tx);
896 g_free(rx);
897 }
898
899 static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
900 {
901 uint8_t port;
902 AHCICommand *cmd;
903
904 /* Sanitize */
905 port = ahci_port_select(ahci);
906 ahci_port_clear(ahci, port);
907
908 /* Issue Command */
909 cmd = ahci_command_create(ide_cmd);
910 ahci_command_commit(ahci, cmd, port);
911 ahci_command_issue(ahci, cmd);
912 ahci_command_verify(ahci, cmd);
913 ahci_command_free(cmd);
914
915 return port;
916 }
917
918 static void ahci_test_flush(AHCIQState *ahci)
919 {
920 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
921 }
922
923 static void ahci_test_max(AHCIQState *ahci)
924 {
925 RegD2HFIS *d2h = g_malloc0(0x20);
926 uint64_t nsect;
927 uint8_t port;
928 uint8_t cmd;
929 uint64_t config_sect = TEST_IMAGE_SECTORS - 1;
930
931 if (config_sect > 0xFFFFFF) {
932 cmd = CMD_READ_MAX_EXT;
933 } else {
934 cmd = CMD_READ_MAX;
935 }
936
937 port = ahci_test_nondata(ahci, cmd);
938 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
939 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
940 (uint64_t)d2h->lba_hi[1] << 32 |
941 (uint64_t)d2h->lba_hi[0] << 24 |
942 (uint64_t)d2h->lba_lo[2] << 16 |
943 (uint64_t)d2h->lba_lo[1] << 8 |
944 (uint64_t)d2h->lba_lo[0];
945
946 g_assert_cmphex(nsect, ==, config_sect);
947 g_free(d2h);
948 }
949
950
951 /******************************************************************************/
952 /* Test Interfaces */
953 /******************************************************************************/
954
955 /**
956 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
957 */
958 static void test_sanity(void)
959 {
960 AHCIQState *ahci;
961 ahci = ahci_boot(NULL);
962 ahci_shutdown(ahci);
963 }
964
965 /**
966 * Ensure that the PCI configuration space for the AHCI device is in-line with
967 * the AHCI 1.3 specification for initial values.
968 */
969 static void test_pci_spec(void)
970 {
971 AHCIQState *ahci;
972 ahci = ahci_boot(NULL);
973 ahci_test_pci_spec(ahci);
974 ahci_shutdown(ahci);
975 }
976
977 /**
978 * Engage the PCI AHCI device and sanity check the response.
979 * Perform additional PCI config space bringup for the HBA.
980 */
981 static void test_pci_enable(void)
982 {
983 AHCIQState *ahci;
984 ahci = ahci_boot(NULL);
985 ahci_pci_enable(ahci);
986 ahci_shutdown(ahci);
987 }
988
989 /**
990 * Investigate the memory mapped regions of the HBA,
991 * and test them for AHCI specification adherence.
992 */
993 static void test_hba_spec(void)
994 {
995 AHCIQState *ahci;
996
997 ahci = ahci_boot(NULL);
998 ahci_pci_enable(ahci);
999 ahci_test_hba_spec(ahci);
1000 ahci_shutdown(ahci);
1001 }
1002
1003 /**
1004 * Engage the HBA functionality of the AHCI PCI device,
1005 * and bring it into a functional idle state.
1006 */
1007 static void test_hba_enable(void)
1008 {
1009 AHCIQState *ahci;
1010
1011 ahci = ahci_boot(NULL);
1012 ahci_pci_enable(ahci);
1013 ahci_hba_enable(ahci);
1014 ahci_shutdown(ahci);
1015 }
1016
1017 /**
1018 * Bring up the device and issue an IDENTIFY command.
1019 * Inspect the state of the HBA device and the data returned.
1020 */
1021 static void test_identify(void)
1022 {
1023 AHCIQState *ahci;
1024
1025 ahci = ahci_boot_and_enable(NULL);
1026 ahci_test_identify(ahci);
1027 ahci_shutdown(ahci);
1028 }
1029
1030 /**
1031 * Fragmented DMA test: Perform a standard 4K DMA read/write
1032 * test, but make sure the physical regions are fragmented to
1033 * be very small, each just 32 bytes, to see how AHCI performs
1034 * with chunks defined to be much less than a sector.
1035 */
1036 static void test_dma_fragmented(void)
1037 {
1038 AHCIQState *ahci;
1039 AHCICommand *cmd;
1040 uint8_t px;
1041 size_t bufsize = 4096;
1042 unsigned char *tx = g_malloc(bufsize);
1043 unsigned char *rx = g_malloc0(bufsize);
1044 uint64_t ptr;
1045
1046 ahci = ahci_boot_and_enable(NULL);
1047 px = ahci_port_select(ahci);
1048 ahci_port_clear(ahci, px);
1049
1050 /* create pattern */
1051 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1052
1053 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1054 ptr = guest_alloc(ahci->parent->alloc, bufsize);
1055 g_assert(ptr);
1056 bufwrite(ptr, tx, bufsize);
1057
1058 cmd = ahci_command_create(CMD_WRITE_DMA);
1059 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1060 ahci_command_commit(ahci, cmd, px);
1061 ahci_command_issue(ahci, cmd);
1062 ahci_command_verify(ahci, cmd);
1063 g_free(cmd);
1064
1065 cmd = ahci_command_create(CMD_READ_DMA);
1066 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1067 ahci_command_commit(ahci, cmd, px);
1068 ahci_command_issue(ahci, cmd);
1069 ahci_command_verify(ahci, cmd);
1070 g_free(cmd);
1071
1072 /* Read back the guest's receive buffer into local memory */
1073 bufread(ptr, rx, bufsize);
1074 guest_free(ahci->parent->alloc, ptr);
1075
1076 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1077
1078 ahci_shutdown(ahci);
1079
1080 g_free(rx);
1081 g_free(tx);
1082 }
1083
1084 static void test_flush(void)
1085 {
1086 AHCIQState *ahci;
1087
1088 ahci = ahci_boot_and_enable(NULL);
1089 ahci_test_flush(ahci);
1090 ahci_shutdown(ahci);
1091 }
1092
1093 static void test_flush_retry(void)
1094 {
1095 AHCIQState *ahci;
1096 AHCICommand *cmd;
1097 uint8_t port;
1098 const char *s;
1099
1100 prepare_blkdebug_script(debug_path, "flush_to_disk");
1101 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1102 "format=qcow2,cache=writeback,"
1103 "rerror=stop,werror=stop "
1104 "-M q35 "
1105 "-device ide-hd,drive=drive0 ",
1106 debug_path,
1107 tmp_path);
1108
1109 /* Issue Flush Command and wait for error */
1110 port = ahci_port_select(ahci);
1111 ahci_port_clear(ahci, port);
1112 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1113 ahci_command_commit(ahci, cmd, port);
1114 ahci_command_issue_async(ahci, cmd);
1115 qmp_eventwait("STOP");
1116
1117 /* Complete the command */
1118 s = "{'execute':'cont' }";
1119 qmp_async(s);
1120 qmp_eventwait("RESUME");
1121 ahci_command_wait(ahci, cmd);
1122 ahci_command_verify(ahci, cmd);
1123
1124 ahci_command_free(cmd);
1125 ahci_shutdown(ahci);
1126 }
1127
1128 /**
1129 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1130 */
1131 static void test_migrate_sanity(void)
1132 {
1133 AHCIQState *src, *dst;
1134 const char *uri = "tcp:127.0.0.1:1234";
1135
1136 src = ahci_boot("-m 1024 -M q35 "
1137 "-hda %s ", tmp_path);
1138 dst = ahci_boot("-m 1024 -M q35 "
1139 "-hda %s "
1140 "-incoming %s", tmp_path, uri);
1141
1142 ahci_migrate(src, dst, uri);
1143
1144 ahci_shutdown(src);
1145 ahci_shutdown(dst);
1146 }
1147
1148 /**
1149 * DMA Migration test: Write a pattern, migrate, then read.
1150 */
1151 static void test_migrate_dma(void)
1152 {
1153 AHCIQState *src, *dst;
1154 uint8_t px;
1155 size_t bufsize = 4096;
1156 unsigned char *tx = g_malloc(bufsize);
1157 unsigned char *rx = g_malloc0(bufsize);
1158 unsigned i;
1159 const char *uri = "tcp:127.0.0.1:1234";
1160
1161 src = ahci_boot_and_enable("-m 1024 -M q35 "
1162 "-hda %s ", tmp_path);
1163 dst = ahci_boot("-m 1024 -M q35 "
1164 "-hda %s "
1165 "-incoming %s", tmp_path, uri);
1166
1167 set_context(src->parent);
1168
1169 /* initialize */
1170 px = ahci_port_select(src);
1171 ahci_port_clear(src, px);
1172
1173 /* create pattern */
1174 for (i = 0; i < bufsize; i++) {
1175 tx[i] = (bufsize - i);
1176 }
1177
1178 /* Write, migrate, then read. */
1179 ahci_io(src, px, CMD_WRITE_DMA, tx, bufsize, 0);
1180 ahci_migrate(src, dst, uri);
1181 ahci_io(dst, px, CMD_READ_DMA, rx, bufsize, 0);
1182
1183 /* Verify pattern */
1184 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1185
1186 ahci_shutdown(src);
1187 ahci_shutdown(dst);
1188 g_free(rx);
1189 g_free(tx);
1190 }
1191
1192 /**
1193 * DMA Error Test
1194 *
1195 * Simulate an error on first write, Try to write a pattern,
1196 * Confirm the VM has stopped, resume the VM, verify command
1197 * has completed, then read back the data and verify.
1198 */
1199 static void test_halted_dma(void)
1200 {
1201 AHCIQState *ahci;
1202 uint8_t port;
1203 size_t bufsize = 4096;
1204 unsigned char *tx = g_malloc(bufsize);
1205 unsigned char *rx = g_malloc0(bufsize);
1206 unsigned i;
1207 uint64_t ptr;
1208 AHCICommand *cmd;
1209
1210 prepare_blkdebug_script(debug_path, "write_aio");
1211
1212 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1213 "format=qcow2,cache=writeback,"
1214 "rerror=stop,werror=stop "
1215 "-M q35 "
1216 "-device ide-hd,drive=drive0 ",
1217 debug_path,
1218 tmp_path);
1219
1220 /* Initialize and prepare */
1221 port = ahci_port_select(ahci);
1222 ahci_port_clear(ahci, port);
1223
1224 for (i = 0; i < bufsize; i++) {
1225 tx[i] = (bufsize - i);
1226 }
1227
1228 /* create DMA source buffer and write pattern */
1229 ptr = ahci_alloc(ahci, bufsize);
1230 g_assert(ptr);
1231 memwrite(ptr, tx, bufsize);
1232
1233 /* Attempt to write (and fail) */
1234 cmd = ahci_guest_io_halt(ahci, port, CMD_WRITE_DMA,
1235 ptr, bufsize, 0);
1236
1237 /* Attempt to resume the command */
1238 ahci_guest_io_resume(ahci, cmd);
1239 ahci_free(ahci, ptr);
1240
1241 /* Read back and verify */
1242 ahci_io(ahci, port, CMD_READ_DMA, rx, bufsize, 0);
1243 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1244
1245 /* Cleanup and go home */
1246 ahci_shutdown(ahci);
1247 g_free(rx);
1248 g_free(tx);
1249 }
1250
1251 /**
1252 * DMA Error Migration Test
1253 *
1254 * Simulate an error on first write, Try to write a pattern,
1255 * Confirm the VM has stopped, migrate, resume the VM,
1256 * verify command has completed, then read back the data and verify.
1257 */
1258 static void test_migrate_halted_dma(void)
1259 {
1260 AHCIQState *src, *dst;
1261 uint8_t port;
1262 size_t bufsize = 4096;
1263 unsigned char *tx = g_malloc(bufsize);
1264 unsigned char *rx = g_malloc0(bufsize);
1265 unsigned i;
1266 uint64_t ptr;
1267 AHCICommand *cmd;
1268 const char *uri = "tcp:127.0.0.1:1234";
1269
1270 prepare_blkdebug_script(debug_path, "write_aio");
1271
1272 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1273 "format=qcow2,cache=writeback,"
1274 "rerror=stop,werror=stop "
1275 "-M q35 "
1276 "-device ide-hd,drive=drive0 ",
1277 debug_path,
1278 tmp_path);
1279
1280 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1281 "format=qcow2,cache=writeback,"
1282 "rerror=stop,werror=stop "
1283 "-M q35 "
1284 "-device ide-hd,drive=drive0 "
1285 "-incoming %s",
1286 tmp_path, uri);
1287
1288 set_context(src->parent);
1289
1290 /* Initialize and prepare */
1291 port = ahci_port_select(src);
1292 ahci_port_clear(src, port);
1293
1294 for (i = 0; i < bufsize; i++) {
1295 tx[i] = (bufsize - i);
1296 }
1297
1298 /* create DMA source buffer and write pattern */
1299 ptr = ahci_alloc(src, bufsize);
1300 g_assert(ptr);
1301 memwrite(ptr, tx, bufsize);
1302
1303 /* Write, trigger the VM to stop, migrate, then resume. */
1304 cmd = ahci_guest_io_halt(src, port, CMD_WRITE_DMA,
1305 ptr, bufsize, 0);
1306 ahci_migrate(src, dst, uri);
1307 ahci_guest_io_resume(dst, cmd);
1308 ahci_free(dst, ptr);
1309
1310 /* Read back */
1311 ahci_io(dst, port, CMD_READ_DMA, rx, bufsize, 0);
1312
1313 /* Verify TX and RX are identical */
1314 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1315
1316 /* Cleanup and go home. */
1317 ahci_shutdown(src);
1318 ahci_shutdown(dst);
1319 g_free(rx);
1320 g_free(tx);
1321 }
1322
1323 /**
1324 * Migration test: Try to flush, migrate, then resume.
1325 */
1326 static void test_flush_migrate(void)
1327 {
1328 AHCIQState *src, *dst;
1329 AHCICommand *cmd;
1330 uint8_t px;
1331 const char *s;
1332 const char *uri = "tcp:127.0.0.1:1234";
1333
1334 prepare_blkdebug_script(debug_path, "flush_to_disk");
1335
1336 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1337 "cache=writeback,rerror=stop,werror=stop "
1338 "-M q35 "
1339 "-device ide-hd,drive=drive0 ",
1340 debug_path, tmp_path);
1341 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1342 "cache=writeback,rerror=stop,werror=stop "
1343 "-M q35 "
1344 "-device ide-hd,drive=drive0 "
1345 "-incoming %s", tmp_path, uri);
1346
1347 set_context(src->parent);
1348
1349 /* Issue Flush Command */
1350 px = ahci_port_select(src);
1351 ahci_port_clear(src, px);
1352 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1353 ahci_command_commit(src, cmd, px);
1354 ahci_command_issue_async(src, cmd);
1355 qmp_eventwait("STOP");
1356
1357 /* Migrate over */
1358 ahci_migrate(src, dst, uri);
1359
1360 /* Complete the command */
1361 s = "{'execute':'cont' }";
1362 qmp_async(s);
1363 qmp_eventwait("RESUME");
1364 ahci_command_wait(dst, cmd);
1365 ahci_command_verify(dst, cmd);
1366
1367 ahci_command_free(cmd);
1368 ahci_shutdown(src);
1369 ahci_shutdown(dst);
1370 }
1371
1372 static void test_max(void)
1373 {
1374 AHCIQState *ahci;
1375
1376 ahci = ahci_boot_and_enable(NULL);
1377 ahci_test_max(ahci);
1378 ahci_shutdown(ahci);
1379 }
1380
1381 static void test_reset(void)
1382 {
1383 AHCIQState *ahci;
1384 int i;
1385
1386 ahci = ahci_boot(NULL);
1387 ahci_test_pci_spec(ahci);
1388 ahci_pci_enable(ahci);
1389
1390 for (i = 0; i < 2; i++) {
1391 ahci_test_hba_spec(ahci);
1392 ahci_hba_enable(ahci);
1393 ahci_test_identify(ahci);
1394 ahci_test_io_rw_simple(ahci, 4096, 0,
1395 CMD_READ_DMA_EXT,
1396 CMD_WRITE_DMA_EXT);
1397 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1398 ahci_clean_mem(ahci);
1399 }
1400
1401 ahci_shutdown(ahci);
1402 }
1403
1404 static void test_ncq_simple(void)
1405 {
1406 AHCIQState *ahci;
1407
1408 ahci = ahci_boot_and_enable(NULL);
1409 ahci_test_io_rw_simple(ahci, 4096, 0,
1410 READ_FPDMA_QUEUED,
1411 WRITE_FPDMA_QUEUED);
1412 ahci_shutdown(ahci);
1413 }
1414
1415 /******************************************************************************/
1416 /* AHCI I/O Test Matrix Definitions */
1417
1418 enum BuffLen {
1419 LEN_BEGIN = 0,
1420 LEN_SIMPLE = LEN_BEGIN,
1421 LEN_DOUBLE,
1422 LEN_LONG,
1423 LEN_SHORT,
1424 NUM_LENGTHS
1425 };
1426
1427 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1428 "long", "short" };
1429
1430 enum AddrMode {
1431 ADDR_MODE_BEGIN = 0,
1432 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1433 ADDR_MODE_LBA48,
1434 NUM_ADDR_MODES
1435 };
1436
1437 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1438
1439 enum IOMode {
1440 MODE_BEGIN = 0,
1441 MODE_PIO = MODE_BEGIN,
1442 MODE_DMA,
1443 NUM_MODES
1444 };
1445
1446 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1447
1448 enum IOOps {
1449 IO_BEGIN = 0,
1450 IO_READ = IO_BEGIN,
1451 IO_WRITE,
1452 NUM_IO_OPS
1453 };
1454
1455 enum OffsetType {
1456 OFFSET_BEGIN = 0,
1457 OFFSET_ZERO = OFFSET_BEGIN,
1458 OFFSET_LOW,
1459 OFFSET_HIGH,
1460 NUM_OFFSETS
1461 };
1462
1463 static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1464
1465 typedef struct AHCIIOTestOptions {
1466 enum BuffLen length;
1467 enum AddrMode address_type;
1468 enum IOMode io_type;
1469 enum OffsetType offset;
1470 } AHCIIOTestOptions;
1471
1472 static uint64_t offset_sector(enum OffsetType ofst,
1473 enum AddrMode addr_type,
1474 uint64_t buffsize)
1475 {
1476 uint64_t ceil;
1477 uint64_t nsectors;
1478
1479 switch (ofst) {
1480 case OFFSET_ZERO:
1481 return 0;
1482 case OFFSET_LOW:
1483 return 1;
1484 case OFFSET_HIGH:
1485 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1486 ceil = MIN(ceil, TEST_IMAGE_SECTORS - 1);
1487 nsectors = buffsize / AHCI_SECTOR_SIZE;
1488 return ceil - nsectors + 1;
1489 default:
1490 g_assert_not_reached();
1491 }
1492 }
1493
1494 /**
1495 * Table of possible I/O ATA commands given a set of enumerations.
1496 */
1497 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1498 [MODE_PIO] = {
1499 [ADDR_MODE_LBA28] = {
1500 [IO_READ] = CMD_READ_PIO,
1501 [IO_WRITE] = CMD_WRITE_PIO },
1502 [ADDR_MODE_LBA48] = {
1503 [IO_READ] = CMD_READ_PIO_EXT,
1504 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1505 },
1506 [MODE_DMA] = {
1507 [ADDR_MODE_LBA28] = {
1508 [IO_READ] = CMD_READ_DMA,
1509 [IO_WRITE] = CMD_WRITE_DMA },
1510 [ADDR_MODE_LBA48] = {
1511 [IO_READ] = CMD_READ_DMA_EXT,
1512 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1513 }
1514 };
1515
1516 /**
1517 * Test a Read/Write pattern using various commands, addressing modes,
1518 * transfer modes, and buffer sizes.
1519 */
1520 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1521 unsigned bufsize, uint64_t sector)
1522 {
1523 AHCIQState *ahci;
1524
1525 ahci = ahci_boot_and_enable(NULL);
1526 ahci_test_io_rw_simple(ahci, bufsize, sector,
1527 io_cmds[dma][lba48][IO_READ],
1528 io_cmds[dma][lba48][IO_WRITE]);
1529 ahci_shutdown(ahci);
1530 }
1531
1532 /**
1533 * Demultiplex the test data and invoke the actual test routine.
1534 */
1535 static void test_io_interface(gconstpointer opaque)
1536 {
1537 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1538 unsigned bufsize;
1539 uint64_t sector;
1540
1541 switch (opts->length) {
1542 case LEN_SIMPLE:
1543 bufsize = 4096;
1544 break;
1545 case LEN_DOUBLE:
1546 bufsize = 8192;
1547 break;
1548 case LEN_LONG:
1549 bufsize = 4096 * 64;
1550 break;
1551 case LEN_SHORT:
1552 bufsize = 512;
1553 break;
1554 default:
1555 g_assert_not_reached();
1556 }
1557
1558 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1559 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1560 g_free(opts);
1561 return;
1562 }
1563
1564 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1565 enum BuffLen len, enum OffsetType offset)
1566 {
1567 char *name;
1568 AHCIIOTestOptions *opts = g_malloc(sizeof(AHCIIOTestOptions));
1569
1570 opts->length = len;
1571 opts->address_type = addr;
1572 opts->io_type = type;
1573 opts->offset = offset;
1574
1575 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1576 io_mode_str[type],
1577 addr_mode_str[addr],
1578 buff_len_str[len],
1579 offset_str[offset]);
1580
1581 qtest_add_data_func(name, opts, test_io_interface);
1582 g_free(name);
1583 }
1584
1585 /******************************************************************************/
1586
1587 int main(int argc, char **argv)
1588 {
1589 const char *arch;
1590 int ret;
1591 int fd;
1592 int c;
1593 int i, j, k, m;
1594
1595 static struct option long_options[] = {
1596 {"pedantic", no_argument, 0, 'p' },
1597 {0, 0, 0, 0},
1598 };
1599
1600 /* Should be first to utilize g_test functionality, So we can see errors. */
1601 g_test_init(&argc, &argv, NULL);
1602
1603 while (1) {
1604 c = getopt_long(argc, argv, "", long_options, NULL);
1605 if (c == -1) {
1606 break;
1607 }
1608 switch (c) {
1609 case -1:
1610 break;
1611 case 'p':
1612 ahci_pedantic = 1;
1613 break;
1614 default:
1615 fprintf(stderr, "Unrecognized ahci_test option.\n");
1616 g_assert_not_reached();
1617 }
1618 }
1619
1620 /* Check architecture */
1621 arch = qtest_get_arch();
1622 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1623 g_test_message("Skipping test for non-x86");
1624 return 0;
1625 }
1626
1627 /* Create a temporary qcow2 image */
1628 close(mkstemp(tmp_path));
1629 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB);
1630
1631 /* Create temporary blkdebug instructions */
1632 fd = mkstemp(debug_path);
1633 g_assert(fd >= 0);
1634 close(fd);
1635
1636 /* Run the tests */
1637 qtest_add_func("/ahci/sanity", test_sanity);
1638 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1639 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1640 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1641 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1642 qtest_add_func("/ahci/identify", test_identify);
1643
1644 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1645 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1646 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1647 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1648 create_ahci_io_test(i, j, k, m);
1649 }
1650 }
1651 }
1652 }
1653
1654 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1655
1656 qtest_add_func("/ahci/flush/simple", test_flush);
1657 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1658 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1659
1660 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1661 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1662 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1663 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1664
1665 qtest_add_func("/ahci/max", test_max);
1666 qtest_add_func("/ahci/reset", test_reset);
1667
1668 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1669
1670 ret = g_test_run();
1671
1672 /* Cleanup */
1673 unlink(tmp_path);
1674 unlink(debug_path);
1675
1676 return ret;
1677 }