4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
36 #include "qemu-common.h"
37 #include "qemu/host-utils.h"
39 #include "hw/pci/pci_ids.h"
40 #include "hw/pci/pci_regs.h"
42 /* Test-specific defines -- in MiB */
43 #define TEST_IMAGE_SIZE_MB (200 * 1024)
44 #define TEST_IMAGE_SECTORS ((TEST_IMAGE_SIZE_MB / AHCI_SECTOR_SIZE) \
48 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
49 static bool ahci_pedantic
;
51 /*** Function Declarations ***/
52 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
53 static void ahci_test_pci_spec(AHCIQState
*ahci
);
54 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
56 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
57 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
58 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
62 static void string_bswap16(uint16_t *s
, size_t bytes
)
64 g_assert_cmphex((bytes
& 1), ==, 0);
73 static void generate_pattern(void *buffer
, size_t len
, size_t cycle_len
)
76 unsigned char *tx
= (unsigned char *)buffer
;
80 /* Write an indicative pattern that varies and is unique per-cycle */
82 for (i
= j
= 0; i
< len
; i
++, j
++) {
84 if (j
% cycle_len
== 0) {
89 /* force uniqueness by writing an id per-cycle */
90 for (i
= 0; i
< len
/ cycle_len
; i
++) {
92 if (j
+ sizeof(*sx
) <= len
) {
93 sx
= (size_t *)&tx
[j
];
99 /*** Test Setup & Teardown ***/
102 * Start a Q35 machine and bookmark a handle to the AHCI device.
104 static AHCIQState
*ahci_boot(void)
109 s
= g_malloc0(sizeof(AHCIQState
));
111 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
114 "-device ide-hd,drive=drive0 "
115 "-global ide-hd.ver=%s";
116 s
->parent
= qtest_pc_boot(cli
, tmp_path
, "testdisk", "version");
117 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
119 /* Verify that we have an AHCI device present. */
120 s
->dev
= get_ahci_device(&s
->fingerprint
);
126 * Clean up the PCI device, then terminate the QEMU instance.
128 static void ahci_shutdown(AHCIQState
*ahci
)
130 QOSState
*qs
= ahci
->parent
;
132 ahci_clean_mem(ahci
);
133 free_ahci_device(ahci
->dev
);
139 * Boot and fully enable the HBA device.
140 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
142 static AHCIQState
*ahci_boot_and_enable(void)
147 ahci_pci_enable(ahci
);
148 ahci_hba_enable(ahci
);
153 /*** Specification Adherence Tests ***/
156 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
158 static void ahci_test_pci_spec(AHCIQState
*ahci
)
164 /* Most of these bits should start cleared until we turn them on. */
165 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
166 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
167 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
168 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
169 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
170 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
171 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
172 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
173 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
174 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
175 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
177 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
178 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
179 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
180 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
181 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
182 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
183 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
184 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
185 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
186 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
187 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
189 /* RID occupies the low byte, CCs occupy the high three. */
190 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
192 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
193 * Though in practice this is likely seldom true. */
194 ASSERT_BIT_CLEAR(datal
, 0xFF);
197 /* BCC *must* equal 0x01. */
198 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
199 if (PCI_SCC(datal
) == 0x01) {
201 ASSERT_BIT_SET(0x80000000, datal
);
202 ASSERT_BIT_CLEAR(0x60000000, datal
);
203 } else if (PCI_SCC(datal
) == 0x04) {
205 g_assert_cmphex(PCI_PI(datal
), ==, 0);
206 } else if (PCI_SCC(datal
) == 0x06) {
208 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
210 g_assert_not_reached();
213 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
214 g_assert_cmphex(datab
, ==, 0);
216 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
217 g_assert_cmphex(datab
, ==, 0);
219 /* Only the bottom 7 bits must be off. */
220 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
221 ASSERT_BIT_CLEAR(datab
, 0x7F);
223 /* BIST is optional, but the low 7 bits must always start off regardless. */
224 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
225 ASSERT_BIT_CLEAR(datab
, 0x7F);
227 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
228 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
229 g_assert_cmphex(datal
, ==, 0);
231 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
232 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
233 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
234 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
235 ASSERT_BIT_CLEAR(datal
, 0xFF);
237 /* Capability list MUST be present, */
238 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
239 /* But these bits are reserved. */
240 ASSERT_BIT_CLEAR(datal
, ~0xFF);
241 g_assert_cmphex(datal
, !=, 0);
243 /* Check specification adherence for capability extenstions. */
244 data
= qpci_config_readw(ahci
->dev
, datal
);
246 switch (ahci
->fingerprint
) {
247 case AHCI_INTEL_ICH9
:
248 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
249 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
252 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
253 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
256 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
259 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
260 g_assert_cmphex(datal
, ==, 0);
262 /* IPIN might vary, but ILINE must be off. */
263 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
264 g_assert_cmphex(datab
, ==, 0);
268 * Test PCI capabilities for AHCI specification adherence.
270 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
273 uint8_t cid
= header
& 0xFF;
274 uint8_t next
= header
>> 8;
276 g_test_message("CID: %02x; next: %02x", cid
, next
);
280 ahci_test_pmcap(ahci
, offset
);
283 ahci_test_msicap(ahci
, offset
);
285 case PCI_CAP_ID_SATA
:
286 ahci_test_satacap(ahci
, offset
);
290 g_test_message("Unknown CAP 0x%02x", cid
);
294 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
299 * Test SATA PCI capabilitity for AHCI specification adherence.
301 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
306 g_test_message("Verifying SATACAP");
308 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
309 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
310 g_assert_cmphex(dataw
, ==, 0x10);
312 /* Grab the SATACR1 register. */
313 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
315 switch (datal
& 0x0F) {
316 case 0x04: /* BAR0 */
317 case 0x05: /* BAR1 */
321 case 0x09: /* BAR5 */
322 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
325 /* Invalid BARLOC for the Index Data Pair. */
326 g_assert_not_reached();
330 g_assert_cmphex((datal
>> 24), ==, 0x00);
334 * Test MSI PCI capability for AHCI specification adherence.
336 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
341 g_test_message("Verifying MSICAP");
343 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
344 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
345 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
346 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
348 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
349 g_assert_cmphex(datal
, ==, 0);
351 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
352 g_test_message("MSICAP is 64bit");
353 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
354 g_assert_cmphex(datal
, ==, 0);
355 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
356 g_assert_cmphex(dataw
, ==, 0);
358 g_test_message("MSICAP is 32bit");
359 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
360 g_assert_cmphex(dataw
, ==, 0);
365 * Test Power Management PCI capability for AHCI specification adherence.
367 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
371 g_test_message("Verifying PMCAP");
373 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
374 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
375 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
376 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
377 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
379 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
380 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
381 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
382 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
383 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
386 static void ahci_test_hba_spec(AHCIQState
*ahci
)
394 g_assert(ahci
!= NULL
);
397 * Note that the AHCI spec does expect the BIOS to set up a few things:
398 * CAP.SSS - Support for staggered spin-up (t/f)
399 * CAP.SMPS - Support for mechanical presence switches (t/f)
400 * PI - Ports Implemented (1-32)
401 * PxCMD.HPCP - Hot Plug Capable Port
402 * PxCMD.MPSP - Mechanical Presence Switch Present
403 * PxCMD.CPD - Cold Presence Detection support
405 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
406 * Foreach Port Implemented:
407 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
408 * -PxCLB/U and PxFB/U are set to valid regions in memory
409 * -PxSUD is set to 1.
410 * -PxSSTS.DET is polled for presence; if detected, we continue:
411 * -PxSERR is cleared with 1's.
412 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
413 * the device is ready.
416 /* 1 CAP - Capabilities Register */
417 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
418 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
420 /* 2 GHC - Global Host Control */
421 reg
= ahci_rreg(ahci
, AHCI_GHC
);
422 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
423 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
424 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
425 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
426 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
427 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
429 g_test_message("Supports AHCI/Legacy mix.");
430 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
433 /* 3 IS - Interrupt Status */
434 reg
= ahci_rreg(ahci
, AHCI_IS
);
435 g_assert_cmphex(reg
, ==, 0);
437 /* 4 PI - Ports Implemented */
438 ports
= ahci_rreg(ahci
, AHCI_PI
);
439 /* Ports Implemented must be non-zero. */
440 g_assert_cmphex(ports
, !=, 0);
441 /* Ports Implemented must be <= Number of Ports. */
442 nports_impl
= ctpopl(ports
);
443 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
445 /* Ports must be within the proper range. Given a mapping of SIZE,
446 * 256 bytes are used for global HBA control, and the rest is used
447 * for ports data, at 0x80 bytes each. */
448 g_assert_cmphex(ahci
->barsize
, >, 0);
449 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
450 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
451 g_assert_cmphex((reg
>> maxports
), ==, 0);
454 reg
= ahci_rreg(ahci
, AHCI_VS
);
456 case AHCI_VERSION_0_95
:
457 case AHCI_VERSION_1_0
:
458 case AHCI_VERSION_1_1
:
459 case AHCI_VERSION_1_2
:
460 case AHCI_VERSION_1_3
:
463 g_assert_not_reached();
466 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
467 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
468 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
469 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
470 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
471 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
472 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
474 g_assert_cmphex(reg
, ==, 0);
478 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
479 /* Must be zeroes initially regardless of CAP.CCCS */
480 g_assert_cmphex(reg
, ==, 0);
483 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
484 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
485 g_assert_cmphex(reg
, ==, 0);
489 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
490 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
491 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
492 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
493 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
494 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
496 g_assert_cmphex(reg
, ==, 0);
499 /* 10 CAP2 -- Capabilities Extended */
500 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
501 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
503 /* 11 BOHC -- Bios/OS Handoff Control */
504 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
505 g_assert_cmphex(reg
, ==, 0);
507 /* 12 -- 23: Reserved */
508 g_test_message("Verifying HBA reserved area is empty.");
509 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
510 reg
= ahci_rreg(ahci
, i
);
511 g_assert_cmphex(reg
, ==, 0);
514 /* 24 -- 39: NVMHCI */
515 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
516 g_test_message("Verifying HBA/NVMHCI area is empty.");
517 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
518 reg
= ahci_rreg(ahci
, i
);
519 g_assert_cmphex(reg
, ==, 0);
523 /* 40 -- 63: Vendor */
524 g_test_message("Verifying HBA/Vendor area is empty.");
525 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
526 reg
= ahci_rreg(ahci
, i
);
527 g_assert_cmphex(reg
, ==, 0);
530 /* 64 -- XX: Port Space */
531 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
532 if (BITSET(ports
, 0x1)) {
533 g_test_message("Testing port %u for spec", i
);
534 ahci_test_port_spec(ahci
, i
);
537 uint16_t low
= AHCI_PORTS
+ (32 * i
);
538 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
539 g_test_message("Asserting unimplemented port %u "
540 "(reg [%u-%u]) is empty.",
542 for (j
= low
; j
< high
; ++j
) {
543 reg
= ahci_rreg(ahci
, j
);
544 g_assert_cmphex(reg
, ==, 0);
551 * Test the memory space for one port for specification adherence.
553 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
559 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
560 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
563 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
564 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
565 g_assert_cmphex(reg
, ==, 0);
569 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
570 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
573 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
574 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
575 g_assert_cmphex(reg
, ==, 0);
579 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
580 g_assert_cmphex(reg
, ==, 0);
583 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
584 g_assert_cmphex(reg
, ==, 0);
587 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
588 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
589 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
590 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
591 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
592 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
593 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
594 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
595 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
596 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
597 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
598 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
599 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
600 /* If CPDetect support does not exist, CPState must be off. */
601 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
602 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
604 /* If MPSPresence is not set, MPSState must be off. */
605 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
606 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
608 /* If we do not support MPS, MPSS and MPSP must be off. */
609 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
610 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
611 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
613 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
614 if (BITANY(reg
, AHCI_PX_CMD_CPD
| AHCI_PX_CMD_MPSP
)) {
615 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
617 /* HPCP and ESP cannot both be active. */
618 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
619 /* If CAP.FBSS is not set, FBSCP must not be set. */
620 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
621 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
625 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
626 g_assert_cmphex(reg
, ==, 0);
629 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
630 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
631 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
632 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
633 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
634 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
635 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
636 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
637 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
638 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
641 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
642 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
643 * D2H register FIS and update the signature asynchronously,
644 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
646 /* (10) SSTS / SCR0: SStatus */
647 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
648 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
649 /* Even though the register should be 0 at boot, it is asynchronous and
650 * prone to change, so we cannot test any well known value. */
652 /* (11) SCTL / SCR2: SControl */
653 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
654 g_assert_cmphex(reg
, ==, 0);
656 /* (12) SERR / SCR1: SError */
657 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
658 g_assert_cmphex(reg
, ==, 0);
660 /* (13) SACT / SCR3: SActive */
661 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
662 g_assert_cmphex(reg
, ==, 0);
665 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
666 g_assert_cmphex(reg
, ==, 0);
669 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
670 g_assert_cmphex(reg
, ==, 0);
673 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
674 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
675 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
676 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
677 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
678 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
679 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
680 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
681 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
682 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
685 /* [17 -- 27] RESERVED */
686 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
687 reg
= ahci_px_rreg(ahci
, port
, i
);
688 g_assert_cmphex(reg
, ==, 0);
691 /* [28 -- 31] Vendor-Specific */
692 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
693 reg
= ahci_px_rreg(ahci
, port
, i
);
695 g_test_message("INFO: Vendor register %u non-empty", i
);
701 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
702 * device we see, then read and check the response.
704 static void ahci_test_identify(AHCIQState
*ahci
)
710 const size_t buffsize
= 512;
712 g_assert(ahci
!= NULL
);
715 * This serves as a bit of a tutorial on AHCI device programming:
717 * (1) Create a data buffer for the IDENTIFY response to be sent to
718 * (2) Create a Command Table buffer, where we will store the
719 * command and PRDT (Physical Region Descriptor Table)
720 * (3) Construct an FIS host-to-device command structure, and write it to
721 * the top of the Command Table buffer.
722 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
723 * a location in memory where data may be stored/retrieved.
724 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
725 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
726 * header that points to a Command Table buffer. Pick an unused slot
727 * and update it to point to the Command Table we have built.
728 * (7) Now: Command #n points to our Command Table, and our Command Table
729 * contains the FIS (that describes our command) and the PRDTL, which
730 * describes our buffer.
731 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
732 * #n is ready for processing.
735 /* Pick the first implemented and running port */
736 px
= ahci_port_select(ahci
);
737 g_test_message("Selected port %u for test", px
);
739 /* Clear out the FIS Receive area and any pending interrupts. */
740 ahci_port_clear(ahci
, px
);
742 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
743 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
, 0);
745 /* Check serial number/version in the buffer */
746 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
747 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
748 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
749 * as a consequence, only needs to unchunk the data on LE machines. */
750 string_bswap16(&buff
[10], 20);
751 rc
= memcmp(&buff
[10], "testdisk ", 20);
752 g_assert_cmphex(rc
, ==, 0);
754 string_bswap16(&buff
[23], 8);
755 rc
= memcmp(&buff
[23], "version ", 8);
756 g_assert_cmphex(rc
, ==, 0);
758 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
759 g_assert_cmphex(sect_size
, ==, AHCI_SECTOR_SIZE
);
762 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
763 uint64_t sector
, uint8_t read_cmd
,
768 unsigned char *tx
= g_malloc(bufsize
);
769 unsigned char *rx
= g_malloc0(bufsize
);
771 g_assert(ahci
!= NULL
);
773 /* Pick the first running port and clear it. */
774 port
= ahci_port_select(ahci
);
775 ahci_port_clear(ahci
, port
);
777 /*** Create pattern and transfer to guest ***/
778 /* Data buffer in the guest */
779 ptr
= ahci_alloc(ahci
, bufsize
);
782 /* Write some indicative pattern to our buffer. */
783 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
784 memwrite(ptr
, tx
, bufsize
);
786 /* Write this buffer to disk, then read it back to the DMA buffer. */
787 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
, sector
);
788 qmemset(ptr
, 0x00, bufsize
);
789 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
, sector
);
791 /*** Read back the Data ***/
792 memread(ptr
, rx
, bufsize
);
793 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
795 ahci_free(ahci
, ptr
);
800 static void ahci_test_nondata(AHCIQState
*ahci
, uint8_t ide_cmd
)
806 px
= ahci_port_select(ahci
);
807 ahci_port_clear(ahci
, px
);
810 cmd
= ahci_command_create(ide_cmd
);
811 ahci_command_commit(ahci
, cmd
, px
);
812 ahci_command_issue(ahci
, cmd
);
813 ahci_command_verify(ahci
, cmd
);
814 ahci_command_free(cmd
);
817 static void ahci_test_flush(AHCIQState
*ahci
)
819 ahci_test_nondata(ahci
, CMD_FLUSH_CACHE
);
823 /******************************************************************************/
824 /* Test Interfaces */
825 /******************************************************************************/
828 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
830 static void test_sanity(void)
838 * Ensure that the PCI configuration space for the AHCI device is in-line with
839 * the AHCI 1.3 specification for initial values.
841 static void test_pci_spec(void)
845 ahci_test_pci_spec(ahci
);
850 * Engage the PCI AHCI device and sanity check the response.
851 * Perform additional PCI config space bringup for the HBA.
853 static void test_pci_enable(void)
858 ahci_pci_enable(ahci
);
863 * Investigate the memory mapped regions of the HBA,
864 * and test them for AHCI specification adherence.
866 static void test_hba_spec(void)
871 ahci_pci_enable(ahci
);
872 ahci_test_hba_spec(ahci
);
877 * Engage the HBA functionality of the AHCI PCI device,
878 * and bring it into a functional idle state.
880 static void test_hba_enable(void)
885 ahci_pci_enable(ahci
);
886 ahci_hba_enable(ahci
);
891 * Bring up the device and issue an IDENTIFY command.
892 * Inspect the state of the HBA device and the data returned.
894 static void test_identify(void)
898 ahci
= ahci_boot_and_enable();
899 ahci_test_identify(ahci
);
904 * Fragmented DMA test: Perform a standard 4K DMA read/write
905 * test, but make sure the physical regions are fragmented to
906 * be very small, each just 32 bytes, to see how AHCI performs
907 * with chunks defined to be much less than a sector.
909 static void test_dma_fragmented(void)
914 size_t bufsize
= 4096;
915 unsigned char *tx
= g_malloc(bufsize
);
916 unsigned char *rx
= g_malloc0(bufsize
);
919 ahci
= ahci_boot_and_enable();
920 px
= ahci_port_select(ahci
);
921 ahci_port_clear(ahci
, px
);
924 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
926 /* Create a DMA buffer in guest memory, and write our pattern to it. */
927 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
929 memwrite(ptr
, tx
, bufsize
);
931 cmd
= ahci_command_create(CMD_WRITE_DMA
);
932 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
933 ahci_command_commit(ahci
, cmd
, px
);
934 ahci_command_issue(ahci
, cmd
);
935 ahci_command_verify(ahci
, cmd
);
938 cmd
= ahci_command_create(CMD_READ_DMA
);
939 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
940 ahci_command_commit(ahci
, cmd
, px
);
941 ahci_command_issue(ahci
, cmd
);
942 ahci_command_verify(ahci
, cmd
);
945 /* Read back the guest's receive buffer into local memory */
946 memread(ptr
, rx
, bufsize
);
947 guest_free(ahci
->parent
->alloc
, ptr
);
949 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
957 static void test_flush(void)
961 ahci
= ahci_boot_and_enable();
962 ahci_test_flush(ahci
);
966 /******************************************************************************/
967 /* AHCI I/O Test Matrix Definitions */
971 LEN_SIMPLE
= LEN_BEGIN
,
978 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
983 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
988 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
992 MODE_PIO
= MODE_BEGIN
,
997 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
1008 OFFSET_ZERO
= OFFSET_BEGIN
,
1014 static const char *offset_str
[NUM_OFFSETS
] = { "zero", "low", "high" };
1016 typedef struct AHCIIOTestOptions
{
1017 enum BuffLen length
;
1018 enum AddrMode address_type
;
1019 enum IOMode io_type
;
1020 enum OffsetType offset
;
1021 } AHCIIOTestOptions
;
1023 static uint64_t offset_sector(enum OffsetType ofst
,
1024 enum AddrMode addr_type
,
1036 ceil
= (addr_type
== ADDR_MODE_LBA28
) ? 0xfffffff : 0xffffffffffff;
1037 ceil
= MIN(ceil
, TEST_IMAGE_SECTORS
- 1);
1038 nsectors
= buffsize
/ AHCI_SECTOR_SIZE
;
1039 return ceil
- nsectors
+ 1;
1041 g_assert_not_reached();
1046 * Table of possible I/O ATA commands given a set of enumerations.
1048 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
1050 [ADDR_MODE_LBA28
] = {
1051 [IO_READ
] = CMD_READ_PIO
,
1052 [IO_WRITE
] = CMD_WRITE_PIO
},
1053 [ADDR_MODE_LBA48
] = {
1054 [IO_READ
] = CMD_READ_PIO_EXT
,
1055 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
1058 [ADDR_MODE_LBA28
] = {
1059 [IO_READ
] = CMD_READ_DMA
,
1060 [IO_WRITE
] = CMD_WRITE_DMA
},
1061 [ADDR_MODE_LBA48
] = {
1062 [IO_READ
] = CMD_READ_DMA_EXT
,
1063 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
1068 * Test a Read/Write pattern using various commands, addressing modes,
1069 * transfer modes, and buffer sizes.
1071 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
1072 unsigned bufsize
, uint64_t sector
)
1076 ahci
= ahci_boot_and_enable();
1077 ahci_test_io_rw_simple(ahci
, bufsize
, sector
,
1078 io_cmds
[dma
][lba48
][IO_READ
],
1079 io_cmds
[dma
][lba48
][IO_WRITE
]);
1080 ahci_shutdown(ahci
);
1084 * Demultiplex the test data and invoke the actual test routine.
1086 static void test_io_interface(gconstpointer opaque
)
1088 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1092 switch (opts
->length
) {
1100 bufsize
= 4096 * 64;
1106 g_assert_not_reached();
1109 sector
= offset_sector(opts
->offset
, opts
->address_type
, bufsize
);
1110 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
, sector
);
1115 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1116 enum BuffLen len
, enum OffsetType offset
)
1118 static const char *arch
;
1120 AHCIIOTestOptions
*opts
= g_malloc(sizeof(AHCIIOTestOptions
));
1123 opts
->address_type
= addr
;
1124 opts
->io_type
= type
;
1125 opts
->offset
= offset
;
1128 arch
= qtest_get_arch();
1131 name
= g_strdup_printf("/%s/ahci/io/%s/%s/%s/%s", arch
,
1133 addr_mode_str
[addr
],
1135 offset_str
[offset
]);
1137 g_test_add_data_func(name
, opts
, test_io_interface
);
1141 /******************************************************************************/
1143 int main(int argc
, char **argv
)
1150 static struct option long_options
[] = {
1151 {"pedantic", no_argument
, 0, 'p' },
1155 /* Should be first to utilize g_test functionality, So we can see errors. */
1156 g_test_init(&argc
, &argv
, NULL
);
1159 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1170 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1171 g_assert_not_reached();
1175 /* Check architecture */
1176 arch
= qtest_get_arch();
1177 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1178 g_test_message("Skipping test for non-x86");
1182 /* Create a temporary qcow2 image */
1183 close(mkstemp(tmp_path
));
1184 mkqcow2(tmp_path
, TEST_IMAGE_SIZE_MB
);
1187 qtest_add_func("/ahci/sanity", test_sanity
);
1188 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1189 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1190 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1191 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1192 qtest_add_func("/ahci/identify", test_identify
);
1194 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1195 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1196 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1197 for (m
= OFFSET_BEGIN
; m
< NUM_OFFSETS
; m
++) {
1198 create_ahci_io_test(i
, j
, k
, m
);
1204 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);
1206 qtest_add_func("/ahci/flush/simple", test_flush
);